Display panel and preparation method thereof, motherboard to be cut and preparation method thereof

Abstract

The present disclosure provides a display panel and a method for preparing the same, a motherboard to be cut and a method for preparing the same. The motherboard to be cut comprises: a substrate; a pad assembly, arranged on one side of the substrate and located in the binding area; an insulating material layer, arranged on the side of the pad assembly facing away from the substrate; a light-emitting unit, arranged on the side of the insulating material layer facing away from the substrate; a pixel defining layer, arranged on the side of the insulating material layer facing away from the substrate and surrounding the light-emitting unit; wherein the pixel defining layer is located outside the cutting area. The present disclosure can prevent the film layer of the motherboard to be cut from falling off during the cutting process.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, a motherboard to be cut and a manufacturing method thereof. Background Art

[0002] With the development of economy, display panels have been more and more widely used in people's lives. The display panel mainly includes a light-emitting structure. The light-emitting structure includes two electrodes arranged opposite to each other and a light-emitting layer located between the two electrodes. The two electrodes are electrically connected to a power supply to supply power to the light-emitting layer. The display panel can be formed by cutting a motherboard to be cut. However, the film layer of the existing motherboard to be cut is easy to fall off during the cutting process. Summary of the invention

[0003] The purpose of the present disclosure is to provide a display panel and a manufacturing method thereof, a motherboard to be cut and a manufacturing method thereof, which can prevent a film layer of the motherboard to be cut from falling off during the cutting process.

[0004] According to one aspect of the present disclosure, there is provided a motherboard to be cut, the motherboard to be cut comprising a display area, a binding area and a cutting area, the binding area is located between the cutting area and the display area, and the motherboard to be cut comprises:

[0005] substrate;

[0006] A pad assembly, disposed on one side of the substrate and located in the binding area;

[0007] An insulating material layer, disposed on a side of the pad assembly facing away from the substrate;

[0008] A light emitting unit, disposed on a side of the insulating material layer facing away from the substrate;

[0009] A pixel defining layer, disposed on a side of the insulating material layer facing away from the substrate and surrounding the light emitting unit;

[0010] Wherein, the pixel defining layer is located outside the cutting area.

[0011] Furthermore, the pad assembly includes a plurality of signal lines arranged in parallel, and an orthographic projection of the signal line on the substrate is spaced apart from an orthographic projection of the pixel defining layer on the substrate.

[0012] Further, the orthographic projection of the pixel definition layer on the substrate includes a first boundary and a second boundary that are arranged opposite to each other, the pad assembly is located between the first boundary and the second boundary, and the first boundary and the second boundary are parallel to the extension direction of the signal line;

[0013] The distance between the orthographic projection of the signal line closest to the first boundary among the multiple signal lines and the first boundary on the substrate is 40μm-80μm; and / or the distance between the orthographic projection of the signal line closest to the second boundary among the multiple signal lines and the second boundary on the substrate is 40μm-80μm.

[0014] Furthermore, the insulating material layer is located outside the cutting area.

[0015] Furthermore, the substrate is a silicon-based substrate, the silicon-based substrate is provided with an active area, and the motherboard to be cut further includes:

[0016] A gate insulating layer, disposed on the substrate;

[0017] A gate electrode layer, disposed on a side of the gate insulating layer facing away from the substrate;

[0018] An interlayer insulating layer, disposed on a side of the gate electrode layer facing away from the substrate;

[0019] The first metal layer is arranged on a side of the interlayer insulating layer facing away from the substrate, and the pad assembly is arranged on the same layer as the first metal layer.

[0020] According to one aspect of the present disclosure, a method for preparing a motherboard to be cut is provided, wherein the motherboard to be cut comprises a display area, a binding area and a cutting area, wherein the binding area is located between the cutting area and the display area, and the preparation method comprises:

[0021] forming a pad assembly on one side of a substrate, wherein the pad assembly is located in the binding area;

[0022] forming an insulating material layer on a side of the pad assembly facing away from the substrate;

[0023] forming a second opening on the insulating material layer to expose the pad assembly;

[0024] forming a colloid material layer covering the second opening, and curing the colloid material layer, wherein a partial area of ​​the colloid material layer is located in the cutting area;

[0025] forming a pixel defining layer and a light emitting unit, wherein the light emitting unit is disposed on a side of the insulating material layer facing away from the substrate; a partial area of ​​the pixel defining layer is disposed on a side of the insulating material layer facing away from the substrate and surrounds the light emitting unit; another partial area of ​​the pixel defining layer covers the colloidal material layer;

[0026] Laser ablation is performed on the colloid material layer located in the binding area and the cutting area to remove the colloid material layer and the portion of the pixel definition layer covering the colloid material layer.

[0027] Furthermore, the pad assembly includes a plurality of signal lines arranged in parallel, and orthographic projections of the plurality of signal lines on the substrate are located within an orthographic projection region of the colloid material layer on the substrate.

[0028] Furthermore, the orthographic projection of the colloid material layer includes a first side edge and a second side edge that are arranged opposite to each other, and the first side edge and the second side edge are parallel to the extension direction of the signal line;

[0029] The distance between the orthographic projection of the signal line closest to the first side among the multiple signal lines and the first side on the substrate is 40μm-80μm; and / or the distance between the orthographic projection of the signal line closest to the second side among the multiple signal lines and the second side on the substrate is 40μm-80μm.

[0030] Furthermore, an angle between the side wall of the colloidal material layer and the substrate is an acute angle.

[0031] Furthermore, an angle between a side wall of the colloidal material layer and the substrate is 25°-55°.

[0032] Further, the pad assembly includes a plurality of signal lines arranged in parallel;

[0033] The colloid material layer includes a plurality of colloid material strips arranged in parallel, the extension direction of the colloid material strips is the same as the extension direction of the signal lines, the plurality of colloid material strips cover the plurality of signal lines one by one, and two adjacent colloid material strips are arranged at intervals.

[0034] Furthermore, in the width direction, the colloid material strip includes a first side wall and a second side wall, the angle between the first side wall and the substrate is an acute angle, and the angle between the second side wall and the substrate is an acute angle.

[0035] Furthermore, an included angle between the first side wall and the substrate is 25°-55°, and an included angle between the second side wall and the substrate is 25°-55°.

[0036] According to one aspect of the present disclosure, there is provided a method for preparing a display panel, comprising:

[0037] Providing the motherboard to be cut;

[0038] Cutting is performed along a cutting line in the cutting zone.

[0039] According to one aspect of the present disclosure, a display panel is provided. The display panel is prepared by the method for preparing a display panel.

[0040] The display panel and its preparation method, the motherboard to be cut and its preparation method disclosed in the present invention, during the laser ablation process, not only the colloidal material layer located in the binding area is laser ablated, but also the colloidal material layer located in the cutting area is laser ablated, thereby removing the portion of the pixel defining layer located in the cutting area, and further preventing the pixel defining layer from falling off during the cutting process, thereby preventing the film layer of the motherboard to be cut from falling off during the cutting process. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 Schematic diagram of a mother board to be cut according to an embodiment of the present disclosure.

[0042] Figure 2 It is a schematic diagram after forming the first metal layer in the method for preparing the mother board to be cut according to the embodiment of the present disclosure.

[0043] Figure 3 It is a schematic diagram after forming a pixel defining layer and a light-emitting unit in the method for preparing a motherboard to be cut according to an embodiment of the present disclosure.

[0044] Figure 4 It is a schematic cross-sectional view of a mother board to be cut according to an embodiment of the present disclosure.

[0045] Figure 5 It is a distribution diagram of the first boundary, the second boundary and the pad assembly in the embodiment of the present disclosure.

[0046] Figure 6 and Figure 7 is another cross-sectional schematic diagram of a mother board to be cut according to an embodiment of the present disclosure.

[0047] Explanation of the reference numerals: 1. substrate; 101. active area; 102. source-drain electrode area; 2. gate insulating layer; 3. gate electrode layer; 4. interlayer insulating layer; 5. first metal layer; 6. insulating material layer; 601. first planarization layer; 602. second planarization layer; 7. second metal layer; 8. pad assembly; 801. signal line; 9. light-emitting unit; 901. anode; 902. light-emitting layer; 903. cathode; 10. pixel defining layer; 11. colloidal material layer; 1101. colloidal material strip; 100. display area; 200. binding area; 300. cutting area. DETAILED DESCRIPTION

[0048] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices consistent with some aspects of the present disclosure as detailed in the appended claims.

[0049] The terms used in the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The words "first", "second" and similar words used in the present disclosure specification and claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limit, but indicate that there is at least one. "Multiple" or "several" means two and more than two. Unless otherwise specified, words such as "front", "rear", "lower" and / or "upper" are only for the convenience of explanation and are not limited to one position or one spatial orientation. Words such as "include" or "comprise" mean that the elements or objects appearing in front of "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, and can include electrical connections, whether direct or indirect. As used in this disclosure and the appended claims, the singular forms "a", "an", "said", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.

[0050] The present disclosure provides a motherboard to be cut. Figure 1 and Figure 4 ( Figure 4 yes Figure 1 As shown in the partial cross-sectional schematic diagram of the structure shown in the X direction, the motherboard to be cut may include a display area 100, a binding area 200 and a cutting area 300. The binding area 200 may be located between the cutting area 300 and the display area 100. The motherboard to be cut may include a substrate 1, a pad assembly 8, an insulating material layer 6, a light-emitting unit 9 and a pixel defining layer 10, wherein:

[0051] The pad assembly 8 is disposed on one side of the substrate 1 and is located in the binding area 200. The insulating material layer 6 is disposed on the side of the pad assembly 8 facing away from the substrate 1. The light-emitting unit 9 is disposed on the side of the insulating material layer 6 facing away from the substrate 1. The pixel defining layer 10 is disposed on the side of the insulating material layer 6 facing away from the substrate 1 and surrounds the light-emitting unit 9. The pixel defining layer 10 is located outside the cutting area 300.

[0052] The substrate 1 may be a rigid substrate. The rigid substrate may be a glass substrate or a PMMA (Polymethylmethacrylate) substrate, etc. Of course, the substrate 1 may also be a flexible substrate. The flexible substrate may be a PET (Polyethylene terephthalate) substrate, a PEN (Polyethylene naphthalate two formic acid glycol ester) substrate or a PI (Polyimide) substrate. Of course, the substrate 1 may be a silicon-based substrate. An active area 101 is provided in the silicon-based substrate. The active area 101 may be located in the display area 100. A source-drain electrode area 102 is provided in the active area 101.

[0053] Taking the substrate 1 as a silicon-based substrate as an example, the mother board to be cut may include a gate insulating layer 2, a gate electrode layer 3, an interlayer insulating layer 4, a first metal layer 5, a first planarization layer 601, a second metal layer 7 and a second planarization layer 602. The gate insulating layer 2 may be disposed on the active area 101. The gate electrode layer 3 may be disposed on the gate insulating layer 2. The interlayer insulating layer 4 may cover the gate electrode layer 3 and the source-drain electrode region 102. The first metal layer 5 may be disposed on the side of the interlayer insulating layer 4 facing away from the silicon-based substrate 1, and electrically connected to the source-drain electrode region 102. The first planarization layer 601 may cover the first metal layer 5 and the interlayer insulating layer 4. The second metal layer 7 may be disposed on the side of the first planarization layer 601 facing away from the silicon-based substrate, and electrically connected to the first metal layer 5 via a via hole passing through the first planarization layer 601. The second metal layer 7 may be a metal reflective layer. The second planarization layer 602 may cover the second metal layer 7 and the first planarization layer 601. It should be noted that the gate electrode layer 3, the first metal layer 5 and the second metal layer 7 are all located in the display area 100. The interlayer insulating layer 4, the first planarizing layer 601 and the second planarizing layer 602 are all extended to the binding area 200, and the interlayer insulating layer 4, the first planarizing layer 601 and the second planarizing layer 602 are all extended to the cutting area 300.

[0054] The pad assembly 8 is arranged on one side of the substrate 1 and is located in the binding area 200. The pad assembly 8 may include a plurality of signal lines 801 arranged in parallel. The extension direction of the plurality of signal lines 801 arranged in parallel is the same, and the extension direction of the signal line 801 may be perpendicular to the thickness direction of the substrate 1. The plurality of signal lines 801 are arranged in the same layer. Taking the substrate 1 as a silicon-based substrate as an example, the plurality of signal lines 801 may be arranged in the same layer as the first metal layer 5 mentioned above. The insulating material layer 6 is arranged on the side of the pad assembly 8 facing away from the substrate 1. Among them, the insulating material layer 6 may include the first planarization layer 601 and the second planarization layer 602 mentioned above. Further, the insulating material layer 6 may be composed of the first planarization layer 601 and the second planarization layer 602 mentioned above.

[0055] The light-emitting unit 9 is arranged on the side of the insulating material layer 6 facing away from the substrate 1, and the light-emitting unit 9 is located in the display area 100. The light-emitting unit 9 may include an anode 901, a light-emitting layer 902 and a cathode 903 arranged in a stacked manner. The anode 901 may be arranged on the side of the insulating material layer 6 facing away from the substrate 1, and the cathode 903 may be arranged on the side of the anode 901 facing away from the substrate 1. Specifically, the anode 901 may be arranged on the surface of the second planarization layer 602 facing away from the substrate 1. The number of the light-emitting layers 902 may be multiple, and they may be stacked. Among them, the multiple light-emitting layers 902 may include a red light-emitting layer, a green light-emitting layer and a blue light-emitting layer. The emitted light of the multiple light-emitting layers 902 may form white light. The number of the light-emitting units 9 may be multiple, and the multiple light-emitting units 9 may be arranged at intervals.

[0056] The pixel defining layer 10 is disposed on the side of the insulating material layer 6 facing away from the substrate 1 and surrounds the light emitting unit 9. Specifically, the pixel defining layer 10 can be disposed on the surface of the second planarization layer 602 facing away from the substrate 1. The pixel defining layer 10 can also be located outside the cutting area 300, that is, the cutting area 300 is not provided with the pixel defining layer 10. Further, the insulating material layer 6 can be located outside the cutting area 300. Figure 5 As shown, the orthographic projection of the pixel defining layer 10 on the substrate 1 may include a first boundary L2 and a second boundary L3 that are arranged oppositely. The pad assembly 8 may be located between the first boundary L2 and the second boundary L3. The first boundary L2 and the second boundary L3 are parallel to the extension direction of the signal line 801. The distance D1 between the orthographic projection of the signal line 801 closest to the first boundary L2 among the plurality of signal lines 801 and the first boundary L2 on the substrate 1 may be 40 μm-80 μm, for example, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, etc. The distance D2 between the orthographic projection of the signal line 801 closest to the second boundary L3 among the plurality of signal lines 801 and the second boundary L3 on the substrate 1 is 40 μm-80 μm, for example, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, etc.

[0057] The present disclosure also provides a method for preparing a motherboard to be cut, which is used to prepare the motherboard to be cut described in any of the above embodiments. Figure 2-Figure 4 As shown, the motherboard to be cut may include a display area 100, a binding area 200 and a cutting area 300, wherein the binding area 200 is located between the cutting area 300 and the display area 100. The preparation method may include steps S100 to S150, wherein:

[0058] Step S100 , forming a pad assembly 8 on one side of a substrate 1 , wherein the pad assembly 8 is located in a bonding area 200 .

[0059] Step S110 , forming an insulating material layer 6 on the side of the pad assembly 8 facing away from the substrate 1 .

[0060] Step S120 , forming a second opening on the insulating material layer 6 to expose the pad assembly 8 .

[0061] Step S130 , forming a colloidal material layer 11 covering the second opening, and curing the colloidal material layer 11 , wherein a partial area of ​​the colloidal material layer 11 is located in the cutting area 300 .

[0062] Step S140, forming a pixel defining layer 10 and a light-emitting unit 9, wherein the light-emitting unit 9 is arranged on the side of the insulating material layer 6 facing away from the substrate 1; a partial area of ​​the pixel defining layer 10 is arranged on the side of the insulating material layer 6 facing away from the substrate 1 and surrounds the light-emitting unit 9; another partial area of ​​the pixel defining layer 10 covers the colloidal material layer 11.

[0063] Step S150 , performing laser ablation on the colloid material layer 11 located in the binding area 200 and the cutting area 300 to remove the colloid material layer 11 and the portion of the pixel definition layer 10 covering the colloid material layer 11 .

[0064] In the method for preparing the motherboard to be cut of the embodiment of the present disclosure, during the laser ablation process, not only the colloidal material layer 11 located in the binding area 200 is laser ablated, but also the colloidal material layer 11 located in the cutting area 300 is laser ablated, thereby removing the portion of the pixel defining layer 10 located in the cutting area 300, thereby preventing the pixel defining layer 10 from falling off during the cutting process.

[0065] The steps of the method for preparing the motherboard to be cut according to the embodiment of the present disclosure are described in detail below:

[0066] In step S100 , a pad assembly 8 is formed on one side of a substrate 1 , and the pad assembly 8 is located in a bonding area 200 .

[0067] like Figure 2As shown, taking the substrate 1 as a silicon-based substrate as an example, step S100 may include: forming a gate insulating layer 2 covering the active area 101 of the substrate 1; forming a gate electrode layer 3 on the gate insulating layer 2; forming an interlayer insulating layer 4 covering the gate electrode layer 3 and the source-drain electrode area 102; and forming a first metal layer 5 and a pad assembly 8 on the side of the interlayer insulating layer 4 facing away from the silicon-based substrate 1 through a one-step process.

[0068] In step S110 , an insulating material layer 6 is formed on a side of the pad assembly 8 facing away from the substrate 1 .

[0069] like Figure 2 As shown, taking the insulating material layer 6 including the above-mentioned first planarization layer 601 and the second planarization layer 602 as an example, step S110 may include: forming a first planarization layer 601 covering the first metal layer 5 and the pad assembly 8; forming a second metal layer 7 on the side of the first planarization layer 601 facing away from the silicon-based substrate, and the second metal layer 7 is electrically connected to the first metal layer 5 via a via passing through the first planarization layer 601; forming a second planarization layer 602 covering the second metal layer 7 and the first planarization layer 601.

[0070] In step S120 , a second opening exposing the pad assembly 8 is formed on the insulating material layer 6 .

[0071] The present disclosure can form a second opening exposing the pad assembly 8 on the insulating material layer 6 by a photolithography process. Taking the pad assembly 8 as an example, the number of the second openings is also multiple, and the multiple second openings correspond to each other to expose the multiple signal lines 801. The second opening can also be in a strip shape, and the extension direction of the second opening can be the same as the extension direction of the signal line 801.

[0072] In step S130, Figure 3 As shown, a colloidal material layer 11 covering the second opening is formed, and the colloidal material layer 11 is solidified, and a partial area of ​​the colloidal material layer 11 is located in the cutting area 300 .

[0073] The colloid material layer 11 may be made of photoresist, but the present disclosure does not specifically limit this. The colloid material layer 11 may be located outside the display area 100. The orthographic projections of the multiple signal lines 801 of the pad assembly 8 on the substrate 1 are located within the orthographic projection area of ​​the colloid material layer 11 on the substrate 1. During the curing process of the colloid material layer 11, the colloid material layer 11 will shrink in a direction parallel to the substrate 1. Since the orthographic projections of the multiple signal lines 801 of the pad assembly 8 on the substrate 1 are located within the orthographic projection area of ​​the colloid material layer 11 on the substrate 1 (the area of ​​the colloid material layer 11 is relatively large), the shrunk colloid material layer 11 can still cover the signal lines 801.

[0074] The orthographic projection of the colloidal material layer 11 may include a first side edge and a second side edge that are arranged opposite to each other. The first side edge and the second side edge are parallel to the extension direction of the signal line 801. The distance between the orthographic projection of the signal line 801 closest to the first side edge among the multiple signal lines 801 and the first side edge on the substrate 1 may be 40 μm-80 μm, for example, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, etc. The distance between the orthographic projection of the signal line 801 closest to the second side edge among the multiple signal lines 801 and the second side edge on the substrate 1 is 40 μm-80 μm, for example, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, etc.

[0075] In addition, if Figure 6 As shown, the angle between the side wall of the colloidal material layer 11 and the substrate 1 is an acute angle. Specifically, the angle α between the side wall of the colloidal material layer 11 and the substrate 1 can be 25°-55°, for example, 25°, 29°, 33°, 52°, 55°, etc. Such a setting can change the curing characteristics of the colloidal material layer 11 and reduce the degree of shrinkage of the colloidal material layer 11 during the curing process. Taking the example that the pad assembly 8 includes a plurality of signal lines 801 arranged in parallel, the colloidal material layer 11 can also include a plurality of colloidal material strips 1101 arranged in parallel, and the plurality of colloidal material strips 1101 cover the plurality of signal lines 801 one by one, and two adjacent colloidal material strips 1101 are arranged at intervals. Among them, the extension direction of the colloidal material strip 1101 can be the same as the extension direction of the signal line 801. As shown Figure 7 As shown, the colloidal material strip 1101 may include a first side wall and a second side wall in the width direction. Both the first side wall and the second side wall extend along the extension direction of the signal line 801. The angle β between the first side wall and the substrate 1 may be an acute angle, such as 25°-55°, and may specifically be 25°, 28°, 30°, 50°, 55°, etc. The angle γ between the second side wall and the substrate 1 may be an acute angle, such as 25°-55°, and may specifically be 25°, 32°, 40°, 50°, 55°, etc. Among them, the angle between the first side wall and the substrate 1 and the angle between the second side wall and the substrate 1 may be the same, or of course, they may be different.

[0076] In step S140, if Figure 4 As shown, a pixel defining layer 10 and a light-emitting unit 9 are formed. The light-emitting unit 9 is arranged on the side of the insulating material layer 6 facing away from the substrate 1; a partial area of ​​the pixel defining layer 10 is arranged on the side of the insulating material layer 6 facing away from the substrate 1 and surrounds the light-emitting unit 9; another partial area of ​​the pixel defining layer 10 covers the colloidal material layer 11.

[0077] The material of the pixel defining layer 10 may include inorganic materials, such as silicon oxide, etc. Taking the colloidal material layer 11 including a plurality of colloidal material strips 1101 arranged in parallel as an example, the pixel defining layer 10 not only covers the colloidal material strips 1101 , but also covers the insulating material layer 6 between adjacent colloidal material strips 1101 .

[0078] In step S150 , the colloid material layer 11 located in the binding area 200 and the cutting area 300 is laser ablated to remove the colloid material layer 11 and the portion of the pixel definition layer 10 covering the colloid material layer 11 .

[0079] Laser ablation refers to the carbonization of the colloidal material layer 11 by laser, and a large amount of heat will be generated in the process, which can explode the colloidal material layer 11. Among them, when the colloidal material layer 11 explodes, the part of the pixel defining layer 10 covering the colloidal material layer 11 will also explode under the explosion of the colloidal material layer 11. It should be noted that the pixel defining layer 10 is an inorganic material such as silicon oxide, and the rest of the pixel defining layer 10 (the part of the pixel defining layer 10 not covered by the colloidal material layer 11) will not explode under the action of laser ablation. In addition, in step S130, the orthographic projections of the multiple signal lines 801 of the pad assembly 8 on the substrate 1 are located within the orthographic projection area of ​​the colloidal material layer 11 on the substrate 1, so that the signal lines 801 can be exposed through the laser ablation process. In the related art, the colloidal material layer 11 shrinks greatly after curing, resulting in part of the signal line 801 not being covered by the colloidal material layer 11, resulting in the signal line 801 being covered by the subsequently formed pixel defining layer 10. Since the pixel defining layer 10 directly covering the signal line 801 cannot be removed during the laser ablation process, the pixel defining layer 10 that is arranged on the signal line 801 and cannot be removed will affect the connection characteristics of the signal line 801, thereby reducing the reliability level.

[0080] The present disclosure provides a method for manufacturing a display panel. The method for manufacturing a display panel may include: Figure 1 As shown, a mother board to be cut as described in any of the above embodiments is provided; cutting is performed along a cutting line L1 in a cutting area 300. The cutting line L1 may also be referred to as a cutting street.

[0081] The embodiment of the present disclosure provides a display panel, which can be manufactured by the above-mentioned method for manufacturing a display panel.

[0082] The motherboard to be cut, the method for preparing the motherboard to be cut, the display panel and the method for preparing the display panel provided in the embodiments of the present disclosure belong to the same inventive concept, and the description of the relevant details and beneficial effects can be referred to each other and will not be repeated here.

[0083] The above is only a preferred embodiment of the present disclosure and does not limit the present disclosure in any form. Although the present disclosure has been disclosed as a preferred embodiment as above, it is not used to limit the present disclosure. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present disclosure. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present disclosure without departing from the content of the technical solution of the present disclosure are still within the scope of the technical solution of the present disclosure.

Claims

1. A motherboard to be cut, comprising a display area, a binding area and a cutting area, wherein the binding area is located between the cutting area and the display area, characterized in that: The motherboard to be cut comprises: substrate; A pad assembly, disposed on one side of the substrate and located in the binding area; An insulating material layer, disposed on a side of the pad assembly facing away from the substrate; A light emitting unit, disposed on a side of the insulating material layer facing away from the substrate; A pixel defining layer, disposed on a side of the insulating material layer facing away from the substrate and surrounding the light emitting unit; Wherein, the pixel defining layer is located outside the cutting area; The pad assembly includes a plurality of signal lines arranged in parallel, wherein the orthographic projections of the signal lines on the substrate are spaced apart from the orthographic projections of the pixel defining layer on the substrate; The orthographic projection of the pixel definition layer on the substrate includes a first boundary and a second boundary that are arranged opposite to each other, the pad assembly is located between the first boundary and the second boundary, and the first boundary and the second boundary are parallel to the extension direction of the signal line; The distance between the orthographic projection of the signal line closest to the first boundary among the multiple signal lines and the first boundary on the substrate is 40μm-80μm; and / or the distance between the orthographic projection of the signal line closest to the second boundary among the multiple signal lines and the second boundary on the substrate is 40μm-80μm.

2. The motherboard to be cut according to claim 1, characterized in that: The insulating material layer is located outside the cutting area.

3. The motherboard to be cut according to claim 1, characterized in that: The substrate is a silicon-based substrate, and the silicon-based substrate is provided with an active area. The motherboard to be cut also includes: A gate insulating layer, disposed on the substrate; A gate electrode layer, disposed on a side of the gate insulating layer facing away from the substrate; An interlayer insulating layer, disposed on a side of the gate electrode layer facing away from the substrate; The first metal layer is arranged on a side of the interlayer insulating layer facing away from the substrate, and the pad assembly is arranged on the same layer as the first metal layer.

4. A method for preparing a motherboard to be cut, wherein the motherboard to be cut comprises a display area, a binding area and a cutting area, wherein the binding area is located between the cutting area and the display area, characterized in that: The preparation method comprises: forming a pad assembly on one side of a substrate, wherein the pad assembly is located in the binding area; forming an insulating material layer on a side of the pad assembly facing away from the substrate; forming a second opening on the insulating material layer to expose the pad assembly; forming a colloid material layer covering the second opening, and curing the colloid material layer, wherein a partial area of ​​the colloid material layer is located in the cutting area; forming a pixel defining layer and a light emitting unit, wherein the light emitting unit is disposed on a side of the insulating material layer facing away from the substrate; a partial area of ​​the pixel defining layer is disposed on a side of the insulating material layer facing away from the substrate and surrounds the light emitting unit; another partial area of ​​the pixel defining layer covers the colloidal material layer; Performing laser ablation on the colloid material layer located in the binding area and the cutting area to remove the colloid material layer and a portion of the pixel definition layer covering the colloid material layer; The pad assembly includes a plurality of signal lines arranged in parallel, and the orthographic projections of the plurality of signal lines on the substrate are located within the orthographic projection area of ​​the colloid material layer on the substrate; The orthographic projection of the colloid material layer includes a first side edge and a second side edge that are arranged opposite to each other, and the first side edge and the second side edge are parallel to the extension direction of the signal line; The distance between the orthographic projection of the signal line closest to the first side among the multiple signal lines and the first side on the substrate is 40μm-80μm; and / or the distance between the orthographic projection of the signal line closest to the second side among the multiple signal lines and the second side on the substrate is 40μm-80μm.

5. The method for preparing a motherboard to be cut according to claim 4, characterized in that: The included angle between the side wall of the colloidal material layer and the substrate is an acute angle.

6. The method for preparing a motherboard to be cut according to claim 5, characterized in that: The angle between the side wall of the colloidal material layer and the substrate is 25°-55°.

7. The method for preparing a motherboard to be cut according to claim 4, characterized in that: The pad assembly includes a plurality of signal lines arranged in parallel; The colloid material layer includes a plurality of colloid material strips arranged in parallel, the extension direction of the colloid material strips is the same as the extension direction of the signal lines, the plurality of colloid material strips cover the plurality of signal lines one by one, and two adjacent colloid material strips are arranged at intervals.

8. The method for preparing a motherboard to be cut according to claim 7, characterized in that: In the width direction, the colloid material strip includes a first side wall and a second side wall. The angle between the first side wall and the substrate is an acute angle, and the angle between the second side wall and the substrate is an acute angle.

9. The method for preparing a motherboard to be cut according to claim 8, characterized in that: The included angle between the first side wall and the substrate is 25°-55°, and the included angle between the second side wall and the substrate is 25°-55°.

10. A method for preparing a display panel, characterized in that: include: Providing a mother board to be cut according to any one of claims 1 to 3; Cutting is performed along a cutting line in the cutting zone.

11. A display panel, characterized in that: The display panel is prepared by the method for preparing a display panel according to claim 10.

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