A multi-element array bipolar transistor structure and method of fabrication

Abstract

The application provides a multi-element array bipolar transistor structure and a manufacturing method. The structure comprises a first conductive type substrate, a second conductive type base region, a first conductive type emitter region, a second conductive type base region lead-out region and a plurality of first conductive type collector regions. The base region is in the substrate, the emitter region is in the base region, the base region lead-out region is in the base region, the base region lead-out region surrounds the emitter region and is spaced apart from the emitter region by a preset distance, and the plurality of collector regions are in the upper layer of the base region and are separately arranged between the emitter region and the base region lead-out region. In the multi-element array bipolar transistor structure and the manufacturing method, the separate collector regions are arranged, different amplification coefficients can be realized according to different connection modes, and the circuit design freedom of the device is improved. In addition, the emitter region is arranged at the center of the whole structure, the collector regions are symmetrically distributed around the emitter region, and the space utilization of the layout can be improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology and relates to a multi-element array bipolar transistor structure and its fabrication method. Background Technology

[0002] Currently, the design of bipolar junction transistors (BJTs) in semiconductor devices mostly uses a single structure, employing different sizes and ion implantation methods to adjust the device's characteristic parameters (such as key parameters like beta, where beta represents the ratio of collector current to base current or the ratio of their current changes during operation). BJTs are divided into two types: NPN and PNP, and can also be classified by ion implantation method as lateral and vertical BJTs. Taking lateral PNP transistors as an example, common layout designs include... Figure 1 As shown, by setting a collector region 40' around the emitter region 30', wherein the emitter region 30' and the collector region 40' are located in the base region 20', and an emitter E is formed at the preset active region of the emitter region 30', a collector C is formed at the preset active region of the collector region 40', and a base B is formed at the preset active region of the base region 20', once the transistor's set size is fixed, its characteristics are also fixed for a specific process, and it cannot be adjusted; only a single amplification factor can be achieved.

[0003] Therefore, how to provide a multi-element array bipolar transistor structure and fabrication method that enables a single device to achieve different amplification factors and improve the freedom of circuit design has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a multi-element array bipolar transistor structure and fabrication method to solve the problems of fixed-size devices only being able to achieve a single amplification factor and low circuit design freedom in the prior art.

[0005] To achieve the above and other related objectives, the present invention provides a multi-element array bipolar transistor structure, comprising:

[0006] First conductivity type substrate;

[0007] A base region of the second conductivity type is located in the substrate;

[0008] The first conductivity type emitter region is located in the base region;

[0009] A second conductivity type base region lead-out area is located in the base region, and the base region lead-out area surrounds the emitter region and is spaced at a predetermined distance from the emitter region;

[0010] Multiple collector regions of the first conductivity type are located on the upper surface of the base region, and the multiple collector regions are separately disposed between the emitter region and the base region lead-out region.

[0011] Optionally, the base region includes a first base region and a second base region, the second base region being located above the first base region and protruding from the upper surface of the base region, and the doping concentration of the second base region being higher than that of the first base region.

[0012] Optionally, the upper surface of the emitter region is provided with a first conductivity type emitter lead-out region, the doping concentration of the emitter lead-out region is greater than the doping concentration of the emitter region; the upper surface of the substrate is provided with a first conductivity type substrate lead-out region, the substrate lead-out region is located outside the base region lead-out region and is isolated from the base region lead-out region, the doping concentration of the substrate lead-out region is greater than the doping concentration of the substrate.

[0013] Optionally, it also includes:

[0014] A first dielectric layer is located above the substrate and covers the emitter region, the base region, and the collector region;

[0015] Multiple contact vias penetrate the first dielectric layer in a vertical direction, and the bottom ends of the contact vias are respectively connected to the emitter region, the collector region, the base region and the substrate;

[0016] A first metal interconnect layer, located above the first dielectric layer, includes an emitter metal lead-out, a collector, a base, and a substrate ground electrode. The emitter metal lead-out is connected to the emitter region, the collector is connected to the collector region, the base is connected to the base lead-out region, and the substrate ground electrode is connected to the substrate.

[0017] A second dielectric layer is located above the first dielectric layer. The second dielectric layer has a connection hole that penetrates the second dielectric layer in a vertical direction. The bottom end of the connection hole is led out and connected to the metal of the emission area.

[0018] A second metal interconnect layer, located above the second dielectric layer, includes an emitter connected to the top of the connection hole.

[0019] Optionally, multiple collector regions are symmetrically distributed around the emitter region.

[0020] The present invention also provides a method for fabricating a multi-element array bipolar transistor structure, comprising the following steps:

[0021] Provide a substrate of the first conductivity type;

[0022] A base region of a second conductivity type is formed in the substrate;

[0023] A first conductivity type emitter region is formed in the base region;

[0024] A second conductivity type base region lead-out region is formed in the base region, and the base region lead-out region surrounds the emitter region and is spaced at a predetermined distance from the emitter region;

[0025] Multiple collector regions of the first conductivity type are formed on the upper surface of the base region, and the multiple collector regions are separately disposed between the emitter region and the base region lead-out region.

[0026] Optionally, the following steps are also included:

[0027] A first dielectric layer is formed above the substrate, the first dielectric layer covering the emitter region, the base region and the collector region;

[0028] A plurality of contact vias are formed in the first dielectric layer in a vertical direction, and the bottom ends of the contact vias are respectively connected to the emitter region, the collector region, the base region and the substrate;

[0029] A first metal interconnect layer is formed above the first dielectric layer. The metal interconnect layer includes an emitter metal lead-out, a collector, a base, and a substrate ground electrode. The emitter metal lead-out is connected to the emitter region, the collector is connected to the collector region, the base is connected to the base lead-out region, and the substrate ground electrode is connected to the substrate.

[0030] A second dielectric layer is formed above the first dielectric layer. A connection hole is provided in the second dielectric layer in a vertical direction, and the bottom end of the connection hole is led out and connected to the metal of the emission area.

[0031] A second metal interconnect layer is formed above the second dielectric layer, the second metal interconnect layer including an emitter connected to the top end of the connection hole.

[0032] Optionally, before forming the first dielectric layer, the method further includes the steps of forming a first conductivity type emitter lead-out region on the upper surface of the emitter region and forming a first conductivity type substrate lead-out region on the upper surface of the substrate, wherein the doping concentration of the emitter lead-out region is greater than the doping concentration of the emitter region, the substrate lead-out region is located outside the base lead-out region and isolated from the base lead-out region, and the doping concentration of the substrate lead-out region is greater than the doping concentration of the substrate.

[0033] Optionally, the base region includes a first base region and a second base region, the second base region being located above the base region and protruding from the upper surface of the base region, and the doping concentration of the second base region being higher than that of the first base region.

[0034] Optionally, multiple collector regions are symmetrically distributed around the emitter region.

[0035] As described above, the multi-element array bipolar transistor and its fabrication method provided by this invention, by setting discrete collector regions, can achieve different amplification factors according to different connection methods, thereby improving the circuit design freedom of the device. Furthermore, by placing the emitter region at the center of the entire structure and symmetrically distributing the collector regions around the emitter region, the space utilization of the layout is improved. Attached Figure Description

[0036] Figure 1 The diagram shows a schematic of a lateral transistor.

[0037] Figure 2 The diagram shown is a planar layout of the multi-element array bipolar transistor structure of the present invention after removing the metal layer and interlayer connections.

[0038] Figure 3 The diagram shown is a cross-sectional view of the multi-element array bipolar transistor structure of the present invention.

[0039] Figure 4 The diagram shows a schematic of all collector units in the multi-element array bipolar transistor structure of the present invention connected to the output terminal.

[0040] Figure 5 The diagram shows a schematic of the collector unit portion of the multi-element array bipolar transistor structure of the present invention connected to the output terminal.

[0041] Component designation explanation

[0042] 20' base area

[0043] 30' Launch Area

[0044] 40' collector area

[0045] 10 Substrates

[0046] 101 Substrate lead-out region

[0047] 20 base areas

[0048] 201 Base Area Lead-out Area

[0049] 2010 Base Area First Leading Area

[0050] 2011 Base Area Second Exit Area

[0051] Launch Area 30

[0052] Launch Zone 301

[0053] 40 collector areas

[0054] 401 Eight collector units form the collector terminals.

[0055] 402 Five collector units form the collector terminals.

[0056] 403 Three collector units form the collector terminals.

[0057] 50 isolation layers

[0058] 60 First dielectric layer

[0059] 70 Contact Through Hole

[0060] 80 First metal interconnect layer

[0061] 801 Launch Area Metal Extraction

[0062] 802 collector

[0063] 803 base

[0064] 804 substrate grounding electrode

[0065] 90 Second dielectric layer

[0066] 100 Second metal interconnect layer

[0067] 1001 emitter Detailed Implementation

[0068] The following specific examples illustrate the embodiments of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. For ease of explanation, when detailing the embodiments of the present invention, the cross-sectional views showing the device structure are partially enlarged, not according to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0069] Please see Figures 1 to 5It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0070] Example 1

[0071] This embodiment provides a multi-element array bipolar transistor structure. Please refer to [link / reference]. Figures 2 to 3 The images show a planar layout of the multi-element array bipolar transistor structure after removing the metal layer and interlayer connections, and a cross-sectional view of the multi-element array bipolar transistor structure. The multi-element array bipolar transistor structure includes a first conductivity type substrate 10, a second conductivity type base region 20, a first conductivity type emitter region 30, a second conductivity type base region lead-out region 201, and multiple first conductivity type collector regions 40. The base region 20 is located in the substrate 10, the emitter region 30 is located in the base region 20, the base region lead-out region 201 is located in the base region 20, the base region lead-out region 201 surrounds the emitter region 30 and is spaced at a predetermined distance from the emitter region 30, and the multiple collector regions 40 are located on the upper surface layer of the base region 20 and are separately disposed between the emitter region 30 and the base region lead-out region 20.

[0072] As an example, the first conductivity type is P-type and the second conductivity type is N-type; or the first conductivity type is N-type and the second conductivity type is P-type.

[0073] Specifically, this embodiment takes a lateral PNP transistor as an example, where the first conductivity type is P-type and the second conductivity type is N-type.

[0074] As an example, the substrate 10 may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, silicon-on-insulator, or germanium-on-insulator, etc., or it may be a substrate including other elemental semiconductors or compound semiconductors, such as silicon carbide, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, aluminum indium arsenide, indium gallium arsenide, gallium antimony phosphide, or indium phosphide, etc. In this embodiment, the substrate 10 is a P-type silicon substrate.

[0075] As an example, the base region 20 is an N-well formed by N-type ion implantation, and the N-type impurity ions doped in the base region 20 include one or more of phosphorus ions, arsenic ions and antimony ions.

[0076] As an example, the emitter region 30 is formed by P-type body implantation in the base region 20, wherein the P-type impurity ions include one or more of boron ions, indium ions and gallium ions.

[0077] As an example, the emission area 30 is located at the center of the base area 20 in the horizontal direction, that is, at the center of the entire structure. Its size is not fixed and can be adjusted according to needs.

[0078] As an example, the base region 201 includes a first base region 2010 and a second base region 2011. The second base region 2011 is located above the first base region 2010. The first base region 2010 is located within the base region 20. The second base region 2011 is located on the upper surface of the base region 20 in the vertical direction. The first base region 2010 is formed by N-type body implantation, and the second base region 2011 is formed by ion implantation or diffusion. The doping concentration of the second base region 2011 is greater than that of the first base region 2011. The second base region 2011 is heavily N-type doped, which helps to reduce the contact resistance between the base 803 and the base region 20.

[0079] As an example, the base region lead-out area 201 is arranged in a square ring around the emission region 30 and is spaced at a predetermined distance from the emission region 30.

[0080] As an example, the collector region 40 is P-type heavily doped, and the collector regions 40 are symmetrically distributed around the emitter region 30. In this embodiment, there are 8 collector regions 40, which are arranged in a square in the horizontal direction. The emitter region 30 is located at the center of the square in the horizontal direction to improve the layout space utilization.

[0081] It should be noted that this embodiment only lists 8 collector areas. In other embodiments, more than 8 collector areas or less than 8 collector areas can be set according to needs, and this embodiment is not a limitation.

[0082] As an example, a first conductivity type emitter lead-out region 301 is provided above the emitter region 30. The emitter lead-out region 301 is P-type heavily doped, which helps to reduce the contact resistance between the emitter 1001 and the emitter region 30.

[0083] As an example, the upper surface of the substrate 10 is provided with a first conductivity type substrate lead-out region 101. The substrate lead-out region 101 is located outside the base region lead-out region 201 and is isolated from the base region lead-out region 201. The doping concentration of the substrate lead-out region 101 is greater than the doping concentration of the substrate 10. The substrate lead-out region 101 is heavily P-type doped, which helps to reduce the contact resistance between the substrate ground electrode 804 and the substrate 10.

[0084] As an example, an isolation layer 50 is formed in the substrate 10. The isolation layer 50 is used to electrically isolate adjacent device unit regions such as the emitter region 301, the plurality of discrete collector regions 40, the base region 201 and the substrate region 101. The isolation layer 50 includes an oxide isolation layer, such as a silicon dioxide isolation layer or an isolation layer of other suitable material.

[0085] As an example, the multi-element array bipolar transistor structure further includes a first dielectric layer 60, a plurality of contact vias 70, a first metal interconnect layer 80, a second dielectric layer 90, and a second metal interconnect layer 100. The first dielectric layer 60 is located above the substrate 10 and covers the emitter region 30, the base region 20, and the collector region 40. The plurality of contact vias 70 penetrate the first dielectric layer 60 vertically. A portion of the contact vias 70 are connected to the emitter region 30 via the emitter region lead-out area 301, a portion are connected to the base region 20 via the base region lead-out area 201, a portion are connected to the substrate 10 via the substrate lead-out area 101, and a portion are connected to the collector region 40. The first metal interconnect layer 80 is located above the first dielectric layer 60 and includes a first dielectric layer 60, a plurality of contact vias 70, a first metal interconnect layer 80, a second dielectric layer 90, and a second metal interconnect layer 100. The system comprises an emitter metal lead-out 801, a collector 802, a base 803, and a substrate ground electrode 804. The emitter metal lead-out 801 is connected to the emitter lead-out area 301 via a contact via 70. The collector 802 is connected to the collector area 40 via a contact via 70. The base 803 is connected to the base lead-out area 201 via a contact via 70. The substrate ground electrode 804 is connected to the substrate lead-out area 101 via a contact via 70. The second dielectric layer 90 is located above the first dielectric layer 60. The second dielectric layer 90 has a connecting hole that penetrates the second dielectric layer 90 in a vertical direction. The bottom end of the connecting hole is connected to the emitter metal lead-out 801. The second metal interconnect layer 100 is located above the second dielectric layer 90 and includes an emitter 1001. The emitter 1001 is connected to the top end of the connecting hole.

[0086] As an example, the first dielectric layer 60 is an oxide dielectric layer, including SiO2, Al2O3 or other suitable dielectric layers; the first metal interconnect layer 80 includes metal layers with good conductivity such as copper, aluminum, nickel, gold, silver, and titanium; the second dielectric layer 90 is an intermetallic dielectric layer, including dielectric layers of oxide, nitride or other suitable materials; the second metal interconnect layer 100 includes metal layers with good conductivity such as copper, aluminum, nickel, gold, silver, and titanium.

[0087] It should be noted that in some other embodiments, where the layout routing allows, the emitter metal lead-out can form an emitter, thus eliminating the need for the second dielectric layer and the second metal interconnect layer to form the emitter.

[0088] As an example, by setting up multiple collector areas 40 separately and then connecting these units to different pins (different ports in the circuit) through subsequent metal connections, it can meet the requirements of different amplification factors and can work simultaneously in multiple circuit environments.

[0089] Specifically, for bipolar junction transistors (BJTs), they are generally operated in the amplification region during use. In this region, charge carriers (holes in this embodiment) flow from the emitter (E) to the base (B). Some charge carriers pass through the B terminal and are collected at the collector (C). The flow of charge carriers from the E terminal to the C terminal is determined by the voltage across both terminals. Under a fixed voltage, due to the discrete connection of each unit at the C terminal, different total currents can be obtained at the C terminal, and correspondingly, the current at the B terminal will also change. For example, as... Figure 4 As shown, connecting all eight collector units to the output terminal to form collector terminal 401 results in the best current collection capability and the largest amplification factor. If only one collector unit is connected to the output terminal, the collector current decreases accordingly, and the amplification factor is minimized. Of course, each discrete collector unit can be connected to different ports via metal wires according to actual needs, such as... Figure 5 As shown, five collector units or three collector units can be connected to the output terminal to form different collector terminals 402 and 403, in order to meet the requirements of different amplification factors and achieve the desired effect. Figure 4 Different amplification factors are required. Of course, one, two, four, six, or seven collector units can also be connected to the output terminal to achieve different results, depending on actual needs. Figure 4 or Figure 5 The magnification factor.

[0090] It should be noted that the structure described in this embodiment is based on a lateral PNP transistor, but it is not limited to this structure. The layout design of any bipolar transistor can adopt the layout design method described in this invention.

[0091] In summary, the multi-element array bipolar transistor structure provided in this embodiment, by setting discrete collector regions, can achieve different amplification factors according to different connection methods, thereby improving the circuit design freedom of the device. Furthermore, by placing the emitter region at the center of the entire structure and symmetrically distributing the collector regions around it, the space utilization of the layout is improved.

[0092] Example 2

[0093] This embodiment provides a method for fabricating a multi-element array bipolar transistor structure. This embodiment uses... Figure 2 and Figure 3 Taking the horizontal PNP shown as an example, the steps include:

[0094] S1: Provides a substrate 10 of a first conductivity type;

[0095] As an example, the substrate 10 may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, silicon-on-insulator, or germanium-on-insulator, etc., or it may be a substrate including other elemental semiconductors or compound semiconductors, such as silicon carbide, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, aluminum indium arsenide, indium gallium arsenide, gallium antimony phosphide, or indium phosphide, etc. In this embodiment, the substrate 10 is a P-type silicon substrate.

[0096] S2: A base region 20 of a second conductivity type is formed in the substrate 10;

[0097] As an example, the base region 20 is an N-well formed by N-type ion implantation, and the N-type impurity ions doped in the base region 20 include one or more of phosphorus ions, arsenic ions and antimony ions.

[0098] It should be noted that before forming the base region 20, the process includes forming an isolation layer 50 in the substrate 10: trenches are formed at predetermined locations on the substrate 10 using processes such as masking and etching, and then the isolation layer 50 is formed in the trenches. The method for forming the isolation layer 50 is implemented using conventional techniques in the art and will not be described in detail. Specifically, the isolation layer 50 is an oxide isolation layer used to electrically isolate adjacent device unit regions.

[0099] S3: A first conductivity type emission region 30 is formed in the base region 20;

[0100] As an example, the emitter region 30 is formed by P-type body implantation in the base region 20, wherein the P-type impurity ions include one or more of boron ions, indium ions and gallium ions.

[0101] As an example, the emission area 30 is located at the center of the base area 20 in the horizontal direction, that is, at the center of the entire structure. Its size is not fixed and can be adjusted according to needs.

[0102] S4: A second conductivity type base region lead-out region 201 is formed in the base region 20, the base region lead-out region 201 surrounds the emitter region 30 and is spaced from the emitter region 30 by a predetermined distance;

[0103] As an example, the base region 201 includes a first base region 2010 and a second base region 2011. The second base region 2011 is located above the first base region 2010. The first base region 2010 is located within the base region 20. The second base region 2011 is located on the upper surface of the base region 20 in the vertical direction. The first base region 2010 is formed by N-type body implantation, and the second base region 2011 is formed by ion implantation or diffusion. The doping concentration of the second base region 2011 is greater than that of the first base region 2011. The second base region 2011 is heavily N-type doped, which is beneficial for reducing the contact resistance between the base 803 and the base region 20.

[0104] As an example, the base region lead-out area 201 is arranged in a square ring around the emission region 30 and is spaced at a predetermined distance from the emission region 30.

[0105] S5: A plurality of first conductivity type collector regions 40 are formed on the upper surface layer of the base region 20, and the plurality of collector regions 40 are disposed separately between the emitter region 30 and the base region lead-out region 201.

[0106] As an example, the collector region 40 is P-type heavily doped, and the collector regions 40 are symmetrically distributed around the emitter region 30. In this embodiment, there are 8 collector regions 40, which are arranged in a square in the horizontal direction. The emitter region 30 is located at the center of the square in the horizontal direction to improve the layout space utilization.

[0107] It should be noted that this embodiment only lists 8 collector areas. In other embodiments, more than 8 collector areas or less than 8 collector areas can be set according to needs, and this embodiment is not a limitation.

[0108] As an example, a first conductivity type emitter lead-out region 301 is provided above the emitter region 30. The emitter lead-out region 301 is heavily P-type doped, which is beneficial for reducing the contact resistance between the emitter 1001 and the emitter region 30. A first conductivity type substrate lead-out region 101 is provided on the upper surface of the substrate 10. The substrate lead-out region 101 is located outside the base lead-out region 201 and is isolated from the base lead-out region 201. The doping concentration of the substrate lead-out region 101 is greater than the doping concentration of the substrate 10. The substrate lead-out region 101 is heavily P-type doped, which is beneficial for reducing the contact resistance between the substrate ground electrode 804 and the substrate 10.

[0109] It should be noted that the isolation layer 50 isolates adjacent region units such as the emitter region 301, the multiple discrete collector regions 40, the base region 201, and the substrate region 101.

[0110] As an example, the method also includes the steps of forming a first dielectric layer 60, a plurality of contact vias 70, a first metal interconnect layer 80, a second dielectric layer 90, and a second metal interconnect layer 100, including:

[0111] (i) A first dielectric layer 60 is formed on the substrate 10, the first dielectric layer 60 covering the emitter region 30, the base region 20 and the collector region 40;

[0112] As an example, the first dielectric layer 60 can be formed by chemical vapor deposition, physical vapor deposition or other suitable methods. The first dielectric layer 60 includes an oxide dielectric layer, which may be SiO2, Al2O3 or other suitable dielectric layers.

[0113] (ii) A plurality of contact vias 70 are formed in the first dielectric layer 60 in a vertical direction, and the bottom ends of the contact vias are respectively connected to the emitter region 30, the collector region 40, the base region 20 and the substrate 10.

[0114] As an example, the contact vias 70 are formed at predetermined positions in the first dielectric layer 60 through processes such as masking and etching. Among them, the bottom end of a portion of the contact vias 70 is connected to the emitter region 30 through the emitter region lead-out region 301, a portion of the contact vias 70 is connected to the base region 20 through the base region lead-out region 201, a portion of the contact vias 70 is connected to the substrate 10 through the substrate lead-out region 101, and a portion of the contact vias 70 is connected to the collector region 40.

[0115] (iii) A first metal interconnect layer 80 is formed above the first dielectric layer 60. The first metal interconnect layer 80 includes an emitter metal lead-out 801, a collector 802, a base 803, and a substrate ground electrode 804. The emitter metal lead-out 801 is connected to the emitter 30, the collector 802 is connected to the collector 40, the base 803 is connected to the base lead-out region 201, and the substrate ground electrode 804 is connected to the substrate 10.

[0116] As an example, the first metal interconnect layer 80 is formed by deposition, electroplating, sputtering or other suitable methods, and then the first metal interconnect layer 80 is etched by processes such as masking and etching to form an emitter metal lead-out 801, a collector 802, a base 803 and a substrate ground electrode 804. The emitter metal lead-out 801 is connected to the emitter lead-out region 301 through a contact via 70, the base 803 is connected to the base lead-out region 201 through the contact via 70, the collector 802 is connected to the collector region 40 through a contact via 70, and the substrate ground electrode 804 is connected to the substrate lead-out region 101 through a contact via 70.

[0117] As an example, the first metal interconnect layer 80 includes metal layers with good electrical conductivity such as copper, aluminum, nickel, gold, silver, and titanium.

[0118] (iv) A second dielectric layer 90 is formed above the first dielectric layer 60. The second dielectric layer 90 has a connection hole that penetrates the second dielectric layer 90 in a vertical direction. The bottom end of the connection hole is connected to the emitter metal lead-out 801.

[0119] As an example, a second dielectric layer 90 can be formed by chemical vapor deposition, physical vapor deposition or other suitable methods. The second dielectric layer 90 is an intermetallic dielectric layer, including a dielectric layer of oxide, nitride or other suitable material. Then, a connection hole is formed in a predetermined position in the second dielectric layer 90 by processes such as masking and etching.

[0120] (v) A second metal interconnect layer 100 is formed above the second dielectric layer 90. The second metal interconnect layer 100 includes an emitter 1001, which is connected to the top end of the connection hole.

[0121] As an example, the second metal interconnect layer 100 is formed by deposition, electroplating, sputtering or other suitable methods, and then the emitter 1001 is formed by processes such as masking and etching.

[0122] As an example, the second metal interconnect layer 100 includes metal layers with good electrical conductivity such as copper, aluminum, nickel, gold, silver, and titanium.

[0123] It should be noted that in some other embodiments, where the layout routing allows, the emitter metal lead-out can form an emitter, thus eliminating the need for the second dielectric layer and the second metal interconnect layer to form the emitter.

[0124] As an example, by setting up multiple collector regions 40 separately, and then connecting these units to different pins (different ports in the circuit) through subsequent collector-metal connections, it can meet the requirements of different amplification factors and can work simultaneously in multiple circuit environments.

[0125] Specifically, for bipolar junction transistors (BJTs), they are generally operated in the amplification region during use. In this region, charge carriers (holes in this embodiment) flow from the emitter (E) to the base (B). Some charge carriers pass through the B terminal and are collected at the collector (C). The flow of charge carriers from the E terminal to the C terminal is determined by the voltage across both terminals. Under a fixed voltage, due to the discrete connection of each unit at the C terminal, different total currents can be obtained at the C terminal, and correspondingly, the current at the B terminal will also change. For example, as... Figure 4 As shown, connecting all eight collector units to the output terminal to form collector terminal 401 results in the best current collection capability and the largest amplification factor. If only one collector unit is connected to the output terminal, the collector current decreases accordingly, and the amplification factor is minimized. Of course, each discrete collector unit can be connected to different ports via metal wires according to actual needs, such as... Figure 5 As shown, five collector units or three collector units can be connected to the output terminal to form different collector terminals 402 and 403, in order to meet the requirements of different amplification factors and achieve the desired effect. Figure 4 Different amplification factors are required. Of course, one, two, four, six, or seven collector units can also be connected to the output terminal to achieve different results, depending on actual needs. Figure 4 or Figure 5 The magnification factor.

[0126] In summary, the multi-element array bipolar transistor structure and fabrication method provided by this invention, by setting discrete collector regions, can achieve different amplification factors according to different connection methods, thereby improving the freedom of circuit design. Furthermore, by placing the emitter region at the center of the entire structure and symmetrically distributing the collector regions around it, the space utilization of the layout is improved. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0127] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A multi-element array bipolar transistor structure, characterized in that, include: First conductivity type substrate; A base region of the second conductivity type is located in the substrate; An emitter region of a first conductivity type is located in the base region; A second conductivity type base region lead-out area is located in the base region, and the base region lead-out area surrounds the emitter region and is spaced at a predetermined distance from the emitter region; Multiple collector regions of the first conductivity type are located on the upper surface of the base region, and the multiple collector regions are separately disposed between the emitter region and the base region lead-out region; In this process, different numbers of collector regions are connected to the circuit according to requirements to obtain different total currents at the collector terminals, thereby meeting the requirements of different amplification factors.

2. The multi-element array bipolar transistor structure according to claim 1, characterized in that: The base region includes a first base region and a second base region. The second base region is located above the first base region and protrudes from the upper surface of the base region. The doping concentration of the second base region is higher than that of the first base region.

3. The multi-element array bipolar transistor structure according to claim 1, characterized in that: The upper surface of the emitter region is provided with a first conductivity type emitter region lead-out region, and the doping concentration of the emitter region lead-out region is greater than the doping concentration of the emitter region; the upper surface of the substrate is provided with a first conductivity type substrate lead-out region, the substrate lead-out region is located outside the base region lead-out region and is isolated from the base region lead-out region, and the doping concentration of the substrate lead-out region is greater than the doping concentration of the substrate.

4. The multi-element array bipolar transistor structure according to claim 1, characterized in that, Also includes: A first dielectric layer is located above the substrate and covers the emitter region, the base region, and the collector region; Multiple contact vias penetrate the first dielectric layer in a vertical direction, and the bottom ends of the contact vias are respectively connected to the emitter region, the collector region, the base region and the substrate; A first metal interconnect layer, located above the first dielectric layer, includes an emitter metal lead-out, a collector, a base, and a substrate ground electrode. The emitter metal lead-out is connected to the emitter region, the collector is connected to the collector region, the base is connected to the base lead-out region, and the substrate ground electrode is connected to the substrate. A second dielectric layer is located above the first dielectric layer. The second dielectric layer has a connection hole that penetrates the second dielectric layer in a vertical direction. The bottom end of the connection hole is led out and connected to the metal of the emission area. A second metal interconnect layer, located above the second dielectric layer, includes an emitter connected to the top of the connection hole.

5. The multi-element array bipolar transistor structure according to claim 1, characterized in that: Multiple collector regions are symmetrically distributed around the emitter region.

6. A method for fabricating a multi-element array bipolar transistor structure, characterized in that, Includes the following steps: Provide a substrate of the first conductivity type; A base region of a second conductivity type is formed in the substrate; A first conductivity type emitter region is formed in the base region; A second conductivity type base region lead-out region is formed in the base region, and the base region lead-out region surrounds the emitter region and is spaced at a predetermined distance from the emitter region; Multiple collector regions of the first conductivity type are formed on the upper surface of the base region, and the multiple collector regions are separately disposed between the emitter region and the base region lead-out region; In this process, different numbers of collector regions are connected to the circuit according to requirements to obtain different total currents at the collector terminals, thereby meeting the requirements of different amplification factors.

7. The method for fabricating a multi-element array bipolar transistor structure according to claim 6, characterized in that, It also includes the following steps: A first dielectric layer is formed above the substrate, the first dielectric layer covering the emitter region, the base region and the collector region; A plurality of contact vias are formed in the first dielectric layer in a vertical direction, and the bottom ends of the contact vias are respectively connected to the emitter region, the collector region, the base region and the substrate; A first metal interconnect layer is formed above the first dielectric layer. The first metal interconnect layer includes an emitter metal lead-out, a collector, a base, and a substrate ground electrode. The emitter metal lead-out is connected to the emitter region, the collector is connected to the collector region, the base is connected to the base lead-out region, and the substrate ground electrode is connected to the substrate. A second dielectric layer is formed above the first dielectric layer. A connection hole is provided in the second dielectric layer in a vertical direction, and the bottom end of the connection hole is led out and connected to the metal of the emission area. A second metal interconnect layer is formed above the second dielectric layer, the second metal interconnect layer including an emitter connected to the top end of the connection hole.

8. The method for fabricating a multi-element array bipolar transistor structure according to claim 7, characterized in that: Before forming the first dielectric layer, the method further includes the steps of forming a first conductivity type emitter lead-out region on the upper surface of the emitter region and forming a first conductivity type substrate lead-out region on the upper surface of the substrate, wherein the doping concentration of the emitter lead-out region is greater than the doping concentration of the emitter region, the substrate lead-out region is located outside the base lead-out region and is isolated from the base lead-out region, and the doping concentration of the substrate lead-out region is greater than the doping concentration of the substrate.

9. The method for fabricating a multi-element array bipolar transistor structure according to claim 6, characterized in that: The base region includes a first base region and a second base region. The second base region is located above the first base region and protrudes from the upper surface of the base region. The doping concentration of the second base region is higher than that of the first base region.

10. The method for fabricating a multi-element array bipolar transistor structure according to claim 6, characterized in that: Multiple collector regions are symmetrically distributed around the emitter region.

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