A low-power under-voltage release based on high-end NMOS drive

Abstract

The application belongs to the technical field of low-voltage electrical apparatus, and particularly provides a low-power under-voltage release based on high-end NMOS driving, which comprises a surge absorption circuit, a rectification circuit, a DC / DC circuit, a voltage detection and release driving circuit, a starting time control circuit, a starting current control circuit, a release control circuit and a release coil; the rectification circuit is connected with the surge absorption circuit, the DC / DC circuit and the starting current control circuit respectively; the DC / DC circuit is further connected with the voltage detection and release driving circuit and the starting time control circuit respectively; the voltage detection and release driving circuit is further connected with the release control circuit; the release control circuit, the starting time control circuit and the starting current control circuit are sequentially connected; and the release control circuit and the starting current control circuit are both connected with the release coil. The low-power under-voltage release based on high-end NMOS driving has the advantages of low power consumption, long service life, stable action voltage and the like.

Description

Technical Field

[0001] This invention relates to the field of low-voltage electrical equipment technology, and more specifically, to a low-power undervoltage release device based on high-end NMOS drive. Background Technology

[0002] Traditional circuit breaker undervoltage release mechanisms typically employ an electromagnet structure. The electromagnet's core is pushed out by a spring, and the electromagnetic force generated when the coil is energized is opposite to the spring force. When the voltage exceeds 70% of the rated voltage, the electromagnetic force is greater than the spring force, drawing the core into the electromagnet and allowing the circuit breaker to close normally. When the voltage is less than 35% of the rated voltage, the electromagnetic force is less than the spring force, pushing the core out and triggering the traction rod to trip the circuit breaker, thus achieving the undervoltage protection function.

[0003] The undervoltage release device based on the above technology has the following disadvantages:

[0004] 1. The coil consumes a lot of power when powered by mains for a long time;

[0005] 2. It generates a lot of heat, resulting in a high failure rate in high-temperature environments;

[0006] 3. The operating voltage has large dispersion, and it takes a long time to adjust the operating voltage during the production process;

[0007] 4. Near the coil's zero-point of operation, the electromagnetic force and spring force are roughly equal, making the product prone to tripping when subjected to vibration. Summary of the Invention

[0008] The purpose of this invention is to provide a low-power undervoltage release device based on high-end NMOS drive, so as to solve the problems of high power consumption, high heat generation and instability of existing undervoltage release devices in the background art, which cannot meet the user requirements in some high temperature or vibration environments.

[0009] As a first aspect of the present invention, a low-power undervoltage release device based on high-end NMOS drive is provided, comprising a surge absorption circuit, a rectification circuit, a DC / DC circuit, a voltage detection and tripping drive circuit, a start-up time control circuit, a start-up current control circuit, a tripping control circuit, and a tripping coil. The rectification circuit is connected to the surge absorption circuit, the DC / DC circuit, and the start-up current control circuit respectively. The DC / DC circuit is also connected to the voltage detection and tripping drive circuit and the start-up time control circuit respectively. The voltage detection and tripping drive circuit is also connected to the tripping control circuit. The tripping control circuit, the start-up time control circuit, and the start-up current control circuit are connected in sequence. Both the tripping control circuit and the start-up current control circuit are connected to the tripping coil.

[0010] The startup current control circuit includes a third MOSFET Q3, a sixteenth resistor R16, a seventeenth resistor R17, a first Zener diode ZD4, an optocoupler PC1, and a twenty-second resistor R22. The gate of the third MOSFET Q3 is connected to one end of the seventeenth resistor R17, one end of the first Zener diode ZD4, and the collector of the phototransistor in the optocoupler PC1. The other end of the seventeenth resistor R17 is connected to one end of the sixteenth resistor R16, and the other end of the sixteenth resistor R16 is connected to the drain of the third MOSFET Q3. The drain of Q3 is also connected to the positive output terminal HV+ of the rectifier circuit. The source of the third MOSFET Q3 is connected to the other end of the first Zener diode ZD4, the emitter of the phototransistor of the optocoupler PC1, the trip control circuit, and the trip coil. The positive terminal of the LED of the optocoupler PC1 is connected to one end of the 22nd resistor R22, and the negative terminal of the LED of the optocoupler PC1 is connected to the other end of the 22nd resistor R22. One end of the 22nd resistor R22 is also grounded, and the other end of the 22nd resistor R22 is also connected to the start-up time control circuit.

[0011] Furthermore, the surge absorption circuit includes a first resistor RF1, a varistor RV1, and a second resistor RF2. One end of the first resistor RF1 is connected to the mains power, and the other end is connected to one end of the varistor RV1. The other end of the varistor RV1 is connected to one end of the second resistor RF2, and the other end of the second resistor RF2 is connected to the mains power.

[0012] Furthermore, the rectifier circuit includes a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, and an eighth diode D8. The anode of the first diode D1 is connected to the cathode of the second diode D2, the other end of the first resistor RF1, and one end of the varistor RV1. The cathode of the fourth diode D4 is connected to the anode of the third diode D3, one end of the second resistor RF2, and the other end of the varistor RV1. The anode of the eighth diode D8 is connected to the cathode of the first diode D1 and the cathode of the third diode D3.

[0013] Further, the DC / DC circuit includes a first capacitor C1, a power supply chip U1, a second capacitor C2, a fourth resistor R4, a third resistor R3, a third capacitor C3, a fifth diode D5, an inductor L1, a sixth diode D6, a fourth capacitor C4, and a fifth capacitor C5. The positive terminal of the first capacitor C1 is connected to the negative terminal of the eighth diode D8 and the fourth pin of the power supply chip U1. The negative terminal of the first capacitor C1, the positive terminal of the second diode D2, the positive terminal of the fourth diode D4, the positive terminal of the fifth diode D5, the negative terminal of the fourth capacitor C4, and one end of the fifth capacitor C5 are all connected and grounded. The first pin of the power supply chip U1 is connected to one end of the second capacitor C2. The second pin of the power chip U1 is connected to one end of the third resistor R3 and one end of the fourth resistor R4, respectively; the other end of the third resistor R3 is connected to the positive terminal of the third capacitor C3 and the negative terminal of the sixth diode D6, respectively; the fifth, sixth, seventh and eighth pins of the power chip U1 are all connected to the other end of the second capacitor C2, and the other end of the second capacitor C2 is also connected to the other end of the fourth resistor R4, the negative terminal of the third capacitor C3, the negative terminal of the fifth diode D5 and one end of the inductor L1, respectively; the other end of the inductor L1 is connected to the positive terminal of the fourth capacitor C4, the positive terminal of the sixth diode D6 and the other end of the fifth capacitor C5, respectively.

[0014] Furthermore, the voltage detection and tripping drive circuit includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a thirteenth resistor R13, a sixth capacitor C6, a second Zener diode ZD5, a ninth capacitor C9, and a first operational amplifier U2A; the start-up time control circuit includes a fourteenth resistor R14, an eighteenth resistor R18, a nineteenth resistor R19, a twentieth resistor R20, a twenty-first resistor R21, a seventh capacitor C7, a tenth capacitor C10, and a second operational amplifier U2B.

[0015] In this configuration, one end of the fifth resistor R5, the sixth resistor R6, and the seventh resistor R7 are connected sequentially. The other end of the seventh resistor R7 is connected to one end of the sixth capacitor C6, one end of the thirteenth resistor R13, the cathode of the second Zener diode ZD5, one end of the ninth capacitor C9, one end of the tenth resistor R10, and the non-inverting input of the first operational amplifier U2A. The other end of the sixth capacitor C6 is connected to the other end of the thirteenth resistor R13 and the anode of the second Zener diode ZD5, and is also grounded. The other end of the ninth capacitor C9 is connected to one end of the eighth resistor R8, one end of the ninth resistor R9, and the inverting input of the first operational amplifier U2A, and is also grounded. The output terminal of operational amplifier U2A is connected to the other end of the tenth resistor R10 and one end of the fourteenth resistor R14, respectively; the other end of the fourteenth resistor R14 is connected to one end of the eighteenth resistor R18, one end of the seventh capacitor C7, one end of the tenth capacitor C10, and the non-inverting input terminal of the second operational amplifier U2B, respectively; the other end of the eighteenth resistor R18 is connected to the other end of the seventh capacitor C7, and the other end of the eighteenth resistor R18 is also grounded; the other end of the tenth capacitor C10 is connected to one end of the nineteenth resistor R19, one end of the twentieth resistor R20, and the inverting input terminal of the second operational amplifier U2B, and the other end of the twentieth resistor R20 is grounded; the output terminal of the second operational amplifier U2B is connected to one end of the twenty-first resistor R21.

[0016] Furthermore, the trip control circuit includes a ninth diode D9, a seventh diode D7, a second MOSFET Q2, an eighth capacitor C8, an eleventh resistor R11, and a twelfth resistor R12, and the trip coil includes an undervoltage trip coil.

[0017] The source of the third MOSFET Q3 is connected to the cathode of the ninth diode D9, the cathode of the seventh diode D7, and one end of the undervoltage release coil. The other end of the twelfth resistor R22 is connected to the other end of the twelfth resistor R21. The anode of the ninth diode D9 is connected to the power supply voltage VP. The anode of the seventh diode D7 is connected to the other end of the undervoltage release coil and the drain of the second MOSFET Q2. The gate of the second MOSFET Q2 is connected to one end of the eleventh resistor R11, one end of the twelfth resistor R12, and one end of the eighth capacitor C8. The source of the second MOSFET Q2, the other end of the twelfth resistor R12, and the other end of the eighth capacitor C8 are connected and grounded. The other end of the eleventh resistor R11 is connected to the output terminal of the first operational amplifier U2A.

[0018] The low-power undervoltage release device based on high-end NMOS drive provided by this invention has the following advantages:

[0019] (1) Low power consumption: a large current is used to attract the coil at the moment of power-on, and a low voltage and small current are used to maintain it thereafter.

[0020] (2) Long lifespan: The coil mainly operates in the low voltage and low current maintenance stage, with low heat generation and low temperature rise, which greatly extends the lifespan of the coil.

[0021] (3) The operating voltage is stable. The operational amplifier is used to compare the power supply voltage and control the coil, and the consistency is excellent.

[0022] (4) High stability; near the zero point of coil operation, the electromagnetic force is much greater than the spring force.

[0023] (5) The startup current uses optocoupler isolation to drive high-end NMOS technology, which is low in cost and high in stability. Attached Figure Description

[0024] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the following detailed description to explain the invention, but do not constitute a limitation thereof.

[0025] Figure 1 The schematic diagram of the low-power undervoltage release device based on high-end NMOS drive provided by the present invention.

[0026] Figure 2 The circuit structure diagram of the low-power undervoltage release device based on high-end NMOS drive provided by the present invention is shown.

[0027] Figure 3 The circuit structure diagram of the surge absorption circuit and rectifier circuit provided by the present invention.

[0028] Figure 4 The circuit structure diagram of the DC / DC loop provided by the present invention.

[0029] Figure 5 The circuit structure diagram of the voltage detection and tripping drive circuit provided by the present invention.

[0030] Figure 6 The circuit structure diagram of the start-up time control circuit, start-up current control circuit, trip control circuit, and trip coil provided by the present invention. Detailed Implementation

[0031] To further illustrate the technical means and effects adopted by the present invention to achieve its intended purpose, the following, in conjunction with the accompanying drawings and preferred embodiments, details the specific implementation, structure, features, and effects of the low-power undervoltage release device based on high-end NMOS drive proposed according to the present invention. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the protection scope of the present invention.

[0032] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0033] In explaining this invention, it should be noted that the terms "installation," "connection," and "linking" should be interpreted broadly unless otherwise specified. For example, a connection can be a fixed connection, a connection through a special interface, or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0034] This embodiment provides a low-power undervoltage release device based on high-side NMOS drive, such as... Figures 1-2As shown, the low-power undervoltage release based on high-end NMOS drive includes a surge absorption circuit, a rectification circuit, a DC / DC circuit, a voltage detection and tripping drive circuit, a start-up time control circuit, a start-up current control circuit, a tripping control circuit, and a tripping coil. The rectification circuit is connected to the surge absorption circuit, the DC / DC circuit, and the start-up current control circuit. The DC / DC circuit is also connected to the voltage detection and tripping drive circuit and the start-up time control circuit. The voltage detection and tripping drive circuit is also connected to the tripping control circuit. The tripping control circuit, the start-up time control circuit, and the start-up current control circuit are connected sequentially. Both the tripping control circuit and the start-up current control circuit are connected to the tripping coil. The start-up current control circuit includes a third MOS transistor Q3, a sixteenth resistor R16, a seventeenth resistor R17, a first Zener diode ZD4, an optocoupler PC1, and a twenty-second resistor R22. The gates of the three MOSFETs Q3 are connected to one end of the seventeenth resistor R17, one end of the first Zener diode ZD4, and the collector of the phototransistor in the optocoupler PC1. The other end of the seventeenth resistor R17 is connected to one end of the sixteenth resistor R16, and the other end of the sixteenth resistor R16 is connected to the drain of the third MOSFET Q3. The drain of the MOSFET Q3 is also connected to the positive output terminal HV+ of the rectifier circuit. The source of the third MOSFET Q3 is connected to the other end of the first Zener diode ZD4, the emitter of the phototransistor in the optocoupler PC1, the trip control circuit, and the trip coil. The anode of the LED in the optocoupler PC1 is connected to one end of the twenty-second resistor R22, and the cathode of the LED in the optocoupler PC1 is connected to the other end of the twenty-second resistor R22. One end of the twenty-second resistor R22 is also grounded, and the other end of the twenty-second resistor R22 is also connected to the start-up time control circuit.

[0035] Preferably, such as Figure 3 As shown, the surge absorption circuit includes a first resistor RF1, a varistor RV1, and a second resistor RF2. One end of the first resistor RF1 is connected to the mains power, and the other end is connected to one end of the varistor RV1. The other end of the varistor RV1 is connected to one end of the second resistor RF2, and the other end of the second resistor RF2 is connected to the mains power. When an external surge voltage is input, the varistor RV1 short-circuits, generating a surge current. This surge current flows through resistors RF1 and RF2, creating a voltage drop that significantly reduces the surge voltage reaching subsequent stages, thus protecting the downstream circuitry.

[0036] Preferably, such as Figure 3As shown, the rectifier circuit includes a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, and an eighth diode D8. The anode of the first diode D1 is connected to the cathode of the second diode D2, the other end of the first resistor RF1, and one end of the varistor RV1. The cathode of the fourth diode D4 is connected to the anode of the third diode D3, one end of the second resistor RF2, and the other end of the varistor RV1. The anode of the eighth diode D8 is connected to the cathodes of the first diode D1 and the third diode D3. Diodes D1 to D4 form a rectifier bridge, rectifying the input AC voltage into DC voltage for use by subsequent circuits. The eighth diode D8 is a reverse-charging protection diode to prevent the voltage across C1 from being pulled low during the high-current startup phase, which could lead to insufficient power supply to U1 and system instability.

[0037] Preferably, such as Figure 4 As shown, the DC / DC circuit includes a first capacitor C1, a power supply chip U1, a second capacitor C2, a fourth resistor R4, a third resistor R3, a third capacitor C3, a fifth diode D5, an inductor L1, a sixth diode D6, a fourth capacitor C4, and a fifth capacitor C5. The positive terminal of the first capacitor C1 is connected to the negative terminal of the eighth diode D8 and the fourth pin of the power supply chip U1. The negative terminal of the first capacitor C1, the positive terminal of the second diode D2, the positive terminal of the fourth diode D4, the positive terminal of the fifth diode D5, the negative terminal of the fourth capacitor C4, and one end of the fifth capacitor C5 are all connected and grounded. The first pin of the power supply chip U1 is connected to one end of the second capacitor C2. The second pin of the power chip U1 is connected to one end of the third resistor R3 and one end of the fourth resistor R4, respectively; the other end of the third resistor R3 is connected to the positive terminal of the third capacitor C3 and the negative terminal of the sixth diode D6, respectively; the fifth, sixth, seventh, and eighth pins of the power chip U1 are all connected to the other end of the second capacitor C2, and the other end of the second capacitor C2 is also connected to the other end of the fourth resistor R4, the negative terminal of the third capacitor C3, the negative terminal of the fifth diode D5, and one end of the inductor L1, respectively; the other end of the inductor L1 is connected to the positive terminal of the fourth capacitor C4, the positive terminal of the sixth diode D6, and the other end of the fifth capacitor C5, respectively. The DC / DC circuit converts the input high-voltage DC voltage into a 24V low-voltage DC voltage through PWM technology to power the operational amplifiers U2A and U2B and the undervoltage release coil.

[0038] Preferably, such as Figures 5-6As shown, the voltage detection and tripping drive circuit includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a thirteenth resistor R13, a sixth capacitor C6, a second Zener diode ZD5, a ninth capacitor C9, and a first operational amplifier U2A. The start-up time control circuit includes a fourteenth resistor R14, an eighteenth resistor R18, a nineteenth resistor R19, a twentieth resistor R20, a twenty-first resistor R21, a seventh capacitor C7, a tenth capacitor C10, and a second operational amplifier U2A. 2B; wherein, one end of the fifth resistor R5, the sixth resistor R6, and the seventh resistor R7 are connected in sequence, and the other end of the seventh resistor R7 is connected to one end of the sixth capacitor C6, one end of the thirteenth resistor R13, the negative terminal of the second Zener diode ZD5, one end of the ninth capacitor C9, one end of the tenth resistor R10, and the non-inverting input terminal of the first operational amplifier U2A; the other end of the sixth capacitor C6 is connected to the other end of the thirteenth resistor R13 and the positive terminal of the second Zener diode ZD5. Meanwhile, the other end of the sixth capacitor C6 is grounded; the other end of the ninth capacitor C9 is connected to one end of the eighth resistor R8, one end of the ninth resistor R9, and the inverting input of the first operational amplifier U2A, and the other end of the ninth resistor R9 is grounded; the output of the first operational amplifier U2A is connected to the other end of the tenth resistor R10 and one end of the fourteenth resistor R14; the other end of the fourteenth resistor R14 is connected to one end of the eighteenth resistor R18, one end of the seventh capacitor C7, one end of the tenth capacitor C10, and the non-inverting input of the second operational amplifier U2B; the other end of the eighteenth resistor R18 is connected to the other end of the seventh capacitor C7, and the other end of the eighteenth resistor R18 is also grounded; the other end of the tenth capacitor C10 is connected to one end of the nineteenth resistor R19, one end of the twentieth resistor R20, and the inverting input of the second operational amplifier U2B, and the other end of the twentieth resistor R20 is grounded; the output of the second operational amplifier U2B is connected to one end of the twentieth resistor R21.

[0039] Preferably, such as Figures 5-6As shown, the trip control circuit includes a ninth diode D9, a seventh diode D7, a second MOSFET Q2, an eighth capacitor C8, an eleventh resistor R11, and a twelfth resistor R12. The trip coil includes an undervoltage trip coil. The source of the third MOSFET Q3 is connected to the cathode of the ninth diode D9, the cathode of the seventh diode D7, and one end of the undervoltage trip coil. The other end of the twelfth resistor R22 is connected to the other end of the eleventh resistor R21. The anode of the ninth diode D9 is connected to the power supply voltage VP. The anode of the seventh diode D7 is connected to the other end of the undervoltage trip coil and the drain of the second MOSFET Q2. The gate of the second MOSFET Q2 is connected to one end of the eleventh resistor R11, one end of the twelfth resistor R12, and one end of the eighth capacitor C8. The source of the second MOSFET Q2, the other end of the twelfth resistor R12, and the other end of the eighth capacitor C8 are connected and grounded. The other end of the eleventh resistor R11 is connected to the output terminal of the first operational amplifier U2A.

[0040] Specifically, the trip coil has a typical electromagnet structure, with the iron core of the electromagnet pushed out by a spring. The electromagnetic force generated by the trip coil after it is energized is opposite to the spring force.

[0041] The low-power undervoltage release device based on high-end NMOS drive provided by this invention operates on the following principle:

[0042] (1) Resistors R5~R7 and R13 sample the power supply voltage. Operational amplifier U2A (LM258) compares the sampled voltage. When the sampled voltage is greater than 70% of the rated voltage, operational amplifier U2A outputs a high level, controlling MOSFET Q2 to conduct, energizing the undervoltage release coil, pulling the iron core back, and allowing the circuit breaker to close. When the sampled voltage is less than 35% of the rated voltage, operational amplifier U2A outputs a low level, MOSFET Q2 is turned off, the undervoltage release coil is de-energized, the iron core pops out, and pushes the traction rod to open the circuit breaker.

[0043] (2) In the initial stage of system power-on, the voltage at the positive input terminal of op-amp U2B is lower than the voltage at the negative input terminal, op-amp U2B outputs a low level, optocoupler PC1 is cut off, and MOSFET Q3 is turned on. When op-amp U2A outputs a high level, MOSFET Q2 is turned on and charges capacitor C7 through resistor R14. After a period of charging, when the voltage on capacitor C7 is higher than the reference voltage of op-amp U2B, op-amp U2B outputs a high level, optocoupler PC1 is turned on, the gate voltage of MOSFET Q3 is pulled low, MOSFET Q3 is turned off, and the startup current is turned off. After that, the undervoltage release coil is powered by VP (DC 24V) through diode D9 and enters a low power consumption state.

[0044] (3) Resistors R16 and R17 provide bias voltage to MOSFET Q3, and Zener diode ZD4 clamps the gate voltage of MOSFET Q3 within a safe range. When optocoupler PC1 is turned on, the gate voltage of MOSFET Q3 is pulled low, and MOSFET Q3 is turned off; when optocoupler PC1 is turned off, the gate of MOSFET Q3 is energized, and MOSFET Q3 is turned on. The high voltage after mains rectification is directly applied to the undervoltage trip coil, generating a large current that causes the iron core to be attracted.

[0045] (4) When the gate of MOSFET Q2 is low, MOSFET Q2 is cut off, the undervoltage release coil is de-energized, and the iron core pops out under the action of the spring, pushing the traction rod to open the circuit breaker. After the starting current is turned off, the low-voltage DC power after the DC / DC circuit conversion supplies power to the undervoltage release coil through diode D9. When MOSFETs Q2 and Q3 are turned off, the current on the undervoltage release coil cannot change abruptly. Diode D7 provides a freewheeling circuit to prevent high voltage from being generated across the undervoltage release coil, which could cause other components to break down.

[0046] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A low-power undervoltage release device based on high-end NMOS drive, characterized in that, The circuit includes a surge absorption circuit, a rectification circuit, a DC / DC circuit, a voltage detection and tripping drive circuit, a start-up time control circuit, a start-up current control circuit, a tripping control circuit, and a tripping coil. The rectification circuit is connected to the surge absorption circuit, the DC / DC circuit, and the start-up current control circuit. The DC / DC circuit is also connected to the voltage detection and tripping drive circuit and the start-up time control circuit. The voltage detection and tripping drive circuit is also connected to the tripping control circuit. The tripping control circuit, the start-up time control circuit, and the start-up current control circuit are connected in sequence. Both the tripping control circuit and the start-up current control circuit are connected to the tripping coil. The startup current control circuit includes a third MOSFET Q3, a sixteenth resistor R16, a seventeenth resistor R17, a first Zener diode ZD4, an optocoupler PC1, and a twenty-second resistor R22. The gate of the third MOSFET Q3 is connected to one end of the seventeenth resistor R17, one end of the first Zener diode ZD4, and the collector of the phototransistor in the optocoupler PC1. The other end of the seventeenth resistor R17 is connected to one end of the sixteenth resistor R16, and the other end of the sixteenth resistor R16 is connected to the drain of the third MOSFET Q3. The drain of Q3 is also connected to the positive output terminal HV+ of the rectifier circuit. The source of the third MOSFET Q3 is connected to the other end of the first Zener diode ZD4, the emitter of the phototransistor of the optocoupler PC1, the trip control circuit, and the trip coil. The positive terminal of the LED of the optocoupler PC1 is connected to one end of the 22nd resistor R22, and the negative terminal of the LED of the optocoupler PC1 is connected to the other end of the 22nd resistor R22. One end of the 22nd resistor R22 is also grounded, and the other end of the 22nd resistor R22 is also connected to the start-up time control circuit.

2. The low-power undervoltage release device based on high-end NMOS drive according to claim 1, characterized in that, The surge absorption circuit includes a first resistor RF1, a varistor RV1, and a second resistor RF2. One end of the first resistor RF1 is connected to the mains power, and the other end is connected to one end of the varistor RV1. The other end of the varistor RV1 is connected to one end of the second resistor RF2, and the other end of the second resistor RF2 is connected to the mains power.

3. A low-power undervoltage release device based on high-end NMOS drive according to claim 2, characterized in that, The rectifier circuit includes a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, and an eighth diode D8. The anode of the first diode D1 is connected to the cathode of the second diode D2, the other end of the first resistor RF1, and one end of the varistor RV1. The cathode of the fourth diode D4 is connected to the anode of the third diode D3, one end of the second resistor RF2, and the other end of the varistor RV1. The anode of the eighth diode D8 is connected to the cathode of the first diode D1 and the cathode of the third diode D3.

4. A low-power undervoltage release device based on high-end NMOS drive according to claim 3, characterized in that, The DC / DC circuit includes a first capacitor C1, a power supply chip U1, a second capacitor C2, a fourth resistor R4, a third resistor R3, a third capacitor C3, a fifth diode D5, an inductor L1, a sixth diode D6, a fourth capacitor C4, and a fifth capacitor C5. The positive terminal of the first capacitor C1 is connected to the negative terminal of the eighth diode D8 and the fourth pin of the power supply chip U1. The negative terminal of the first capacitor C1, the positive terminal of the second diode D2, the positive terminal of the fourth diode D4, the positive terminal of the fifth diode D5, the negative terminal of the fourth capacitor C4, and one end of the fifth capacitor C5 are all connected and grounded. The first pin of the power supply chip U1 is connected to one end of the second capacitor C2. The second pin of the power chip U1 is connected to one end of the third resistor R3 and one end of the fourth resistor R4, respectively; the other end of the third resistor R3 is connected to the positive terminal of the third capacitor C3 and the negative terminal of the sixth diode D6, respectively; the fifth, sixth, seventh and eighth pins of the power chip U1 are all connected to the other end of the second capacitor C2, and the other end of the second capacitor C2 is also connected to the other end of the fourth resistor R4, the negative terminal of the third capacitor C3, the negative terminal of the fifth diode D5 and one end of the inductor L1, respectively; the other end of the inductor L1 is connected to the positive terminal of the fourth capacitor C4, the positive terminal of the sixth diode D6 and the other end of the fifth capacitor C5, respectively.

5. A low-power undervoltage release device based on high-end NMOS drive according to claim 1, characterized in that, The voltage detection and tripping drive circuit includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a thirteenth resistor R13, a sixth capacitor C6, a second Zener diode ZD5, a ninth capacitor C9, and a first operational amplifier U2A. The start-up time control circuit includes a fourteenth resistor R14, an eighteenth resistor R18, a nineteenth resistor R19, a twentieth resistor R20, a twenty-first resistor R21, a seventh capacitor C7, a tenth capacitor C10, and a second operational amplifier U2B. In this configuration, one end of the fifth resistor R5, the sixth resistor R6, and the seventh resistor R7 are connected sequentially. The other end of the seventh resistor R7 is connected to one end of the sixth capacitor C6, one end of the thirteenth resistor R13, the cathode of the second Zener diode ZD5, one end of the ninth capacitor C9, one end of the tenth resistor R10, and the non-inverting input of the first operational amplifier U2A. The other end of the sixth capacitor C6 is connected to the other end of the thirteenth resistor R13 and the anode of the second Zener diode ZD5, and is also grounded. The other end of the ninth capacitor C9 is connected to one end of the eighth resistor R8, one end of the ninth resistor R9, and the inverting input of the first operational amplifier U2A, and is also grounded. The output terminal of operational amplifier U2A is connected to the other end of the tenth resistor R10 and one end of the fourteenth resistor R14, respectively; the other end of the fourteenth resistor R14 is connected to one end of the eighteenth resistor R18, one end of the seventh capacitor C7, one end of the tenth capacitor C10, and the non-inverting input terminal of the second operational amplifier U2B, respectively; the other end of the eighteenth resistor R18 is connected to the other end of the seventh capacitor C7, and the other end of the eighteenth resistor R18 is also grounded; the other end of the tenth capacitor C10 is connected to one end of the nineteenth resistor R19, one end of the twentieth resistor R20, and the inverting input terminal of the second operational amplifier U2B, and the other end of the twentieth resistor R20 is grounded; the output terminal of the second operational amplifier U2B is connected to one end of the twenty-first resistor R21.

6. A low-power undervoltage release device based on high-end NMOS drive according to claim 5, characterized in that, The trip control circuit includes a ninth diode D9, a seventh diode D7, a second MOSFET Q2, an eighth capacitor C8, an eleventh resistor R11, and a twelfth resistor R12. The trip coil includes an undervoltage trip coil. The source of the third MOSFET Q3 is connected to the cathode of the ninth diode D9, the cathode of the seventh diode D7, and one end of the undervoltage release coil. The other end of the twelfth resistor R22 is connected to the other end of the twelfth resistor R21. The anode of the ninth diode D9 is connected to the power supply voltage VP. The anode of the seventh diode D7 is connected to the other end of the undervoltage release coil and the drain of the second MOSFET Q2. The gate of the second MOSFET Q2 is connected to one end of the eleventh resistor R11, one end of the twelfth resistor R12, and one end of the eighth capacitor C8. The source of the second MOSFET Q2, the other end of the twelfth resistor R12, and the other end of the eighth capacitor C8 are connected and grounded. The other end of the eleventh resistor R11 is connected to the output terminal of the first operational amplifier U2A.

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