PFC circuit and its control method, power conversion device

Abstract

The present invention provides a control method for a PFC circuit. The PFC circuit includes a diode bridge arm, a DNPC bridge arm, and a capacitor bank connected in parallel. The method includes: when modulating the positive half-cycle of the modulation wave, within one switching period, causing the PFC circuit to switch between the +2 mode and the +0 mode via the +1 mode; and when modulating the negative half-cycle of the modulation wave, within one switching period, causing the PFC circuit to switch between the -2 mode and the -0 mode via the -1 mode. Among them, the durations of the +1 mode and the -1 mode are as short as possible to reduce the current flowing into or out of the midpoint of the capacitor bank, thereby reducing the voltage fluctuation at the midpoint. The present invention also provides a PFC circuit using the above control method and a power conversion device having the PFC circuit.

Description

Technical Field

[0001] The present application relates to voltage modulation technology. Specifically, the present application relates to a voltage modulation strategy based on quasi-two-levels, a PFC circuit using this modulation strategy, and a power conversion device having this PFC circuit. Background Art

[0002] With the progress of distributed new energy power generation technology and the increasing number of DC electrical equipment, the demand for low-voltage DC power distribution is rising. In traditional solutions, a power frequency transformer is usually first used to convert medium-voltage alternating current (MVAC) into low-voltage alternating current, and then an AC / DC converter is used to convert the low-voltage alternating current into low-voltage direct current (LVDC). A Power Electronic Transformer (PET) is a power conversion device that uses a high-frequency isolation circuit to achieve the power conversion from medium-voltage alternating current to low-voltage direct current. Compared with the traditional solution based on a power frequency transformer, it has higher power density and efficiency.

[0003] In existing PETs, it usually includes two-stage circuits. The front-stage circuit uses cascaded AC / DC converters to convert the input medium-voltage alternating current into multiple intermediate direct currents, usually called the CHB structure; the rear-stage circuit uses DC / DC converters to convert the intermediate direct current into low-voltage direct current and perform high-frequency isolation. The low-voltage DC output terminals of multiple DC / DC converters are connected in parallel. Each pair of AC / DC converters and DC / DC converters constitutes a modular power electronic conversion unit. However, each power electronic conversion unit requires corresponding medium-voltage isolation transformers, insulators, mechanical components, optical fiber connectors, etc. The more the number of units, the higher the complexity and cost of the system. Due to the low voltage withstand level of currently commercial semiconductor devices, a three-level topology can be selected for the power electronic conversion unit to increase the intermediate DC voltage level (>1.5 kV), thereby reducing the number of cascaded units.

[0004] The three-level AC / DC converter topology is widely used in various application fields. Among them, the bidirectional five-level circuit composed of two DNPC bridge arms is widely used, such as Figure 1 shown. This topology is composed of 8 switching tubes and 4 clamping diodes. This bidirectional topology is symmetric, has flexible control, and can operate in four quadrants, but has a large number of devices and high cost. For unidirectional power flow application scenarios such as data centers, it is more appropriate to use a unidirectional AC / DC topology to form a PET system.

[0005] The prior art has proposed a bridge-less DNPC three-level topology, such as Figure 2As shown, its left bridge arm is a diode half-bridge, and its right bridge arm is a DNPC bridge arm. This topology consists of 4 switching tubes S1 to S4, 2 clamping diodes Dp and Dn, and 2 industrial-frequency rectifier diodes D1 and D2. The main advantages of this topology are that the number of devices is small, the cost is low, and the current flows through only 3 devices at any given time. Therefore, the conduction loss is small and the efficiency is high.

[0006] However, using traditional modulation methods, the above-mentioned bridge-less DNPC three-level topology generally operates in six modes (+2 mode, +1 mode, +0 mode, -2 mode, -1 mode, and -0 mode), and can only switch between two adjacent modes within each switching period. For example, it can switch between the +2 mode and the +1 mode, or between the +1 mode and the +0 mode. Therefore, the existing modulation methods result in fluctuations in the midpoint potential of the DC-link capacitor with a power-frequency period, and the amplitude of the fluctuations is relatively large. When the value of the DC-Link capacitor is 1.5 mF, the voltage fluctuation at the midpoint of the DC-bus capacitor can reach 30 V. This is because in the positive half power-frequency period of the modulation wave, the +1 mode is always involved in the modulation, that is, the current always flows into the midpoint when the +1 mode is active, and in the negative half power-frequency period of the modulation wave, the -1 mode is always involved in the modulation, that is, the current always flows out of the midpoint when the -1 mode is active. Due to the limited voltage stress of the switching tubes, the voltage fluctuations of the upper and lower capacitors should not be too large. Therefore, a larger DC-Link capacitor is required to absorb the second-harmonic fluctuations at the midpoint, resulting in a higher requirement for the capacitance value of the DC-Link in the prior art, higher cost, and larger volume.

[0007] Therefore, for the above-mentioned bridge-less DNPC three-level topology, an improved voltage modulation strategy is needed to reduce the voltage fluctuation at the midpoint of the DC bus. Summary of the Invention

[0008] The purpose of this application is to solve the problem of large midpoint voltage fluctuations when using the bridge-less DNPC three-level topology for voltage modulation.

[0009] To solve the above problems, according to one aspect of this application, a control method for a PFC circuit is proposed. The PFC circuit includes a diode bridge arm, a DNPC bridge arm, and a capacitor bank connected in parallel. The DNPC bridge arm includes a first switching tube, a second switching tube, a third switching tube, and a fourth switching tube connected in series, as well as a clamping diode branch. One end of the clamping diode branch is connected to the connection point of the first switching tube and the second switching tube, and the other end is connected to the connection point of the third switching tube and the fourth switching tube. The midpoint of the clamping diode branch is connected to the midpoint of the capacitor bank;

[0010] The control method includes the following steps:

[0011] When modulating the positive half - cycle of the modulation wave, within one switching period, the PFC circuit is switched between the +2 mode and the +0 mode via the +1 mode, and

[0012] When modulating the negative half - cycle of the modulation wave, within one switching period, the PFC circuit is switched between the -2 mode and the -0 mode via the -1 mode, where

[0013] During the positive half - cycle of the modulation wave, the input current of the PFC circuit flows into the mid - point of the DNPC bridge arm. In the +2 mode, only the first switch and the second switch in the DNPC bridge arm are turned on. In the +1 mode, only the third switch in the DNPC bridge arm is turned on. And in the +0 mode, only the third switch and the fourth switch in the DNPC bridge arm are turned on, and

[0014] During the negative half - cycle of the modulation wave, the input current flows out from the mid - point of the DNPC bridge arm. In the -2 mode, only the third switch and the fourth switch in the DNPC bridge arm are turned on. In the -1 mode, only the second switch in the DNPC bridge arm is turned on. And in the -0 mode, only the first switch and the second switch in the DNPC bridge arm are turned on.

[0015] In the above - mentioned method, when the PFC circuit switches between the +2 mode and the +0 mode, the duration of the PFC circuit in the +1 mode is not greater than 10% of the switching period. And when the PFC circuit switches between the -2 mode and the -0 mode, the duration of the PFC circuit in the -1 mode is not greater than 10% of the switching period.

[0016] In the above - mentioned method, the first switch and the third switch work complementarily, the dead - time between the first switch and the third switch is greater than or equal to the commutation time of the first switch or the third switch, and the second switch and the fourth switch work complementarily, the dead - time between the second switch and the fourth switch is greater than or equal to the commutation time of the second switch or the fourth switch.

[0017] In the above - mentioned method, it further includes at least one of the following steps:

[0018] When switching the PFC circuit from the +0 mode via the +1 mode to the +2 mode, the following operations are performed in sequence: turn off the fourth switch, turn on the second switch, turn off the third switch and turn on the first switch;

[0019] When switching the PFC circuit from the +2 mode via the +1 mode to the +0 mode, the following operations are sequentially performed: turning off the first switching transistor, turning on the third switching transistor, turning off the second switching transistor, and turning on the fourth switching transistor;

[0020] When switching the PFC circuit from the -2 mode via the -1 mode to the -0 mode, the following operations are sequentially performed: turning off the fourth switching transistor, turning on the second switching transistor, turning off the third switching transistor, and turning on the first switching transistor; and

[0021] When switching the PFC circuit from the -0 mode via the -1 mode to the -2 mode, the following operations are sequentially performed: turning off the first switching transistor, turning on the third switching transistor, turning off the second switching transistor, and turning on the fourth switching transistor.

[0022] The above method further includes at least one of the following steps:

[0023] When switching the PFC circuit from the +0 mode via the +1 mode to the +2 mode, the following operations are sequentially performed: turning off the fourth switching transistor, turning off the third switching transistor, turning on the second switching transistor, and turning on the first switching transistor;

[0024] When switching the PFC circuit from the +2 mode via the +1 mode to the +0 mode, the following operations are sequentially performed: turning off the first switching transistor, turning off the second switching transistor, turning on the third switching transistor, and turning on the fourth switching transistor;

[0025] When switching the PFC circuit from the -2 mode via the -1 mode to the -0 mode, the following operations are sequentially performed: turning off the fourth switching transistor, turning off the third switching transistor, turning on the second switching transistor, and turning on the first switching transistor; and

[0026] When switching the PFC circuit from the -0 mode via the -1 mode to the -2 mode, the following operations are sequentially performed: turning off the first switching transistor, turning off the second switching transistor, turning on the third switching transistor, and turning on the fourth switching transistor.

[0027] The above method satisfies at least one of the following items:

[0028] When the PFC circuit switches from the +0 mode to the +2 mode, the time interval between the step of turning on the second switching transistor and the step of turning off the third switching transistor is less than or equal to 10% of the switching period;

[0029] When the PFC circuit switches from the +2 mode to the +0 mode, the time interval between the step of turning on the third switching transistor and the step of turning off the second switching transistor is less than or equal to 10% of the switching period;

[0030] When the PFC circuit switches from the -2 mode to the -0 mode, the time interval between the step of turning on the second switching transistor and the step of turning off the third switching transistor is less than or equal to 10% of the switching period; and

[0031] When the PFC circuit switches from the -0 mode to the -1 mode, the time interval between the step of turning on the third switching transistor and the step of turning off the second switching transistor is less than or equal to 10% of the switching period.

[0032] In the above method, an impedance is connected in parallel with each of the second switching transistor and the third switching transistor, and the resistance value of the impedance satisfies: where Za is the resistance value of the impedance, and C d is the capacitance value of the parasitic capacitance of the clamping diode in the clamping diode branch.

[0033] According to another aspect of the present application, a PFC circuit is further provided, including:

[0034] A diode bridge arm, including a first diode and a second diode connected in series;

[0035] A DNPC bridge arm connected in parallel with the diode bridge arm, including a first switching transistor, a second switching transistor, a third switching transistor, and a fourth switching transistor connected in series, and a clamping diode branch, one end of the clamping diode branch is connected to the connection point between the first switching transistor and the second switching transistor, and the other end is connected to the connection point between the third switching transistor and the fourth switching transistor;

[0036] A capacitor bank, connected in parallel with the diode bridge arm and the DNPC bridge arm, and including a first capacitor and a second capacitor connected in series, the connection point between the first capacitor and the second capacitor forms the midpoint of the capacitor bank, and the midpoint of the clamping diode branch is connected to the midpoint of the capacitor bank; and

[0037] A controller, the controller controls the mode of the PFC circuit to perform modulation, wherein the controller is used for:

[0038] When modulating the positive half cycle of the modulation wave, within one switching period, the PFC circuit is switched between the +2 mode and the +0 mode via the +1 mode, and

[0039] When modulating the negative half cycle of the modulation wave, within one switching period, the PFC circuit is switched between the -2 mode and the -0 mode via the -1 mode, where

[0040] During the positive half - cycle of the modulation wave, the input current of the PFC circuit flows into the mid - point of the DNPC bridge arm. In the +2 mode, only the first switch and the second switch in the DNPC bridge arm are turned on. In the +1 mode, only the third switch in the DNPC bridge arm is turned on. And in the +0 mode, only the third switch and the fourth switch in the DNPC bridge arm are turned on, and

[0041] During the negative half - cycle of the modulation wave, the input current of the PFC circuit flows out of the mid - point of the DNPC bridge arm. In the - 2 mode, only the third switch and the fourth switch in the DNPC bridge arm are turned on. In the - 1 mode, only the second switch in the DNPC bridge arm is turned on. And in the - 0 mode, only the first switch and the second switch in the DNPC bridge arm are turned on.

[0042] In the above - mentioned PFC circuit, the controller is further configured to: when the PFC circuit switches between the +2 mode and the +0 mode, make the duration of the PFC circuit in the +1 mode not greater than 10% of the switching period; and when the PFC circuit switches between the - 2 mode and the - 0 mode, make the duration of the PFC circuit in the - 1 mode not greater than 10% of the switching period.

[0043] In the above - mentioned PFC circuit, at least one of the following items is satisfied:

[0044] When the PFC circuit switches from the +0 mode through the +1 mode to the +2 mode, the controller sequentially turns off the fourth switch, turns on the second switch, turns off the third switch, and turns on the first switch;

[0045] When the PFC circuit switches from the +2 mode through the +1 mode to the +0 mode, the controller sequentially turns off the first switch, turns on the third switch, turns off the second switch, and turns on the fourth switch;

[0046] When the PFC circuit switches from the - 2 mode through the - 1 mode to the - 0 mode, the controller sequentially turns off the fourth switch, turns on the second switch, turns off the third switch, and turns on the first switch; and

[0047] When the PFC circuit switches from the -0 mode to the -2 mode via the -1 mode, the controller sequentially turns off the first switching transistor, turns on the third switching transistor, turns off the second switching transistor, and turns on the fourth switching transistor.

[0048] In the above PFC circuit, at least one of the following items is satisfied:

[0049] When the PFC circuit is switched from the +0 mode to the +2 mode via the +1 mode, the controller sequentially turns off the fourth switching transistor, turns off the third switching transistor, turns on the second switching transistor, and turns on the first switching transistor;

[0050] When the PFC circuit is switched from the +2 mode to the +0 mode via the +1 mode, the controller sequentially turns off the first switching transistor, turns off the second switching transistor, turns on the third switching transistor, and turns on the fourth switching transistor;

[0051] When the PFC circuit is switched from the -2 mode to the -0 mode via the -1 mode, the controller sequentially turns off the fourth switching transistor, turns off the third switching transistor, turns on the second switching transistor, and turns on the first switching transistor; and

[0052] When the PFC circuit is switched from the -0 mode to the -2 mode via the -1 mode, the controller sequentially turns off the first switching transistor, turns off the second switching transistor, turns on the third switching transistor, and turns on the fourth switching transistor.

[0053] In the above PFC circuit, an impedance is connected in parallel with each of the second switching transistor and the third switching transistor, and the resistance value of the impedance satisfies: where Za is the resistance value of the impedance, and C d is the capacitance value of the parasitic capacitance of the clamping diode in the clamping diode branch.

[0054] According to another aspect of the present application, a power conversion device is further provided, including at least one power conversion unit, each voltage conversion unit including the above-mentioned PFC circuit; a first bridge arm, connected in parallel with the first capacitor of the PFC circuit and including a fifth switching transistor and a sixth switching transistor connected in series; a second bridge arm, connected in parallel with the second capacitor of the PFC circuit and including a seventh switching transistor and an eighth switching transistor connected in series; a transformer, one end of the primary winding of the transformer is connected to the connection point of the fifth switching transistor and the sixth switching transistor, and the other end is electrically connected to the connection point of the seventh switching transistor and the eighth switching transistor; and a secondary side circuit, connected to the secondary winding of the transformer.

[0055] The above power conversion device further includes a controller configured to output a first control signal, a second control signal, a third control signal, and a fourth control signal to the control terminals of the fifth switch, the sixth switch, the seventh switch, and the eighth switch respectively. Wherein, the first control signal and the second control signal are complementary, the third control signal and the fourth control signal are complementary, and both are square wave signals with a preset period. There is a first phase shift angle between the first control signal and the fourth control signal, and there is the first phase shift angle between the second control signal and the third control signal; and control the first phase shift angle to reduce the voltage difference between the first capacitor and the second capacitor.

[0056] In the above power conversion device, the controller is further configured to detect a first voltage across the first capacitor and a second voltage across the second capacitor; determine the first phase shift angle according to the voltage difference between the first voltage and the second voltage. When the voltage difference is positive, reduce the first phase shift angle; when the voltage difference is negative, increase the first phase shift angle.

[0057] The above power conversion device includes a plurality of power conversion units, and the input ends of the plurality of power conversion units are connected in series in sequence. Description of the Drawings

[0058] Figure 1 Shows the circuit diagram of a bidirectional five-level in the prior art.

[0059] Figure 2 Shows the circuit diagram of the PFC circuit according to an embodiment of the present application.

[0060] Figure 3 is Figure 2 Schematic diagram of the operating mode of the PFC circuit shown.

[0061] Figure 4 Shows applying the existing modulation strategy to Figure 2 The voltage waveform of the PFC circuit shown.

[0062] Figure 5 Shows using Figure 4 The simulation waveform of the circuit under the modulation strategy.

[0063] Figure 6A and Figure 6B Shows the voltage waveform obtained according to the modulation strategy of an embodiment of the present application, where Figure 6B is Figure 6A The partial enlarged view of.

[0064] Figure 7 Shows Figure 6A The simulation waveform of the circuit under the modulation strategy shown.

[0065] Figure 8 Shows the switching timing diagram of the DNPC bridge arm switching tubes according to an embodiment of the present application.

[0066] Figure 9 Shows the Figure 8 voltage waveforms of the respective switching tubes corresponding to the switching timing shown.

[0067] Figures 10A to 10G Shows the Figure 8 circuit operating state when switching from the +0 mode to the +2 mode in the switching timing diagram.

[0068] Figures 11A to 11E Shows the Figure 8 circuit operating state when switching from the +2 mode to the +0 mode in the switching timing diagram.

[0069] Figure 12 Is Figure 9 the simulation waveform of the circuit under the switching timing shown.

[0070] Figure 13 Shows the switching timing diagram of the DNPC bridge arm switching tubes according to another embodiment of the present application.

[0071] Figure 14 Shows the circuit diagram of a PFC circuit according to another embodiment of the present application.

[0072] Figure 15 Shows the schematic diagram of two PFC circuit input terminals connected in series according to an embodiment of the present application.

[0073] Figure 16 Shows the circuit diagram of a power conversion unit of a power conversion device according to an embodiment of the present application.

[0074] Figure 17 Is the schematic diagram of the midpoint balance control method in the DC / DC converter of the power conversion unit according to an embodiment of the present application. Detailed Embodiments

[0075] Various embodiments herein will now be described in detail, one or more examples of which are shown in the drawings. In the following description of the drawings, the same reference numerals indicate the same components or elements. Only the differences regarding each embodiment are described. Each example is provided by way of illustration and is not meant to limit the scope herein. Additionally, features illustrated or described as part of one embodiment may be used on or combined with other embodiments to yield another embodiment. The description is intended to include such modifications and variations.

[0076] The following refers to Figure 2Describe the bridgeless DNPC three-level circuit topology as the PFC circuit 10.

[0077] As Figure 2 shown, the PFC circuit 10 includes a diode bridge arm 11, a DNPC bridge arm 12, and a capacitor bank 13 connected in parallel. The diode bridge arm 11 includes two industrial-frequency rectifier diodes D1 and D2 connected in series. The DNPC bridge arm 12 includes a first switch tube S1, a second switch tube S2, a third switch tube S3, and a fourth switch tube S4 connected in series in sequence. The capacitor bank 13 includes a first capacitor Cp and a second capacitor Cn connected in series. In addition, the DNPC bridge arm further includes a clamping diode branch 14. The clamping diode branch 14 includes two clamping diodes Dp and Dn. One end of the clamping diode branch 14 is connected to the connection point p1 formed by the series connection of the first switch tube S1 and the second switch tube S2, and the other end of the clamping diode branch 14 is connected to the connection point p2 formed by the series connection of the third switch tube S3 and the fourth switch tube S4. The midpoint of the clamping diode branch 14 is connected to the midpoint of the capacitor bank 13 to serve as the midpoint N. It should be noted that the types of the first to fourth switch tubes S1 - S4 are not limited in this application, for example, they can be MOSFETs, IGBTs, or other types of semiconductor switching devices.

[0078] In the PFC circuit 10, define the midpoint of the DNPC bridge arm 12 as point A (i.e., the node formed by the series connection of the second switch tube S2 and the third switch tube S3), and the midpoint of the diode bridge arm 11 as point B (i.e., the node formed by the series connection of the rectifier diodes D1 and D2). Based on the above definitions, the bridge arm input voltage of the PFC circuit 10 can be defined as V AB , that is, the voltage between ports A and B. In addition, define the grid current I grid (input current) flowing into point A of the DNPC bridge arm 12 and flowing out of point B of the diode bridge arm 11 as the positive direction, and the midpoint current i n flowing out of point N as the positive direction.

[0079] Continue to refer to Figure 3 Describe the various operating modes of the PFC circuit 10. Among them, the operating modes of the PFC circuit 10 consist of 6 modes.

[0080] In the positive half industrial-frequency cycle of the modulation wave, the input current direction is flowing into point A, the midpoint of the DNPC bridge arm 12, and flowing out of point B, the midpoint of the diode bridge arm 11. At this time, the rectifier diode D2 is conducting, and the input current is in the positive direction.

[0081] As Figure 3 (a) shown, the PFC circuit 10 operates in the +2 mode. At this time, the input current flows through the first switch tube S1, the second switch tube S2, the first capacitor Cp and the second capacitor Cn of the capacitor bank 13. The voltage between ports A and B of the PFC circuit 10 is (V dcP + VdcN ), where V dcP is the voltage across the first capacitor Cp, and V dcN is the voltage across the second capacitor Cn, which is defined as the +2 level at this time. As Figure 3 (b) shows, the PFC circuit 10 operates in the +1 mode. At this time, the input current flows through the third switch tube S3, the clamping diode Dn, and the second capacitor Cn. Then the voltage between ports A and B is V dcN , which is defined as the +1 level at this time. As Figure 3 (c) shows, the PFC circuit 10 operates in the +0 mode. At this time, the input current only flows through the third switch tube S3 and the fourth switch tube S4. Then the voltage between ports A and B is 0. Also, because the current is in the positive direction at this time, it is defined as the +0 level at this time.

[0082] During the negative half power frequency period of the modulation wave, the direction of the input current is from point A, the midpoint of the DNPC bridge arm 12, and the current flows into from point B, the midpoint of the diode bridge arm 11. The rectifier diode D1 conducts, and the current is in the negative direction at this time.

[0083] As Figure 3 (d) shows, the PFC circuit 10 operates in the -2 mode. At this time, the current flows through the first capacitor Cp, the second capacitor Cn, the third switch tube S3, and the fourth switch tube S4 of the capacitor bank 13. The voltage between ports A and B is -(V dcP +V dcN ), which is defined as the -2 level. As Figure 3 (e) shows, the PFC circuit 10 operates in the -1 mode. The current flows through the first capacitor Cp, the clamping diode Dp, and the second switch tube S2. Then the voltage between ports A and B is -V dcP , which is defined as the -1 level at this time. As Figure 3 (f) shows, the PFC circuit 10 operates in the -0 mode. The current flows through the first switch tube S1 and the second switch tube S2. Then the voltage between ports A and B is 0. Also, because the current is in the negative direction at this time, it is defined as the -0 level at this time.

[0084] Referring to Figure 4 , Figure 4 shows Figure 2 the voltage waveforms of the PFC circuit shown using the existing modulation strategy. As Figure 4 shown, the term "modulation" used in this application refers to the process of making the voltage between ports A and B of the PFC circuit fit the modulation wave (for example, Figure 3 the sine curve of the voltage Vm shown in Figure 4 ) by controlling the duration of each mode of the PFC circuit using the various modes of the PFC circuit described above in conjunction with

[0085] AsFigure 4 As shown, when the modulation wave is between 0.5V dc and V dc , by controlling the PFC circuit 10 to switch back and forth between the +1 mode and the +2 mode, and modulating by controlling the duty ratios of the +1 mode and the +2 mode; when the modulation wave is between 0 and 0.5V dc , by controlling the PFC circuit 10 to switch back and forth between the +1 mode and the +0 mode, and modulating by controlling the duty ratios of the +1 mode and the +0 mode; when the modulation wave is between -0.5V dc and -V dc , by controlling the PFC circuit 10 to switch back and forth between the -1 mode and the -2 mode, and modulating by controlling the duty ratios of the -1 mode and the -2 mode; when the modulation wave is between 0 and -0.5V dc , by controlling the PFC circuit 10 to switch back and forth between the -1 mode and the -0 mode, and modulating by controlling the duty ratios of the -1 mode and the -0 mode. In addition, Figure 4 it also shows the voltage V AN between point A and point N of the circuit during modulation BN and the voltage waveform of the voltage V

[0086] Figure 5 shows the simulation waveforms of the circuit under the existing modulation strategy shown Figure 4 . In Figure 5 , the grid current I grid is in phase with the grid voltage V grid , that is, the power factor is 1, but the potential of the midpoint N has a power frequency period fluctuation, and the fluctuation amplitude is large. The voltage fluctuation of the midpoint is defined as ΔV dc = V dcP - V dcN . In the simulation model, when the capacitance value of the DC-Link is 1.5 mF, the voltage fluctuation of the midpoint N is 30V. This is because when the grid current is positive, the +1 mode is always involved in modulation, and during the positive half power frequency period, the current always flows into the midpoint N in the +1 mode; when the grid current is negative, the -1 mode is always involved in modulation, and during the negative half power frequency period, the current always flows out of the midpoint N in the -1 mode. Due to the limited voltage stress of the switching tubes, the voltage fluctuations of the first capacitor Dp and the second capacitor Dn should not be too large. Therefore, a larger DC-Link capacitor is required to absorb the second harmonic fluctuation of the midpoint N, resulting in the problems of high requirements for the capacitance value of the DC-Link, high cost, and large volume in the prior art.

[0087] In view of the above deficiencies of the prior art, the present application proposes a method based on Figure 2The quasi-two-level modulation strategy of the PFC circuit 10 shown. This modulation strategy can significantly reduce the voltage fluctuation at the midpoint of the capacitor bank, save the capacitor usage, and at the same time make the effective value of the current flowing through the clamping diode very small, which can save the capacity of the clamping diode, reduce the device cost, and reduce the conduction loss of the clamping diode, thereby improving the efficiency.

[0088] Figure 6A shows a quasi-two-level modulation strategy of the PFC circuit 10 based on Figure 2 the one shown. Similar to Figure 4 , the preferred embodiment of the present application utilizes the various modes of the PFC circuit described above in conjunction with Figure 3 , and by controlling the duration of the PFC circuit in each mode, the port voltage of the PFC circuit is made to fit the modulation wave ( Figure 6A the sine curve of the voltage Vm shown in Figure 4 ). Different from the modulation strategy in the prior art shown in Figure 4 , the modulation strategy of the present application reduces the current flowing into or out of the midpoint N by shortening the duration of the +1 mode and the -1 mode, thereby reducing the voltage fluctuation at the midpoint. The specific modulation process will be described below.

[0089] As Figure 6A shown, in this embodiment, when the modulation wave V m is between 0 and V dc , within each switching period, the PFC circuit is modulated by briefly switching between the +2 mode and the +0 mode via the +1 mode, that is, when the PFC circuit switches between the +2 mode and the +0 mode, the PFC circuit only passes through the +1 mode for a very short time for transition; similarly, when the modulation wave V m is between 0 and -V dc , within each switching period, the PFC circuit is modulated by briefly switching between the -2 mode and the -0 mode via the -1 mode, that is, when the PFC circuit switches between the -2 mode and the -0 mode, the PFC circuit only passes through the -1 mode for a very short time for transition.

[0090] In this embodiment, as Figure 6A shown, it is assumed that the voltage V dcP across the first capacitor Cp is equal to the voltage V dcN across the second capacitor Cn, both being 0.5V dc , and the voltage V AN switches between +0.5V dc and -0.5V dc within each switching period and passes through the 0 level for a very short time for transition. Since the rectifier diode D2 is always conducting when the modulation wave is between 0 and V dc , the voltage VBN Maintained at -0.5V dc ; conversely, when the modulation wave is between 0 and -V dc , the rectifier diode D1 is always conducting, so the voltage V BN is maintained at +0.5V dc . According to the voltage V AN and the voltage V BN , the port voltage V AB can be obtained.

[0091] Figure 6B Shows an enlarged view of the dashed box in Figure 6A . In Figure 6B , the PFC circuit 10 transitions from the +0 mode through the +1 mode for a very short time to the +2 mode, which represents one switching cycle. In one switching cycle, the PFC circuit lasts for D1 + D5 in the +0 mode, D2 + D4 in the +1 mode, and D3 in the +2 mode. In other embodiments that can be combined with the first embodiment of the present application, for each of the durations D2 and D4 of the PFC circuit in the +1 mode, it does not exceed 10% of one switching cycle (D1 + D2 + D3 + D4 + D5), preferably does not exceed 5%, and even does not exceed 1%, that is, the total duration D2 + D4 of the PFC circuit in the +1 mode does not exceed 20% of one switching cycle (D1 + D2 + D3 + D4 + D5), preferably does not exceed 10%, or does not exceed 5%, and even does not exceed 1%. In short, on the premise of ensuring normal commutation of the circuit, the shorter the duration of the PFC circuit in the +1 mode, the smaller the impact on the voltage fluctuation at the midpoint, and the more conducive it is to reducing the voltage fluctuation at the midpoint of the bus capacitor.

[0092] Similarly, in this embodiment, when the PFC circuit switches between the -2 mode and the -0 mode, the PFC circuit transitions through the -1 mode for a very short time. And preferably, the duration of the PFC circuit in the -1 mode does not exceed 20% of one switching cycle, preferably does not exceed 10%, or does not exceed 5%, and even does not exceed 1%. In short, on the premise of ensuring normal commutation of the circuit, the shorter the duration of the PFC circuit in the -1 mode, the more conducive it is to reducing the voltage fluctuation at the midpoint.

[0093] Since the PFC circuit switches between the +0 mode and the +2 mode, or between the -0 mode and the -2 mode within each switching cycle, and the action time of the +1 and -1 modes as transitional modes is very short, the current flowing into or out of the midpoint ( Figure 2 the midpoint N in

[0094] Figure 7 shows the simulation waveforms of the circuit under the modulation strategy adopted Figure 6A as shown. Compared with the circuit simulation waveforms under the prior art modulation strategy Figure 4 shown, in Figure 7 , the grid current I grid is in phase with the grid voltage V grid , the action time of the ±1 modes is very short, and since the grid current only flows into the midpoint within a very short time, the effective value of the midpoint current is extremely small. Similarly, when the value of the DC-Link capacitor is 1.5 mF, the voltage fluctuation ΔV dc of the midpoint is only 1.5 V, and the voltage fluctuation of the midpoint is reduced by 95% compared with the prior art. In other words, under the same ripple requirement, adopting the quasi-two-level modulation strategy Figure 6A shown can greatly reduce the usage of the DC-Link capacitor, reduce the cost, and reduce the volume of the capacitor bank.

[0095] In Figure 6A the quasi-two-level modulation strategy shown, the voltage V AN of the DNPC leg switches between 0.5V dc and -0.5V dc within each switching period and transitions through the 0 level in the middle. The four switching devices of the DNPC leg need to reasonably allocate the switching timing to ensure the safety of the devices, otherwise there will be a risk of overvoltage. The switching timing of the four switching devices of the DNPC leg under the quasi-two-level modulation strategy proposed in this application will be further described below.

[0096] Figure 8 shows the switching timing diagram of the switching devices of the DNPC leg (the switching devices S1 - S4 of the DNPC leg 12 of the PFC circuit 10 Figure 2 shown) according to an embodiment of the present application. As Figure 8 shown, the first switching device S1 and the third switching device S3 are complementary, the second switching device S2 and the fourth switching device S4 are complementary, and the dead time is T d . In some embodiments, the dead time T d of the first switching device S1 and the third switching device S3 is greater than or equal to the commutation time of the first switching device S1 or the third switching device S3, and the dead time T d of the second switching device S2 and the fourth switching device S4 is greater than or equal to the commutation time of the second switching device S2 or the fourth switching device S4. Combining Figure 6A and further referring to Figure 8 , the leg voltage V AN of the DNPC leg switches from -0.5V dc to 0.5V dc corresponds to the process of Figure 6AThe process of the PFC circuit shown switching from the +0 mode to the +2 mode (when the input current is in the positive direction) or from the -2 mode to the -0 mode (when the input current is in the negative direction). At this time, first turn off the fourth switch tube S4, then turn on the second switch tube S2, then turn off the third switch tube S3, and finally turn on the first switch tube S1. The overlapping time when the second switch S2 and the third switch tube S3 are conducting simultaneously is T x . Similarly, the arm voltage V AN of the DNPC arm switches from 0.5V dc to -0.5V dc , and the process corresponds to Figure 6A the process of the PFC circuit shown switching from the +2 mode to the +0 mode (when the input current is in the positive direction) or from the -0 mode to the -2 mode (when the input current is in the negative direction). At this time, first turn off the first switch tube S1, then turn on the third switch tube S3, then turn off the second switch tube S2, and finally turn on the fourth switch tube S4. This switching timing can ensure that the outer tubes (the switch tubes outside the DNPC arm, that is, the first switch tube S1 and the fourth switch tube S4) complete commutation first, and the voltage stress reaches 0.5V dc , and the inner tubes (the switch tubes inside the DNPC arm, that is, the second switch tube S2 and the third switch tube S3) commutate later, so there will be no overvoltage. It is applicable in both the positive and negative half-cycles of the current, does not rely on current direction recognition, and has symmetry within one switching period, making it simple to implement.

[0097] Below, taking one switching period in the positive half-cycle of the current as an example, combined with Figure 9 , Figures 10A - 10G and Figure 11A -11E specifically describes the switching timing under the quasi-two-level modulation strategy of this application. Among them Figure 9 shows the driving signal timing of the first switch tube to the fourth switch tube S1 - S4, and shows the port voltage V AB at different moments in the timing diagram and the voltages V ds1 - V ds4 of the first switch tube to the fourth switch tube S1 - S4. Figures 10A - 10G and Figure 11A -11E respectively show the states of the PFC circuit at different moments in the timing diagram.

[0098] First, describe the process of the PFC circuit switching from the +0 mode moment to the +2 mode. The switching timing is as shown in the left half of Figure 9 . Referring to Figure 10A again, before the t0 moment, the third switch tube S3 and the fourth switch tube S4 are conducting, and the current flows through the channels of the third switch tube S3 and the fourth switch tube S4, and the port voltage V AB is 0. At the t0 moment, as shown in Figure 10BAs shown, the fourth switching transistor S4 is turned off, and the current can no longer flow through the channel of the fourth switching transistor S4. Thus, the current charges the junction capacitance of the fourth switching transistor S4, and the junction capacitance of the clamping diode D n discharges, and at the same time, the junction capacitances of the first switching transistor S1 and the second switching transistor S2 discharge. During this process, V ds4 rises, V ds1 and V ds2 fall. Since the first switching transistor S1 and the clamping diode D p are in parallel and have a larger equivalent capacitance and a slower discharge speed, V ds1 is higher than V ds2 . As Figure 10C shown, at time t1, the discharge ends. At this time, V ds4 = 0.5V dc , V ds1 + V ds2 = 0.5V dc , and the junction capacitance of the clamping diode D n discharges to 0. The current flows through the third switching transistor S3 and the clamping diode D n . During this stage, the fourth switching transistor S4 preferentially completes commutation, and the voltage is clamped to 0.5V dc . As Figure 10D shown, at time t2, the second switching transistor S2 is turned on, and V ds2 instantly drops to 0, and V ds1 instantly rises to 0.5V dc . The current still flows through the third switching transistor S3 and the clamping diode D n . As Figure 10E shown, at time t3, the third switching transistor S3 is turned off, and the current can no longer flow through the third switching transistor S3. Therefore, the current charges the junction capacitance of the third switching transistor S3, and the junction capacitance of the first switching transistor S1 discharges. Since V ds4 has reached 0.5V dc , the third switching transistor S3 will not be charged to overvoltage. As Figure 10F shown, at time t4, V ds3 rises to 0.5V dc , V ds1 drops to 0, and the current flows through the channel of the second switching transistor S2 and the body diode of the first switch S1. At this time, the DNCP bridge arm becomes the +2 mode. Finally, as Figure 10G shown, at time t5, the first switch S1 is turned on, and the current flows through the channels of the first switching transistor S1 and the second switching transistor S2.

[0099] Next, the process of the PFC circuit switching from the +2 mode to the +0 mode is described. The switching timing is as shown in the right half of Figure 9 , and referring to Figure 11A, before time t6, the first switch tube S1 and the second switch tube S2 are turned on, and the PFC circuit is in the +2 mode. At this time, the third switch tube S3 and the fourth switch tube S4 respectively bear a voltage of 0.5V dc . As Figure 11B shown, at time t6, the first switch tube S1 is turned off, and the current can still flow through the body diode of the first switch tube S1, and the state remains unchanged. As Figure 11C shown, at time t7, the third switch tube S3 is turned on. The potential of the midpoint of the DNPC bridge arm is higher than the potential of the midpoint of the capacitor, and the clamping diode Dn is turned on. The current flows through the third switch tube S3 and the clamping diode Dn, and the potential of the midpoint of the DNPC bridge arm is equal to the potential of the midpoint of the capacitor. Therefore, the voltage across the first switch tube S1 is instantly raised to 0.5V dc , and the terminal voltage V ds3 of the third switch tube S3 = 0. The first switch tube S1 on the outer side of the DNPC bridge arm gives priority to commutation and is clamped to 0.5V dc . As Figure 11D shown, at time t8, the second switch tube S2 is turned off, and the current still flows through the third switch tube S3 and the clamping diode Dn, and the state remains unchanged. As Figure 11E shown, at time t9, the fourth switch tube S4 is turned on, and the potential V AN is directly pulled down to -V dc , and the current directly flows through the third switch tube S3 and the fourth switch tube S4. At this time, V ds4 drops to 0, and V ds2 rises to 0.5V dc . Since V ds1 has reached 0.5V dc , the second switch tube S2 will not be charged to overvoltage.

[0100] In the switching timings shown in Figure 9 , Figures 10A to 10G and Figures 11A to 11E , the dead time T d between complementary switches (for example, the first switch tube S1 and the third switch tube S3 are complementary, and the second switch tube S2 and the fourth switch tube S4 are complementary) should be greater than or equal to the time required for the switch tube commutation. The action time difference T x between the second switch tube S2 and the third switch tube S3 should be greater than or equal to 0 and as small as possible. The time when the PFC circuit is in the +1 mode is between T x and (T x + T d ). Therefore, T x and T dThey should all be made as small as possible, so as to reduce the duration of the +1 mode while meeting the requirement of safe commutation, minimize the current flowing into the midpoint, and thus reduce the voltage fluctuation at the midpoint. In some embodiments, when the PFC circuit switches from the +0 mode to the +2 mode, the time interval Tx between turning on the second switch tube S2 and turning off the third switch tube S3 is less than or equal to 10% of the switching period, preferably less than or equal to 5% of the switching period, and particularly less than or equal to 1% of the switching period; and when the PFC circuit switches from the +2 mode to the +0 mode, the time interval between turning on the third switch tube S3 and turning off the second switch tube S2 is less than or equal to 10% of the switching period, preferably less than or equal to 5% of the switching period, and more particularly less than or equal to 1% of the switching period.

[0101] Figure 12 For the Figure 9 simulation waveforms of the circuit under the shown switching timing. Within one switching period, the switching process between the +0 mode and the +2 mode is completely consistent with the theoretical analysis. The voltage stress of the switch tube does not exceed 0.5V dc , and the switching process is safe and reliable. The duration of the +1 mode is very short, about 1 us, and the grid current only flows through the midpoint during the transition process of the level switching.

[0102] As described above in combination with Figures 9 to 12 Taking one switching period of the positive half-cycle as an example, the switching timing under the quasi-two-level modulation strategy of this article is described. Similarly, for one switching period of the negative half-cycle, when the PFC circuit switches from the -2 mode to the -0 mode via the -1 mode, the fourth switch tube S4 is turned off in sequence, the second switch tube S2 is turned on, the third switch tube S3 is turned off, and the first switch tube S1 is turned on; and when the PFC circuit switches from the -0 mode to the -2 mode via the -1 mode, the first switch tube S1 is turned off in sequence, the third switch tube S3 is turned on, the second switch tube S2 is turned off, and the fourth switch tube S4 is turned on. In addition, when the PFC circuit switches from the -2 mode to the -0 mode, the time interval between turning on the second switch tube S2 and turning off the third switch tube S3 is less than or equal to 10% of the switching period, preferably less than or equal to 5% of the switching period, and more particularly less than or equal to 1% of the switching period; and when the PFC circuit switches from the -0 mode to the -2 mode, the time interval between turning on the third switch tube S3 and turning off the second switch tube S2 is less than or equal to 10% of the switching period, preferably less than or equal to 5% of the switching period, and more particularly less than or equal to 1% of the switching period, so as to reduce the duration of the -1 mode while meeting the requirement of safe commutation, minimize the current flowing out of the midpoint, and thus reduce the voltage fluctuation at the midpoint.

[0103] Figure 13 shows the switching timing diagram of the DNPC bridge arm switch tube according to another embodiment of the present application. As Figure 13As shown, the first switching transistor S1 and the third switching transistor S3 are complementary, the second switching transistor S2 and the fourth switching transistor S4 are complementary, and the dead time is T d . In some embodiments, the dead time T of the first switching transistor S1 and the third switching transistor S3 d is greater than or equal to the commutation time of the first switching transistor S1 or the third switching transistor S3, and the dead time T of the second switching transistor S2 and the fourth switching transistor S4 d is greater than or equal to the commutation time of the second switching transistor S2 or the fourth switching transistor S4. Combining Figure 6A and further referring to Figure 13 , the arm voltage V of the DNPC arm AN switches from 0.5V dc to -0.5V dc in a process corresponding to Figure 6A the process of the PFC circuit switching from the +2 mode to the +0 mode (input current in the positive direction) or from the -0 mode to the -2 mode (input current in the negative direction) as shown. At this time, first turn off the first switching transistor S1, then turn off the second switching transistor S2, then turn on the third switching transistor D3, and finally turn on the fourth switching transistor S4. The arm voltage V of the DNPC arm AN switches from -0.5V dc to 0.5V dc in a process corresponding to Figure 6A the process of the PFC circuit switching from the +0 mode to the +2 mode (input current in the positive direction) or from the -2 mode to the -0 mode (input current in the negative direction) as shown. At this time, first turn off the fourth switching transistor S4, then turn off the third switching transistor S3, then turn on the second switching transistor S2, and finally turn on the first switching transistor S1. The time interval between turning off the third switching transistor S3 and turning on the second switching transistor S2 or the time interval between turning off the second switching transistor S2 and turning on the third switching transistor S3 is T x. In some embodiments, when the PFC circuit switches from the +0 mode to the +2 mode, the time interval Tx between turning off the third switch tube S3 and turning on the second switch tube S2 is less than or equal to 10% of the switching period, preferably less than or equal to 5% of the switching period, and more particularly less than or equal to 1% of the switching period; when the PFC circuit switches from the +2 mode to the +0 mode, the time interval Tx between turning off the second switch tube S2 and turning on the third switch tube S3 is less than or equal to 10% of the switching period, preferably less than or equal to 5% of the switching period, and more particularly less than or equal to 1% of the switching period; when the PFC circuit switches from the -2 mode to the -0 mode, the time interval Tx between turning off the third switch tube S3 and turning on the second switch tube S2 is less than or equal to 10% of the switching period, particularly less than or equal to 5% of the switching period, and more particularly less than or equal to 1% of the switching period; and when the PFC circuit switches from the -0 mode to the -2 mode, the time interval Tx between turning off the second switch tube S2 and turning on the third switch tube S3 is less than or equal to 10% of the switching period, preferably less than or equal to 5% of the switching period, and more particularly less than or equal to 1% of the switching period. Thus, on the premise of meeting safe commutation, the duration of the +1 mode or -1 mode is reduced, the current flowing into or out of the midpoint N is decreased, and the voltage fluctuation at the midpoint is reduced.

[0104] Figure 13 The switching timing of Figure 8 Compared with the switching timing of dc , there is a risk that the voltage stress of the switch tubes (i.e., the second switch tube S2 and the third switch tube S3) located inside the DNCP bridge arm exceeds 0.5V. Figure 14 As shown in the PFC circuit 20 shown in a , an impedance Z can be connected in parallel to the switch tubes (i.e., the second switch tube S2 and the third switch tube S3) located inside the DNCP bridge arm, dc so that during the commutation process, the charging current of the inner switch tubes is reduced, and the charging speed is slower than that of the outer tubes. Thus, the outer tubes complete commutation and clamping first, ensuring that the voltage stress of the inner switch tubes does not exceed 0.5V. a The value of the parallel impedance Z

[0105]

[0106] where Za is the resistance value of the parallel impedance, and C d is the capacitance value of the parasitic capacitance of the clamping diode Dp or Dn in the clamping diode branch.

[0107] The above describes the proposed based on Figure 2The quasi-two-level modulation strategy of the PFC circuit 10 shown, and the switching timings of the four switching transistors on the DNCP leg. It should be noted that the switching states of the four switching transistors on the DNCP leg can be controlled by a control mechanism included in the PFC circuit 10, such as a controller (not shown), to implement the above-mentioned quasi-two-level modulation strategy and switching timings.

[0108] In some embodiments, the input terminals of the PFC circuits in N of the foregoing embodiments are connected in series to form a medium-voltage rectifier circuit for use in a medium-high voltage power conversion system. For example, Figure 15 A medium-voltage rectifier circuit 30 with the input terminals of two bridgeless PFC circuits connected in series is shown, which has two bridgeless PFC circuits 31 and 32 connected in series, and each of the two bridgeless PFC circuits 31 and 32 has the same structure as Figure 2 the circuit 10 shown or Figure 14 the circuit 20 shown. The total leg voltage after the input terminals of the two bridgeless PFC circuits are connected in series is a five-level waveform, and the equivalent switching frequency is twice that of a single bridgeless PFC circuit unit, and the midpoint of the DC-Link voltage is balanced and evenly distributed.

[0109] The PFC circuit using the quasi-two-level modulation described above can be combined with a three-level DC / DC circuit to form a unit of a power conversion device (such as a PET). Figure 16 The circuit diagram of a power conversion unit 40 of a power conversion device according to an embodiment herein is shown. As Figure 16 shown, each power conversion unit 40 includes a cascaded bridgeless PFC circuit 41 and a DC / DC circuit 42. The bridgeless PFC circuit 41 has the same structure as Figure 2 the PFC circuit 10 shown or Figure 14 the PFC circuit 20 shown. The primary circuit of the DC / DC circuit is a three-level leg 43 formed by a series-connected double half-bridge (SHB) topology. The SHB three-level leg 43 is composed of four series-connected switching transistors Q1 to Q4 and can output three levels of +2, +1, and 0. This topology is simple and has high efficiency.

[0110] Ideally, when the bridgeless PFC circuit 41 operates in quasi-two-level modulation, the current flowing into or out of the midpoint N1 is extremely small, and the positive and negative half-cycles are symmetric with an average value of 0. When the DC / DC circuit 42 operates in two-level modulation, there is no midpoint current. However, in actual products, due to reasons such as inconsistent parameters and asynchronous driving, the positive and negative bus voltages will be unbalanced, resulting in a DC offset. Therefore, the voltages of the two capacitors Cp and Cn must be evenly controlled.

[0111] As Figure 16As shown, the first end of the first capacitor Cp of the bridgeless PFC circuit 41 is node N1, and the second end is node N2; the first end of the second capacitor Cn of the bridgeless PFC circuit 41 is node N1, and the second end is node N3. The first switching element Q1 and the second switching element Q2 of the SHB three-level bridge arm 43 form a bridge arm 1A coupled between node N1 and node N2, and the first switching element Q1 and the second switching element Q2 are connected in series to form node N4; the third switching element Q3 and the fourth switching element Q4 of the SHB three-level bridge arm 43 form a bridge arm 1B coupled between node N1 and node N3, and the third switching element Q3 and the fourth switching element Q4 are connected in series to form node N5. The primary winding of the transformer 44 of the DC / DC circuit 42 is electrically connected to node N4 and node N5 through node N6 and node N7 respectively. The secondary side circuit 45 of the DC / DC circuit 42 is electrically connected to the secondary winding of the transformer 44 through node N8 and node N9.

[0112] A controller (not shown) is coupled to the capacitors Cp and Cn, the bridge arms 1A and 1B, and the secondary side circuit 45, and is configured to output a first control signal, a second control signal, a third control signal, and a fourth control signal to the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 according to the voltage difference between the capacitor Cp and the capacitor Cn. The first control signal, the second control signal, the third control signal, and the fourth control signal are all square wave signals with a preset period. The first control signal and the second control signal are complementary, the third control signal and the fourth control signal are complementary, and there is a first phase shift angle between the first control signal and the fourth control signal, and there is also the same first phase shift angle between the second control signal and the third control signal. The controller reduces the voltage difference between the first capacitor Cp and the second capacitor Cn by controlling the first phase shift angle.

[0113] Figure 17 is provided in this article Figure 16 Schematic diagram of the midpoint balance control method of the DC / DC circuit 42.

[0114] Figure 17 In, V gs is the control signal level of each switching element Q1-Q4, and i Lr is the current flowing through the primary circuit of the transformer 44, and i Lm is the current in the exciting inductor of the transformer 44, and i Nd is the current at node N1, that is, the midpoint current.

[0115] Refer to Figure 17, in the embodiments of the present application, the control signals for controlling the first switching element Q1 and the second switching element Q2 are complementary and conductive, and the control signals for controlling the third switching element Q3 and the fourth switching element Q4 are complementary and conductive. Ignoring the dead zone, ideally the duty cycle of all switching tube control signals is 50%, and there is a first phase shift angle φ1 between the control signals of the switching elements Q1, Q2 and the control signals of the switching elements Q3, Q4. It is defined that when the fourth switching element Q4 lags behind the first switching element Q1 in turning on, the first phase shift angle is positive, and when the fourth switching element Q4 leads the first switching element Q1 in turning on, the first phase shift angle is negative. In the embodiments of the present disclosure, this method is referred to as the phase-shifting modulation method. Without considering the dead time, the SHB three-level bridge arm 43 can form 4 switching modes within one switching cycle. Taking the case where the first phase shift angle is positive as an example, refer to Figure 17 :

[0116] The switching elements Q1 and Q4 are simultaneously conductive, and the two capacitors Cp and Cn are connected in series to the converter. The total output voltage of the bridge arm 1A and the bridge arm 1B is (V dcP +V dcN ), the output level is 2, the midpoint (node N1) is not connected to the circuit, and this mode has no influence on the midpoint potential.

[0117] The switching elements Q2 and Q3 are simultaneously conductive, and the two capacitors Cp and Cn are not connected to the converter. The total output voltage of the bridge arm 1A and the bridge arm 1B is 0, the output level is 0, the midpoint (node N1) is not connected to the circuit, and this mode has no influence on the midpoint potential.

[0118] The switching elements Q1 and Q3 are simultaneously conductive, the total output voltage of the bridge arm 1A and the bridge arm 1B is V dcP , the output level is 1, the midpoint (node N1) is connected to the circuit, and the primary current i Lr of the DC / DC circuit flows out of the midpoint through the two switching elements Q1 and Q3.

[0119] The switching elements Q2 and Q4 are simultaneously conductive, the total output voltage of the bridge arm 1A and the bridge arm 1B is V dcN , the output level is 1, the midpoint (node N1) is connected to the circuit, and the primary current i Lr of the DC / DC circuit flows out of the midpoint through the two switching elements Q2 and Q4.

[0120] Among the above four switching modes, the 0 level and the 2 level have no influence on the midpoint potential. When the primary circuit of the DC / DC circuit 42 operates in the 0 level and 2 level modulation modes, the DC / DC circuit 42 itself does not have the ability to regulate the midpoint. Therefore, when midpoint balance adjustment is required, the 1 level mode must be reasonably utilized to adjust the midpoint potential.

[0121] In Figure 17In the control method shown, the SHB three-level arm 43 experiences two one-level modes within one switching period: when the first phase-shift angle is positive, the current is always in the direction of flowing out of the midpoint, the first capacitor Cp is charged, and the second capacitor Cn is discharged, causing the midpoint potential to drop and the voltage difference between the two capacitors to decrease; when the phase-shift angle is negative, the current is always in the direction of flowing into the midpoint, the second capacitor Cn is charged, and the first capacitor Cp is discharged, causing the midpoint potential to rise and the voltage difference between the two capacitors to decrease.

[0122] Therefore, the phase-shift angles of the control signals of the two arms determine the direction of the current flowing through the midpoint. The larger the phase-shift angle, the longer the time of the one-level action, the longer the time the current flows through the midpoint, the higher the average value of the midpoint current, and the stronger the regulation ability. In this embodiment, when the voltage difference between the two capacitors Cp and Cn is positive, the first phase-shift angle is decreased, and when the voltage difference between the two capacitors Cp and Cn is negative, the first phase-shift angle is increased to achieve midpoint balance.

[0123] Although the foregoing is directed to embodiments, other and further embodiments may be devised without departing from the basic scope, and this scope is determined by the appended claims.

Claims

1. A control method for a PFC circuit, The PFC circuit includes a diode bridge arm, a DNPC bridge arm, and a capacitor bank connected in parallel. The DNPC bridge arm includes a first switch, a second switch, a third switch, and a fourth switch connected in series in sequence, and a clamping diode branch. One end of the clamping diode branch is connected to the connection point of the first switch and the second switch, the other end is connected to the connection point of the third switch and the fourth switch, and the midpoint of the clamping diode branch is connected to the midpoint of the capacitor bank; The control method includes the following steps: When modulating the positive half-cycle of the modulation wave, within one switching period, the PFC circuit is switched between the +2 mode and the +0 mode via the +1 mode, and When modulating the negative half-cycle of the modulation wave, within one switching period, the PFC circuit is switched between the -2 mode and the -0 mode via the -1 mode, where During the positive half-cycle of the modulation wave, the input current of the PFC circuit flows in from the midpoint of the DNPC bridge arm. In the +2 mode, only the first switch and the second switch in the DNPC bridge arm are turned on. In the +1 mode, only the third switch in the DNPC bridge arm is turned on, and in the +0 mode, only the third switch and the fourth switch in the DNPC bridge arm are turned on, and During the negative half-cycle of the modulation wave, the input current flows out from the midpoint of the DNPC bridge arm. In the -2 mode, only the third switch and the fourth switch in the DNPC bridge arm are turned on. In the -1 mode, only the second switch in the DNPC bridge arm is turned on, and in the -0 mode, only the first switch and the second switch in the DNPC bridge arm are turned on.

2. The control method according to claim 1, wherein, When the PFC circuit switches between the +2 mode and the +0 mode, the duration of the PFC circuit in the +1 mode is not greater than 10% of the switching period, and When the PFC circuit switches between the -2 mode and the -0 mode, the duration of the PFC circuit in the -1 mode is not greater than 10% of the switching period.

3. The control method according to claim 1, wherein, The first switch and the third switch work complementarily, and the dead time of the first switch and the third switch is greater than or equal to the commutation time of the first switch or the third switch, and, The second switch and the fourth switch work complementarily, and the dead time of the second switch and the fourth switch is greater than or equal to the commutation time of the second switch or the fourth switch.

4. The control method according to claim 1, further includes at least one of the following steps: When the PFC circuit is switched from the +0 mode via the +1 mode to the +2 mode, the following operations are sequentially performed: turning off the fourth switching transistor, turning on the second switching transistor, turning off the third switching transistor, and turning on the first switching transistor; When the PFC circuit is switched from the +2 mode via the +1 mode to the +0 mode, the following operations are sequentially performed: turning off the first switching transistor, turning on the third switching transistor, turning off the second switching transistor, and turning on the fourth switching transistor; When the PFC circuit is switched from the -2 mode via the -1 mode to the -0 mode, the following operations are sequentially performed: turning off the fourth switching transistor, turning on the second switching transistor, turning off the third switching transistor, and turning on the first switching transistor; and When the PFC circuit is switched from the -0 mode via the -1 mode to the -2 mode, the following operations are sequentially performed: turning off the first switching transistor, turning on the third switching transistor, turning off the second switching transistor, and turning on the fourth switching transistor.

5. The control method according to claim 1, further comprising at least one of the following steps: When the PFC circuit is switched from the +0 mode via the +1 mode to the +2 mode, the following operations are sequentially performed: turning off the fourth switching transistor, turning off the third switching transistor, turning on the second switching transistor, and turning on the first switching transistor; When the PFC circuit is switched from the +2 mode via the +1 mode to the +0 mode, the following operations are sequentially performed: turning off the first switching transistor, turning off the second switching transistor, turning on the third switching transistor, and turning on the fourth switching transistor; When the PFC circuit is switched from the -2 mode via the -1 mode to the -0 mode, the following operations are sequentially performed: turning off the fourth switching transistor, turning off the third switching transistor, turning on the second switching transistor, and turning on the first switching transistor; and When the PFC circuit is switched from the -0 mode via the -1 mode to the -2 mode, the following operations are sequentially performed: turning off the first switching transistor, turning off the second switching transistor, turning on the third switching transistor, and turning on the fourth switching transistor.

6. The control method according to claim 4 or 5, wherein the control method satisfies at least one of the following items: When the PFC circuit is switched from the +0 mode to the +2 mode, the time interval between the step of turning on the second switching transistor and the step of turning off the third switching transistor is less than or equal to 10% of the switching period; When the PFC circuit is switched from the +2 mode to the +0 mode, the time interval between the step of turning on the third switching transistor and the step of turning off the second switching transistor is less than or equal to 10% of the switching period; When the PFC circuit is switched from the -2 mode to the -0 mode, the time interval between the step of turning on the second switching transistor and the step of turning off the third switching transistor is less than or equal to 10% of the switching period; When the PFC circuit switches from the -0 mode to the -2 mode, the time interval between the step of turning on the third switching device and the step of turning off the second switching device is less than or equal to 10% of the switching period.

7. The control method according to claim 5, wherein An impedance is connected in parallel to each of the second switching transistor and the third switching transistor, and the resistance value of the impedance satisfies: where Za is the resistance value of the impedance, and C d is the capacitance value of the parasitic capacitance of the clamping diode in the clamping diode branch.

8. A PFC circuit, comprising: A diode bridge arm including a first diode and a second diode connected in series; A DNPC bridge arm connected in parallel with the diode bridge arm, including a first switching device, a second switching device, a third switching device, and a fourth switching device connected in series in sequence, and a clamping diode branch, one end of the clamping diode branch is connected to the connection point of the first switching device and the second switching device, and the other end is connected to the connection point of the third switching device and the fourth switching device; A capacitor bank connected in parallel with the diode bridge arm and the DNPC bridge arm, and including a first capacitor and a second capacitor connected in series, the connection point of the first capacitor and the second capacitor forms the midpoint of the capacitor bank, and the midpoint of the clamping diode branch is connected to the midpoint of the capacitor bank; and A controller, the controller controls the mode of the PFC circuit to perform modulation, wherein the controller is configured to: When modulating the positive half-cycle of the modulation wave, within one switching period, cause the PFC circuit to switch between the +2 mode and the +0 mode via the +1 mode, and When modulating the negative half-cycle of the modulation wave, within one switching period, cause the PFC circuit to switch between the -2 mode and the -0 mode via the -1 mode, wherein Within the positive half-cycle of the modulation wave, the input current of the PFC circuit flows into from the midpoint of the DNPC bridge arm. In the +2 mode, only the first switching device and the second switching device in the DNPC bridge arm are turned on. In the +1 mode, only the third switching device in the DNPC bridge arm is turned on. And in the +0 mode, only the third switching device and the fourth switching device in the DNPC bridge arm are turned on, and Within the negative half-cycle of the modulation wave, the input current of the PFC circuit flows out from the midpoint of the DNPC bridge arm. In the -2 mode, only the third switching device and the fourth switching device in the DNPC bridge arm are turned on. In the -1 mode, only the second switching device in the DNPC bridge arm is turned on. And in the -0 mode, only the first switching device and the second switching device in the DNPC bridge arm are turned on.

9. The PFC circuit according to claim 8, wherein, The controller is further configured to: When the PFC circuit switches between the +2 mode and the +0 mode, make the duration of the PFC circuit in the +1 mode not greater than 10% of the switching period, and When the PFC circuit switches between the -2 mode and the -0 mode, make the duration of the PFC circuit in the -1 mode not greater than 10% of the switching period.

10. The PFC circuit according to claim 8 satisfies at least one of the following items: When the PFC circuit switches from the +0 mode via the +1 mode to the +2 mode, the controller sequentially turns off the fourth switch tube, turns on the second switch tube, turns off the third switch tube, and turns on the first switch tube; When the PFC circuit switches from the +2 mode via the +1 mode to the +0 mode, the controller sequentially turns off the first switch tube, turns on the third switch tube, turns off the second switch tube, and turns on the fourth switch tube; When the PFC circuit switches from the -2 mode via the -1 mode to the -0 mode, the controller sequentially turns off the fourth switch tube, turns on the second switch tube, turns off the third switch tube, and turns on the first switch tube; and When the PFC circuit switches from the -0 mode via the -1 mode to the -2 mode, the controller sequentially turns off the first switch tube, turns on the third switch tube, turns off the second switch tube, and turns on the fourth switch tube.

11. The PFC circuit according to claim 8 satisfies at least one of the following items: When the PFC circuit is switched from the +0 mode via the +1 mode to the +2 mode, the controller sequentially turns off the fourth switch tube, turns off the third switch tube, turns on the second switch tube, and turns on the first switch tube; When the PFC circuit is switched from the +2 mode via the +1 mode to the +0 mode, the controller sequentially turns off the first switch tube, turns off the second switch tube, turns on the third switch tube, and turns on the fourth switch tube; When the PFC circuit is switched from the -2 mode via the -1 mode to the -0 mode, the controller sequentially turns off the fourth switch tube, turns off the third switch tube, turns on the second switch tube, and turns on the first switch tube; and When the PFC circuit is switched from the -0 mode via the -1 mode to the -2 mode, the controller sequentially turns off the first switch tube, turns off the second switch tube, turns on the third switch tube, and turns on the fourth switch tube.

12. The PFC circuit according to claim 11, wherein an impedance is connected in parallel to each of the second switching transistor and the third switching transistor, and the resistance value of the impedance satisfies: where Za is the resistance value of the impedance, and C d is the capacitance value of the parasitic capacitance of the clamping diode in the clamping diode branch.

13. A power conversion device includes at least one power conversion unit, and each power conversion unit includes: The PFC circuit according to any one of claims 8-12; A first bridge arm, which is connected in parallel with the first capacitor of the PFC circuit and includes a fifth switch tube and a sixth switch tube connected in series; A second bridge arm, which is connected in parallel with the second capacitor of the PFC circuit and includes a seventh switch tube and an eighth switch tube connected in series; A transformer, one end of the primary winding of the transformer is connected to the connection point of the fifth switch tube and the sixth switch tube, and the other end is connected to the connection point of the seventh switch tube and the eighth switch tube; and, A secondary side circuit, which is connected to the secondary winding of the transformer.

14. The power conversion device according to claim 13 further includes a controller, and the controller is used for: Output the first control signal, the second control signal, the third control signal, and the fourth control signal to the control terminals of the fifth switching transistor, the sixth switching transistor, the seventh switching transistor, and the eighth switching transistor respectively, where The first control signal and the second control signal are complementary, the third control signal and the fourth control signal are complementary, and they are all square wave signals with a preset period. There is a first phase shift angle between the first control signal and the fourth control signal, and there is the first phase shift angle between the second control signal and the third control signal; and control the first phase shift angle to reduce the voltage difference between the first capacitor and the second capacitor.

15. The power conversion device according to claim 14, wherein the controller is further configured to: respectively detect a first voltage across the first capacitor and a second voltage across the second capacitor; determine the first phase shift angle according to the voltage difference between the first voltage and the second voltage. When the voltage difference is positive, reduce the first phase shift angle; when the voltage difference is negative, increase the first phase shift angle.

16. The power conversion device according to claim 13, comprising a plurality of power conversion units, and the input ends of the plurality of power conversion units are connected in series in sequence.

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