A method for manufacturing a double-layer wiring board

Abstract

The application discloses a preparation method of a double-layer circuit board, which comprises the following steps: printing a photosensitive ink layer on the surface of a peelable copper layer of a carrier sheet, manufacturing a first hollow pattern on the photosensitive ink layer, wherein the first hollow pattern comprises a pattern corresponding to a first circuit layer and a plurality of alignment mark holes; electroplating the hollow part of the first hollow pattern to manufacture the first circuit layer and the plurality of alignment mark points; removing the carrier sheet after pasting a peelable carrier plate, etching the copper layer shielding the alignment mark points, covering a photosensitive layer on the second surface of the copper layer, manufacturing a second hollow pattern on the photosensitive layer, wherein the hollow part of the second hollow pattern corresponds to the pattern of a second circuit layer; taking the alignment mark points as alignment points when manufacturing the second hollow pattern; plating tin on the surface of the copper layer in the hollow part of the second hollow pattern; etching the copper layer after removing the photosensitive layer to form the second circuit layer. The manufacturing process of the application has less alignment times, small alignment error and is convenient for manufacturing the double-layer circuit board.

Description

Technical Field

[0001] The present invention relates to circuit board manufacturing, and in particular to a method for manufacturing a double-layer circuit board. Background Art

[0002] During the manufacturing process of double-layer circuit boards, there are issues with the alignment of the second and first circuit layers. The traditional alignment method for double-layer circuit boards involves completing the first circuit layer on the first side of the substrate, then drilling positioning holes into the substrate according to pre-set positioning points. The substrate is flipped over, aligned using the positioning holes, and the second circuit layer is produced on the other side. The disadvantage of this traditional alignment process is that multiple alignments are required, resulting in large cumulative errors. This makes it easy for the two layers of a double-layer circuit board to misalign, making it unsuitable for the production of precision circuit boards. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a method for preparing a double-layer circuit board with small alignment error.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is a method for preparing a double-layer circuit board, comprising the following steps:

[0005] 101) One side of the carrier sheet is covered with a removable copper layer, a photosensitive ink layer is printed on the first surface exposed to the copper layer, the photosensitive ink layer is exposed and developed, and a first hollow pattern is formed on the photosensitive ink layer; the hollow portion of the first hollow pattern includes a pattern corresponding to the first circuit layer and a plurality of alignment marking holes near the edge of the copper layer;

[0006] 102) Electroplating the hollowed portion of the first hollowed pattern, first electroplating an alkali-resistant metal layer, then sequentially plating copper and solderable metal layers, to produce a first circuit layer and a plurality of alignment marking points;

[0007] 103) Affixing a peelable carrier plate to the exposed surfaces of the photosensitive ink layer, the first circuit layer, and the plurality of alignment marking points;

[0008] 104) removing the carrier sheet;

[0009] 105) etching away the copper layer that obscures the alignment mark points to expose the plurality of alignment mark points; covering the exposed second surface of the copper layer with a photosensitive layer, exposing and developing the photosensitive layer to produce a second hollow pattern on the photosensitive layer, the second hollow pattern corresponding to the pattern of the second circuit layer; when exposing the photosensitive layer, using the plurality of alignment mark points as exposure alignment points;

[0010] 106) Etching the copper layer to form a second circuit layer.

[0011] In the above-mentioned method for preparing a double-layer circuit board, in step 101, the carrier sheet is a stainless steel sheet, a protective adhesive layer is covered on the back of the stainless steel sheet, and copper is plated on the front of the steel sheet to obtain the copper layer.

[0012] In the above-described method for preparing a double-layer circuit board, in step 106, the photosensitive layer is covered on the second surface exposed by the copper layer by printing positive photosensitive adhesive; when printing the positive photosensitive adhesive, the area where the plurality of alignment marking points are located is avoided; after printing the positive photosensitive adhesive, etching is performed to etch away the copper layer that blocks the plurality of alignment marking points.

[0013] The above-described method for preparing a double-layer circuit board includes the following steps: in step 105, the hollow portion of the second hollow pattern corresponds to the pattern of the second circuit layer; in step 106, an alkali-resistant metal layer is plated on the surface of the copper layer in the hollow portion of the second hollow pattern; the photosensitive layer is removed and the copper layer is alkaline-etched to form the second circuit layer.

[0014] The above-described method for preparing a double-layer circuit board includes the following steps: in step 105, the solid portion of the second hollow pattern corresponds to the pattern of the second circuit layer; in step 106, the copper layer is acid-etched to form the solid portion of the second circuit layer; the photosensitive layer is removed, and a solderable metal layer is plated on the solid portion of the second circuit layer.

[0015] In the above-described method for preparing a double-layer circuit board, the double-layer circuit board with a removable carrier board is a chip packaging carrier board, and the double-layer circuit board includes a plurality of unit circuits arranged in a matrix, and the unit circuits include a plurality of electrodes, and the electrodes include top electrodes and bottom electrodes; the first circuit layer includes the bottom electrodes of all unit circuits, and the second circuit layer includes the top electrodes of all unit circuits, and the top electrode and the bottom electrode of the same electrode are interconnected.

[0016] In the above-described method for preparing a double-layer circuit board, in step 103, the hollow portion of the first hollow pattern includes a plurality of bottom electrode holes of all unit circuits; electroplating is performed on the plurality of bottom electrode holes of all unit circuits, first nickel plating, then copper plating, and finally tin plating, to form a plurality of bottom electrodes of all unit circuits.

[0017] In the above-mentioned method for preparing the double-layer circuit board, when the chip packaging carrier is used for chip packaging, the plurality of alignment marking points are used for alignment.

[0018] The manufacturing process of the double-layer circuit board of the present invention requires fewer alignment times and has a small alignment error, thereby facilitating the manufacture of a precise double-layer circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0020] Figure 1 is a schematic diagram of step 1 of the method for preparing a double-layer circuit board according to Embodiment 1 of the present application.

[0021] Figure 2 is a schematic diagram of step 2 of the method for preparing a double-layer circuit board according to Embodiment 1 of the present application.

[0022] Figure 3 is a schematic diagram of step 3 of the method for preparing a double-layer circuit board according to Embodiment 1 of the present application.

[0023] Figure 4 is a schematic diagram of step 4 of the method for preparing a double-layer circuit board according to Embodiment 1 of the present application.

[0024] Figure 5 is a schematic diagram of step 5 of the method for preparing a double-layer circuit board according to Embodiment 1 of the present application.

[0025] Figure 6 is a schematic diagram of step 6 of the method for preparing a double-layer circuit board according to Embodiment 1 of the present application.

[0026] Figure 7 is a schematic diagram of step 7 of the method for preparing a double-layer circuit board according to Embodiment 1 of the present application.

[0027] Figure 8 is a schematic diagram of step 8 of the method for preparing a double-layer circuit board according to Embodiment 1 of the present application.

[0028] Figure 9 is a schematic diagram of a single unit of a double-layer circuit board according to Embodiment 1 of the present application.

[0029] Figure 10 is a schematic diagram of a double-layer circuit board for chip packaging according to Embodiment 2 of the present application.

[0030] Figure 11 is a schematic diagram of a single unit of a chip package according to Embodiment 2 of the present application.

[0031] Figure 12 is a schematic diagram of step 5 of the method for preparing a double-layer circuit board according to Embodiment 3 of the present application.

[0032] Figure 13 is a schematic diagram of step 6 of the method for preparing a double-layer circuit board according to Embodiment 3 of the present application.

[0033] Figure 14 is a schematic diagram of step 7 of the method for preparing a double-layer circuit board according to Embodiment 3 of the present application.

[0034] Figure 15 is a schematic diagram of step 8 of the method for preparing a double-layer circuit board according to Embodiment 3 of the present application.

[0035] Figure 16This is a schematic diagram of a unit circuit of a double-layer circuit board according to embodiment 3 of the present invention. DETAILED DESCRIPTION

[0036] like Figure 9 As shown, the double-layer circuit board with a peelable carrier plate 8 attached thereto in embodiment 1 of the present invention is a chip packaging carrier. The double-layer circuit board includes a plurality of unit circuits arranged in a matrix. Figure 9 The figure shows a unit circuit of a double-layer circuit board. Each unit circuit includes two electrodes 6, each electrode including a top electrode 61 and a bottom electrode 62. The first circuit layer includes the bottom electrodes 62 of all unit circuits, and the second circuit layer includes the top electrodes 61 of all unit circuits. The top electrode 61 and bottom electrode 62 of the same electrode 6 are interconnected.

[0037] The preparation method of the chip packaging carrier (double-layer circuit board) in embodiment 1 of the present invention is as follows Figures 1 to 9 As shown, the following steps are included:

[0038] 1) If Figure 1 As shown, a stainless steel sheet is used as a carrier sheet 1, a protective adhesive layer 11 is covered on the back of the stainless steel carrier sheet 1, and a copper layer 2 is obtained by copper plating on the front of the stainless steel carrier sheet 1;

[0039] 2) If Figure 2 As shown, a photosensitive ink layer 3 is printed on the first exposed surface of the copper layer 2, and the photosensitive ink layer 3 is exposed and developed to produce a first hollow pattern on the photosensitive ink layer 3; the hollow portion of the first hollow pattern includes two bottom electrode holes 31 of all unit circuits and at least two alignment mark holes 32 near the edge of the copper layer 2;

[0040] 3) If Figure 3 As shown, electroplating is performed on the two bottom electrode holes 31 of all unit circuits, first nickel plating, then copper plating, and finally tin plating, to obtain a nickel plating layer 63, a copper plating layer 64, and a tin plating layer 65, forming two bottom electrodes 62 and two alignment marking points 4 of the first circuit layer of all unit circuits;

[0041] 4) If Figure 4 As shown, a peelable carrier plate 8 is pasted on the exposed surfaces of the photosensitive ink layer 3, the two bottom electrodes 62 and the two alignment marking points 4 using a high-temperature adhesive 81;

[0042] 5) If Figure 5 As shown, the stainless steel carrier sheet 1 with the protective adhesive layer 11 is removed and then turned over; a positive photoresist layer 5 is covered on the second surface exposed by the copper layer 2 by printing the positive photoresist; when printing the positive photoresist, avoid the area 41 where the two alignment marking points are located;

[0043] 6) If Figure 6As shown, the copper layer 2 covered with the positive photoresist is etched to remove the copper layer 21 that blocks the two alignment marking points;

[0044] 7) If Figure 7 As shown, the positive photoresist layer 5 is exposed and developed, and a second hollow pattern is produced on the positive photoresist layer 5. The hollow portion of the second hollow pattern includes two top electrode holes 51 of all unit circuits. When the positive photoresist layer 5 is exposed, the two alignment marking points 4 are used as exposure alignment points.

[0045] 8) If Figure 8 As shown, a solderable metal layer, i.e., a tinned layer 66, of a top electrode is formed on the surface of the copper layer 2 in the two top electrode holes 51;

[0046] 9) If Figure 9 As shown, the positive photosensitive adhesive layer 5 is removed, and the copper layer 2 is alkali-etched to form the top electrodes 61 of all unit circuits of the second circuit layer, thereby completing the production of the chip packaging carrier (double-layer circuit board) of Example 1.

[0047] like Figure 10 As shown, Example 2 of the present invention uses the chip packaging carrier 100 completed in Example 1 to package the chip 9. During chip packaging, two alignment marking points 4 of the chip packaging carrier 100 are used for alignment. Chip packaging includes welding the two bottom electrodes of the chip 9 to the top electrode of the unit circuit and covering them with encapsulation glue 10.

[0048] like Figure 11 As shown, after the chip 9 is packaged, the carrier plate 8 is peeled off to obtain the chip package 200.

[0049] The preparation method of the chip packaging carrier (double-layer circuit board) of embodiment 3 of the present invention is as follows Figures 1 to 4 as well as Figures 12 to 16 As shown. Steps 1 to 4 of the method for preparing a chip package carrier (double-layer circuit board) in Example 3 of the present invention are the same as Steps 1 to 4 in Example 1. Based on Step 4 in Example 1, the following steps are performed:

[0050] 5) If Figure 12 As shown, the stainless steel carrier sheet 1 with the protective adhesive layer 11 is removed and then turned over; a negative photoresist layer 7 is printed on the exposed second surface of the copper layer 2; when printing the negative photoresist, avoid the area 41 where the two alignment marking points are located;

[0051] 6) If Figure 13 As shown, the copper layer 2 covered with the negative photoresist is etched to remove the copper layer 21 that blocks the two alignment marking points;

[0052] 7) If Figure 14As shown, the negative photosensitive glue layer 7 is exposed and developed, and the second hollow pattern is made on the negative photosensitive glue layer 7, and the solid part 71 of the second hollow pattern corresponds to two top electrodes of all unit circuits; when the negative photosensitive glue layer 7 is exposed, two alignment mark points 4 are used as exposure alignment points;

[0053] 8) as shown in Figure 15 The copper layer 2 is acid etched to form the top electrode 61 of all unit circuits of the second circuit layer;

[0054] 9) as shown in Figure 16 The photosensitive glue layer 71 is removed, the top electrode 61 is tinned, the outer surface of the top electrode 61 forms a tinned layer, and the manufacturing of the chip packaging carrier (double-layer circuit board) of example 3 is completed.

[0055] The manufacturing method of the double-layer circuit board in the above examples simultaneously manufactures two alignment mark points when manufacturing the first circuit layer, and aligns the two alignment mark points when manufacturing the second circuit layer, so that the alignment error is small, and it is convenient to manufacture a precise double-layer circuit board.

Claims

1. A method for preparing a double-layer circuit board, characterized in that: The following steps are involved: 101) One side of the carrier sheet is covered with a removable copper layer, a photosensitive ink layer is printed on the first surface exposed to the copper layer, the photosensitive ink layer is exposed and developed, and a first hollow pattern is formed on the photosensitive ink layer; the hollow portion of the first hollow pattern includes a pattern corresponding to the first circuit layer and a plurality of alignment marking holes near the edge of the copper layer; 102) Electroplating the hollowed portion of the first hollowed pattern, first electroplating an alkali-resistant metal layer, then sequentially plating copper and solderable metal layers, to produce a first circuit layer and a plurality of alignment marking points; 103) Affixing a peelable carrier plate to the exposed surfaces of the photosensitive ink layer, the first circuit layer, and the plurality of alignment marking points; 104) removing the carrier sheet; 105) etching away the copper layer that obscures the alignment marking points to expose the plurality of alignment marking points; covering the exposed second surface of the copper layer with a photosensitive layer, exposing and developing the photosensitive layer to form a second hollow pattern on the photosensitive layer, the second hollow pattern corresponding to the pattern of the second circuit layer; When exposing the photosensitive layer, the plurality of alignment marking points are used as exposure alignment points; 106) Etching the copper layer to form a second circuit layer.

2. The method for preparing a double-layer circuit board according to claim 1, wherein: In step 101, the carrier sheet is a stainless steel sheet, the back of the stainless steel sheet is covered with a protective adhesive layer, and the front of the steel sheet is copper-plated to obtain the copper layer.

3. The method for preparing a double-layer circuit board according to claim 1, wherein: In step 106, the photosensitive layer is covered on the second surface exposed by the copper layer by printing photosensitive adhesive; the area where the plurality of alignment marking points are located is avoided when printing the photosensitive adhesive; and the positive photosensitive adhesive is printed and then etched to etch away the copper layer that blocks the plurality of alignment marking points.

4. The method for preparing a double-layer circuit board according to claim 1, wherein: The following steps are involved: In step 105, the hollow portion of the second hollow pattern corresponds to the pattern of the second circuit layer; in step 106, an alkali-resistant metal layer is plated on the surface of the copper layer in the hollow portion of the second hollow pattern; the photosensitive layer is removed and the copper layer is alkaline-etched to form the second circuit layer.

5. The method for preparing a double-layer circuit board according to claim 1, wherein: The following steps are involved: In step 105, the solid part of the second hollow pattern corresponds to the pattern of the second circuit layer; in step 106, the copper layer is acid-etched to form the solid part of the second circuit layer; the photosensitive layer is removed, and a solderable metal layer is plated on the solid part of the second circuit layer.

6. The method for preparing a double-layer circuit board according to claim 1, wherein: A double-layer circuit board with a peelable carrier board is a chip packaging carrier board. The double-layer circuit board includes a plurality of unit circuits arranged in a matrix. The unit circuits include a plurality of electrodes, and the electrodes include top electrodes and bottom electrodes. The first circuit layer includes the bottom electrodes of all unit circuits, and the second circuit layer includes the top electrodes of all unit circuits. The top electrode and the bottom electrode of the same electrode are interconnected.

7. The method for preparing a double-layer circuit board according to claim 6, wherein: In step 103, the hollow portion of the first hollow pattern includes a plurality of bottom electrode holes of all unit circuits; the plurality of bottom electrode holes of all unit circuits are electroplated, first with nickel, then with copper, and finally with tin, to form a plurality of bottom electrodes of all unit circuits.

8. The method for preparing a double-layer circuit board according to claim 6, wherein: When the chip packaging carrier is used for chip packaging, the plurality of alignment marking points are used for alignment.

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