Cleaning method for electronic components and manufacturing method for element chips

Abstract

A cleaning method for an electronic component includes: a preparation process of preparing an electronic component having a first surface covered with a protective film, a second surface opposite to the first surface, a side wall located between the first surface and the second surface, and an attachment adhered to the side wall; and a side wall cleaning process of cleaning the side wall of the electronic component. The side wall cleaning process includes: a deposition process of depositing a first film on the surfaces of the protective film and the attachment using a first plasma; and a removal process of removing at least a part of the attachment together with the first film deposited on the surface of the attachment using a second plasma. In the side wall cleaning process, the deposition process and the removal process are alternately repeated multiple times so that the protective film remains. Accordingly, the side wall can be cleaned while reducing the damage to the electronic component.

Description

Technical Field

[0001] The present invention relates to a method for cleaning electronic components and a method for manufacturing element chips. Background Art

[0002] As a dicing method for manufacturing element chips from a substrate, a dicing method using a cutting tool, a laser cutting method using a laser, a stealth dicing method, a plasma cutting method using plasma, etc. have been proposed. Among these, the plasma cutting method is being developed as a construction method that causes less mechanical damage to the substrate and suppresses the degradation of device characteristics (for example, Patent Documents 1 and 2). In the plasma cutting method, a technique called the Bosch process is sometimes used.

[0003] Prior Art Documents

[0004] Patent Documents

[0005] Patent Document 1: JP-T 2014-513868

[0006] Patent Document 2: JP-A 2016-146395 Summary of the Invention

[0007] Problems to be Solved by the Invention

[0008] The Bosch process is a method in which a cycle alternately including an etching step using a plasma of a fluorine-based gas and a film deposition step using a plasma of a fluorocarbon gas is repeated for a dicing channel (division area) that demarcates an element area of a substrate, to form a groove corresponding to the dicing channel and advance the excavation. By this method, a groove with a high aspect ratio can be formed. However, on the inner wall of the formed groove, that is, on the side wall of the obtained element chip, a polymer mainly composed of a fluorocarbon compound is likely to adhere. Further, fluorine atoms may be included in the above polymer. The higher the aspect ratio of the groove, the more easily the above polymer adheres.

[0009] The obtained element chip is supplied to a packaging process after being picked up. In the case where a polymer adheres to the side wall, the polymer may peel off during picking up and cause contamination, or in the packaging process, the adhesion between the sealing resin and the element chip may be reduced. Further, the fluorine atoms contained in the polymer are likely to move, which may cause a reduction in the reliability of the device.

[0010] In order to reduce the adhesion amount of the above polymer, it is only necessary to optimize the conditions of the Bosch process. The optimum values of the conditions of the Bosch process vary depending on the size of the desired element chip, the width of the division area, the depth of the groove, etc. Therefore, every time the above values are changed, it is necessary to optimize the conditions of the Bosch process, and this method is likely to damage productivity.

[0011] The above polymer is also removed by an ashing process performed after the Bosch process. The ashing process is performed to remove a protective film (mask) provided on the surface of the component chip, wherein the protective film (mask) is provided to protect the component area. In the ashing process, plasma generated by oxygen is generally used. The surface of the component chip is easily exposed to plasma, while its side wall is difficult to be exposed to plasma. Therefore, if the ashing process is performed to the extent of removing the attachments on the side wall, the protective film will be removed excessively, and the component area may sometimes be damaged.

[0012] In addition, there is a method of removing the above polymers by using a chemical solution. However, if a chemical solution is used, process management becomes complicated and waste liquid treatment is required, which costs a lot. As described above, a method of removing the polymers attached to the side walls of the component chip by a simpler method with a wide process window is sought.

[0013] Means for solving problems

[0014] One aspect of the present invention relates to a method for cleaning an electronic component, comprising: a preparation step of preparing an electronic component having a first surface covered by a protective film, a second surface on the opposite side of the first surface, a side wall between the first surface and the second surface, and an attachment attached to the side wall; and a side wall cleaning step of cleaning the side wall of the electronic component, the side wall cleaning step comprising: a deposition step of depositing a first film on the surface of the protective film and the attachment using a first plasma; and a removal step of removing at least a portion of the attachment together with the first film deposited on the surface of the attachment using a second plasma, wherein in the side wall cleaning step, the deposition step and the removal step are repeated alternately multiple times so that the protective film remains.

[0015] Another aspect of the present invention relates to a method for manufacturing an element chip, comprising: a substrate preparation step of preparing a substrate having a plurality of element regions and division regions defining the element regions and having a first surface and a second surface opposite to the first surface; a protective film formation step of forming a protective film on the first surface; an opening formation step of forming an opening in the protective film to expose the division regions in the first surface; an etching step of repeating a cycle including a first step of forming a recess corresponding to the exposed division regions by plasma treatment and a second step of depositing a second film on the inner wall of the recess by plasma treatment to obtain an electronic component having the first surface covered with the protective film, the second surface, sidewalls located between the first surface and the second surface, and attachments attached to the sidewalls; and a sidewall cleaning step of cleaning the sidewalls of the electronic component, the sidewall cleaning step comprising: a deposition step of depositing a first film on the surfaces of the protective film and the attachments using a first plasma; a removal step of removing at least a part of the attachments together with the first film deposited on the surfaces of the attachments using a second plasma, and in the sidewall cleaning step, the deposition step and the removal step are alternately repeated a plurality of times so that the protective film remains.

[0016] Another aspect of the present invention relates to a method for cleaning an electronic component, comprising: a preparation step of preparing an electronic component having a first surface covered with a protective film, a second surface opposite to the first surface, sidewalls located between the first surface and the second surface, and attachments attached to the sidewalls; and a sidewall cleaning step of cleaning the sidewalls of the electronic component, the sidewall cleaning step being performed by exposing the electronic component to a fourth plasma generated using a process gas containing a carbon oxide gas.

[0017] Another aspect of the present invention relates to a method for manufacturing an element chip, comprising: a substrate preparation step of preparing a substrate having a plurality of element regions and division regions defining the element regions and having a first surface and a second surface opposite to the first surface; a protective film formation step of forming a protective film on the first surface; an opening formation step of forming an opening in the protective film to expose the division regions in the first surface; an etching step of repeating a cycle including a first step of forming a recess corresponding to the exposed division regions by plasma treatment and a second step of depositing a second film on the inner wall of the recess by plasma treatment to obtain an electronic component having the first surface covered with the protective film, the second surface, sidewalls located between the first surface and the second surface, and attachments attached to the sidewalls; and a sidewall cleaning step of cleaning the sidewalls of the electronic component, the sidewall cleaning step being performed by exposing the electronic component to a fourth plasma generated using a process gas containing a carbon oxide gas.

[0018] Advantages of the Invention

[0019] According to the present invention, it is possible to clean the sidewalls while reducing the damage to the electron donor component.

[0020] The novel features of the present invention are described in the appended claims. For the present invention, both the structure and the content can be further understood well together with other objects and features of the present application through the following detailed description with reference to the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 FIG. is a cross-sectional view schematically showing the main part of an electron donor component supplied to the sidewall cleaning process according to Embodiment 1 of the present invention.

[0022] Figure 2 FIG. is a cross-sectional view schematically showing the main part of the electron donor component after the first deposition process according to Embodiment 1 of the present invention.

[0023] Figure 3 FIG. is a cross-sectional view schematically showing the main part of the electron donor component after the first removal process according to Embodiment 1 of the present invention.

[0024] Figure 4 FIG. is a cross-sectional view schematically showing the main part of the electron donor component after the Nth (N≥2) deposition process according to Embodiment 1 of the present invention.

[0025] Figure 5 FIG. is a cross-sectional view schematically showing the main part of the electron donor component after the Nth (N≥2) removal process according to Embodiment 1 of the present invention.

[0026] Figure 6 FIG. is a flowchart showing the cleaning method of the electron donor component according to Embodiment 1 of the present invention.

[0027] Figure 7A FIG. is a top view schematically showing the electron donor component prepared in the electron donor component preparation process according to Embodiments 1 and 2 of the present invention.

[0028] Figure 7B FIG. is Figure 7A a cross-sectional view taken along line A-A of

[0029] Figure 8 FIG. is a flowchart showing the manufacturing method of the element chip according to Embodiment 1 of the present invention.

[0030] Figure 9 FIG. is a top view schematically showing the substrate prepared through the substrate preparation process according to Embodiments 1 and 2 of the present invention.

[0031] Figure 10 It is a cross-sectional view schematically showing a part of the substrate prepared through the substrate preparation process according to Embodiment 1 and Embodiment 2 of the present invention.

[0032] Figure 11 It is a cross-sectional view schematically showing a part of the substrate after the protective film formation process according to Embodiment 1 and Embodiment 2 of the present invention.

[0033] Figure 12 It is a cross-sectional view schematically showing a part of the substrate after the opening formation process according to Embodiment 1 and Embodiment 2 of the present invention.

[0034] Figure 13 It is a cross-sectional view schematically showing the element chip fabricated in the etching process according to Embodiment 1 and Embodiment 2 of the present invention.

[0035] Figure 14 It is a cross-sectional view schematically showing the element chip after the protective film removal process according to Embodiment 1 and Embodiment 2 of the present invention.

[0036] Figure 15 It is a cross-sectional view schematically showing the structure of the plasma processing apparatus used in Embodiment 1 and Embodiment 2 of the present invention.

[0037] Figure 16 It is a block diagram of the plasma processing apparatus used in Embodiment 1 and Embodiment 2 of the present invention.

[0038] Figure 17 It is a graph showing the relationship between the etching rates in the longitudinal and transverse directions of the polymer and the pressure in the vacuum chamber.

[0039] Figure 18 It is a graph showing the relationship between the ratio of the etching rates in the longitudinal and transverse directions of the polymer and the pressure in the vacuum chamber.

[0040] Figure 19 It is a cross-sectional view schematically showing the main part of the electronic component supplied to the sidewall cleaning process according to Embodiment 2 of the present invention.

[0041] Figure 20 It is a cross-sectional view schematically showing the main part of the electronic component in the sidewall cleaning process according to Embodiment 2 of the present invention.

[0042] Figure 21 It is a cross-sectional view schematically showing the main part of the electronic component after the sidewall cleaning process according to Embodiment 2 of the present invention.

[0043] Figure 22This is a flowchart showing a method for cleaning electronic components according to Embodiment 2 of the present invention.

[0044] Figure 23 This is a flowchart showing a method for manufacturing a device chip according to the second embodiment of the present invention. DETAILED DESCRIPTION

[0045] Implementation Method 1

[0046] Embodiment 1 of the present invention is described. In this embodiment, the difference in ease of plasma treatment between the main surface and the side wall of the electronic component is used to clean the side wall of the electronic component. As a result, the attachments attached to the side wall can be removed while leaving the protective film (mask) covering the main surface of the electronic component intact. In the side wall cleaning process of this embodiment, the following deposition process and removal process are repeated.

[0047] In the deposition process, the first plasma is used to deposit the first film on the surface of the protective film and the side wall of one main surface (first surface) of the electronic component. The first film is deposited thicker on the surface of the protective film that is easily irradiated with plasma. On the other hand, the first film is deposited thinner on the side wall than on the surface of the protective film. The first surface is protected by the protective film and the first film.

[0048] In the removal process, the second plasma is used to remove at least a portion of the deposits attached to the side wall together with the first film. As described above, since the first film is deposited thinner on the side wall, the deposits attached to the side wall are also removed together with the first film by the removal process. On the other hand, since the first film is deposited thicker on the first surface, the protective film is not etched by the removal process, or the etching amount thereof is suppressed.

[0049] By repeating the above-mentioned deposition process and removal process, the deposition and removal of the first film are repeated on the first surface. In other words, even if the deposition process and the removal process are repeated, the etching of the protective film itself can be suppressed. Therefore, the damage to the first surface caused by the side wall cleaning process can be suppressed. On the other hand, on the surface of the side wall, the deposition and removal of the first film are repeated, and the attachments are also removed when the first film is removed. In this way, the side wall is cleaned. The number of repetitions is not particularly limited, and it can be repeated until the attachments on the side wall are removed. As mentioned above, this is to suppress the etching of the protective film itself.

[0050] The cleaning method according to this embodiment is particularly suitable for cleaning the sidewalls of electronic components that have undergone the Bosch process. The Bosch process alternately repeats the following steps on a substrate: the first step of forming recesses corresponding to the dividing regions by plasma treatment; and the second step of depositing a second film on the inner walls of the recesses by plasma treatment. Therefore, deposition films, reaction products of the deposition films with plasma, etc. (adhesions) are likely to adhere to the sidewalls of the formed element chips. Further, irregularities called scallops are formed on the sidewalls. It is difficult to remove the adhesions attached to the scallops. According to the cleaning method according to this embodiment, such adhesions can be removed by a simple method. This embodiment includes a method for manufacturing an element chip having an etching process using the Bosch process.

[0051] The sidewall cleaning process will be described in detail below.

[0052] The sidewall cleaning process includes a deposition process and a removal process. In the sidewall cleaning process, the deposition process and the removal process are alternately repeated multiple times.

[0053] (a) Deposition process

[0054] On the sidewalls of the electronic components, for example, adhesions containing a film deposited by the Bosch process (deposition film) and reaction products of the deposition film with plasma are attached. Such adhesions are mainly composed of a polymer (fluorocarbon) containing carbon atoms and fluorine atoms, and further contain silicon and oxygen. In this process, a first film is further deposited on the surfaces of the protective film and the adhesions (i.e., the sidewalls).

[0055] In the deposition of the first film, for example, a first plasma generated using a first process gas containing carbon atoms (C) is used. The first film is efficiently deposited on the surfaces of the protective film and the sidewalls using a gas containing carbon atoms. Examples of the gas containing carbon atoms include C 4 F 8 、C 5 F 8 and other fluorocarbon gases; CHF 3 、CH 2 F 2 and other fluorohydrocarbons.

[0056] The first process gas may contain other gases, such as Ar, CH 4 、H 2 、N 2 etc. The proportion of the gas containing carbon atoms in the first process gas may be 10% by volume or more and less than 100% by volume, or may be 30% by volume or more and 98% by volume or less.

[0057] The thickness of the first film deposited on the surface of the protective film is not particularly limited. The thickness of the first film deposited on the surface of the protective film may be appropriately set in consideration of the conditions of the removal process, productivity, etc. The thickness of the first film deposited on the surface of the protective film may be 3 nm or more and 660 nm or less, or may be 50 nm or more and 300 nm or less. Such a first film can be formed under the conditions of a deposition rate of 200 nm / min or more and 2000 nm / min or less, and a deposition time of 1 second or more and 20 seconds or less.

[0058] It is desirable that the first film does not deposit excessively on the surface of the sidewall. The ratio D2 / D1 of the thickness D2 of the first film deposited on the surface of the sidewall to the thickness D1 of the first film deposited on the surface of the protective film is preferably 4 / 10 or less, more preferably 3 / 10 or less. D2 / D1 is preferably 1 / 100 or more, more preferably 1 / 50 or more. The thickness D2 is the average value of any five points of the thickness of the first film deposited on the surface of the sidewall. Generally, the closer to the first surface, the thicker the first film deposited on the surface of the sidewall.

[0059] The conditions for generating the first plasma are appropriately set corresponding to the thickness and composition of the first film, etc. Among these, the first plasma is desirably processed under the following conditions, that is, a first film of sufficient thickness is deposited on the surface of the protective film, and on the other hand, the first film is not deposited excessively on the surface of the sidewall. Thereby, the adherents can be removed with a small number of cycles, and the productivity can be improved.

[0060] Let the speed of depositing the first film on the surface of the protective film in the deposition process be speed RD1. Let the speed of depositing the first film on the surface of the sidewall in the deposition process be speed RD2. From the above viewpoints, the ratio RD2 / RD1 of speed RD2 to speed RD1 is preferably 4 / 10 or less, more preferably 3 / 10 or less. RD2 / RD1 is preferably 1 / 100 or more, more preferably 1 / 50 or more.

[0061] The deposition rate of the first film can be controlled, for example, in a plasma processing apparatus used in the sidewall cleaning process, by the high-frequency power applied to the first electrode, the high-frequency power applied to the second electrode built in the stage, the pressure in the processing chamber, the flow rate of the gas, and the temperature of the electronic component, etc., where the first electrode is arranged to face the stage on which the electronic component is placed. By applying high-frequency power to the second electrode, a bias voltage is applied to the stage. Among them, it is desirable that the high-frequency power applied to the second electrode in the deposition process is low, and it can be 0 W. Thereby, the speed RD2 of the first film depositing on the surface of the sidewall can be suppressed.

[0062] In order to deposit a first film having a sufficient thickness on the surface of the protective film without excessively depositing the first film on the surface of the side wall, a method of increasing the pressure in the processing chamber can be cited. In particular, a method of increasing the pressure in the processing chamber while increasing the absolute value of the deposition rate of the first film is effective. As a result, the difference between the amount of the first film deposited on the surface of the protective film and the amount deposited on the surface of the side wall per unit time becomes larger, and RD2 / RD1 tends to become smaller.

[0063] In order to increase the pressure in the processing chamber, for example, a method of increasing the gas flow rate can be cited. In order to increase the absolute value of the deposition rate of the first film, for example, a method of increasing the gas flow rate, a method of increasing the high-frequency power applied to the first electrode, a method of reducing the temperature of the electronic component, etc. can be cited. Among them, for the gas flow rate, an upper limit value (threshold) is set corresponding to the power value of the high-frequency power applied to the first electrode. Therefore, by adjusting the exhaust speed on the basis of setting the gas flow rate to near the upper limit value, the increase in the pressure in the processing chamber and the increase in the absolute value of the deposition rate of the first film can be taken into account. It is also possible to combine two or more of the above methods. For example, it is also possible to cool the electronic components while increasing the gas flow rate, thereby increasing the high-frequency power applied to the first electrode. In the deposition process, the pressure in the processing chamber is preferably above 10Pa. The cooling of the electronic components can be carried out, for example, by strongly adsorbing them to the cooled carrier.

[0064] The conditions for generating the first plasma are, for example, as follows. 4 F 8 The pressure in the vacuum chamber is between 100 sccm and 600 sccm. The pressure in the vacuum chamber is between 10 Pa and 40 Pa, the high frequency power PD1 is between 1000 W and 4800 W, and the high frequency power PD2 is between 0 W and 100 W. The stage temperature is between -15°C and 15°C. According to the above conditions, the deposition rate is between 100 nm / min and 2500 nm / min. The processing time can be set in consideration of the thickness of the first film deposited on the surface of the protective film. The processing time is, for example, between 1 second and 10 seconds.

[0065] (b) Removal process

[0066] In this process, at least a portion of the attachments attached to the side wall of the electronic component is removed by the second plasma. The attachments are removed together with the first film. The first film on the surface of the protective film can also be removed. Among them, since the first film on the protective film is thick, damage to the protective film can be suppressed.

[0067] In the removal of the attached matter and / or the first film (hereinafter sometimes collectively referred to as the attached matter, etc.), for example, a second plasma generated using a second process gas containing an oxygen atom is used. The attached matter, etc. containing an organic substance as a main component is efficiently removed by the second plasma derived from the gas containing an oxygen atom. As the gas containing an oxygen atom, for example, O 2 、CO 2 、CO, etc.

[0068] The second process gas may contain other gases, for example, a fluorine-containing gas. Thereby, the removal effect of the attached matter, etc. is likely to become high. As the fluorine-containing gas, for example, CF 4 、C 4 F 8 and other carbon fluoride gases, CHF 3 and other fluorinated hydrocarbons, SF 6 and the like. The proportion of the gas containing an oxygen atom in the second process gas may be 10% by volume or more and less than 100% by volume, or may be 30% by volume or more and 98% by volume or less.

[0069] The conditions for generating the second plasma are appropriately set according to the amount and composition of the attached matter, etc. Among them, the second plasma is desirably generated under the condition that the first film on the protective film is not excessively removed. Thereby, damage to the protective film can be suppressed and the first surface can be protected.

[0070] Let the speed of removing the first film on the surface of the protective film in the removal process be speed RR1. Let the speed of removing the first film on the surface of the sidewall in the removal process be speed RR2. From the above viewpoints, the ratio RR2 / RR1 of speed RR2 to speed RR1 is preferably 3 / 10 or more and 10 / 10 or less, for example.

[0071] The removal speed of the first film on the surface of the sidewall can also be controlled by the high-frequency power applied to the first electrode, the high-frequency power applied to the second electrode, the pressure in the processing chamber, the gas flow rate, and the temperature of the stage, etc.

[0072] In order to prevent the first film on the protective film from being excessively removed, a method of increasing the pressure in the processing chamber can be cited, similar to the deposition process. In particular, a method of increasing the pressure in the processing chamber while increasing the absolute value of the removal rate of the first film is effective. To increase the absolute value of the removal rate of the first film, for example, methods such as increasing the gas flow rate, increasing the high-frequency power applied to the first electrode, and increasing the temperature of the electronic component can be cited. Two or more of the above methods can be combined. For example, the gas flow rate can be increased while increasing the temperature of the electronic component, and then the high-frequency power applied to the first electrode can be increased. To increase the temperature of the electronic component, a method of weakening the adsorption force of the electronic component to the stage can be cited. The adsorption force of the electronic component to the stage is controlled by the voltage value applied to the ESC electrode described later. In the removal process, the pressure in the processing chamber is preferably 20 Pa or more, and more preferably 30 Pa or more.

[0073] The conditions for generating the second plasma are as follows, for example. As the process gas, O 2 and CF 4 (flow ratio CF 4 / O 2 = 0% or more and 10% or less) of the mixed gas is supplied to the vacuum chamber at 50 sccm or more and 600 sccm or less. The pressure in the vacuum chamber is 10 Pa or more and 60 Pa or less, the high-frequency power PR1 is 1000 W or more and 4800 W or less, the high-frequency power PR2 is 0 W or more and 100 W or less, and the stage temperature is -15°C or more and 15°C or less. Under the above conditions, the removal rate becomes 200 nm / min or more and 3000 nm / min or less. The processing time can be set to the extent that the film thickness of the first film deposited on the surface of the protective film in the deposition process is removed. The processing time is, for example, 0.1 second or more and 200 seconds or less, and preferably 6 seconds or more and 15 seconds or less.

[0074] The deposition process and the removal process are alternately repeated multiple times. Each time the removal process is performed, the amount of deposits on the sidewalls continuously decreases. On the other hand, the thickness of the protective film is maintained. Each deposition process can be performed under the same conditions or under different conditions. For example, the processing time in the deposition process can be gradually shortened. Each removal process can also be performed under the same conditions or under different conditions. For example, the processing time in the removal process can be gradually extended. Or, the high-frequency power PR2 applied to the second electrode can be changed over time in the removal process. The sidewall cleaning process can start from the deposition process or from the removal process. Among them, it is desirable to end with the removal process.

[0075] The sidewall cleaning process is performed as described above, taking advantage of the difference in the ease of plasma treatment between the main surface and the sidewalls of the electronic component. The sidewall cleaning process is preferably performed such that the ratio RD2 / RD1 of the speed RD2 to the speed RD1 in the deposition process and the ratio RR2 / RR1 of the speed RR2 to the speed RR1 in the removal process satisfy the relationship RD2 / RD1 < RR2 / RR1. That is, it is preferable to perform the sidewall cleaning process under the following conditions: compared with the first film on the protective film, it is more difficult to deposit the first film on the sidewalls, while the first film on the sidewalls is more easily removed. Thereby, the cleaning of the sidewalls can be performed more efficiently.

[0076] In order to satisfy the relationship RD2 / RD1 < RR2 / RR1, for example, it is sufficient to control the pressure PD1 in the processing chamber during the deposition process and the pressure PR1 in the processing chamber during the removal process to satisfy the relationship PD1 < PR1.

[0077] In addition, the high-frequency power PD2 applied to the second electrode during the deposition process and the high-frequency power PD2 applied to the second electrode during the removal process can be controlled to satisfy the relationship PD2 ≤ PR2.

[0078] In the sidewall cleaning process, multiple electronic components can be processed simultaneously. Thereby, the productivity is improved. In this case, the distance W between the opposing sidewalls of any two electronic components and the height H of the sidewall of any one of the electronic components can satisfy the relationship H ≥ 5 × W. In the case where there are such high aspect ratio irregularities, according to the present embodiment, it is also possible to remove the attachments adhering to the sidewalls while maintaining the protective film covering the main surface of the electronic component unchanged. Furthermore, the relationship H ≤ 50 × W can also be satisfied.

[0079] The height H of the above-mentioned sidewalls is not particularly limited. The height H of the sidewalls is, for example, 20 μm or more and 700 μm or less. The distance W between the sidewalls is also not particularly limited. The distance W between the sidewalls is, for example, 4 μm or more and 60 μm or less.

[0080] The distance W is the average value of the shortest distances between any two points at the ends on the first surface side of the opposing sidewalls of any two electronic components. In the case where the entire sidewalls are not opposed, it is sufficient to measure the shortest distance between the opposing portions of the sidewalls. The height H of the sidewalls is the lower one of the average values of the heights of any two points of the two sidewalls (or portions thereof) used to calculate the distance W. The height of the sidewall is the shortest distance between the first surface and the second surface to which the sidewall is connected.

[0081] Hereinafter, an electronic component having a semiconductor layer and a wiring layer will be exemplified, and the present embodiment will be specifically described with reference to the accompanying drawings. However, the present embodiment is not limited thereto.

[0082] Figure 1 It is a cross-sectional view schematically showing the main part of an electronic component supplied to a sidewall cleaning process. A plurality of electronic components 200 are supported by a holding piece 22 described later. The holding piece 22 is used to improve operability and is not necessarily required.

[0083] The electronic component 200 includes a semiconductor layer 11 and a wiring layer 12 disposed on the first surface 200X side of the semiconductor layer 11. The first surface 200X is covered with a protective film 40. Serrations are formed on the sidewall 200Z of the electronic component 200. An attachment 60 is attached to the sidewall 200Z. In addition, in the illustrated example, the serrations and the attachment are exaggeratedly shown.

[0084] Figure 2 It is a cross-sectional view schematically showing the main part of the electronic component after the first deposition process. A first film 50 is deposited on the surface of the protective film 40 and the surface of the sidewall 200Z, respectively. Among them, the first film 50 deposited on the surface of the sidewall 200Z is thinner than the first film 50 deposited on the surface of the protective film 40.

[0085] Figure 3 It is a cross-sectional view schematically showing the main part of the electronic component after the first removal process. The first film 50 deposited by the deposition process is removed. On the sidewall 200Z, a part of the attachment 60 is also removed together with the first film 50, and the layer of the attachment 60 becomes thinner.

[0086] Figure 4 It is a cross-sectional view schematically showing the main part of the electronic component after the Nth (N≥2) deposition process. A first film 50 is deposited on the surface of the protective film 40 and the surface of the sidewall 200Z, respectively. The first film 50 deposited on the surface of the sidewall 200Z is thinner than the first film 50 deposited on the surface of the protective film 40.

[0087] Figure 5 It is a cross-sectional view schematically showing the main part of the electronic component after the Nth (N≥2) removal process. The first film 50 deposited by the Nth (N≥2) deposition process is removed. On the sidewall 200Z, the remaining part of the attachment 60 is removed together with the first film 50, and the sidewall 200Z is exposed.

[0088] Next, a cleaning method including the above sidewall cleaning process will be described.

[0089] A. Cleaning method for electronic components

[0090] The cleaning method for electronic components according to the present embodiment includes: a preparation process of preparing an electronic component having a first surface covered with a protective film, a second surface opposite to the first surface, a sidewall located between the first surface and the second surface, and an attachment attached to the sidewall; and the above sidewall cleaning process for cleaning the sidewall of the electronic component.Figure 6 It is a flowchart showing the cleaning method according to this embodiment.

[0091] (i) Preparation process (S01) of electronic components

[0092] Prepare at least one electronic component having a first surface covered with a protective film, a second surface opposite to the first surface, and side walls located between the first surface and the second surface. The electronic component is, for example, an element chip manufactured by plasma cutting a substrate through the Bosch process. Serrations, that is, recesses and protrusions, may be formed on the side walls.

[0093] The electronic component, for example, includes a semiconductor layer and a wiring layer.

[0094] The semiconductor layer includes, for example, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), etc. The thickness of the semiconductor layer in the electronic component is not particularly limited. For example, it is 20 μm or more and 1000 μm or less, and may be 50 μm or more and 300 μm or less.

[0095] The wiring layer forms, for example, a semiconductor circuit, electronic component elements (LEDs, lasers, MEMS, etc.), and may include an insulating film, a metal material, a resin layer (e.g., polyimide), a resist layer, an electrode pad, bumps, etc. The insulating film may be included as a laminate (multi-layer wiring layer or rewiring layer) with the wiring metal material.

[0096] The protective film includes, for example, a thermosetting resin such as polyimide, a photoresist such as phenolic resin, or a water-soluble resist such as acrylic resin, etc., which are so-called resist materials. The protective film formed of such a resist material is usually formed to protect the electronic component during manufacturing and is removed during the period before the completion of the electronic component. The insulating film (silicon nitride, silicon oxide film, etc.) and / or resin layer (polyimide) disposed on the outermost surface of the electronic component may be used as the protective film. The protective film formed of such an insulating film is formed not only to protect the electronic component during manufacturing but also to protect the electronic component after circulation and is not removed.

[0097] The thickness of the protective film is not particularly limited. Among them, when the protective film is formed of the above-mentioned resist material, the thickness of the protective film is preferably such that it cannot be completely removed by the etching process using the Bosch process. For example, calculate the amount (thickness) by which the protective film is etched in the above etching process, and set the thickness of the protective film to be equal to or greater than the etching amount. The thickness of the protective film is, for example, 5 μm or more and 60 μm or less. In addition, when the protective film is the above-mentioned insulating film, etc., adjust the conditions of the Bosch process so that the etching amount of the protective film in the above etching process is several μm or less.

[0098] When processing multiple electronic components simultaneously in a sidewall cleaning process, from the perspective of operability, it is desirable to paste the multiple electronic components on a holding sheet fixed to a frame. A member having a frame and a holding sheet fixed to the frame is called a transport carrier.

[0099] (Transport carrier)

[0100] The frame is a box body having an opening large enough to surround multiple electronic components, with a given width and a generally fixed thin thickness. The frame has a rigidity sufficient to transport while holding the holding sheet and multiple electronic components. The shape of the opening of the frame is not particularly limited, and can be, for example, a polygon such as a circle, a rectangle, or a hexagon. As the material of the frame, for example, metals such as aluminum and stainless steel, resins, etc. can be cited.

[0101] The material of the holding sheet is not particularly limited. Among these, in terms of easy pasting of electronic components, the holding sheet preferably includes an adhesive layer and a flexible non - adhesive layer.

[0102] The material of the non - adhesive layer is not particularly limited. For example, polyolefins such as polyethylene and polypropylene, polyesters such as polyvinyl chloride and polyethylene terephthalate, etc., thermoplastic resins can be cited. Rubber components (such as ethylene - propylene rubber (EPM), ethylene - propylene - diene rubber (EPDM), etc.) for adding stretchability, plasticizers, softeners, antioxidants, conductive materials, etc. can be incorporated in the resin film. In addition, the above - mentioned thermoplastic resin can have functional groups showing photopolymerization reaction such as acrylic groups. The thickness of the non - adhesive layer is not particularly limited, for example, it is 50μm or more and 300μm or less, preferably 50μm or more and 150μm or less.

[0103] The outer periphery of the surface having the adhesive layer (adhesive surface) is pasted on one surface of the frame, covering the opening of the frame. By pasting one main surface (the second surface) of the electronic component on the part of the adhesive surface exposed from the opening of the frame, the electronic component is held on the holding sheet. The electronic component can be held on the holding sheet via a die attach film (DAF).

[0104] The adhesive layer is preferably composed of an adhesive component whose adhesive force decreases by irradiation with ultraviolet rays (UV). Thus, when picking up the electronic component after the protective film removal process, by performing UV irradiation, the electronic component can be easily peeled off from the adhesive layer, making it easy to pick up. For example, a UV - curable acrylic adhesive is coated on one side of the non - adhesive layer to a thickness of 5μm or more and 100μm or less (preferably 5μm or more and 15μm or less) to obtain the adhesive layer.

[0105] The preparation process of the above-described electronic component may include: a substrate preparation process of preparing a substrate having a plurality of element regions and dividing regions that define the element regions, and having a first surface and a second surface opposite to the first surface; a protective film formation process of forming a protective film covering the first surface; an opening formation process of forming an opening in the protective film to expose the dividing region in the first surface; and an etching process of repeating a cycle including a first step of forming a concave portion corresponding to the exposed dividing region by plasma treatment and a second step of depositing a second film on the inner wall of the concave portion by plasma treatment. These processes will be described later. Thus, a plurality of electronic components are prepared with a given interval therebetween.

[0106] Figure 7A FIG. is a top view schematically showing an electronic component prepared in the preparation process of the electronic component. Figure 7B is Figure 7A a cross-sectional view taken along line A-A of. In Figure 7B for convenience, attached substances are omitted.

[0107] The transport carrier 20 includes a frame 21 and a holding piece 22 fixed to the frame 21. Notches 21a and cut corners 21b for positioning are provided in the frame 21. The holding piece 22 has an adhesive surface 22X and a non-adhesive surface 22Y, and the outer peripheral edge of the adhesive surface 22X is pasted to one surface of the frame 21. The second surface 200Y of the electronic component 200 is pasted to the portion of the adhesive surface 22X that is exposed from the opening of the frame 21.

[0108] A plurality of electronic components 200 are pasted on the adhesive surface 22X of the holding piece 22 at intervals. Such electronic components 200 are obtained by plasma cutting a substrate through a Bosch process. The electronic component 200 includes a semiconductor layer 11 and a wiring layer 12 laminated on the first surface 200X side of the semiconductor layer 11. A protective film 40 is formed on the first surface 200X of the electronic component 200.

[0109] (ii) Sidewall cleaning process (S02)

[0110] Clean the sidewalls of the element chip.

[0111] The sidewall cleaning process is performed through the above-described (a) deposition process (S021) and (b) removal process (S022). According to the above sidewall cleaning process, the attached substances on the sidewalls can be removed while the protective film remains. The deposition process and the removal process are repeated until the attached substances are removed.

[0112] (iii) Protective film removal process (S03)

[0113] The protective film can be removed after the final removal process.

[0114] In the removal of the protective film, for example, use is made of oxygen (O2 ) The third plasma generated by the third process gas. The third process gas contains a fluorine-containing gas together with O 2 . As the fluorine-containing gas, the same compounds as those described above can be cited. The proportion of O 2 in the third process gas can be 10% by volume or more and less than 100% by volume, or can be 30% by volume or more and 98% by volume or less.

[0115] The conditions for generating the third plasma are appropriately set according to the amount and composition of the protective film, etc.

[0116] The conditions for generating the third plasma are as follows, for example. As the ashing gas, a mixed gas of CF 4 and O 2 (flow rate ratio CF 4 / O 2 = 0% or more and 10% or less) is supplied to the vacuum chamber at 50 sccm or more and 600 sccm or less. The pressure in the vacuum chamber is 1 Pa or more and 30 Pa or less, the high-frequency power PA1 applied to the first electrode is 1000 W or more and 4800 W or less, and the high-frequency power PA2 applied to the second electrode is 0 W or more and 100 W or less. It is desirable to set the high-frequency power PA2 applied to the second electrode in the protective film removal process to be smaller than the applied power applied to the second electrode in the etching process. The processing time is appropriately set according to the amount of the protective film, for example, 3 seconds or more and 300 seconds or less.

[0117] In the case where the protective film is water-soluble, the protective film can be removed by water washing instead of the third plasma. In the case where the protective film is an insulating film and / or a resin layer disposed on the outermost surface of the electronic component, the protective film may not be removed. This is because such a protective film is formed not only to protect the electronic component during manufacturing but also to protect the electronic component after circulation.

[0118] B. Method for manufacturing an element chip

[0119] The method for manufacturing an element chip according to the present embodiment includes: a substrate preparation step of preparing a substrate having a plurality of element regions and division regions defining the element regions and having a first surface and a second surface opposite to the first surface; a protective film formation step of forming a protective film on the first surface; an opening formation step of forming an opening in the protective film to expose the division regions in the first surface; an etching step of repeating a cycle including a first step of forming a recess corresponding to the exposed division regions by plasma treatment and a second step of depositing a second film on the inner wall of the recess by plasma treatment to obtain an electronic component having a first surface covered with a protective film, a second surface, side walls located between the first surface and the second surface, and an attachment attached to the side walls; and a side wall cleaning step of cleaning the side walls of the electronic component.

[0120] The sidewall cleaning process includes: a deposition process in which a first film is deposited on the surface of the protective film and the attachment using a first plasma; and a removal process in which at least a part of the attachment and the first film deposited on the surface of the attachment are removed using a second plasma. The deposition process and the removal process are alternately repeated multiple times so that the protective film remains. Figure 8 It is a flowchart showing a method for manufacturing an element chip according to the present embodiment.

[0121] (1) Substrate preparation process (S11)

[0122] First, a substrate to be processed is prepared.

[0123] (Substrate)

[0124] The substrate has a first surface and a second surface, and has a plurality of element regions and division regions that define the element regions. The substrate has the above-described semiconductor layer. The element regions of the substrate may also have the above-described wiring layer. The division regions of the substrate may also have a metal material such as an insulating film and a TEG (Test Element Group). By etching the substrate in the division regions, a plurality of element chips are obtained.

[0125] The size of the substrate is not particularly limited, for example, it is about 50 mm to 300 mm in maximum diameter. The shape of the substrate is not particularly limited, for example, it is circular or square. In addition, a notch such as an orientation flat or a notch may be provided in the substrate.

[0126] The shape of the division region is not limited to a straight line, and it may be set according to the shape of the desired element chip, and it may be zigzag or wavy. In addition, as the shape of the element chip, for example, a rectangle, a hexagon, etc. can be cited.

[0127] The width of the division region is not particularly limited, and it may be appropriately set according to the size of the substrate, the element chip, etc. The width of the division region is, for example, 10 μm or more and 300 μm or less. The widths of the plurality of division regions may be the same or different. Usually, a plurality of division regions are arranged on the substrate. The distance between adjacent division regions is not particularly limited, and it may be appropriately set according to the size of the substrate, the element chip, etc.

[0128] The second surface of the substrate may be pasted on a holding piece fixed to a frame. Thereby, the workability is improved. By cutting the substrate pasted on the holding piece, a plurality of element chips arranged at intervals are obtained on the holding piece. The shape, material, etc. of the frame and the holding piece are as described above.

[0129] (2) Protective film formation process (S12)

[0130] Form a protective film on the first surface of the coated substrate.

[0131] The protective film is provided to protect the component area of the substrate from the influence of plasma or the like. After the etching process, the protective film is removed. The material and thickness of the protective film are as described above.

[0132] For example, after forming the resist material into a sheet, the sheet is attached to the substrate, or the raw material liquid of the resist material is applied to the substrate by methods such as spin coating or spraying, thereby forming a protective film. By changing the coating amount of the raw material liquid while performing the coating, the thickness of the protective film can be partially changed. Spin coating and spraying can also be used in combination to adjust the coating amount.

[0133] (3) Opening formation process (S13)

[0134] Openings are formed in the protective film to expose the dividing area of the substrate.

[0135] The openings are formed, for example, by removing the area corresponding to the dividing area in the protective film formed of photoresist by photolithography. The area corresponding to the dividing area in the protective film formed of thermosetting resin or water-soluble resist can also be patterned by laser scribing to form openings.

[0136] The openings can be formed by removing the protective film and the wiring layer in the dividing area. The removal of the wiring layer in the dividing area can be performed in the etching process described later. In this case, the conditions for generating the plasma for removing the wiring layer and the conditions for generating the plasma for etching the substrate can be different.

[0137] (4) Etching process (S14)

[0138] The substrate is exposed to plasma, and the dividing area exposed from the openings is etched to the second surface, and a plurality of component chips are formed from the substrate. The plurality of component chips are obtained while being held on the holding sheet.

[0139] The etching process is performed by the so-called Bosch process. In the Bosch process, the substrate is subjected to one or more cycles including a first step of forming a groove corresponding to the dividing area and a second step of depositing a film on the inner wall of the groove. Further, a step of removing the above-mentioned film (deposited film) is performed between the first step and the second step.

[0140] In the first step of the first cycle, a shallow recess corresponding to the divided region is first formed. Next, in the second step, a deposition film is formed on the inner wall of the formed shallow recess. The second cycle starts from the step of removing the deposition film. In the deposition film removal step, anisotropic etching is performed. That is, the deposition film covering the bottom among the inner walls of the recess is removed. Next, the first step is performed to isotropically etch the bottom of the recess. After the first step, the second step is performed again to form a deposition film on the inner wall of the recess. By repeating the second cycle (deposition film removal step, first step, and second step) in this way, at least one element chip having a first surface, a second surface, and side walls covered with a protective film is obtained. An attachment including a deposition film, a reaction product of the deposition film and plasma, etc. is attached to the side walls of the formed element chip. Serrations may also be formed on the side walls.

[0141] The processing conditions in the deposition film removal step are as follows, for example. As the process gas, SF 6 is supplied to the vacuum chamber at 200 sccm or more and 1000 sccm or less, and O 2 is supplied at 0 sccm or more and 20 sccm or less. The pressure in the vacuum chamber is 5 Pa or more and 30 Pa or less, the high-frequency power applied to the first electrode is 1500 W or more and 4800 W or less, the high-frequency power applied to the second electrode is 50 W or more and 200 W or less. The processing time is 1 second or more and 5 seconds or less.

[0142] The processing conditions in the first step are as follows, for example. As the process gas, SF 6 is supplied to the vacuum chamber at 200 sccm or more and 1000 sccm or less, and O 2 is supplied at 0 sccm or more and 20 sccm or less. The pressure in the vacuum chamber is 5 Pa or more and 30 Pa or less, the high-frequency power applied to the first electrode is 1500 W or more and 4800 W or less, the high-frequency power applied to the second electrode is 0 W or more and 100 W or less. The processing time is 3 seconds or more and 30 seconds or less.

[0143] The processing conditions in the second step are as follows, for example. As the process gas, C 4 F 8 is supplied to the vacuum chamber at 100 sccm or more and 600 sccm or less. The pressure in the vacuum chamber is 5 Pa or more and 30 Pa or less, the high-frequency power applied to the first electrode is 1500 W or more and 4800 W or less, the high-frequency power applied to the second electrode is 0 W or more and 100 W or less. The processing time is 1 second or more and 10 seconds or less.

[0144] By repeating the second step, the deposited film removal step, and the first step under the above-described conditions, a semiconductor layer containing Si can be etched perpendicular to the depth direction at a rate of 10 μm / min or more and 20 μm / min or less.

[0145] (5) Sidewall cleaning process (S15)

[0146] Clean the sidewalls of the obtained electronic component. The sidewall cleaning process is performed by the sidewall cleaning process (ii) in the above-described cleaning method for electronic components. According to the sidewall cleaning process according to the present embodiment, the attachments on the sidewalls can be removed while maintaining the protective film.

[0147] The plasma processing apparatuses used in the etching process and the sidewall cleaning process may be the same or different. In the case of using the same plasma processing apparatus, the two processes can be performed continuously.

[0148] (6) Protective film removal process (S16)

[0149] The protective film removal process is performed by the protective film removal process (iii) in the above-described cleaning method for electronic components. Thereby, the protective film is removed.

[0150] The plasma processing apparatuses used in the sidewall cleaning process and the protective film removal process may be the same or different. In the case of using the same plasma processing apparatus, the two processes can be performed continuously.

[0151] After the protective film removal process, the element chip is removed from the holding wafer.

[0152] The element chip is pushed up together with the holding wafer, for example, from the non-bonding surface side of the holding wafer using an upper pusher. Thereby, at least a part of the element chip floats from the holding wafer. Thereafter, the element chip is removed from the holding wafer by a pick-up device.

[0153] Hereinafter, the manufacturing method of the element chip will be specifically described with reference to the accompanying drawings. However, the present embodiment is not limited thereto.

[0154] Figure 9 is a top view schematically showing a substrate prepared by the substrate preparation process according to the present embodiment. Figure 10 is a cross-sectional view schematically showing a part of the substrate. The substrate 10 includes a first surface 10X and a second surface 10Y, and includes a plurality of element regions 101 and a dividing region 102 that defines the element regions 101. The element region 101 includes a semiconductor layer 11 and a wiring layer 12 laminated on the first surface 10X side of the semiconductor layer 11. The dividing region 102 includes a semiconductor layer 11 and an insulating film 14. The second surface 10Y of the substrate 10 is bonded to a holding wafer 22 provided in the transport carrier 20.

[0155] Figure 11 It is a cross-sectional view schematically showing a part of the substrate after the protective film forming process according to the present embodiment. A protective film 40 is formed on the first surface 10X of the substrate 10.

[0156] Figure 12 It is a cross-sectional view schematically showing a part of the substrate after the opening forming process according to the present embodiment. The protective film 40 and the insulating film 14 in the dividing region 102 are removed, and in the dividing region 102, the semiconductor layer 11 is exposed from the opening.

[0157] Figure 13 It is a cross-sectional view schematically showing an element chip manufactured in the etching process according to the present embodiment. The dividing region of the substrate is etched to form a plurality of element chips 200 from the substrate. Serrations are formed on the side walls 200Z of the electronic component. The first surface 200X of the element chip 200 is covered with the protective film 40.

[0158] Figure 14 It is a cross-sectional view schematically showing the element chip after the protective film removing process according to the present embodiment. The protective film 40 covering the first surface 200X is removed.

[0159] The following refers to Figure 15 to specifically describe the plasma processing apparatus used in the etching process, the side wall cleaning process, and the protective film removing process. However, the plasma processing apparatus is not limited thereto. Figure 15 It is a cross-sectional view schematically showing the structure of the plasma processing apparatus 100. In Figure 15 a plurality of electronic components (element chips) are held on a transport carrier.

[0160] (Plasma Processing Apparatus)

[0161] The plasma processing apparatus 100 includes a stage 111. The transport carrier 20 holding a plurality of electronic components 200 is mounted on the stage 111 such that the surface of the electronic component 200 holding the holding piece 22 faces upward. The stage 111 has a size large enough to place the entire transport carrier 20. An outer cover 124 is disposed above the stage 111, and the outer cover 124 has a window portion 124W for exposing at least one electronic component 200. A pressing member 107 is disposed on the outer cover 124, and the pressing member 107 is used to press the frame 21 when the frame 21 is placed on the stage 111. The pressing member 107 is preferably a member capable of making point contact with the frame 21 (for example, a helical spring, an elastic resin). Thereby, while suppressing the thermal interaction between the frame 21 and the outer cover 124, the deformation of the frame 21 can be corrected.

[0162] The stage 111 and the outer cover 124 are arranged inside the vacuum chamber 103. The vacuum chamber 103 is generally cylindrical with an upper opening, and the upper opening is closed by a dielectric member 108 serving as a cover. Examples of the material constituting the vacuum chamber 103 include aluminum, stainless steel (SUS), and aluminum with anodized aluminum surface. Examples of the material constituting the dielectric member 108 include yttrium oxide (Y 2 O 3 ), aluminum nitride (AlN), aluminum oxide (Al 2 O 3 ), and dielectric materials such as quartz (SiO 2 ). Above the dielectric member 108, a first electrode 109 serving as an upper electrode is arranged. The first electrode 109 is electrically connected to the first high-frequency power supply 110A. The stage 111 is arranged on the bottom side inside the vacuum chamber 103. The stage 111 and the first electrode 109 face each other.

[0163] A gas inlet 103a is connected to the vacuum chamber 103. A process gas source 112 serving as a supply source of a plasma generation gas (process gas) and an ashing gas source 113 are respectively connected to the gas inlet 103a through pipes. In addition, an exhaust port 103b is provided in the vacuum chamber 103, and a decompression mechanism 114 including a vacuum pump for exhausting the gas inside the vacuum chamber 103 to perform decompression is connected to the exhaust port 103b. In a state where the process gas is supplied to the vacuum chamber 103, high-frequency power is supplied from the first high-frequency power supply 110A to the first electrode 109, thereby generating plasma inside the vacuum chamber 103.

[0164] The stage 111 has a second electrode 120 built therein. Specifically, the stage 111 includes an electrode layer 115, a metal layer 116, each of which is substantially circular, a base 117 supporting the electrode layer 115 and the metal layer 116, and an outer peripheral portion 118 surrounding the electrode layer 115, the metal layer 116, and the base 117. Inside the electrode layer 115, an electrode for electrostatic chuck (hereinafter referred to as ESC electrode 119) is arranged; and a second electrode 120 electrically connected to the second high-frequency power supply 110B. The outer peripheral portion 118 is made of a metal having conductivity and etching resistance, and protects the electrode layer 115, the metal layer 116, and the base 117 from the influence of plasma. An annular outer peripheral ring 129 is arranged on the upper surface of the outer peripheral portion 118. The outer peripheral ring 129 serves to protect the upper surface of the outer peripheral portion 118 from the influence of plasma. The electrode layer 115 and the outer peripheral ring 129 are made of the above dielectric material, for example.

[0165] A DC power supply 126 is electrically connected to the ESC electrode 119. The electrostatic adsorption mechanism is composed of the ESC electrode 119 and the DC power supply 126. The holding sheet 22 is pressed and fixed to the stage 111 by the electrostatic adsorption mechanism. Hereinafter, as an example of the fixing mechanism for fixing the holding sheet 22 to the stage 111, the case where the electrostatic adsorption mechanism is provided will be described, but it is not limited thereto. The fixing of the holding sheet 22 to the stage 111 may also be performed by a clamp (not shown).

[0166] The metal layer 116 is composed of, for example, aluminum having an anodized coating formed on its surface. A refrigerant flow path 127 is formed in the metal layer 116. The refrigerant flow path 127 cools the stage 111. By cooling the stage 111, the holding sheet 22 mounted on the stage 111 is cooled, and also a part of the outer cover 124 in contact with the stage 111 is cooled. Thereby, damage to the electronic component 200 and the holding sheet 22 due to heating during plasma processing can be suppressed. The refrigerant in the refrigerant flow path 127 is circulated by a refrigerant circulation device 125.

[0167] A plurality of support portions 122 penetrating the stage 111 are arranged near the outer periphery of the stage 111. The support portions 122 support the frame 21 of the transfer carrier 20. The support portions 122 are lifted and driven by a first lifting mechanism 123A. When the transfer carrier 20 is transported into the vacuum chamber 103, it is handed over to the support portions 122 that have risen to a given position. The transfer carrier 20 is placed on a given position of the stage 111 by the upper end surface of the support portion 122 descending below the same level as the stage 111.

[0168] A plurality of lifting rods 121 are connected to the end of the outer cover 124 so that the outer cover 124 can be lifted and lowered. The lifting rods 121 are lifted and driven by a second lifting mechanism 123B. The lifting operation of the outer cover 124 performed by the second lifting mechanism 123B can be performed independently of the first lifting mechanism 123A.

[0169] The control device 128 controls the operations of the elements constituting the plasma processing apparatus 100 including the first high-frequency power supply 110A, the second high-frequency power supply 110B, the process gas source 112, the ashing gas source 113, the pressure reducing mechanism 114, the refrigerant circulation device 125, the first lifting mechanism 123A, the second lifting mechanism 123B, and the electrostatic adsorption mechanism. Figure 16 It is a block diagram of the plasma processing apparatus used in the present embodiment.

[0170] The transfer carrier 20 holding the electronic component 200 is transported into the vacuum chamber, and plasma processing of the electronic component 200 is performed in a state where the electronic component 200 is placed on the stage 111.

[0171] When the transfer vehicle 20 is carried in, inside the vacuum chamber 103, the outer cover 124 is raised to a given position by driving the lifting rod 121. A gate valve (not shown) is opened, and the transfer vehicle 20 is carried in. The plurality of support portions 122 standby in the raised state. When the transfer vehicle 20 reaches a given position above the stage 111, the transfer vehicle 20 is transferred to the support portions 122. The transfer vehicle 20 is transferred to the upper end surface of the support portions 122 such that the adhesive surface of the holding piece 22 faces upward.

[0172] If the transfer vehicle 20 is transferred to the support portions 122, the vacuum chamber 103 is placed in a sealed state. Next, the support portions 122 start to descend. By the upper end surface of the support portions 122 descending below the same level as the stage 111, the transfer vehicle 20 is placed on the stage 111. Then, the lifting rod 121 is driven. The lifting rod 121 lowers the outer cover 124 to a given position. At this time, the distance between the outer cover 124 and the stage 111 is adjusted so that the pressing member 107 disposed on the outer cover 124 can make point contact with the frame 21. Thus, the frame 21 is pressed by the pressing member 107, and the frame 21 is covered by the outer cover 124, and the substrate 10 is exposed from the window portion 124W.

[0173] The outer cover 124 is, for example, an annular shape having a substantially circular outer contour, and has a certain width and a thin thickness. The diameter of the window portion 124W is smaller than the inner diameter of the frame 21, and its outer diameter is larger than the outer diameter of the frame 21. Therefore, if the transfer vehicle 20 is mounted on a given position of the stage 111 and the outer cover 124 is lowered, the outer cover 124 can cover the frame 21. At least one electronic component 200 is exposed from the window portion 124W.

[0174] The outer cover 124 is made of, for example, a dielectric such as ceramics (such as alumina, aluminum nitride, etc.), quartz, or a metal such as aluminum or aluminum with an anodized aluminum surface. The pressing member 107 can be made of a resin material in addition to the above-mentioned dielectric and metal.

[0175] After the transfer vehicle 20 is transferred to the support portions 122, a voltage is applied to the ESC electrode 119 from the DC power supply 126. Thereby, the holding piece 22 is electrostatically adsorbed to the stage 111 while being in contact with the stage 111. In addition, the voltage application to the ESC electrode 119 can start after the holding piece 22 is placed on the stage 111 (after contact).

[0176] When the plasma treatment is completed, the gas in the vacuum chamber 103 is exhausted and the gate valve is opened. The transport vehicle 20 carrying the plurality of electronic components 200 is transported out of the plasma processing apparatus 100 by the transport mechanism entering through the gate valve. When the transport vehicle 20 is transported out, the gate valve is quickly closed. The process of transporting out the transport vehicle 20 can be performed in the reverse order of the order in which the transport vehicle 20 is loaded onto the stage 111 as described above. That is, after raising the outer cover 124 to a given position, the applied voltage applied to the ESC electrode 119 is set to zero to release the adsorption of the transport vehicle 20 to the stage 111, and the support portion 122 is raised. After the support portion 122 is raised to a given position, the transport vehicle 20 is transported out.

[0177] <<Embodiment 2>>

[0178] Embodiment 2 of the present invention will be described. In the present embodiment, the side walls of the electronic components are cleaned by utilizing the difference in the ease of plasma treatment between the main surfaces and the side walls of the electronic components. Thereby, it is possible to remove the attachments adhering to the side walls while keeping the protective film (mask) covering the main surface of the electronic components intact.

[0179] In the side wall cleaning process according to the present embodiment, the electronic components are exposed to the fourth plasma containing a carbon oxide gas. The reason for being able to remove the attachments adhering to the side walls while keeping the protective film covering the main surface of the electronic components intact by the fourth plasma is considered as follows.

[0180] The carbon oxide gas contained in the process gas dissociates into oxygen atoms and carbon atoms in the plasma processing apparatus. Therefore, the plasma generated in the plasma processing apparatus contains carbon ions and radicals. When the carbon ions and radicals collide with the electronic components, carbon (C) derived from the carbon ions and radicals is deposited on their surfaces. In particular, carbon is easily deposited on the protective film, which is the main surface of the electronic components.

[0181] Furthermore, the plasma generated in the plasma processing apparatus also contains oxygen ions and radicals. When the oxygen ions and radicals collide with the electronic components, the attachments are oxidized and decomposed together with the carbon on the side walls of the electronic components, and thus removed. On the main surface of the electronic components, mainly the deposited carbon is etched.

[0182] Specific data is used to show the effect that the attachments adhering to the side walls can be removed while keeping the protective film covering the main surface of the electronic components intact by the fourth plasma. Figure 17 It is a graph showing the relationship between the etching rates in the longitudinal and transverse directions of the polymer and the pressure in the processing chamber (vacuum chamber). Figure 18It is a graph showing the relationship between the ratio of the etching rate of the longitudinal direction of the polymer to the transverse direction (etching rate in the longitudinal direction / etching rate in the transverse direction, hereinafter referred to as the aspect ratio) and the pressure in the vacuum chamber. In Figure 17 and Figure 18 , for comparison, data in the case of using oxygen (O 2 ) as the process gas are also shown. In addition, the longitudinal polymer etching rate refers to the rate of etching the polymer deposited on the main surface of the electronic component. The transverse polymer etching rate refers to the rate of etching the polymer deposited on the side wall of the electronic component.

[0183] As a sample, a silicon substrate on which a polymer (fluorocarbon) is deposited is used. The generation conditions of the polymer are as follows. C 4 F 8 is supplied to the vacuum chamber at 600 sccm, the pressure in the vacuum chamber is set to 10 Pa, the high-frequency power applied to the electrode (first electrode) opposed to the stage on which the sample is placed is set to 4800 W, the high-frequency power applied to the electrode (second electrode) built in the stage is set to 0 W, the stage temperature is set to -10 °C, and the processing time is set to 2 minutes.

[0184] The etching conditions of the polymer are as follows. As the process gas, CO 2 is supplied to the vacuum chamber at 200 sccm, the pressure in the vacuum chamber is adjusted to 30 Pa or less, the high-frequency power applied to the first electrode is set to 3000 W, the high-frequency power applied to the second electrode is set to 0 W, the stage temperature is set to -10 °C, and the processing time is set to 1 minute. The polymer etching using oxygen (O 2 ) is also carried out under the same conditions.

[0185] As Figure 17 shown, the longitudinal etching rate in the polymer etching using CO 2 is sufficiently smaller than that in the case of using O 2 . It is considered that this is because, as described above, carbon dissociated from CO 2 is deposited on the main surface of the electronic component during the etching process. By depositing carbon on the main surface simultaneously with the etching, the apparent longitudinal etching rate becomes smaller. Therefore, the protective film covering the main surface of the electronic component can remain. On the other hand, since carbon is not deposited in the polymer etching using O 2 , the protective film on the surface of the electronic component is etched.

[0186] In addition, as Figure 17 shown, the longitudinal etching rate in the polymer etching is regardless of the case of using CO 2 and the case of using O 2In any of the cases, it becomes smaller as the pressure in the chamber rises. When using O 2 In the case of, the lateral etching rate also becomes smaller as the pressure in the chamber rises. On the other hand, from Figure 17 it can be seen that when using CO 2 In the case of, the lateral etching rate is hardly affected by the pressure in the chamber.

[0187] As Figure 18 shown, the aspect ratio becomes smaller as the pressure rises in any of the cases of CO 2 and O 2 . Furthermore, in the case of using CO 2 in the region where the pressure is about 7 Pa or more, the aspect ratio drops below 1. That is, it can be seen that in the case of using CO 2 the lateral etching progresses more easily than the longitudinal etching. Thus, the above-described effects can be obtained. In addition, in the case of using O 2 in the region up to a pressure of 30 Pa, the aspect ratio exceeds 1.

[0188] That is, through the above-described sidewall cleaning process, the attached substances can be removed from the surface of the sidewall, and on the other hand, the etching of the protective film itself can be suppressed on the first surface. Thus, it is possible to clean the sidewalls of the electronic component while suppressing the damage to the first surface caused by the sidewall cleaning process.

[0189] The cleaning method according to the present embodiment is particularly suitable for cleaning the sidewalls of electronic components that have undergone the Bosch process. The Bosch process alternately repeats a first step of forming recesses corresponding to divided regions by plasma treatment and a second step of depositing a second film on the inner walls of the recesses by plasma treatment on a substrate. Therefore, on the sidewalls of the formed element chips, it is easy to attach deposition films, reaction products of the deposition films and plasma, etc. (attached substances). Furthermore, unevenness called crenellations is formed on the sidewalls. The attached substances adhering to the crenellations are difficult to remove. According to the cleaning method according to the present embodiment, such attached substances can be removed by a simple method. The present embodiment includes a method for manufacturing an element chip having an etching process using the Bosch process.

[0190] The sidewall cleaning process will be described in detail below.

[0191] The sidewall cleaning process is performed by exposing the electronic component to the fourth plasma. The fourth plasma is generated using a process gas containing a carbon oxide gas.

[0192] An attachment such as a film deposited by a Bosch process (deposited film) and a reaction product of the deposited film and plasma is attached to the side wall of the electronic component. Such an attachment mainly consists of a polymer (fluorocarbon compound) containing carbon atoms and fluorine atoms, and further contains silicon and oxygen. The fluorine atoms contained in the polymer are prone to move, which may cause a reduction in the reliability of the device. The polymer can be easily removed by oxygen ions and radicals.

[0193] The fourth plasma is generated using a process gas containing a carbon oxide gas (the fourth process gas). The carbon oxide gas is prone to dissociate into oxygen atoms and carbon atoms in the plasma processing apparatus. Therefore, oxygen ions and radicals are easily generated, and the above-mentioned polymer can be quickly removed. On the other hand, the dissociated carbon atoms are prone to attach to the protective film.

[0194] Table 1 shows the measurement results of the impurity concentrations (C, O, F, Si, metal elements) on the surface of the electronic component before and after the side wall cleaning process. The electronic component is a silicon chip with a thickness of 200 μm, having a polyimide layer on the surface and a metal electrode (Au electrode) disposed in the opening of the polyimide layer. The concentration was measured by X-ray photoelectron spectroscopy on the metal electrode on the chip surface and on the side wall of the chip. The cleaning conditions are as follows. As the process gas, CO2 was supplied to the vacuum chamber at 200 sccm, the pressure in the vacuum chamber was set to 1 Pa, the high-frequency power applied to the first electrode was set to 3000 W, the high-frequency power applied to the second electrode was set to 0 W, and the processing time was set to 5 minutes.

[0195] In Table 1, for comparison, the data in the case of using oxygen (O 2 ) as the process gas is also shown. The cleaning conditions are the same as above except that the process gas is changed from CO 2 to O 2 . Through the cleaning under the above conditions, in the case of using CO 2 , the polyimide layer was etched by 0.9 μm, and in the case of using O 2 , the polyimide layer was etched by 2.5 μm.

[0196] As shown in Table 1, in the case of using CO 2 , the fluorine concentrations on the surface and side wall of the metal electrode were reduced to 1.4 atomic % and 1.5 atomic %, respectively. On the other hand, in the case of using O 2 , although the fluorine concentrations on the surface and side wall of the metal electrode also decreased, they were 3.5 atomic % and 3.65 atomic %, respectively. That is, in the case of using CO 2 , on the main surface side of the electronic component, the etching of the polyimide layer is suppressed, and on the other hand, fluorine atoms are efficiently removed. In the case of using CO 2In this case, the removal effect of fluorine at the side walls of the electronic component is also high.

[0197] [Table 1]

[0198]

[0199] Carbon oxides are compounds of carbon and oxygen, for example represented by C x O y (x = 1 to 5, y = 1, 2). Specifically, carbon monoxide (CO), carbon dioxide (CO 2 ), tricarbon dioxide, pentacarbon dioxide, carbonyl sulfide (COS), etc. can be cited. One of them alone or a combination of two or more is used. Due to the ease of availability, the carbon oxide gas can be CO, CO 2 .

[0200] The fourth process gas may contain other gases, for example, it contains Ar, H 2 , N 2 , He, etc. The proportion of the carbon oxide gas in the fourth process gas can be 10% by volume or more and less than 100% by volume, or can be 30% by volume or more and 98% by volume or less.

[0201] The conditions for generating the fourth plasma are appropriately set according to the amount of the adherent, etc. The conditions for generating the fourth plasma are as follows, for example. As the process gas, CO 2 is supplied to the vacuum chamber at 50 sccm or more and 400 sccm or less. The pressure in the vacuum chamber is 0.6 Pa or more and 30 Pa or less, the high-frequency power applied to the first electrode is 500 W or more and 5000 W or less, and the high-frequency power applied to the second electrode is 0 W or more and 100 W or less. The stage temperature is -20°C or more and 40°C or less. The pressure in the vacuum chamber is preferably 5 Pa or more, more preferably 7 Pa or more.

[0202] According to the above conditions, the effective etching rate of the protective film on the surface of the electronic component becomes 50 nm / min or more and 200 nm / min or less, and the effective etching rate of the adherent on the side of the electronic component becomes 100 nm / min or more and 130 nm / min or less. The processing time can be set considering the thickness of the protective film and the thickness of the adherent. The processing time is, for example, 60 seconds or more and 300 seconds or less.

[0203] In the sidewall cleaning process, multiple electronic components can be processed at the same time. As a result, productivity is improved. In this case, the distance W between the opposing sidewalls of any two electronic components and the height H of the sidewall of any one of the electronic components can satisfy the relationship of H≥5×W. In the case of such high aspect ratio concave-convex, according to this embodiment, it is also possible to remove the attachments attached to the sidewall while maintaining the protective film covering the main surface of the electronic component. Furthermore, the relationship of H≤50×W can also be satisfied.

[0204] The height H of the side wall is not particularly limited. For example, the height H of the side wall is 20 μm or more and 700 μm or less. The distance W between the side walls is also not particularly limited. For example, the distance W between the side walls is 4 μm or more and 60 μm or less.

[0205] The distance W is the average value of the shortest distances between any two points on the first surface side of the opposing side walls of any two electronic components. In the case where the entire side walls are not facing each other, the shortest distances between the opposing parts of the side walls can be measured. The height H of the side wall is the height of the lower side among the average values ​​of the heights of any two points of the two side walls (or their parts) used to calculate the distance W. The height of the side wall is the shortest distance between the first surface and the second surface connected to the side wall.

[0206] The present embodiment will be described in detail below by taking an electronic component including a semiconductor layer and a wiring layer as an example and referring to the drawings, but the present embodiment is not limited thereto.

[0207] Figure 19 2 is a cross-sectional view schematically showing a main part of the electronic components supplied to the side wall cleaning process. A plurality of electronic components 200 are supported by a holding sheet 22 described later. The holding sheet 22 is used to improve the workability and is not necessarily required.

[0208] The electronic component 200 includes a semiconductor layer 11 and a wiring layer 12 disposed on the first surface 200X side of the semiconductor layer 11. The first surface 200X is covered with a protective film 40. Scallops are formed on the side wall 200Z of the electronic component 200. Attachments 60 are attached to the side wall 200Z. In the example shown in the figure, the scallops and the attachments are exaggeratedly shown.

[0209] Figure 20 2 is a cross-sectional view schematically showing the main part of the electronic component in the side wall cleaning process. No significant reduction is observed in the film thickness of the protective film 40, while on the side wall 200Z, part of the deposit 60 is removed, and the layer of the deposit 60 becomes thinner.

[0210] Figure 21It is a cross-sectional view schematically showing the main part of an electronic component after the sidewall cleaning process. The protective film 40 remains. On the other hand, on the sidewall 200Z, the remaining part of the attachment 60 is removed, and the sidewall 200Z is exposed.

[0211] Next, a cleaning method including the above-described sidewall cleaning process will be described.

[0212] A. Cleaning Method of Electronic Component

[0213] The cleaning method of the electronic component according to the present embodiment includes: a preparation process of preparing an electronic component having a first surface covered with a protective film, a second surface opposite to the first surface, a sidewall located between the first surface and the second surface, and an attachment attached to the sidewall; and the above-described sidewall cleaning process of cleaning the sidewall of the electronic component. Figure 22 It is a flowchart showing the cleaning method according to the present embodiment.

[0214] (i) Preparation Process of Electronic Component (S01)

[0215] Prepare at least one electronic component having a first surface covered with a protective film, a second surface opposite to the first surface, and a sidewall located between the first surface and the second surface. The electronic component is, for example, an element chip manufactured by plasma cutting a substrate through a Bosch process. Serrations, that is, concave portions and convex portions, can be formed on the sidewall.

[0216] The electronic component can be the same as that in Embodiment 1, for example.

[0217] In the case of simultaneously processing a plurality of electronic components in the sidewall cleaning process, from the viewpoint of operability, it is desirable that the plurality of electronic components be adhered to a holding sheet fixed to a frame. A member including a frame and a holding sheet fixed to the frame is referred to as a transport carrier.

[0218] (Transport Carrier)

[0219] The transport carrier can be the same as that in Embodiment 1, for example.

[0220] The above-described preparation process of the electronic component can include: a substrate preparation process of preparing a substrate having a plurality of element regions and division regions defining the element regions and having a first surface and a second surface opposite to the first surface; a protective film formation process of forming a protective film covering the first surface; an opening formation process of forming an opening in the protective film to expose the division region in the first surface; and an etching process of repeating a cycle including a first step of forming a concave portion corresponding to the exposed division region by plasma treatment and a second step of depositing a second film on the inner wall of the concave portion by plasma treatment. These processes will be described later. Thus, a plurality of electronic components arranged at a given interval are prepared.

[0221] Figure 7A is a top view schematically showing an electronic component prepared in the preparation process of the electronic component. Figure 7B is Figure 7A a sectional view taken along line A-A of Figure 7B . In

[0222] The transport carrier 20 includes a frame 21 and a holding piece 22 fixed to the frame 21. In the frame 21, notches 21a and chamfers 21b for positioning can be provided. The holding piece 22 has an adhesive surface 22X and a non-adhesive surface 22Y, and the outer peripheral edge of the adhesive surface 22X is pasted on one surface of the frame 21. The second surface 200Y of the electronic component 200 is pasted on the portion of the adhesive surface 22X that is exposed from the opening of the frame 21 (refer to Figure 19 etc.).

[0223] A plurality of electronic components 200 are pasted on the adhesive surface 22X of the holding piece 22 at intervals. Such electronic components 200 are obtained by plasma cutting a substrate through a Bosch process. The electronic component 200 includes a semiconductor layer 11 and a wiring layer 12 laminated on the first surface 200X side of the semiconductor layer 11. A protective film 40 is formed on the first surface 200X of the electronic component 200.

[0224] (ii) Sidewall cleaning process (S02)

[0225] Clean the sidewalls of the element chip.

[0226] The sidewall cleaning process is performed as described above by exposing the electronic component to a fourth plasma generated using a process gas containing a carbon oxide gas. According to the above sidewall cleaning process, the attachments on the sidewalls can be removed while the protective film remains.

[0227] (iii) Protective film removal process (S03)

[0228] The protective film can be removed after the final removal process.

[0229] In the removal of the protective film, for example, a third plasma generated using a third process gas containing oxygen (O 2 ) is used. The third process gas may contain a fluorine-containing gas together with O 2 . As the fluorine-containing gas, the same compounds as those described above can be cited. The proportion of O 2 in the third process gas can be 10 vol% or more and less than 100 vol%, or can be 30 vol% or more and 98 vol% or less.

[0230] The conditions for generating the third plasma can be the same as those in Embodiment 1.

[0231] In the case where the protective film is water-soluble, it is also possible to replace the third plasma and remove the protective film by water washing. In the case where the protective film is an insulating film (such as silicon nitride or silicon oxide film) and / or a resin layer (such as polyimide) disposed on the outermost surface of the electronic component, since the protective film is used not only to protect the electronic component during manufacturing but also to protect the electronic component after circulation, the protective film may not be removed.

[0232] B. Method for manufacturing element chip

[0233] The method for manufacturing an element chip according to the present embodiment includes: a substrate preparation step of preparing a substrate having a plurality of element regions and dividing regions that define the element regions and having a first surface and a second surface opposite to the first surface; a protective film formation step of forming a protective film on the first surface; an opening formation step of forming an opening in the protective film to expose the dividing region in the first surface; an etching step of repeating a cycle including a first step of forming a recess corresponding to the exposed dividing region by plasma treatment and a second step of depositing a second film on the inner wall of the recess by plasma treatment to obtain an electronic component having a first surface covered with a protective film, a second surface, side walls located between the first surface and the second surface, and an attachment attached to the side walls; and a side wall cleaning step of cleaning the side walls of the electronic component.

[0234] The side wall cleaning step is performed by exposing the electronic component to a fourth plasma generated using a process gas containing a carbon oxide gas. Figure 23 It is a flowchart showing the method for manufacturing an element chip according to the present embodiment.

[0235] (1) Substrate preparation step (S11)

[0236] First, a substrate to be processed is prepared.

[0237] (Substrate)

[0238] The substrate can be the same as that in Embodiment 1.

[0239] The second surface of the substrate can be pasted on a holding sheet fixed to a frame. Thereby, the operability is improved. By cutting the substrate pasted on the holding sheet, a plurality of element chips are obtained and arranged at intervals on the holding sheet. The shape, material, etc. of the frame and the holding sheet are as described above.

[0240] (2) Protective film formation step (S12)

[0241] A protective film covering the first surface of the substrate is formed.

[0242] The protective film is provided to protect the element region of the substrate from plasma. The protective film is removed after the etching step. The material and thickness of the protective film are as described above.

[0243] The protective film can be formed, for example, by the same method as in Embodiment 1.

[0244] (3) Opening formation step (S13)

[0245] An opening is formed in the protective film to expose the dicing area of the substrate.

[0246] The opening can be formed, for example, by the same method as in Embodiment 1.

[0247] (4) Etching step (S14)

[0248] The substrate is exposed to plasma, and the dicing area exposed from the opening is etched to the second surface, and a plurality of element chips are formed from the substrate. The plurality of element chips are obtained while being held by the holding sheet.

[0249] The etching step can be performed in the same manner as in Embodiment 1.

[0250] (5) Sidewall cleaning step (S15)

[0251] The sidewalls of the obtained electronic components are cleaned.

[0252] The sidewall cleaning step is performed by the sidewall cleaning step (ii) in the above-described cleaning method for electronic components. According to the sidewall cleaning step according to the present embodiment, the attachments on the sidewalls can be removed while maintaining the protective film.

[0253] The plasma processing apparatuses used in the etching step and the sidewall cleaning step may be the same or different. When the same plasma processing apparatus is used, the two steps can be performed continuously.

[0254] (6) Protective film removal step (S16)

[0255] The protective film removal step is performed by the protective film removal step (iii) in the above-described cleaning method for electronic components. Thereby, the protective film is removed.

[0256] The plasma processing apparatuses used in the sidewall cleaning step and the protective film removal step may be the same or different. When the same plasma processing apparatus is used, the two steps can be performed continuously.

[0257] After the protective film removal step, the element chips are removed from the holding sheet.

[0258] The element chips are pushed up together with the holding sheet from the non-bonding surface side of the holding sheet, for example, by an upper pusher. Thereby, at least a part of the element chips floats from the holding sheet. Thereafter, the element chips are removed from the holding sheet by a pick-up device.

[0259] The manufacturing method of the element chip will be specifically described with reference to the accompanying drawings. However, the present embodiment is not limited thereto.

[0260] Figure 9 It is a top view schematically showing the substrate prepared by the substrate preparation process according to the present embodiment. Figure 10 It is a cross-sectional view schematically showing a part of the substrate. The substrate 10 has a first surface 10X and a second surface 10Y, and has a plurality of element regions 101 and a dividing region 102 that demarcates the element regions 101. The element region 101 has a semiconductor layer 11 and a wiring layer 12 laminated on the first surface 10X side of the semiconductor layer 11. The dividing region 102 has a semiconductor layer 11 and an insulating film 14. The second surface 10Y of the substrate 10 is adhered to the holding piece 22 provided on the transport carrier 20.

[0261] Figure 11 It is a cross-sectional view schematically showing a part of the substrate after the protective film forming process according to the present embodiment. A protective film 40 is formed on the first surface 10X of the substrate 10.

[0262] Figure 12 It is a cross-sectional view schematically showing a part of the substrate after the opening forming process according to the present embodiment. The protective film 40 and the insulating film 14 in the dividing region 102 are removed, and the semiconductor layer 11 is exposed from the opening in the dividing region 102.

[0263] Figure 13 It is a cross-sectional view schematically showing the element chip manufactured in the etching process according to the present embodiment. The dividing region of the substrate is etched to form a plurality of element chips 200 from the substrate. Serrations are formed on the side wall 200Z of the electronic component. The first surface 200X of the element chip 200 is covered with the protective film 40.

[0264] Figure 14 It is a cross-sectional view schematically showing the element chip after the protective film removing process according to the present embodiment. The protective film 40 covering the first surface 200X is removed.

[0265] The plasma processing apparatus used in the etching process, the side wall cleaning process, and the protective film removing process can be the same as that in Embodiment 1, for example. Figure 15 It is a cross-sectional view schematically showing the structure of the plasma processing apparatus 100. Figure 16 It is a block diagram of the plasma processing apparatus used in the present embodiment.

[0266] The present invention will be described with respect to a preferred embodiment at the current time point, but such a disclosure should not be construed in a limiting manner. For various modifications and changes, those skilled in the art in the technical field to which the present invention pertains will be clearly and unmistakably able to understand them by reading the above disclosure. Therefore, the appended claims should be construed to include all modifications and changes without departing from the true spirit and scope of the present invention.

[0267] Industrial Applicability

[0268] The cleaning method of the present invention is particularly suitable as a post-treatment for component chips manufactured by plasma cutting based on the Bosch process because it can clean the side walls while reducing the damage to electronic components.

[0269] Explanation of Reference Numerals

[0270] 200: Electronic Component (Component Chip)

[0271] 200X: First Surface

[0272] 200Y: Second Surface

[0273] 200Z: Side Wall

[0274] 10: Substrate

[0275] 10X: First Surface

[0276] 10Y: Second Surface

[0277] 11: Semiconductor Layer

[0278] 12: Wiring Layer

[0279] 14: Insulating Film

[0280] 20: Transfer Carrier

[0281] 21: Frame

[0282] 21a: Notch

[0283] 21b: Chamfer

[0284] 22: Holding Piece

[0285] 22X: Adhesive Surface

[0286] 22Y: Non-Adhesive Surface

[0287] 40: Protective Film

[0288] 50: First Film

[0289] 60: Attachment

[0290] 100: Plasma Processing Apparatus

[0291] 103: Vacuum chamber

[0292] 103a: Gas inlet

[0293] 103b: Exhaust port

[0294] 108: Dielectric member

[0295] 109: First electrode

[0296] 110A: First high-frequency power supply

[0297] 110B: Second high-frequency power supply

[0298] 111: Stage

[0299] 112: Process gas source

[0300] 113: Ashing gas source

[0301] 114: Pressure reducing mechanism

[0302] 115: Electrode layer

[0303] 116: Metal layer

[0304] 117: Base

[0305] 118: Outer peripheral part

[0306] 119: ESC electrode

[0307] 120: Second electrode

[0308] 121: Lifting rod

[0309] 122: Support part

[0310] 123A, 123B: Lifting mechanism

[0311] 124: Outer cover

[0312] 124W: Window part

[0313] 125: Refrigerant circulation device

[0314] 126: DC power supply

[0315] 127: Refrigerant flow path

[0316] 128: Control device

[0317] 129: Outer peripheral ring

Claims

1. A cleaning method for an electronic component, comprising: A preparation step of preparing an electronic component having a first surface covered with a protective film, a second surface opposite to the first surface, a side wall located between the first surface and the second surface, and an attachment attached to the side wall; and A side wall cleaning step of cleaning the side wall of the electronic component, The side wall cleaning step includes: A deposition step of depositing a first film on the surfaces of the protective film and the attachment using a first plasma; and A removal step of removing at least a part of the attachment together with the first film deposited on the surface of the attachment using a second plasma, In the side wall cleaning step, the deposition step and the removal step are alternately repeated multiple times so that the protective film remains, The side wall cleaning step is performed so that the ratio RD2 / RD1 of the deposition rate RD2 of the first film on the surface of the side wall to the deposition rate RD1 of the first film on the surface of the protective film in the deposition step, and the ratio RR2 / RR1 of the removal rate RR2 of the first film attached to the side wall to the removal rate RR1 of the first film on the surface of the protective film in the removal step satisfy the relationship RR2 / RR1 > RD2 / RD1.

2. The cleaning method for an electronic component according to claim 1, wherein, The side wall cleaning step is performed in a processing chamber of a plasma processing apparatus, The pressure PD1 in the processing chamber in the deposition step and the pressure PR1 in the processing chamber in the removal step satisfy the relationship PD1 < PR1.

3. The cleaning method for an electronic component according to claim 1 or 2, wherein, The side wall cleaning step is performed using a plasma processing apparatus, which includes: A stage for placing the electronic component; A first electrode configured to face the stage; and A second electrode built in the stage, The high-frequency power PD2 applied to the second electrode in the deposition step and the high-frequency power PR2 applied to the second electrode in the removal step satisfy the relationship PD2 ≤ PR2.

4. The cleaning method for an electronic component according to claim 1 or 2, wherein, In the side wall cleaning step, a plurality of the electronic components are processed, The distance W between the opposing side walls of any two of the electronic components and the height H of the side wall of any one of the electronic components satisfy the relationship H ≥ 5 × W.

5. The cleaning method for an electronic component according to claim 1 or 2, wherein, The preparation step of the electronic component includes: A substrate preparation step of preparing a substrate having a plurality of element regions and dividing regions defining the element regions and having the first surface and the second surface; A protective film forming step of forming the protective film on the first surface; An opening forming step of forming an opening in the protective film to expose the dividing region in the first surface; and The etching process repeats a cycle including a first step of forming a recess corresponding to the exposed divided area by plasma treatment and a second step of depositing a second film on the inner wall of the recess by plasma treatment.

6. The cleaning method for an electronic component according to claim 1 or 2, wherein, the cleaning method for the electronic component includes: a protective film removing process of removing the protective film after the last removing process.

7. The cleaning method for an electronic component according to claim 1 or 2, wherein, the first plasma is generated using a process gas containing carbon atoms.

8. The cleaning method for an electronic component according to claim 1 or 2, wherein, the second plasma is generated using a process gas containing oxygen atoms.

9. A manufacturing method for an element chip includes: a substrate preparation process of preparing a substrate having a plurality of element areas and divided areas defining the element areas and having a first surface and a second surface opposite to the first surface; a protective film forming process of forming a protective film on the first surface; an opening forming process of forming an opening in the protective film to expose the divided area in the first surface; and an etching process of repeating a cycle including a first step of forming a recess corresponding to the exposed divided area by plasma treatment and a second step of depositing a second film on the inner wall of the recess by plasma treatment to obtain an electronic component having the first surface covered by the protective film, the second surface, side walls between the first surface and the second surface, and attachments attached to the side walls; and a side wall cleaning process of cleaning the side walls of the electronic component, the side wall cleaning process includes: a deposition process of depositing a first film on the surfaces of the protective film and the attachments using a first plasma; and a removal process of removing at least a part of the attachments together with the first film deposited on the surfaces of the attachments using a second plasma, in the side wall cleaning process, the deposition process and the removal process are alternately repeated multiple times so that the protective film remains, the side wall cleaning process is performed so that the ratio RD2 / RD1 of the deposition rate RD2 of the first film on the surface of the side wall to the deposition rate RD1 of the first film on the surface of the protective film in the deposition process and the ratio RR2 / RR1 of the removal rate RR2 of the first film attached to the side wall to the removal rate RR1 of the first film on the surface of the protective film in the removal process satisfy the relationship RR2 / RR1 > RD2 / RD1.

10. A cleaning method for an electronic component includes: a preparation process of preparing an electronic component having a first surface covered by a protective film, a second surface opposite to the first surface, side walls between the first surface and the second surface, and attachments attached to the side walls; and a side wall cleaning process of cleaning the side walls of the electronic component, the side wall cleaning process is performed by exposing the electronic component to a fourth plasma generated using a process gas containing a carbon oxide gas. A plurality of the electronic components are processed in the sidewall cleaning process. For any two of the electronic components, the distance W between the opposing sidewalls of each component and the height H of the sidewall of any one of the electronic components satisfy the relationship H ≥ 5 × W.

11. The method for cleaning an electronic component according to claim 10, wherein, the preparation process of the electronic component includes: a substrate preparation process of preparing a substrate having a plurality of component regions, dividing regions defining the component regions, and having a first surface and a second surface; a protective film formation process of forming the protective film on the first surface; an opening formation process of forming an opening in the protective film to expose the dividing region in the first surface; and an etching process of repeating a cycle including a first step of forming a recess corresponding to the exposed dividing region by plasma treatment and a second step of depositing a second film on the inner wall of the recess by plasma treatment.

12. The method for cleaning an electronic component according to claim 10, wherein, the method for cleaning the electronic component includes: a protective film removal process of removing the protective film after the sidewall cleaning process.

13. A method for manufacturing an element chip, comprising: a substrate preparation process of preparing a substrate having a plurality of component regions, dividing regions defining the component regions, and having a first surface and a second surface opposite to the first surface; a protective film formation process of forming a protective film on the first surface; an opening formation process of forming an opening in the protective film to expose the dividing region in the first surface; an etching process of repeating a cycle including a first step of forming a recess corresponding to the exposed dividing region by plasma treatment and a second step of depositing a second film on the inner wall of the recess by plasma treatment to obtain an electronic component having the first surface covered with the protective film, the second surface, sidewalls located between the first surface and the second surface, and attachments adhering to the sidewalls; and a sidewall cleaning process of cleaning the sidewalls of the electronic component, wherein the sidewall cleaning process is performed by exposing the electronic component to a fourth plasma generated using a process gas containing a carbon oxide gas, in the sidewall cleaning process, a plurality of the electronic components are processed, for any two of the electronic components, the distance W between the opposing sidewalls of each component and the height H of the sidewall of any one of the electronic components satisfy the relationship H ≥ 5 × W.

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