Circuit arrangement for balancing a split direct voltage intermediate circuit

Abstract

A circuit arrangement (1) for balancing a separate DC voltage intermediate circuit arranged between a first DC voltage connection terminal (2) and a second DC voltage connection terminal (3) is disclosed. The first DC voltage connection terminal (2) is connected to a first intermediate point (5) via a first semiconductor switch (T1), the first intermediate point (5) is connected to a bridge center point (6) via a second semiconductor switch (T2), the bridge center point (6) is connected to a second intermediate point (7) via a third semiconductor switch (T3), and the second intermediate point (7) is connected to the second DC voltage connection terminal (3) via a fourth semiconductor switch (T4). Furthermore, a first connection terminal of a resonant capacitor (Cres) is connected to the first intermediate point (5), and a second connection terminal of the resonant capacitor (Cres) is connected to the intermediate circuit center point (4) via a connection path in which a resonant choke (Lres) is arranged in series with the third semiconductor switch (T3), and the connection path extends through the second intermediate point (7). The additional winding (L1) is magnetically coupled to the resonant choke (Lres), wherein the first connection terminal of the additional winding (L1) is connected to the first connection terminal (22) of the reverse voltage source (23) through a first diode (D1), and the second connection terminal of the additional winding (L1) is connected to the second connection terminal (24) of the reverse voltage source (23) in such a way that the energy coupled into the additional winding (L1) from the resonant choke (Lres) is discharged into the reverse voltage source (23).

Description

Technical Field

[0001] The present invention relates to a circuit arrangement for balancing a discrete DC voltage intermediate circuit. Background Technology

[0002] A multi-point inverter, also known as a multi-level inverter, typically has a discrete DC voltage intermediate circuit, which includes a series circuit of a first intermediate circuit capacitor and a second intermediate circuit capacitor between a first DC voltage connection terminal and a second DC voltage connection terminal, and has an intermediate circuit center point between the two intermediate circuit capacitors.

[0003] When operating such a multipoint inverter to form independent power supply networks (Inselnetzes), it must be suitable for connecting any load. The problem arises with appliances that draw different power depending on voltage polarity, such as hair dryers whose heating coils operate via diodes, or larger loads connected via a center-point rectifier. When such loads are connected to a multipoint inverter with a separate DC voltage intermediate circuit, without further measures, the potential at the center point of the intermediate circuit will be deflected in the potential direction at one of the DC voltage connection terminals, resulting in overvoltages at the intermediate circuit half and the associated semiconductor switches.

[0004] Therefore, it is known that a circuit for balancing a split DC voltage intermediate circuit, when the voltage is unevenly distributed across the two intermediate circuit halves, induces charge balance between the intermediate circuit capacitors, thereby shifting the potential at the center point of the intermediate circuit in the direction that the potential is located at the midpoint of the potential at the two DC voltage connection terminals.

[0005] The IEEE Transactions on Industrial Applications, specifically K. Sano and H. Fujita's "Voltage-Balancing Circuit Based on a Resonant Switched-Capacitor Converter for Multilevel Inverters" (Vol. 44, No. 6, pp. 1768-1776, November-December 2008), discloses, for example, a discussion of prior art, the use of a bidirectional resonant switched-capacitor converter (RSCC) to balance a discrete DC voltage intermediate circuit. Here, a series circuit of first and second semiconductor switches, each with anti-parallel diodes, is arranged in parallel with a first intermediate circuit capacitor. A series circuit of third and fourth semiconductor switches, each with anti-parallel diodes, is arranged in parallel with a second intermediate circuit capacitor. A first intermediate point between the first and second semiconductor switches is connected to a second intermediate point between the third and fourth semiconductor switches via a series circuit consisting of a resonant capacitor and a resonant choke.

[0006] In addition to the aforementioned balancing circuit, a discussion of prior art reveals a circuit in document WO 2016 / 011380 A1 that differs from the balancing circuit in that the resonant choke is not positioned between the resonant capacitor and the second intermediate point, but rather between the point between the second and third semiconductor switches and the center point of the intermediate circuit. In this case, the first intermediate point is connected to the second intermediate point via the resonant capacitor.

[0007] This circuit can be used to balance a separate DC voltage intermediate circuit in the same way as the balancing circuit described above, wherein the semiconductor switches are operated in exactly the same way in both circuits.

[0008] Besides the voltage imbalance in the split DC voltage intermediate circuit caused by unbalanced loads, a temporal fluctuation in the instantaneous load of the intermediate circuit half occurs under balanced load conditions. For example, in the case of a three-phase three-level inverter, the instantaneous power fluctuation of the intermediate circuit half is approximately one-third of the average power. Since this power fluctuation occurs in opposite phases for the two intermediate circuit halves, the intermediate circuit halves discharge unevenly, and the potential at the center point of the intermediate circuit fluctuates at three times the grid frequency. However, the resulting voltage imbalance in the split DC voltage intermediate circuit is balanced over time, making balancing redundant in this case and only causing unnecessary losses.

[0009] To avoid such unnecessary operation, it is conceivable to activate the balancing circuit only when a strong imbalance exists, i.e., only when the voltage difference between the intermediate circuit halves exceeds a predetermined threshold. However, in inverters whose dimensions are determined by high-voltage operation at the DC intermediate circuit, the potential fluctuation at the center point of the intermediate circuit may exhibit high values, for example, greater than ±10V. Therefore, if the balancing circuit of the aforementioned type is activated only when the voltage difference exceeds a correspondingly high threshold, the resonant current will oscillate very rapidly due to the high differential voltage, thereby posing a risk of damaging the semiconductor switches. Furthermore, the voltage at the resonant capacitor Cres can oscillate to such a high value that, in the case of a circuit structure according to WO 2016 / 011380 A1 where the voltage is temporarily applied to switch T2 or T3, the switch may be damaged. Summary of the Invention

[0010] Therefore, one object of the present invention is to provide a circuit arrangement for balancing a discrete DC voltage intermediate circuit, which is suitable for equalizing voltage imbalances at the intermediate circuit half of the discrete DC voltage intermediate circuit without generating dangerously high currents or voltages that could damage semiconductor switches.

[0011] According to the invention, this task is accomplished by the circuit arrangement according to independent claim 1. Advantageous configurations of the invention are described in the dependent claims.

[0012] In a circuit arrangement according to the invention for a balanced discrete DC voltage intermediate circuit—the DC voltage intermediate circuit comprising a series circuit of a first intermediate circuit capacitor and a second intermediate circuit capacitor between a first DC voltage connection terminal and a second DC voltage connection terminal, and having an intermediate circuit center point between the first intermediate circuit capacitor and the second intermediate circuit capacitor—the first DC voltage connection terminal is connected to a first intermediate point via a first semiconductor switch, the first intermediate point is connected to a bridge center point via a second semiconductor switch, the bridge center point is connected to a second intermediate point via a third semiconductor switch, and the second intermediate point is connected to a second DC voltage connection terminal via a fourth semiconductor switch. Each of the semiconductor switches has an anti-parallel diode. Furthermore, a first connection terminal of a resonant capacitor is connected to the first intermediate point, and a second connection terminal of the resonant capacitor is connected to the intermediate circuit center point via a connection path in which a resonant choke is arranged in series with the third semiconductor switch, and the connection path extends through the second intermediate point. The resonant capacitor and the resonant choke thus form a resonant circuit or are interconnected with the resonant circuit at least by closing the second or third semiconductor switch.

[0013] In the circuit arrangement according to the invention, the additional winding is magnetically coupled to the resonant choke, wherein the first connection terminal of the additional winding is connected to the first connection terminal of the reverse voltage source via a first diode. The second connection terminal of the additional winding is connected to the second connection terminal of the reverse voltage source in such a way that energy coupled into the additional winding from the resonant choke is discharged into the reverse voltage source through the first diode. The polarity of the first diode relative to the first connection terminal of the additional winding and the first connection terminal of the reverse voltage source is essentially determined by the characteristic that energy coupled into the additional winding is discharged into the reverse voltage source through the first diode. Here, discharge occurs only when the voltage on the additional winding is greater than the reverse voltage due to the reverse voltage source plus the forward voltage of the first diode; that is, not all the energy of the resonant circuit formed by the resonant capacitor and the resonant choke is coupled into the additional winding and thus fed into the reverse voltage source, but only a portion of it.

[0014] In an embodiment of the circuit arrangement according to the invention, the second connection terminal of the additional winding is directly connected to the second connection terminal of the reverse voltage source, wherein, in another embodiment, the first connection terminal of the additional winding is connected to the third connection terminal of the reverse voltage source via a second diode. In this arrangement, depending on the polarity of the voltage on the additional winding, the energy coupled into the additional winding from the resonant choke is discharged through the first diode to the portion of the reverse voltage source between the first and second connection terminals, or through the second diode to the portion of the reverse voltage source between the second and third connection terminals. The polarity of the second diode relative to the first connection terminal of the additional winding and the third connection terminal of the reverse voltage source should be chosen such that the energy coupled into the additional winding is discharged into the reverse voltage source through the second diode.

[0015] In another embodiment of the circuit arrangement according to the invention, the second connection terminal of the additional winding is connected to the second connection terminal of the reverse voltage source not directly, but through a fourth diode. Furthermore, the first connection terminal of the additional winding is connected to the second connection terminal of the reverse voltage source through a second diode, and the second connection terminal of the additional winding is connected to the first connection terminal of the reverse voltage source through a third diode. The polarities of the second, third, and fourth diodes relative to the first or second connection terminal of the additional winding and the first or second connection terminal of the reverse voltage source should be chosen such that the energy coupled into the additional winding is discharged to the reverse voltage source through the diodes.

[0016] In this arrangement, depending on the polarity of the voltage on the additional winding, the potential applied at the first connection terminal of the reverse voltage source or the potential applied at the second connection terminal of the reverse voltage source is applied at the second connection terminal of the additional winding, offsetting only the conduction voltage of the third or fourth diode, respectively. Thus, the energy coupled into the additional winding from the resonant choke is discharged into the reverse voltage source through the first and fourth diodes or through the second and third diodes, depending on the polarity of the voltage on the additional winding.

[0017] In the circuit arrangement according to the invention, oscillation of the resonant current is prevented by the following means: the voltage of the drive current is limited in the resonant circuit formed by the resonant capacitor and the resonant choke by the following means: the voltage is transferred to an additional winding by magnetic coupling, where—according to the embodiment—the voltage is clamped to the voltage applied at the reverse voltage source by a first or second diode, or by a first and a fourth diode, or by a second and a third diode.

[0018] In an embodiment of the circuit arrangement according to the invention, wherein the second connection terminal of the additional winding is connected to the first connection terminal of the reverse voltage source via a third diode and to the second connection terminal of the reverse voltage source via a fourth diode, a switchable connection may be optionally provided between the second connection terminal of the additional winding and the connection terminal of the reverse voltage source at an intermediate potential, which is between the potentials applied at the first and second connection terminals of the reverse voltage source. When the switchable connection is closed, the second connection terminal of the additional winding is then connected to the intermediate potential, and when the switchable connection is open, the second connection terminal of the additional winding is connected to the potential at the first connection terminal of the reverse voltage source via the third diode and to the potential at the second connection terminal of the reverse voltage source via the fourth diode. As a result, through the switchable connection, the reverse voltage clamped onto the additional winding can be switched between half-voltage and full-voltage of the reverse voltage source, thereby allowing the balanced power to be changed.

[0019] Another implementation is conceivable in which the voltage value of the reverse voltage source can be adjusted and / or the effective reverse voltage can be switched between the voltage of the entire reverse voltage source and only a portion of the voltage of the reverse voltage source, so that the effective reverse voltage and therefore the balanced power are adjustable.

[0020] In the circuit arrangement according to the invention, the reverse voltage source may be formed by a first intermediate circuit capacitor and / or a second intermediate circuit capacitor. Here, the first DC voltage connection terminal corresponds to the first connection terminal of the reverse voltage source, and according to an embodiment, the center point of the intermediate circuit corresponds to the second connection terminal of the reverse voltage source, and the second DC voltage connection terminal corresponds to the third connection terminal of the reverse voltage source, or however, the second DC voltage connection terminal corresponds to the second connection terminal of the reverse voltage source.

[0021] The advantage of constructing a reverse voltage source through the intermediate circuit capacitor of the DC voltage intermediate circuit to be balanced is firstly apparent: no additional, separate reverse voltage source is required. Furthermore, the energy absorbed from the DC voltage intermediate circuit through the additional winding during the balancing process is simultaneously, at least partially, fed back into the DC voltage intermediate circuit. According to an embodiment of the circuit arrangement according to the invention, the energy absorbed from the first intermediate circuit capacitor is then fed into the second intermediate circuit capacitor, or vice versa, thereby additionally supporting the balancing process.

[0022] In an embodiment of the circuit arrangement according to the present invention, the resonant choke is arranged between the second connection terminal and the second intermediate point of the resonant capacitor, that is, the first intermediate point is connected to the second intermediate point through a series circuit consisting of the resonant capacitor and the resonant choke, and the bridge center point is directly connected to the center point of the intermediate circuit.

[0023] In another embodiment of the circuit arrangement according to the invention, the resonant choke is arranged between the intermediate circuit center point and the bridge center point, such that the first intermediate point is directly connected to the second intermediate point through a resonant capacitor.

[0024] In the circuit arrangement according to the invention, preferably, the four semiconductor switches are arranged such that they have the same conduction direction and blocking direction for the current flow between the first DC voltage connection terminal and the second DC voltage connection terminal, respectively. As a result, the anti-parallel diodes of the four semiconductor switches also have the same conduction direction and blocking direction between the first DC voltage connection terminal and the second DC voltage connection terminal, which are opposite to the corresponding conduction direction and blocking direction of their respective semiconductor switches.

[0025] In the circuit arrangement according to the invention, the voltage to be limited is applied through a switching process, i.e., suddenly applied to the resonant choke. To avoid high pulse currents in the resonant choke winding and the additional winding, the magnetic coupling between the two windings should therefore not be too good. Advantageously, the coupling factor between the resonant choke and the additional winding can, for example, be in the range of 0.8 to 0.9.

[0026] In an embodiment, the circuit arrangement according to the invention includes a control circuit for manipulating semiconductor switches, wherein the control circuit is configured to control a first semiconductor switch and a third semiconductor switch using a first PWM signal (pulse width modulation signal), and to control a second semiconductor switch and a fourth semiconductor switch using a second PWM signal, which is complementary to the first PWM signal except for the dead time to be considered during the turn-on and turn-off processes. The pulse duration of the PWM signal is here chosen to be, for example, equal to half the period duration of the resonant oscillation of the resonant circuit formed by the resonant capacitor and the resonant choke. For example, the dead time between turning off the first PWM signal and turning on the second PWM signal, or vice versa, is as small as allowed by the semiconductor switches used. Thus, a PWM signal is generated whose frequency is lower than the resonant frequency of the oscillating circuit of the resonant circuit formed by the series circuit of the resonant capacitor and the resonant choke, and whose PWM signal typically has a duty cycle close to 50%.

[0027] When the semiconductor switch is controlled by such first and second PWM signals via the control circuit, in the circuit arrangement according to the invention, a separate DC voltage intermediate circuit is balanced, in which the energy flow direction is automatically adjusted according to the imbalance of voltage present on the intermediate circuit half.

[0028] In another embodiment of the circuit arrangement according to the invention, the control circuit is configured to enable PWM signals for the first and second semiconductor switches via a first enable signal, and to enable PWM signals for the third and fourth semiconductor switches via a second enable signal. The circuit arrangement according to the invention can be selectively activated via the first and second enable signals to transfer charge from the first intermediate circuit capacitor to the second intermediate circuit capacitor, or vice versa.

[0029] In another embodiment, the circuit arrangement according to the invention includes a control circuit for controlling semiconductor switches, wherein the control circuit is configured to control a first semiconductor switch and a fourth semiconductor switch using a first PWM signal, and to control a second semiconductor switch and a third semiconductor switch using a second PWM signal, wherein the second PWM signal is complementary to the first PWM signal except for a dead time to be considered during the turn-on and turn-off processes, wherein the control circuit is configured to enable the PWM signals for the first semiconductor switch and the second semiconductor switch by a first enable signal, and to enable the PWM signals for the third semiconductor switch and the fourth semiconductor switch by a second enable signal.

[0030] Furthermore, the circuit arrangement according to the invention may also include a control circuit for controlling semiconductor switches. This control circuit is configured to control a first semiconductor switch using a first PWM signal and a second semiconductor switch using a second PWM signal, wherein the second PWM signal is complementary to the first PWM signal except for a dead time to be considered during the on and off processes; and to control a third semiconductor switch using a third PWM signal and a fourth semiconductor switch using a fourth PWM signal, wherein the fourth PWM signal is complementary to the third PWM signal except for a dead time to be considered during the on and off processes. In this embodiment, the control circuit is also configured to enable the PWM signals for the first and second semiconductor switches via a first enable signal and to enable the PWM signals for the third and fourth semiconductor switches via a second enable signal.

[0031] Therefore, the circuit arrangement according to the invention may include a control circuit for controlling semiconductor switches, the control circuit being configured to control a first semiconductor switch together with a third semiconductor switch and, complementaryly, control a second semiconductor switch together with a fourth semiconductor switch using a PWM signal, or, respectively, either control only the first semiconductor switch and, complementaryly, only the second semiconductor switch, or control only the third semiconductor switch and, complementaryly, only the fourth semiconductor switch. In particular, the circuit arrangement according to the invention may also include a control circuit for controlling semiconductor switches, the control circuit being configured to exclude simultaneous control of the first and fourth semiconductor switches using the same PWM signal and / or simultaneous control of the second and third semiconductor switches using the same PWM signal.

[0032] The control circuit can, for example, be configured to set a first enable signal when the difference between the voltage at the first intermediate circuit capacitor and the voltage at the second intermediate circuit capacitor is higher than a first threshold, and to reset the first enable signal when the difference between the voltage at the first intermediate circuit capacitor and the voltage at the second intermediate circuit capacitor is lower than a second threshold. Simultaneously, the control circuit can be configured to set a second enable signal when the difference between the voltage at the second intermediate circuit capacitor and the voltage at the first intermediate circuit capacitor is higher than the first threshold, and to reset the second enable signal when the difference between the voltage at the second intermediate circuit capacitor and the voltage at the first intermediate circuit capacitor is lower than the second threshold.

[0033] The first and second thresholds are preferably chosen such that balancing is activated only when the voltage difference at the intermediate circuit half is greater than the periodic fluctuation of the voltage difference at the intermediate circuit half, which may also occur when balancing the load.

[0034] Optionally, the first threshold can also be chosen to be smaller, and above this smaller first threshold, the duty cycle of the PWM signal can first be limited to a smaller value, such as 5%, to precharge the resonant capacitor. Then, the full duty cycle of approximately 50% is only adjusted above a third threshold, which is in the aforementioned order of magnitude.

[0035] In an embodiment where the control circuit is configured to control the first and third semiconductor switches using the first PWM signal and the second and fourth semiconductor switches using the second PWM signal, a common enable signal can be used instead of two enable signals. The common enable signal is set when the difference between the voltage at the first intermediate circuit capacitor and the voltage at the second intermediate circuit capacitor is higher than a first threshold, and the common enable signal is reset when the difference between the voltage at the first intermediate circuit capacitor and the voltage at the second intermediate circuit capacitor is lower than a second threshold.

[0036] According to another embodiment of the circuit arrangement according to the invention, the control circuit is configured to synchronize the activation of the PWM signal by an enable signal on the edge of the PWM signal. This ensures that, when the pulse duration of the PWM signal is selected accordingly, the semiconductor switch, after activation, is controlled for half a cycle of the resonant oscillation of the resonant circuit formed by the resonant capacitor and the resonant choke, rather than for a shorter duration. Attached Figure Description

[0037] The invention will now be described in more detail with reference to the accompanying drawings. The drawings are used herein to illustrate embodiments of the invention, but the invention is not limited to the features shown.

[0038] Figure 1 A first embodiment of the circuit arrangement according to the present invention is shown;

[0039] Figure 2 A second embodiment of the circuit arrangement according to the present invention is shown;

[0040] Figure 3 A third embodiment of the circuit arrangement according to the present invention is shown;

[0041] Figure 4 A fourth embodiment of the circuit arrangement according to the present invention is shown;

[0042] Figure 5 A fifth embodiment of the circuit arrangement according to the present invention is shown;

[0043] Figure 6 A sixth embodiment of the circuit arrangement according to the present invention is shown;

[0044] Figure 7 A seventh embodiment of the circuit arrangement according to the present invention is shown;

[0045] Figure 8 An embodiment of the circuit arrangement according to the invention, having a control circuit for controlling a semiconductor switch, is shown.

[0046] Figure 9 Another embodiment of the circuit arrangement according to the invention, having a control circuit for controlling a semiconductor switch, is shown; and

[0047] Figure 10 A flowchart is shown for generating signals via a state machine for manipulating a semiconductor switch according to the present invention. Detailed Implementation

[0048] Figure 1 A circuit arrangement 1 according to the present invention is shown, in which a separate DC voltage intermediate circuit is arranged between the first DC voltage connection terminal 2 and the second DC voltage connection terminal 3. The DC voltage intermediate circuit is formed by a series circuit of the first intermediate circuit capacitor C1 and the second intermediate circuit capacitor C2, and the series circuit has an intermediate circuit center point 4.

[0049] The series circuit of the first semiconductor switch T1 and the second semiconductor switch T2 is connected in parallel with the first intermediate circuit capacitor C1, and the series circuit of the third semiconductor switch T3 and the fourth semiconductor switch T4 is connected in parallel with the second intermediate circuit capacitor C2. Here, the four semiconductor switches T1, T2, T3, and T4 form a half-bridge between the first DC voltage connection terminal 2 and the second DC voltage connection terminal 3, and the half-bridge has a bridge center point 6, which is directly connected to the intermediate circuit center point 4.

[0050] Four semiconductor switches T1, T2, T3, and T4 are in Figure 1 The circuit arrangement 1 is arranged in such a way that they have the same conduction direction and blocking direction for the current flow between the first DC voltage connection terminal 2 and the second DC voltage connection terminal 3, and each has anti-parallel diodes 8, 9, 10, and 11, the conduction direction and blocking direction of which are opposite to the conduction direction and blocking direction of the semiconductor switches T1, T2, T3, and T4, respectively.

[0051] An oscillating circuit formed by the series connection of resonant capacitor Cres and resonant choke Lres is connected between a first intermediate point 5 and a second intermediate point 7. The first intermediate point 5 is located between a first semiconductor switch T1 and a second semiconductor switch T2, and the second intermediate point 7 is located between a third semiconductor switch T3 and a fourth semiconductor switch T4. Furthermore, an additional winding L1 is magnetically coupled to the resonant choke Lres. The first connection terminal of the additional winding L1 is connected to the first connection terminal 22 of the reverse voltage source 23 via a first diode D1, and the second connection terminal of the additional winding L1 is directly connected to the second connection terminal 24 of the reverse voltage source 23.

[0052] According to Figure 1 According to the embodiment of the circuit arrangement 1 of the present invention, the energy coupled from the resonant choke Lres to the additional winding L1 is discharged to the reverse voltage source 23 through the first diode D1 when the voltage on the additional winding L1 has the corresponding polarity. In this embodiment, the winding orientation of the resonant choke Lres and the additional winding L1 on the common core can be arbitrarily selected, that is, they can be selected not only in the same orientation but also in opposite orientations.

[0053] In the circuit arrangement 1 according to the present invention Figure 2 In the embodiments shown, with Figure 1 Compared to the previous implementation, the first connection terminal of the additional winding L1 is additionally connected to the third connection terminal 25 of the reverse voltage source 23 via the second diode D2. Here, the reverse voltage source 23 is constructed as a split reverse voltage source, wherein the potential at the second connection terminal 24 of the reverse voltage source 23 forms an intermediate potential between the potential at the first connection terminal 22 and the potential at the third connection terminal 25 of the reverse voltage source 23.

[0054] In this embodiment, depending on the polarity of the voltage on the additional winding L1, the energy coupled from the resonant choke Lres to the additional winding L1 is discharged through the first diode D1 to the portion of the reverse voltage source 23 between the first connection terminal 22 and the second connection terminal 24, or through the second diode D2 to the portion of the reverse voltage source 23 between the second connection terminal 24 and the third connection terminal 25. In this embodiment, the winding orientation of the resonant choke Lres and the additional winding L1 on the common core can be arbitrarily selected; that is, they can be selected not only in the same orientation but also in opposite orientations.

[0055] exist Figure 3In an embodiment of the circuit arrangement 1 according to the invention, the second connection terminal of the additional winding L1 is connected to the first connection terminal 22 of the reverse voltage source 23 via a third diode D3 and to the second connection terminal 24 of the reverse voltage source 23 via a fourth diode D4. In this embodiment of the circuit arrangement 1 according to the invention, depending on the polarity of the voltage on the additional winding L1, the energy coupled into the additional winding L1 from the resonant choke Lres is discharged to the reverse voltage source 23 either through the first diode D1 and the fourth diode D4 or through the second diode D2 and the third diode D3. In this embodiment, the winding orientation of the resonant choke Lres and the additional winding L1 on the common core can also be arbitrarily selected, that is, they can be selected not only in the same orientation but also in opposite orientations.

[0056] Figure 4 A circuit arrangement 1 according to the present invention is shown, in which the reverse voltage source 23 is formed by a separate DC voltage intermediate circuit arranged between the first DC voltage connection terminal 2 and the second DC voltage connection terminal 3. Correspondingly, here, in conjunction with... Figure 2 In a similar arrangement, the first connection terminal of the additional winding L1 is connected to the first DC voltage connection terminal 2 via the first diode D1 and to the second DC voltage connection terminal 3 via the second diode D2, and the second connection terminal of the additional winding L1 is directly connected to the center point 4 of the intermediate circuit.

[0057] According to Figure 4 According to the embodiment of the circuit arrangement 1 of the present invention, the energy coupled from the resonant choke Lres to the additional winding L1 is alternately discharged through the first diode D1 to the first intermediate circuit capacitor C1 of the DC voltage intermediate circuit and through the second diode D2 to the second intermediate circuit capacitor C2 of the DC voltage intermediate circuit, that is, alternately discharged to one of the intermediate circuit halves. Similar to... Figure 2 In the implementation method, the winding orientation of the resonant choke Lres and the additional winding L1 on the common iron core can be arbitrarily selected, that is, they can be selected not only in the same orientation but also in opposite orientations.

[0058] According to the circuit arrangement 1 of the present invention, Figure 5 The implementation methods shown are the same as Figure 4 The difference in the implementation method is that the second connection terminal of the additional winding L1 is not connected to the center point 4 of the intermediate circuit, but is similar to Figure 3In this embodiment, the circuit is connected to the first DC voltage connection terminal 2 via a third diode D3 and to the second DC voltage connection terminal 3 via a fourth diode D4. In this embodiment of the circuit arrangement 1 according to the invention, the energy coupled from the resonant choke Lres to the additional winding L1 is discharged either through the first diode D1 and the fourth diode D4 or through the second diode D2 and the third diode D3 into the DC voltage intermediate circuit formed by the series circuit of the first intermediate circuit capacitor C1 and the second intermediate circuit capacitor C2; that is, it is always discharged into both intermediate circuit halves, regardless of the polarity of the voltage on the additional winding. The winding directions of the resonant choke Lres and the coil L1 on the common core can be similar to... Figure 3 The implementation method can be arbitrarily selected, that is, it can be selected not only in the same direction but also in the opposite direction.

[0059] In the circuit arrangement 1 according to the present invention Figure 6 In the embodiments shown, with Figure 5 Compared to the previous implementation, a switchable connection 21 is arranged between the second connection terminal of the additional winding L1 and the center point 4 of the intermediate circuit. When the switchable connection 21 is closed, the second connection terminal of the additional winding L1 is then connected to the center point 4 of the intermediate circuit, and when the switchable connection 21 is open, the second connection terminal of the additional winding L1 is connected to the first DC voltage connection terminal 2 via the third diode D3 and to the second DC voltage connection terminal 3 via the fourth diode D4. Thus, the energy coupled into the additional winding L1 from the resonant choke Lres is as follows when the switchable connection 21 is closed: Figure 5 As in the embodiment, discharge is alternately applied to one of the intermediate circuit halves, and when the switchable connection 21 is open, as in Figure 6 In the embodiment described above, the discharge always goes into both intermediate circuit halves. Correspondingly, in this embodiment, the winding orientation of the resonant choke Lres and the additional winding L1 on the common core can be arbitrarily selected, that is, they can be selected not only in the same orientation but also in opposite orientations.

[0060] Figure 7 An embodiment of the circuit arrangement 1 according to the present invention is shown, wherein, with Figure 4 Compared to the previous implementation, the resonant choke Lres is connected between the intermediate circuit center point 4 and the bridge center point 6. Then, in this case, only the resonant capacitor Cres is connected between the first intermediate point 5 and the second intermediate point 7.

[0061] The resonant choke Lres and the additional winding L1 are wound on the common core with the following orientations: Figure 7 In the cases shown, the same direction is selected. This selection of winding direction is related to... Figure 4and Figure 5 Compared to the implementation method in the previous one, as Figure 7 The advantage of the implementation method is that the energy coupled from the resonant choke Lres to the additional winding L1 is always discharged to the intermediate circuit capacitor of the two intermediate circuit capacitors C1 or C2, where the energy from the resonant circuit formed by the resonant choke Lres and the resonant capacitor Cres is also discharged to the intermediate circuit capacitor. That is, the discharge of energy coupled from the resonant choke Lres to the additional winding L1 in this case additionally contributes to the balance of the DC voltage intermediate circuit.

[0062] The winding orientation of the resonant choke Lres and the additional winding L1 as shown is based on... Figure 7 Another advantage of this implementation is that the arrangement consisting of the additional winding L1 coupled to the resonant choke Lres can be implemented as a component with only three connection ends.

[0063] In principle, such as in Figure 7 Such an implementation is of course also possible, which has the resonant choke Lres and the additional winding L1 on the common core selected in opposite directions, wherein the advantages mentioned above are of course no longer present.

[0064] Furthermore, it is also possible that, in situations such as Figure 7 As shown, with the resonant choke Lres positioned between the center point 4 of the intermediate circuit and the center point 6 of the bridge, the second connection terminal of the additional winding L1 is as follows: Figure 5 The diagram shows a connection to the first DC voltage terminal 2 via a third diode D3 and a connection to the second DC voltage terminal 3 via a fourth diode D4. In this case, it is also as shown in the diagram... Figure 5 As in the implementation, the energy coupled into the additional winding L1 will always be discharged into the two intermediate circuit halves and thus no longer contribute to the balance of the DC voltage intermediate circuit.

[0065] exist Figure 8 The diagram shows an embodiment of the circuit arrangement 1 according to the present invention, having a control circuit 12 for controlling semiconductor switches T1, T2, T3, and T4.

[0066] The signal line for the first enable signal En_Pos is connected to the first input terminal of the first AND gate 13 and the first input terminal of the second AND gate 14. The signal line for the second enable signal En_Neg is connected to the first input terminal of the third AND gate 15 and the first input terminal of the fourth AND gate 16. Furthermore, the signal line for the first PWM signal PWM_1 is connected to the second input terminals of the first AND gate 13 and the third AND gate 16, respectively, and the signal line for the second PWM signal PWM_2 is connected to the second input terminals of the second AND gate 14 and the fourth AND gate 15, respectively. The output terminals of AND gates 13, 14, 15, and 16 are connected to the control input terminals of semiconductor switches T1, T2, T3, and T4 via drivers 17, 18, 19, and 20, respectively.

[0067] Figure 8 The control circuit 12 is thus configured to enable or block the first PWM signal PWM_1 via the first enable signal En_Pos to control the first transistor T1, enable or block the second PWM signal PWM_2 via the first enable signal En_Pos to control the second transistor T2, enable or block the first PWM signal PWM_1 via the second enable signal En_Neg to control the third transistor T3, and enable or block the second PWM signal PWM_2 via the second enable signal En_Neg to control the fourth transistor T4.

[0068] Figure 9 The control circuit 12 according to the embodiment of the circuit arrangement 1 of the present invention and Figure 8 The difference in the control circuit is that the signal lines for the first PWM signal PWM_1 are connected to the second input terminals of the first AND gate 13 and the fourth AND gate 16, respectively, and the signal lines for the second PWM signal PWM_2 are connected to the second input terminals of the second AND gate 14 and the third AND gate 15, respectively.

[0069] Figure 9 The control circuit 12 is thus configured to enable or block the first PWM signal PWM_1 via the first enable signal En_Pos to control the first transistor T1, enable or block the second PWM signal PWM_2 via the first enable signal En_Pos to control the second transistor T2, enable or block the second PWM signal PWM_2 via the second enable signal En_Neg to control the third transistor T3, and enable or block the first PWM signal PWM_1 via the second enable signal En_Neg to control the fourth transistor T4.

[0070] Replace as in Figure 8 and 9The interconnection of logic gates, as shown in control circuit 12, for controlling semiconductor switches T1, T2, T3, and T4, can also be generated by a state machine, for example, when using a microcontroller. The corresponding flowchart is in... Figure 10 As shown in the image.

[0071] First, in step S01, it is checked whether the difference Vpos-Vneg between the voltage Vpos at the first intermediate circuit capacitor C1 and the voltage Vneg at the second intermediate circuit capacitor C2 is higher than a first threshold V1. If not, in step S02, it is checked whether the difference Vneg-Vpos between the voltage Vneg at the second intermediate circuit capacitor C2 and the voltage Vpos at the first intermediate circuit capacitor C1 is higher than the first threshold V1. If this is also not the case, in step S03, all semiconductor switches T1, T2, T3, and T4 are turned off, and steps S01 and S02 are repeated.

[0072] If the check time difference Vpos-Vneg in step S01 is higher than the first threshold V1, then the first semiconductor switch T1 is turned on in the fourth step S04, the time is waited for a duration ta in the fifth step S05, and then the first semiconductor switch T1 is turned off again in the sixth step S06. Here, the duration ta corresponds, for example, to half the period duration of the resonant oscillation of the resonant circuit formed by the resonant capacitor Cres and the resonant choke Lres.

[0073] Then, before turning on the second semiconductor switch T2 in step eight S08, a dead time tb is waited for in step seven S07. The dead time tb takes into account the non-negligible switching times of semiconductor switches T1, T2, T3, and T4 to ensure that the first semiconductor switch T1 and the second semiconductor switch T2 cannot be turned on simultaneously and then short-circuit the first intermediate circuit capacitor C1. For example, the dead time tb should be chosen to be as small as allowed by the semiconductor switches used.

[0074] In the ninth step S09, the time duration ta is waited for again, and then in the tenth step S10, the second semiconductor switch T2 is turned off again. In the eleventh step S11, the dead time tb is waited for again to ensure that the first semiconductor switch T1 and the second semiconductor switch T2 cannot be turned on at the same time.

[0075] In step S12, it is checked whether the difference Vpos-Vneg is lower than the second threshold V2. If not, steps S04 to S12 are repeated. Otherwise, the process branches to step S03, in which all semiconductor switches T1, T2, T3, and T4 are turned off, and then steps S01 and S02 are traversed again as described above.

[0076] Here, the second threshold V2 should be selected to be less than the first threshold V1 in order to achieve hysteresis for activating the circuit arrangement 1 for balancing. If the difference Vneg-Vpos mentioned in the check in step S02 is higher than the first threshold V1, the fourth semiconductor switch T4 is turned on in the thirteenth step S13, the duration ta is waited in the fourteenth step S14, and then the fourth semiconductor switch T4 is turned off again in the fifteenth step S15.

[0077] Then, before turning on the third semiconductor switch T3 in step seventeen S17, a dead time tb is waited for in step sixteen S16. In this case, the non-negligible switching time of semiconductor switches T1, T2, T3, and T4 is taken into account by the dead time tb, so as to ensure that the third semiconductor switch T3 and the fourth semiconductor switch T4 are not turned on at the same time, because otherwise they would short-circuit the second intermediate circuit capacitor C2.

[0078] In step S18, the time duration ta is waited for again. Then, in step S19, the third semiconductor switch T3 is turned off again. In step S20, the dead time tb is waited for again to ensure that the third semiconductor switch T3 and the fourth semiconductor switch T4 are not turned on at the same time.

[0079] In step S21, it is checked whether the difference Vneg-Vpos is lower than the second threshold V2. If not, steps S13 to S21 are repeated. Otherwise, the process branches to step S03, where all semiconductor switches T1, T2, T3, and T4 are turned off, and then steps S01 and S02 are traversed again as described above.

[0080] In an alternative, unshown configuration of the state machine, it is also possible to... Figure 10 In steps S01 and S12, the difference Vpos-Vneg is checked to see if it is higher than the first threshold V1 or lower than the second threshold V2. In this configuration of the state machine, steps S02, S21, and S13 to S20 are then omitted, and in steps S04 to S11, semiconductor switch T3 and semiconductor switch T1 are simultaneously turned on or off, and semiconductor switch T4 and semiconductor switch T2 are simultaneously turned on or off.

[0081] The present invention is not limited to the embodiments explicitly shown, but can be modified in various ways and methods, especially in combination with other embodiments shown or known to those skilled in the art.

[0082] List of reference numerals

[0083] 1. Circuit layout

[0084] 2 DC voltage connection terminal

[0085] 3 DC voltage connection terminal

[0086] 4. Center point of intermediate circuit

[0087] 5. Midpoint

[0088] 6. Bridge center point

[0089] 7. Midpoint

[0090] 8 anti-parallel diodes

[0091] 9 Anti-parallel diodes

[0092] 10 Anti-parallel diodes

[0093] 11 Anti-parallel diodes

[0094] 12 Control Circuit

[0095] 13. and the door

[0096] 14. and the door

[0097] 15. With the door

[0098] 16. With the door

[0099] 17 drives

[0100] 18 drives

[0101] 19 drives

[0102] 20 drives

[0103] 21. Switchable connection part

[0104] 22 Connection end

[0105] 23 Reverse voltage source

[0106] 24 Connection end

[0107] 25 Connecting end

[0108] T1–T4 Semiconductor Switches

[0109] Diodes D1–D4

[0110] C1 Intermediate circuit capacitor

[0111] C2 Intermediate circuit capacitor

[0112] Cres resonant capacitor

[0113] Lres resonant choke

[0114] L1 Additional winding

[0115] Steps S01–S21

[0116] Vpos voltage

[0117] Vneg voltage

[0118] V1 threshold

[0119] V2 threshold

[0120] PWM_1 PWM signal

[0121] PWM_2 PWM signal

[0122] En_Pos enable signal

[0123] En_Neg enable signal

Claims

1. A circuit arrangement (1) for balancing a discrete DC voltage intermediate circuit, the DC voltage intermediate circuit comprising a series circuit of a first intermediate circuit capacitor (C1) and a second intermediate circuit capacitor (C2) between a first DC voltage connection terminal (2) and a second DC voltage connection terminal (3), and the DC voltage intermediate circuit having an intermediate circuit center point (4) between the first intermediate circuit capacitor (C1) and the second intermediate circuit capacitor (C2), wherein, In the circuit arrangement (1), the first DC voltage connection terminal (2) is connected to the first intermediate point (5) via a first semiconductor switch (T1), the first intermediate point (5) is connected to the bridge center point (6) via a second semiconductor switch (T2), the bridge center point (6) is connected to the second intermediate point (7) via a third semiconductor switch (T3), and the second intermediate point (7) is connected to the second DC voltage connection terminal (3) via a fourth semiconductor switch (T4). The semiconductor switches (T1, T2, T3, T4) each have anti-parallel diodes (8, 9, 10, 11). Furthermore, the first connection terminal of the resonant capacitor (Cres) is connected to the first intermediate point (5), and the second connection terminal of the resonant capacitor (Cres) is connected to the intermediate circuit center point (4) via a connection path. In this connection path, a resonant choke (…) The additional winding (Lres) is arranged in series with the third semiconductor switch (T3), and the connection path extends through the second intermediate point (7). The additional winding (L1) is magnetically coupled to the resonant choke (Lres), wherein the first connection terminal of the additional winding (L1) is connected to the first connection terminal (22) of the reverse voltage source (23) through a first diode (D1), and the second connection terminal of the additional winding (L1) is connected to the second connection terminal (24) of the reverse voltage source (23) in such a way that a discharge path is formed for energy coupled from the resonant choke (Lres) into the additional winding (L1) and discharged through the first diode (D1) into the reverse voltage source (23), wherein the reverse voltage source (23) is formed by the first intermediate circuit capacitor (C1) and / or the second intermediate circuit capacitor (C2).

2. The circuit arrangement (1) according to claim 1, wherein, The second connection terminal of the additional winding (L1) is directly connected to the second connection terminal (24) of the reverse voltage source (23).

3. The circuit arrangement (1) according to claim 2, wherein, The first connection terminal of the additional winding (L1) is connected to the third connection terminal (25) of the reverse voltage source (23) via the second diode (D2).

4. The circuit arrangement (1) according to claim 1, wherein, The first connection terminal of the additional winding (L1) is connected to the second connection terminal (24) of the reverse voltage source (23) through the second diode (D2), and the second connection terminal of the additional winding (L1) is connected to the first connection terminal (22) of the reverse voltage source (23) through the third diode (D3) and to the second connection terminal (24) of the reverse voltage source (23) through the fourth diode (D4).

5. The circuit arrangement (1) according to any one of claims 1 to 4, wherein, The resonant choke (Lres) is arranged between the second connection terminal of the resonant capacitor (Cres) and the second midpoint (7).

6. The circuit arrangement (1) according to any one of claims 1 to 4, wherein, The resonant choke (Lres) is arranged between the center point (4) of the intermediate circuit and the center point (6) of the bridge.

7. The circuit arrangement (1) according to any one of the preceding claims, wherein, The semiconductor switches (T1, T2, T3, T4) are arranged such that they have the same conduction direction and blocking direction for the current flow between the first DC voltage connection terminal (2) and the second DC voltage connection terminal (3).

8. The circuit arrangement (1) according to any one of the preceding claims, wherein, The coupling factor between the resonant choke (Lres) and the additional winding (L1) is in the range of 0.8 to 0.

9.

9. The circuit arrangement (1) according to any one of the preceding claims, the circuit arrangement comprising a control circuit (12) for controlling the semiconductor switches (T1, T2, T3, T4) using PWM signals (PWM_1, PWM_2), wherein, The control circuit (12) is configured to exclude simultaneous control of the first semiconductor switch (T1) and the fourth semiconductor switch (T4) using the same PWM signal (PWM_1, PWM_2) and / or exclude simultaneous control of the second semiconductor switch (T2) and the third semiconductor switch (T3) using the same PWM signal (PWM_1, PWM_2).

10. The circuit arrangement (1) according to any one of claims 1 to 9, wherein the circuit arrangement comprises a control circuit (12) for controlling the semiconductor switches (T1, T2, T3, T4), wherein, The control circuit (12) is configured to control the first semiconductor switch (T1) together with the third semiconductor switch (T3) using PWM signals (PWM_1, PWM_2) and, complementaryly, control the second semiconductor switch (T2) together with the fourth semiconductor switch (T4).

11. The circuit arrangement (1) according to any one of claims 1 to 9, wherein the circuit arrangement includes a control circuit (12) for controlling the semiconductor switches (T1, T2, T3, T4), wherein, The control circuit (12) is configured to use PWM signals (PWM_1, PWM_2) to either control only the first semiconductor switch (T1) and, complementaryly, only the second semiconductor switch (T2), or to control only the third semiconductor switch (T3) and, complementaryly, only the fourth semiconductor switch (T4).

12. The circuit arrangement (1) according to claim 10, wherein, The control circuit (12) is configured to control the first semiconductor switch (T1) and the third semiconductor switch (T3) using a first PWM signal (PWM_1), and to control the second semiconductor switch (T2) and the fourth semiconductor switch (T4) using a second PWM signal (PWM_2), wherein the second PWM signal is complementary to the first PWM signal (PWM_1).

13. The circuit arrangement (1) according to claim 12, wherein, The control circuit (12) is configured to enable PWM signals (PWM_1, PWM_2) for the first semiconductor switch (T1) and the second semiconductor switch (T2) via a first enable signal (En_Pos), and to enable PWM signals (PWM_1, PWM_2) for the third semiconductor switch (T3) and the fourth semiconductor switch (T4) via a second enable signal (En_Neg).

14. The circuit arrangement (1) according to claim 11, wherein, The control circuit (12) is configured to control the first semiconductor switch (T1) and the fourth semiconductor switch (T4) using a first PWM signal (PWM_1), and to control the second semiconductor switch (T2) and the third semiconductor switch (T3) using a second PWM signal (PWM_2), wherein the second PWM signal is complementary to the first PWM signal (PWM_1). The control circuit (12) is configured to enable the PWM signals (PWM_1, PWM_2) for the first semiconductor switch (T1) and the second semiconductor switch (T2) using a first enable signal (En_Pos), and to enable the PWM signals (PWM_1, PWM_2) for the third semiconductor switch (T3) and the fourth semiconductor switch (T4) using a second enable signal (En_Neg).

15. The circuit arrangement (1) according to claim 13 or 14, wherein, The control circuit (12) is configured to set the first enable signal (En_Pos) when the difference between the voltage at the first intermediate circuit capacitor (C1) and the voltage at the second intermediate circuit capacitor (C2) is higher than a first threshold (V1), and to reset the first enable signal again when the difference between the voltage at the first intermediate circuit capacitor (C1) and the voltage at the second intermediate circuit capacitor (C2) is lower than a second threshold (V2). The control circuit is also configured to set the second enable signal (En_Neg) when the difference between the voltage at the second intermediate circuit capacitor (C2) and the voltage at the first intermediate circuit capacitor (C1) is higher than the first threshold (V1), and to reset the second enable signal again when the difference between the voltage at the second intermediate circuit capacitor (C2) and the voltage at the first intermediate circuit capacitor (C1) is lower than the second threshold (V2).

16. The circuit arrangement (1) according to any one of claims 13 to 15, wherein, The control circuit (12) is configured to synchronize the activation of the PWM signals (PWM_1, PWM_2) at the edges of the PWM signals (PWM_1, PWM_2) via the enable signals (En_Pos, En_Neg).

17. The circuit arrangement (1) according to any one of claims 9 to 16, wherein, The frequencies of the PWM signals (PWM_1, PWM_2) are lower than the resonant frequency of the oscillation circuit formed by the series circuit of the resonant capacitor (Cres) and the resonant choke (Lres).

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