Method of manufacturing a semiconductor device using a photomask

Abstract

The present application relates to a method of manufacturing a semiconductor device using a photomask. In the method of manufacturing a semiconductor device, an EUV lithography operation using an EUV mask is performed on a photoresist layer formed over a semiconductor substrate in an EUV scanner. After the EUV lithography operation, the EUV mask is unloaded from a mask stage of the EUV scanner. The EUV mask is placed under a reduced pressure lower than an atmospheric pressure. The EUV mask is heated at a first temperature in a range of 100°C to 350°C under the reduced pressure. After the heating, the EUV mask is stored in a mask stocker.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to the field of semiconductor technology, and more particularly to a method of manufacturing a semiconductor device using a photomask. BACKGROUND

[0002] As the semiconductor industry moves to nanometer technology nodes in pursuit of higher device densities, higher performance, and lower costs, the challenges from manufacturing and design issues become greater. Technological advances in IC materials and design have produced generations of ICs, each having more functionality and greater complexity than the one before. As ICs evolve, the functional density (i.e., the number of interconnected devices per chip area) has generally increased while the geometric size (i.e., the smallest component (or line) that can be created) has decreased. This scaling down process generally provides benefits in increased production capacity and lower costs. This scaling down also increases the complexity of processing and manufacturing ICs. Photolithography operations are one of the key operations in the semiconductor manufacturing process. Photolithography technology includes ultraviolet photolithography, deep ultraviolet photolithography, and extreme ultraviolet lithography (EUVL). Photomasks are an important component in photolithography operations. It is critical to manufacture and maintain photomasks free of resolvable defects. SUMMARY

[0003] According to an aspect of the present application, there is provided a method of manufacturing a semiconductor device, comprising: performing, in an EUV scanner, an EUV lithography operation on a photoresist layer formed over a semiconductor substrate using an EUV mask; unloading, after the EUV lithography operation, the EUV mask from a mask stage of the EUV scanner; placing the EUV mask under a reduced pressure lower than an atmospheric pressure; heating the EUV mask at a first temperature in a range of 100°C to 350°C under the reduced pressure; and storing, after the heating, the EUV mask in a mask stocker.

[0004] According to another aspect of the present application, there is provided a method of manufacturing a semiconductor device, comprising: performing, in an EUV lithography apparatus, an EUV lithography operation using an EUV mask; unloading, after the EUV lithography operation, the EUV mask from a mask stage of the EUV lithography apparatus; heating the EUV mask at a first temperature in a range of 100°C to 350°C under a reduced pressure lower than an atmospheric pressure; and storing, after the heating, the EUV mask in a mask stocker, wherein outgassing from the EUV mask is monitored during the heating.

[0005] According to still another aspect of the present application, there is provided a method of manufacturing a semiconductor device, comprising: performing an EUV lithography operation using an EUV mask in an EUV lithography apparatus; unloading the EUV mask from a mask stage of the EUV lithography apparatus after the EUV lithography operation; heating the EUV mask at a first temperature in a range of 100°C to 350°C under a reduced pressure lower than an atmospheric pressure; and storing the EUV mask in a mask stocker after the heating, wherein the EUV mask comprises: a substrate; a reflective layer comprising a plurality of layers of Si and Mo and arranged above the substrate; one or more intermediate layers arranged above the reflective layer; and an absorber layer arranged above the one or more intermediate layers, wherein the absorber layer comprises a plurality of dummy patterns having a size below a resolution limit of EUV lithography, and one of the one or more intermediate layers is exposed at a bottom of the plurality of dummy patterns. BRIEF DESCRIPTION OF DRAWINGS

[0006] The present disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, according to the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for the sake of discussion. To facilitate an understanding of this disclosure, a number of terms are defined below.

[0007] Figure 1 An extreme ultraviolet lithography tool is shown.

[0008] Figure 2A A simplified schematic of an extreme ultraviolet lithography tool is shown, and Figure 2B A schematic of details of an extreme ultraviolet lithography tool is shown.

[0009] Figure 3 is a cross-sectional view of a reflective mask.

[0010] Figure 4 is a flowchart illustrating a method of processing a photomask according to an embodiment of the present disclosure.

[0011] Figure 5 Effects of heating a photomask according to an embodiment of the present disclosure are shown.

[0012] Figure 6 A schematic of a photomask heating apparatus according to an embodiment of the present disclosure is shown.

[0013] Figure 7 A schematic of an EUV lithography system according to an embodiment of the present disclosure is shown.

[0014] Figure 8 A schematic of an EUV lithography system according to an embodiment of the present disclosure is shown.

[0015] Figure 9 A schematic diagram of an EUV lithography system is shown in accordance with embodiments of the present disclosure.

[0016] Figure 10 A schematic diagram of an EUV lithography system is shown in accordance with embodiments of the present disclosure.

[0017] Figure 11A and Figure 11B A cross-sectional view of an EUV reflective photomask is shown in accordance with embodiments of the present disclosure.

[0018] Figure 12A A plan (layout) view of an EUV reflective photomask is shown in accordance with embodiments of the present disclosure. Figure 12B 、 Figure 12C 、 Figure 12D 、 Figure 12E and Figure 12F A sub-resolution pattern used in an EUV reflective photomask in accordance with embodiments of the present disclosure is shown.

[0019] Figure 13 is a flowchart illustrating a method of manufacturing a photomask in accordance with embodiments of the present disclosure.

[0020] Figure 14A A flowchart of a method of manufacturing a semiconductor device is shown, and Figure 14B 、 Figure 14C 、 Figure 14D and Figure 14E Sequential manufacturing operations of a method of manufacturing a semiconductor device in accordance with embodiments of the present disclosure are shown. DETAILED DESCRIPTION

[0021] It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different characteristics of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, dimensions of the elements can depend on the process conditions and / or desired characteristics of the devices. Moreover, in the following description, forming a first feature over or on a second feature can include embodiments where the first feature is formed directly in contact with the second feature, and can also include embodiments where additional features can be formed between the first feature and the second feature such that the first feature and the second feature can not be directly in contact. For the sake of simplicity and clarity, various features can be illustrated with callouts, dashed lines, and / or cross-hatching.

[0022] Moreover, spatially relative terms (e.g., "beneath," "below," "lower," "above," "upper," and the like) can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Also, the term "comprising" can mean "including," "comprising," or "consisting of." The materials, constructions, dimensions, processes, and / or operations described in one embodiment can be applied to other embodiments, and detailed descriptions thereof can be omitted.

[0023] The present disclosure generally relates to extreme ultraviolet (EUV) lithography masks and methods. In EUVL tools, a laser-produced plasma (LPP) generates extreme ultraviolet radiation that is used to image a substrate coated with photoresist. In EUV tools, a firing laser heats a metal (e.g., tin, lithium, etc.) target droplet in an LPP chamber to ionize the droplet into a plasma that emits EUV radiation. To reproducibly generate EUV radiation, the target droplets that reach a focal point (also referred to herein as a "firing zone") must have substantially the same size and reach the firing zone at the same time as a firing pulse from the firing laser reaches the firing zone. Thus, the stable generation of target droplets that travel from a target droplet generator to the firing zone at a uniform (or predictable) velocity contributes to the efficiency and stability of the LPP EUV radiation source.

[0024] Figure 1 is a schematic diagram of an EUV lithography tool having a laser-produced plasma (LPP) based EUV radiation source constructed in accordance with some embodiments of the present disclosure. The EUV lithography tool includes an EUV radiation source 100 for generating EUV radiation, an exposure device 200 such as a scanner, and a firing laser source 300. As shown, in some embodiments, the EUV radiation source 100 and the exposure device 200 are mounted on a main floor MF of a clean room, while the firing laser source 300 is mounted in a base floor BF located below the main floor. Each of the EUV radiation source 100 and the exposure device 200 are placed above pedestal plates PP1 and PP2 via dampers DP1 and DP2, respectively. The EUV radiation source 100 and the exposure device 200 are coupled to each other by a coupling mechanism, which can include a focusing unit. Figure 1

[0025] ​EUV lithography tools are designed to expose a resist layer by EUV light (also referred to herein interchangeably as EUV radiation). The resist layer is a material that is sensitive to EUV light. EUV lithography tools employ an EUV radiation source 100 to generate EUV light, e.g., EUV light having a wavelength in a range between about 1 nm and about 100 nm. In one particular example, the EUV radiation source 100 generates EUV light having a wavelength centered at about 13.5 nm. In the present embodiment, the EUV radiation source 100 utilizes a laser-produced plasma (LPP) mechanism to generate EUV radiation.

[0026] The exposure device 200 includes various reflective optical elements (e.g., convex / concave / planar mirrors), a mask holding mechanism including a mask table, and a wafer holding mechanism. The EUV radiation generated by the EUV radiation source 100 is directed by the reflective optical elements onto a photomask fixed on the mask table. In some embodiments, the mask table includes an electrostatic chuck (e-chuck) for fixing the photomask.

[0027] Figure 2A is a simplified schematic diagram of an extreme ultraviolet lithography tool, and Figure 2B is a schematic diagram showing details of an extreme ultraviolet lithography tool according to embodiments of the present disclosure, showing exposure of a photoresist-coated substrate 210 with a patterned EUV light beam. The exposure device 200 is an integrated circuit lithography tool, e.g., a stepper, a scanner, a step-and-scan system, a direct write system, a device using a contact and / or proximity mask, etc., provided with one or more optical devices 205a, 205b (e.g., for illuminating a patterned optical device 205c (e.g., a photomask) with an EUV light beam to generate a patterned light beam), and one or more demagnifying projection optical devices 205d, 205e (for projecting the patterned light beam onto the substrate 210). A mechanical assembly (not shown) can be provided to create a controlled relative motion between the substrate 210 and the patterned optical device 205c. As Figure 2A and Figure 2B As further shown, the EUVL tool includes an EUV radiation source 100 including an EUV light radiator ZE emitting EUV light in a chamber 105, which is reflected by a collector 110 along a path into the exposure device 200 to illuminate the substrate 210.

[0028] In some embodiments, the photomask (mask template) 205c is held by an electrostatic chuck 221, and the photomask (mask template) 205c and the electrostatic chuck 221 are positioned such that the EUV radiation provided from the EUV radiation source is focused when it reaches the surface of the semiconductor wafer. In some embodiments, a hydrogen flow is provided along the surface of the photomask 205c. In some embodiments, a nozzle 920 is installed to inject hydrogen gas 930 along the y-axis. The y-axis is perpendicular to the x-axis of the photomask (the axis of motion along the hydrogen gas) and perpendicular to the z-axis (which is substantially orthogonal to the surface of the mask template).

[0029] Nozzle 920 is configured to eject a gas (e.g., hydrogen) along the y-axis. During the EUV lithography process, the hydrogen gas stream 930 ejected by nozzle 920 along the y-axis drifts toward the surface of the photomask due to its light molecular weight. Because hydrogen is lighter than air, it rises vertically relative to air. The drifting hydrogen 930 accumulates / deposits at the edge 950 of the photomask 205c, permeating into the space between the photomask and the cover film 952.

[0030] As used herein, the term "optical device" is intended to be interpreted broadly as including, but not limited to, one or more components that reflect and / or transmit and / or act on incident light, and including, but not limited to, one or more lenses, windows, filters, wedges, prisms, prism gratings, gratings, transmission fibers, etalons, diffusers, homogenizers, detectors and other instrument components, apertures, axial prisms and mirrors, including multilayer mirrors, near-normal incident mirrors, grazing incident mirrors, specular reflectors, diffusers and combinations thereof. Furthermore, unless otherwise stated, the term "optical device" as used herein is not intended to be limited to components that operate alone or advantageously within one or more specific wavelength ranges (e.g., according to the EUV output light wavelength, the irradiating laser wavelength, the wavelength suitable for metrology, or any other specific wavelength).

[0031] Because gas molecules absorb EUV light, lithography systems used for EUV lithography patterning are kept in a vacuum or low-pressure environment to avoid loss of EUV intensity.

[0032] In this disclosure, the terms mask, photomask, and photomask template are used interchangeably. In this embodiment, Figure 3 The patterned optical device 205c shown is a reflective light mask. In one embodiment, the reflective mask 205c includes a substrate 30 having a suitable material (e.g., a low thermal expansion material or fused silica), such as... Figure 3The material includes TiO2-doped SiO2, or other suitable material with low thermal expansion, in various examples. In some embodiments, the low thermal expansion glass substrate transmits light at visible wavelengths, a portion of infrared wavelengths near the visible spectrum (near infrared), and a portion of ultraviolet wavelengths. In some embodiments, the low thermal expansion glass substrate absorbs extreme ultraviolet wavelengths and deep ultraviolet wavelengths near the extreme ultraviolet.

[0033] The reflective mask plate 205c includes a plurality of reflective layers 35 deposited on a substrate. The plurality of reflective layers 35 includes a plurality of film pairs, such as molybdenum-silicon (Mo / Si) film pairs (e.g., in each film pair, a molybdenum layer 39 is above or below a silicon layer 37). Alternatively, the plurality of reflective layers 35 can include molybdenum-beryllium (Mo / Be) film pairs, or other suitable material configured to highly reflect EUV light. In some embodiments, the Mo / Si multilayer stack 35 includes about 30 alternating layers (each alternating layer composed of silicon and molybdenum) to about 60 alternating layers (each alternating layer composed of silicon and molybdenum). In some embodiments, about 35 to about 50 alternating layers are formed, each alternating layer composed of silicon and molybdenum. In certain embodiments, there are about 40 alternating layers, each alternating layer composed of silicon and molybdenum. In some embodiments, the silicon and molybdenum layers are formed by chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD) (sputtering), or any other suitable film formation method. Each layer of silicon and molybdenum has a thickness of about 2 nm to about 10 nm. In some embodiments, the silicon layers and the molybdenum layers have approximately the same thickness. In other embodiments, the silicon layers and the molybdenum layers have different thicknesses. In some embodiments, each layer of silicon and molybdenum has a thickness of about 3 nm to about 4 nm.

[0034] The mask 205c can also include a capping layer 40, such as a layer made of ruthenium (Ru), for protecting the multilayer 35. The capping layer 40 is disposed above the Mo / Si multilayer 35. In some embodiments, the capping layer 40 is made of ruthenium with a thickness of about 2 nm to about 10 nm. In certain embodiments, the capping layer 40 has a thickness of about 2 nm to about 4 nm. In some embodiments, the capping layer 40 is formed by chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, or any other suitable film formation method.

[0035] In some embodiments, a mirror layer 38 is disposed between the plurality of reflective layers 35 and the capping layer 40. In some embodiments, the mirror layer 38 includes an oxide layer made of, for example, an oxide of silicon. In some embodiments, the oxide layer is formed by a deposition method as shown above or oxidation of a top Si layer of the reflective layers 35. In some embodiments, the mirror layer 38 has a thickness in a range of about 2 nm to about 10 nm.

[0036] The mask further includes an absorber (or absorption) layer 45. In some embodiments, the absorption layer 45 is disposed above the capping layer 40. The absorption layer 45 is patterned to define layers of an integrated circuit (IC).

[0037] In some embodiments, the absorption layer 45 is a Ta-based material. In some embodiments, the absorption layer is made of TaN, TaO, TaBN, or TaBO with a thickness of about 25 nm to about 100 nm. In certain embodiments, the thickness of the absorption layer 45 is in the range of about 50 nm to about 75 nm. In some embodiments, the absorption layer 45 is formed by chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, or any other suitable film formation method.

[0038] In some embodiments, an anti-reflective layer (not shown) is optionally formed above the absorption layer 45. The anti-reflective layer has a thickness of about 2 nm to about 10 nm. In some embodiments, the anti-reflective layer has a thickness of about 3 nm to about 6 nm. In some embodiments, the anti-reflective layer is formed by chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, or any other suitable film formation method. EUV masks require very low surface roughness and must be free of resolvable defects.

[0039] In some embodiments, the reflective mask 205c includes a backside conductive layer 60. In some embodiments, the conductive layer 60 is formed on a second major surface of the substrate 30 that is opposite to a first major surface of the substrate 30 on which the Mo / Si multilayer 35 is formed. In some embodiments, the conductive layer 60 is made of chromium, chromium nitride, or TaB with a thickness of about 25 nm to about 150 nm. In some embodiments, the conductive layer 60 has a thickness of about 70 nm to about 100 nm. In some embodiments, the conductive layer 60 is formed by chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, or any other suitable film formation method.

[0040] In some embodiments, the reflective mask 205c includes a boundary 65, also referred to as a black boundary 65, etched down to the substrate 30 around the pattern 55 to define a circuit area to be imaged and a peripheral area not to be imaged. In some embodiments, the black boundary reduces light leakage.

[0041] In various embodiments of the present disclosure, the photoresist-coated substrate 210 is a semiconductor wafer, such as a silicon wafer or other type of wafer to be patterned.

[0042] In some embodiments, the EUVL tool further includes (or is coupled with) other modules. In addition, the EUVL tool includes a radiation source, an EUV exposure tool (scanner), and a photomask stocker (reticle library) for storing a plurality of photomasks under an inert gas environment.

[0043] As shown in Figure 1 EUV radiation source 100 includes a target droplet generator 115 and an LPP collector 110 enclosed by a chamber 105. In some embodiments, target droplet generator 115 includes a container for holding a source material and a nozzle 120 through which target droplets DP of the source material are supplied into chamber 105.

[0044] In some embodiments, target droplets DP are droplets of tin (Sn), lithium (Li), or an alloy of Sn and Li. In some embodiments, target droplets DP each have a diameter in a range from about 10 micrometers (pm) to about 100 pm. For example, in one embodiment, target droplets DP are tin droplets having a diameter of about 10 pm to about 100 pm. In other embodiments, target droplets DP are tin droplets having a diameter of about 25 pm to about 50 pm. In some embodiments, target droplets DP are supplied through nozzle 120 at a rate in a range from about 50 droplets per second (i.e., a shot frequency of about 50 Hz) to about 50,000 droplets per second (i.e., a shot frequency of about 50 kHz). In some embodiments, target droplets DP are supplied at a shot frequency of about 100 Hz to about 25 kHz. In other embodiments, target droplets DP are supplied at a shot frequency of about 500 Hz to about 10 kHz. In some embodiments, target droplets DP are ejected through nozzle 120 and are ejected into excitation zone ZE at a velocity in a range from about 10 meters per second (m / s) to about 100 m / s. In some embodiments, target droplets DP have a velocity of about 10 m / s to about 75 m / s. In other embodiments, target droplets have a velocity of about 25 m / s to about 50 m / s.

[0045] Referring back to Figure 1 Excitation laser LR2 generated by excitation laser source 300 is a pulsed laser. Laser pulses LR2 are generated by excitation laser source 300. Excitation laser source 300 can include a laser generator 310, laser directing optics 320, and a focusing device 330. In some embodiments, laser source 310 includes a carbon dioxide (CO2) or a neodymium-doped yttrium aluminum garnet (Nd:YAG) laser source having a wavelength in the infrared region of the electromagnetic spectrum. For example, in one embodiment, laser source 310 has a wavelength of 9.4 pm or 10.6 pm. Laser LR1 generated by laser generator 300 is directed by laser directing optics 320 and focused by focusing device 330 into excitation laser LR2, which is then introduced into EUV radiation source 100.

[0046] In some embodiments, the excitation laser LR2 includes a preheat laser and a main laser. In such embodiments, the preheat laser pulses (interchangeably referred to herein as "pre-pulses") are used to heat (or pre-heat) a given target droplet to produce a low-density target plume having a plurality of smaller droplets, which are then heated (or re-heated) by a pulse from the main laser, resulting in more EUV light emission.

[0047] In various embodiments, the preheat laser pulses have a spot size of about 100 pm or less, and the main laser pulses have a spot size in the range of about 150 pm to about 300 pm. In some embodiments, the preheat laser and main laser pulses have a pulse duration in the range of about 10 ns to about 50 ns and a pulse frequency in the range of about 1 kHz to about 100 kHz. In various embodiments, the preheat laser and main laser have an average power in the range of about 1 kilowatt (kW) to about 50 kW. In one embodiment, the pulse frequency of the excitation laser LR2 is matched to the ejection frequency of the target droplets DP.

[0048] The laser LR2 is directed through a window (or lens) into the excitation zone ZE. The window employs a suitable material that is substantially transparent to the laser beam. The generation of the pulsed laser is synchronized with the ejection of the target droplets DP through the nozzle 120. As the target droplets move through the excitation zone, the pre-pulses heat the target droplets and transform them into a low-density target plume. The delay between the pre-pulse and the main pulse is controlled to allow the target plume to form and expand to an optimal size and geometry. In various embodiments, the pre-pulse and the main pulse have the same pulse duration and peak power. When the main pulse heats the target plume, a high-temperature plasma is created. The plasma emits EUV radiation, which is collected by the collector 110. The collector 110 further reflects and focuses the EUV radiation for use in a photolithographic exposure process by the exposure device 200. A droplet catcher is used to catch excess target droplets. For example, some target droplets can be intentionally missed by the laser pulses.

[0049] Referring back to Figure 1Collector 110 is designed with a suitable coating material and shape to function as a mirror for collecting, reflecting, and focusing EUV light. In some embodiments, collector 110 is designed to have an elliptical geometry. In some embodiments, the coating material of collector 100 is similar to a reflective multilayer of an EUV mask. In some examples, the coating material of collector 100 comprises alternating stacks of first and second reflective layers (e.g., multiple Mo / Si film pairs) and may further include a capping layer (e.g., Ru) coated on ML to adequately reflect EUV light. In some embodiments, collector 110 may also include a grating structure designed to effectively scatter the laser beam directed onto collector 110. For example, a silicon nitride layer is coated on collector 110 and patterned to have a grating pattern.

[0050] In such an EUV radiation source, the plasma generated by the laser application produces physical debris, such as ions, gases, and atoms of droplets, as well as the required EUV radiation. It is essential to prevent material accumulation on collector 110 and also to prevent physical debris from leaving chamber 105 and entering exposure device 200.

[0051] like Figure 1 As shown, in this embodiment, buffer gas is supplied from a first buffer gas supplier 130 through an orifice in collector 110, through which pulsed laser light is delivered to the molten tin droplet. In some embodiments, the buffer gas is H2, He, Ar, N2, or another inert gas. In some embodiments, H2, used as H radicals generated by the ionization of the buffer gas, is used for cleaning purposes. Buffer gas can also be supplied towards collector 110 and / or at the edge of collector 110 via one or more second buffer gas suppliers 135. Furthermore, chamber 105 includes one or more gas outlets 140 for the buffer gas to be discharged outside chamber 105.

[0052] As mentioned above, hydrogen gas is also supplied to the environment of the photomask. Hydrogen molecules become free radicals through interaction with EUV radiation and then permeate into the photomask. The permeated hydrogen (or hydrogen free radicals) diffuses into the absorber layer and accumulates in the photomask, particularly at the interface between the mirror layer and the capping layer. Accumulated hydrogen can lead to blistering defects, i.e., the capping layer peeling off from the mirror layer. For example, blistering defects are prone to occur when the number of wafers exposed by the EUV radiation tool using the photomask exceeds 10,000. Therefore, it is beneficial to prevent blistering defects caused by hydrogen permeation as part of the photolithography process used to manufacture semiconductor devices.

[0053] In this disclosure, in order to prevent bubbling defects, the photomask is annealed to release or discharge hydrogen that has been trapped or accumulated in the photomask due to repeated use in EUV lithography tools.

[0054] Figure 4 is a flowchart illustrating a method of processing a photomask according to embodiments of the present disclosure. It is to be understood that additional embodiments of the method can be performed before, during, and after the processes shown, and some of the operations described below can be replaced or eliminated. Figure 4 Additional operations can be provided before, during, and after the processes shown, and some of the operations described below can be replaced or eliminated, in alternative embodiments. The order of the operations / processes can be interchanged.

[0055] At S401 of the method 400, a photomask to be used is unloaded from a mask stocker and then loaded into an EUV lithography tool (scanner). In some embodiments, the photomask is transferred from a load lock chamber (interface chamber) to a mask table under reduced pressure (e.g., any pressure below 1 Pa to 1 kPa) by a mask handler inside the EUV lithography tool. In some embodiments, the photomask is mounted into a mask carrier (e.g., a mask POD) having an inner shell and an outer shell. In some embodiments, the inner shell is moved out from the outer shell inside the EUV lithography tool, and the photomask is moved out from the inner shell before being placed on the mask table. Figure 4 Then, at S402, EUV lithography is performed using the photomask to expose a photoresist layer formed over a semiconductor substrate to print a circuit pattern formed on the photomask. In some embodiments, a batch or multiple batches of semiconductor wafers (each batch including, for example, 25 wafers, 40 wafers, or more) are processed using the photomask. After the EUV lithography operation is completed, at S403, the photomask is removed or unloaded from the mask table. At S404, the photomask is heated (annealed) by a heating device. After the annealing, at S406 of the method 400, the photomask is cooled to room temperature (e.g., 25°C) and then stored in a mask stocker.

[0056] Figure 4

[0057] In some embodiments, the annealing (S404) of the photomask is performed under reduced pressure (e.g., any pressure below 1 Pa to 1 kPa). The reduced pressure is equal to or higher than the pressure near the mask table during the EUV lithography operation. In some embodiments, the annealing is performed at a first temperature in a range of about 100°C to about 350°C to drive out hydrogen from the photomask. When the temperature is lower than the range, a sufficient hydrogen drive out can not be obtained, and when the temperature is higher than the range, one or more layers of the photomask can be cracked or damaged.

[0058] In some embodiments, the annealing time is about 1 hour to about 5 hours. When the duration is lower than the range, there can be an insufficient hydrogen drive out, and when the duration is higher than the range, there can be a reduction in efficiency of the entire lithography operation and / or a reduction in productivity of the semiconductor manufacturing operation.

[0059] ​​In some embodiments, an annealing operation is performed when the cumulative number of exposed wafers reaches or exceeds a threshold number. In some embodiments, the threshold number is any number between 5000 and 20000. Until the threshold number is reached, the photomask is unloaded from the EUV exposure tool into the mask hopper without annealing. In other embodiments, an annealing operation is performed each time the photomask is used in an EUV lithography operation. In some embodiments, the annealing operation is performed after the photomask is unloaded from the mask hopper and before EUV lithography is performed.

[0060] In some embodiments, after the photomask is annealed in S404 (first annealing), in Figure 4 In step S405, an additional annealing operation (second annealing) is performed at a second temperature below the first temperature. In some embodiments, the second temperature is in the range of about 80°C to about 180°C. In some embodiments, the duration of the second annealing is about one hour to about three hours.

[0061] Figure 5 The effect of annealing a photomask according to embodiments of the present disclosure is illustrated. The horizontal axis represents the annealing time, and the vertical axis represents the normalized cumulative hydrogen quantity detected in the annealing environment, indicating the amount of hydrogen emitted from the photomask. The hydrogen quantity was obtained using a blank test mask and time-of-flight secondary ion mass spectrometry.

[0062] like Figure 5 As shown, the amount of hydrogen emitted increases with annealing time, reaching a maximum around 3–4 hours. After annealing at the first temperature for approximately four hours, the amount of hydrogen emitted from the photomask during the second heating (annealing) is significantly reduced, indicating that a sufficient amount of hydrogen has been emitted through the first annealing.

[0063] In some embodiments, the photomask undergoes cleaning, inspection, and / or repair operations, which may include heating the photomask at a first temperature. However, the annealing operation described above differs from this heating operation. In some embodiments, the annealing operation of this disclosure is performed within one hour after the photomask is removed from the mask stage of the EUV lithography tool.

[0064] Figure 6 A schematic diagram of a photomask heating apparatus 500 according to an embodiment of the present disclosure is shown.

[0065] In some embodiments, the photomask heating apparatus 500 includes a mask table 510 that also includes a heater therein and is surrounded by a chamber having a lower chamber 520 and an upper chamber 530. The lower chamber 520 and the upper chamber 530 constitute a vacuum environment. In some embodiments, a lid 540 is disposed above the upper chamber 530. In some embodiments, a gas monitor 560, e.g., a hydrogen monitor, is provided to detect hydrogen within the chamber. In addition, a vacuum system 550 coupled to one or more pumps is provided to regulate the pressure within the chamber. In some embodiments, the gas monitor is a quadrupole mass analyzer or a quadrupole mass spectrometer, or any other sensor that can detect hydrogen.

[0066] In some embodiments, the photomask is heated by the heater in the mask table 510. In other embodiments, the photomask is heated by a heater disposed at the upper chamber 530. In other embodiments, the photomask is heated by an infrared lamp disposed within or outside the chamber. In other embodiments, the photomask is heated by a UV lamp, which can also be effective to remove hydrocarbon contamination on the photomask.

[0067] In some embodiments, the mask table also serves as a cooling plate. In this case, a coolant (e.g., water) path is provided inside the mask table 510. In other embodiments, a cooling plate or table is provided separately from the mask table used for heating.

[0068] In some embodiments, the gas monitor 560 monitors outgassing (e.g., hydrogen gas) from the photomask during the annealing operation. In some embodiments, the gas monitor 560 and the heater are coupled to a controller 570 (e.g., a feedback controller) to control the heater based on the detection of the outgassing. In some embodiments, the heating is stopped when the amount of outgassing reaches a threshold. In other embodiments, the heating is stopped when the rate of decrease of the amount of outgassing reaches a threshold. In some embodiments, the controller stops the heating when a predetermined annealing duration has elapsed. In some embodiments, the controller includes a processor and a memory storing a program, and the program executed by the processor causes the controller to perform the control of the photomask heating apparatus 500. In some embodiments, the controller 570 is part of a control system of an EUV lithography tool.

[0069] Figure 7 and Figure 8 A schematic diagram of an EUV lithography system according to embodiments of the present disclosure is shown. As Figure 1 , Figure 2A and Figure 2BConsistently, the EUV lithography system includes an EUV radiation source 100 and an EUV lithography tool 200 (e.g., an EUV scanner). The EUV lithography tool 200 includes a body bottom module for controlling a wafer stage, a body top module for controlling a mask stage, and reflective EUV optics for guiding an EUV beam generated by the EUV radiation source 100 to a photomask held by the mask stage and guiding a reflected EUV beam reflected from the photomask to a wafer held by the wafer stage. Furthermore, the EUV lithography tool 200 includes a wafer handler (including one or more robotic arms and a wafer loading locking chamber for wafer transfer) and a mask handler (including one or more robotic arms and a mask loading locking chamber for photomask transfer).

[0070] In some embodiments, the photomask heating device 500 is disposed inside the EUV lithography tool 200. In other words, the photomask heating device 500 is integrated into the EUV lithography tool 200.

[0071] In an embodiment, such as Figure 7 and Figure 8 As shown, the photomask is unloaded from the mask loader 400 and transferred to the loading port of the EUV lithography tool 200 outside the vacuum chamber by a mask handling robot. Then, the photomask is placed in the vacuum environment of the EUV lithography tool through the mask loading locking chamber. The photomask is transferred to the mask backside inspection stage by a mask processor (processing robot), and if the inspection result is OK, the photomask is placed on the mask stage by a mask exchange device, and then the exposure operation is performed.

[0072] In some embodiments, after the photomask is removed from the mask stage, it is transferred to the mask heating device 500 under reduced pressure by a mask processing machine, where the first and / or second annealing operations as described above are performed. After the photomask is cooled, it is unloaded from the mask heating device 500 and placed into a mask carrier (mask POD device), and the mask carrier is transferred to a mask reservoir.

[0073] In some embodiments, one or more photomasks are stored in a vacuum mask library within the EUV exposure tool, and photomasks are loaded into and / or unloaded from the vacuum mask library.

[0074] Figure 9 A schematic diagram of an EUV lithography system according to an embodiment of the present disclosure is shown.

[0075] exist Figure 9 In one embodiment, the photomask heating device 500 is placed inside the photomask reservoir 400.

[0076] In some embodiments, after the photomask is removed from the reticle stage, the photomask is stored in a reticle carrier, and the reticle carrier is then transferred to the reticle stocker 400 by a carrier system, such as an overhead transport system. The reticle carrier is received by the inlet, and the photomask is removed from the reticle carrier. The first and / or second annealing operations described above are then performed in the reticle heating apparatus 500. After the photomask is cooled, the photomask is unloaded from the reticle heating apparatus 500 and placed in a reticle rack of the reticle stocker 400. In some embodiments, the transport from and / or to the reticle heating apparatus 500 is performed under an inert gas environment (e.g., using N2purging). In some embodiments, the storage of the photomask is also under an inert gas environment (e.g., using N2purging). Except for the reticle heating apparatus in operation, the pressure inside the reticle stocker is not necessarily under reduced pressure, but the pressure can be at or slightly above atmospheric pressure.

[0077] Figure 10 A schematic diagram of an EUV lithography system is shown, in accordance with an embodiment of the present disclosure.

[0078] In Figure 10 In some embodiments, after the photomask is removed from the reticle stage, the photomask is stored in a reticle carrier, and the reticle carrier is then transferred to the reticle heating apparatus 500 by a carrier system, such as an overhead transport system. The photomask is removed from the reticle carrier within the reticle heating apparatus, and the first and / or second annealing operations described above are then performed in the reticle heating apparatus 500. After the photomask is cooled, the photomask is unloaded from the reticle heating apparatus 500 and transferred to the reticle stocker 400. In some embodiments, after the cooling operation, the photomask is placed in a reticle carrier, and the reticle carrier is transported to the reticle stocker 400 by the overhead transport system. In other embodiments, the transport from the reticle heating apparatus 500 to the reticle stocker 400 is performed under an inert gas environment or under a reduced pressure that is lower than atmospheric pressure.

[0079] As described above, the blistering defect is caused by hydrogen accumulated within the photomask, and the annealing operation can drive at least some of the accumulated hydrogen out of the photomask. In the following embodiments, to enhance the driving of hydrogen out of the photomask, a dummy pattern having a size below the resolution limit of the EUV lithography tool is provided to a relatively large opaque region of the photomask. The opaque region is formed by or covered by an absorber layer, and the EUV beam is substantially not reflected.

[0080] Figure 11A and Figure 11B A cross-sectional view of an EUV reflective photomask is shown, in accordance with an embodiment of the present disclosure.

[0081] Figure 11A and Figure 11B The photomask shown in FIG. 2A includes a sub-resolution pattern 58 that cannot be printed in a photoresist layer on a wafer by an EUV radiation tool. In some embodiments, the sub-resolution pattern 58 is formed in the absorber layer and the bottom of the sub-resolution pattern is the capping layer 40, similar to the circuit pattern 55 shown in FIG. 1A. In other embodiments, the sub-resolution pattern 58 is formed in the absorber layer and the capping layer 40, and the bottom of the sub-resolution pattern is the mirror layer 38, as shown in FIG. 2B. Figure 11A Figure 11B

[0082] In some embodiments, the sub-resolution pattern 58 has a size (width or diameter) on the wafer in a range of about 1 nm to about 10 nm (about 4 nm to about 40 nm on a 4X photomask), and in other embodiments in a range of about 2.5 nm to about 5 nm on the wafer (about 10 nm to about 20 nm on a 4X photomask). If the size is less than this range, it is difficult to manufacture a photomask of such small size, and if the size is greater than this range, the pattern can not be printed in the photoresist layer.

[0083] In some embodiments, the sub-resolution pattern 58 includes a periodic pattern with a pitch on the wafer in a range of about 50 nm to about 200 nm (about 200 nm to about 800 nm on a 4X photomask). In other embodiments, the pitch is in a range of about 100 nm to about 150 nm on the wafer (about 400 nm to 600 nm on a 4X photomask). In some embodiments, the periodic pattern includes a line pattern and a space pattern (see FIG. 2C), and in other embodiments, the periodic pattern includes a hole pattern (see FIG. 2D). Figure 12B - Figure 12E Figure 12F

[0084] In some embodiments, the sub-resolution pattern is provided to relatively large opaque areas that are rectangular areas on the wafer with a short side equal to or greater than about 50 pm (about 200 pm on a 4X photomask). In some embodiments, the sub-resolution pattern is provided to the opaque areas in a pattern that is a periodic pattern, as shown in FIG. 3A, or a non-periodic pattern, as shown in FIG. 3B. Figure 12A ​​​​As shown, one photomask includes multiple chip regions divided by a street pattern. Although some fine test patterns are provided for the street pattern, the street pattern is generally considered a large area. Further, in some embodiments, each chip includes one or more large areas to which a sub-resolution pattern is provided. In some embodiments, the pattern density (open areas (patterns) to rectangular large areas) is about 5% to 40%, while in other embodiments in the range of about 10% to 30%. Further, a sub-resolution pattern is provided to the absorber layer in areas outside of the black border pattern 65. When the photomask includes a test chip (process control module), a sub-resolution pattern is provided to a large area in the test chip. In some embodiments, the pattern density (open areas (patterns) to opaque areas) of the entire photomask is about 5% to 50%, while in other embodiments in the range of about 10% to 30%.

[0085] In some embodiments, when a sub-resolution pattern is provided to a chip region, the sub-resolution pattern is separated from the circuit pattern on the wafer by a distance of about 3 μιη to about 10 μιη (about 12 μιη to about 40 μιη on a 4X photomask). Thus, in some embodiments, a sub-resolution pattern is provided to an opaque area that is separated from the circuit pattern by a distance of about 3 μιη to about 10 μιη.

[0086] Figure 13 is a flowchart illustrating a method of manufacturing a photomask according to embodiments of the present disclosure. At S1301, an original pattern layout of a photomask is provided. At S1302, large opaque areas without patterns are found by using a mask design computer. In some embodiments, a large opaque area is defined as a rectangle having a short side on the wafer equal to or greater than about 50 μιη (200 μιη on a 4X photomask). In some embodiments, the computer system finds the large opaque areas by fitting a 50x50 μιη square pattern. In other embodiments, the large opaque areas are determined by: expanding the edges of a circuit pattern (which will be an open pattern in the photomask) by a first amount in the X and Y directions, where the first amount is about 3 μιη to about 10 μιη on the wafer; and determining the large areas as the remaining opaque areas not covered by the expanded circuit pattern.

[0087] The computer system then adds a sub-resolution pattern to the found large opaque areas at S1303. In some embodiments, at S1304, optical proximity correction and / or e-beam proximity correction is performed. Then, at S1305, a photomask including the circuit pattern and the sub-resolution pattern is manufactured. In some embodiments, after the sub-resolution pattern is added, an optical proximity effect correction process is performed to modify the circuit pattern and / or the sub-resolution pattern. Further, in some embodiments, a design rule check process is also performed to find any patterns that violate design rules.

[0088] Figure 14A A flowchart of a method of fabricating a semiconductor device is shown, and Figure 14B 、 Figure 14C 、 Figure 14D and Figure 14E A sequence of fabrication operations of a method of fabricating a semiconductor device according to an embodiment of the present disclosure is shown. A semiconductor substrate or other suitable substrate is provided to be patterned to form integrated circuits thereon. In some embodiments, the semiconductor substrate comprises silicon. Alternatively or additionally, the semiconductor substrate comprises germanium, silicon germanium, or other suitable semiconductor material, such as a III-V semiconductor material. In Figure 14A S1401, a target layer to be patterned is formed over the semiconductor substrate. In certain embodiments, the target layer is the semiconductor substrate. In some embodiments, the target layer comprises a conductive layer, such as a metal layer or a polysilicon layer; a dielectric layer, such as silicon oxide, silicon nitride, SiON, SiOC, SiOCN, SiCN, hafnium oxide, or aluminum oxide; or a semiconductor layer, such as an epitaxially formed semiconductor layer. In some embodiments, the target layer is formed over an underlying structure, such as an isolation structure, a transistor, or a wiring. In Figure 14A S1402, a photoresist layer is formed over the target layer, as shown in Figure 14B During a subsequent photolithography exposure process, the photoresist layer is sensitive to radiation from an exposure source. In the present embodiment, the photoresist layer is sensitive to EUV light used in the photolithography exposure process. The photoresist layer can be formed over the target layer by spin coating or other suitable technique. The coated photoresist layer can be further baked to drive off solvents in the photoresist layer. In Figure 14A S1403, the photoresist layer is patterned using an EUV reflective mask as described above, as shown in Figure 14B The patterning of the photoresist layer includes performing a photolithography exposure process using the EUV mask through an EUV exposure system. During the exposure process, an integrated circuit (IC) design pattern defined on the EUV mask is imaged onto the photoresist layer to form a latent pattern thereon. Images of sub-resolution patterns are not printed. The patterning of the photoresist layer further includes developing the exposed photoresist layer to form a patterned photoresist layer having one or more openings. In one embodiment where the photoresist layer is a positive photoresist layer, the exposed portions of the photoresist layer are removed during the development process. The patterning of the photoresist layer can also include other process steps, such as various baking steps at different stages. For example, a post-exposure bake (PEB) process can be implemented after the photolithography exposure process and before the development process.

[0089] In Figure 14AS1404 utilizes a patterned photoresist layer as an etching mask to pattern the target layer, such as... Figure 14D As shown. In some embodiments, patterning the target layer includes applying an etching process to the target layer using a patterned photoresist layer as an etching mask. The portion of the target layer exposed within the openings of the patterned photoresist layer is etched, while the remaining portion is protected from etching. Furthermore, the patterned photoresist layer can be removed by wet stripping or plasma ashing, such as... Figure 14E As shown.

[0090] In embodiments of this disclosure, the reflective EUV photomask is heated after a period of use to dissipate any hydrogen that has accumulated therein. This suppresses bubbling defects that would otherwise be caused by the accumulated hydrogen. Furthermore, a dummy subresolution pattern is provided to a large opaque area of ​​the photomask to facilitate the dissipation of accumulated hydrogen, which further suppresses bubbling defects.

[0091] It should be understood that not all advantages need to be discussed herein, all embodiments or examples do not require specific advantages, and other embodiments or examples may provide different advantages.

[0092] According to embodiments of this disclosure, in a method of manufacturing a semiconductor device, an EUV lithography operation using an EUV mask is performed on a photoresist layer formed on a semiconductor substrate in an EUV scanner. After the EUV lithography operation, the EUV mask is unloaded from the mask stage of the EUV scanner. The EUV mask is placed under reduced pressure below atmospheric pressure. The EUV mask is heated under reduced pressure at a first temperature in the range of 100°C to 350°C. After heating, the EUV mask is stored in a mask reservoir. In one or more of the foregoing or following embodiments, the reduced pressure is less than 1 Pa to 1 kPa. In one or more of the foregoing or following embodiments, the heating is performed for one to five hours. In one or more of the foregoing or following embodiments, annealing is performed at a second temperature below the first temperature after heating and before storage. In one or more of the foregoing or following embodiments, the second temperature is in the range of 80°C to 180°C. In one or more of the foregoing or following embodiments, the annealing is performed for one to three hours. In one or more of the foregoing or following embodiments, the heating under reduced pressure is performed in a chamber provided inside the EUV scanner. In one or more of the foregoing or following embodiments, heating under reduced pressure is performed in a chamber provided inside the mask accumulator. In one or more of the foregoing or following embodiments, heating under reduced pressure is performed in a chamber provided separately from the EUV scanner and the mask accumulator. In one or more of the foregoing or following embodiments, the EUV mask is transferred from the mask stage to the chamber under reduced pressure below atmospheric pressure.

[0093] According to another aspect of the present disclosure, in a method of manufacturing a semiconductor device, in an EUV lithography apparatus, an EUV lithography operation using an EUV mask is performed. After the EUV lithography operation, the EUV mask is unloaded from a mask stage of the EUV lithography apparatus. The EUV mask is heated at a first temperature in a range of 100 °C to 350 °C under a reduced pressure below atmospheric pressure. After the heating, the EUV mask is stored in a mask stocker. Outgassing from the EUV mask is monitored during the heating. In one or more of the foregoing or following embodiments, the outgassing is hydrogen gas. In one or more of the foregoing or following embodiments, the heating is stopped when an amount of the outgassing is below a threshold. In one or more of the foregoing or following embodiments, the heating is stopped when a rate of decrease of the amount of the outgassing is below a threshold. In one or more of the foregoing or following embodiments, the heating is performed by placing the EUV mask on or above a heating plate. In one or more of the foregoing or following embodiments, hydrogen gas is applied to the EUV mask during the EUV lithography operation. In one or more of the foregoing or following embodiments, the mask stocker is purged with nitrogen gas.

[0094] According to another aspect of the present disclosure, in a method of manufacturing a semiconductor device, in an EUV lithography apparatus, an EUV lithography operation using an EUV mask is performed. After the EUV lithography operation, the EUV mask is unloaded from a mask stage of the EUV lithography apparatus. The EUV mask is heated at a first temperature in a range of 100°C to 350°C under a reduced pressure lower than an atmospheric pressure. After the heating, the EUV mask is stored in a mask stocker. The EUV mask includes a substrate, a reflective layer including a plurality of layers of Si and Mo and arranged above the substrate, one or more intermediate layers arranged above the reflective layer, and an absorber layer arranged above the one or more intermediate layers. The absorber layer includes a plurality of dummy patterns having a size below a resolution limit of the EUV lithography, and at bottoms of the plurality of dummy patterns, one of the one or more intermediate layers is exposed. In one or more of the foregoing or following embodiments, the plurality of dummy patterns has a size of 4 nm to 40 nm on the EUV mask. In one or more of the foregoing or following embodiments, the one or more intermediate layers include a silicon oxide layer on the reflective layer and a Ru layer on the silicon oxide layer, and at the bottoms of the plurality of dummy patterns, the silicon oxide layer is exposed. In one or more of the foregoing or following embodiments, the plurality of dummy patterns includes a periodic pattern having a pitch of 100 nm to 1000 nm on the EUV mask. In one or more of the foregoing or following embodiments, the pitch on the EUV mask is 400 nm to 600 nm. In one or more of the foregoing or following embodiments, the periodic pattern includes a line and space pattern or a hole pattern. In one or more of the foregoing or following embodiments, the plurality of dummy patterns is disposed on a rectangular region having a short side equal to or greater than 200 μm on the EUV mask. In one or more of the foregoing or following embodiments, the plurality of dummy patterns is spaced apart from a circuit pattern formed in the absorber layer by a distance of 12 μm to 40 μm on the EUV mask. In one or more of the foregoing or following embodiments, the plurality of dummy patterns is disposed on a scribe line pattern. In one or more of the foregoing or following embodiments, a pattern density of the plurality of dummy patterns is 40% to 60%.

[0095] Some examples are provided below.

[0096] Example 1. A method of manufacturing a semiconductor device, comprising:

[0097] performing, in an EUV scanner, an EUV lithography operation on a photoresist layer formed above a semiconductor substrate using an EUV mask;

[0098] unloading, after the EUV lithography operation, the EUV mask from a mask stage of the EUV scanner;

[0099] placing the EUV mask under a reduced pressure lower than an atmospheric pressure;

[0100] heating the EUV mask at a first temperature in a range of 100°C to 350°C under a reduced pressure; and

[0101] after the heating, storing the EUV mask in a mask stocker.

[0102] Example 2. The method of example 1, wherein the reduced pressure is less than 1 kPa.

[0103] Example 3. The method of example 1, wherein the heating is for one hour to five hours.

[0104] Example 4. The method of example 1, further comprising, after the heating and before the storing, performing an anneal at a second temperature that is less than the first temperature.

[0105] Example 5. The method of example 4, wherein the second temperature is in a range of 80°C to 180°C.

[0106] Example 6. The method of example 5, wherein the anneal is for one hour to three hours.

[0107] Example 7. The method of example 1, wherein the heating at the reduced pressure is performed in a chamber provided inside the EUV scanner.

[0108] Example 8. The method of example 1, wherein the heating at the reduced pressure is performed in a chamber provided inside the mask stocker.

[0109] Example 9. The method of example 1, wherein the heating at the reduced pressure is performed in a chamber provided separately from the EUV scanner and the mask stocker.

[0110] Example 10. The method of example 1, wherein the EUV mask is transferred from the mask stage to a chamber at a reduced pressure that is less than the atmospheric pressure.

[0111] Example 11. A method of manufacturing a semiconductor device, comprising:

[0112] performing an EUV lithography operation using an EUV mask in an EUV lithography apparatus;

[0113] after the EUV lithography operation, unloading the EUV mask from a mask stage of the EUV lithography apparatus;

[0114] heating the EUV mask at a first temperature in a range of 100°C to 350°C under a reduced pressure that is less than an atmospheric pressure; and

[0115] after the heating, storing the EUV mask in a mask stocker,

[0116] wherein outgassing from the EUV mask is monitored during the heating.

[0117] Example 12. The method of example 11, wherein the outgassing is hydrogen.

[0118] Example 13. The method of example 12, wherein the heating is stopped when the amount of outgassing is below a threshold value.

[0119] Example 14. The method of example 12, wherein the heating is stopped when a rate of decrease of the amount of outgassing is below a threshold value.

[0120] Example 15. The method of example 12, wherein the heating is performed by placing the EUV mask on or above a hot plate.

[0121] Example 16. The method of example 11, wherein hydrogen is applied to the EUV mask during the EUV lithography operation.

[0122] Example 17. The method of example 11, wherein the mask magazine is purged with nitrogen.

[0123] Example 18. A method of manufacturing a semiconductor device, comprising:

[0124] performing an EUV lithography operation using an EUV mask in an EUV lithography apparatus;

[0125] unloading the EUV mask from a mask table of the EUV lithography apparatus after the EUV lithography operation;

[0126] heating the EUV mask at a first temperature in a range of 100 °C to 350 °C under a reduced pressure below atmospheric pressure; and

[0127] storing the EUV mask in a mask magazine after the heating,

[0128] wherein the EUV mask comprises:

[0129] a substrate;

[0130] a reflective layer comprising multiple layers of Si and Mo and arranged above the substrate;

[0131] one or more intermediate layers arranged above the reflective layer; and

[0132] an absorber layer arranged above the one or more intermediate layers,

[0133] wherein the absorber layer comprises a plurality of dummy patterns, the plurality of dummy patterns having a size below a resolution limit of EUV lithography, and

[0134] At a bottom of the plurality of dummy patterns, one of the one or more intermediate layers is exposed.

[0135] Example 19. The method of example 18, wherein the plurality of dummy patterns have a size of 4 nm to 40 nm on the EUV mask.

[0136] Example 20. The method of example 18, wherein:

[0137] the one or more intermediate layers include a silicon oxide layer on the reflective layer and a Ru layer on the silicon oxide layer, and

[0138] At a bottom of the plurality of dummy patterns, the silicon oxide layer is exposed.

[0139] The foregoing outlines features of several embodiments so that those skilled in the art can better understand the aspects of the disclosure. Those skilled in the art should appreciate that they can readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the disclosure.

Claims

1. A method of manufacturing a semiconductor device, comprising: performing, in an extreme ultraviolet lithography (EUV) scanner, an EUV lithography operation on a photoresist layer formed over a semiconductor substrate using an EUV mask, during the EUV lithography operation, hydrogen gas is applied to the EUV mask; after the EUV lithography operation, unloading the EUV mask from a mask stage of the EUV scanner; placing the EUV mask under a reduced pressure that is lower than an atmospheric pressure; heating the EUV mask at a first temperature in a range of 100°C to 350°C under the reduced pressure to release hydrogen accumulated inside the EUV mask; after the heating, storing the EUV mask in a mask stocker. The reduced pressure is lower than 1 kPa.

2. The method of claim 1, wherein, The heating is performed for one hour to five hours.

3. The method of claim 1, wherein, After the heating and before the storing, annealing is performed at a second temperature that is lower than the first temperature.

4. The method of claim 1, further comprising: The second temperature is in a range of 80°C to 180°C.

5. The method of claim 4, wherein, The annealing is performed for one hour to three hours.

6. The method of claim 5, wherein, The heating under the reduced pressure is performed in a chamber provided inside the EUV scanner.

7. The method of claim 1, wherein, The heating under the reduced pressure is performed in a chamber provided inside the mask stocker.

8. The method of claim 1, wherein, The heating under the reduced pressure is performed in a chamber provided separately from the EUV scanner and the mask stocker.

9. The method of claim 1, wherein, The EUV mask is transferred from the mask stage to the chamber under the reduced pressure that is lower than the atmospheric pressure.

10. The method of claim 1, wherein, 11. A method of manufacturing a semiconductor device, comprising: performing, in an extreme ultraviolet lithography (EUV) lithography apparatus, an EUV lithography operation using an EUV mask, during the EUV lithography operation, hydrogen gas is applied to the EUV mask; after the EUV lithography operation, unloading the EUV mask from a mask stage of the EUV lithography apparatus; heating the EUV mask at a first temperature in a range of 100°C to 350°C with a heater under a reduced pressure that is lower than an atmospheric pressure; monitoring hydrogen gas outgassing from inside the EUV mask during the heating; controlling the heater based on a detection result of monitoring the hydrogen gas outgassing; after the heating, storing the EUV mask in a mask stocker. The heating is stopped when an amount of the hydrogen gas outgassing is lower than a threshold value. The heating is stopped when a rate of decrease of the amount of the hydrogen gas outgassing is lower than a threshold value.

12. The method of claim 11, wherein, 14. The method of claim 11, wherein:

13. The method of claim 11, wherein, the heater is a hot plate, and the heating is performed by placing the EUV mask on or above the hot plate. The mask stocker is purged with nitrogen gas.

16. A method of manufacturing a semiconductor device, comprising:

15. The method of claim 11, wherein, performing, in an extreme ultraviolet lithography (EUV) lithography apparatus, an EUV lithography operation using an EUV mask, during the EUV lithography operation, hydrogen gas is applied to the EUV mask; after the EUV lithography operation, unloading the EUV mask from a mask stage of the EUV lithography apparatus; heating the EUV mask at a first temperature in a range of 100°C to 350°C under a reduced pressure that is lower than an atmospheric pressure to release hydrogen accumulated inside the EUV mask; after the heating, storing the EUV mask in a mask stocker. ​ ​ After the heating, the EUV mask is stored in a mask stocker, wherein the EUV mask comprises: a substrate; a reflective layer comprising multiple layers of Si and Mo and arranged above the substrate; one or more intermediate layers arranged above the reflective layer; and an absorber layer arranged above the one or more intermediate layers, wherein the absorber layer comprises a plurality of dummy patterns, the plurality of dummy patterns having a size below a resolution limit of EUV lithography, and at a bottom of the plurality of dummy patterns, one of the one or more intermediate layers is exposed.

17. The method of claim 16, wherein, The plurality of dummy patterns has a size on the EUV mask of 4 nm to 40 nm.

18. The method of claim 16, wherein: the one or more intermediate layers comprise a silicon oxide layer on the reflective layer and a Ru layer on the silicon oxide layer, and at a bottom of the plurality of dummy patterns, the silicon oxide layer is exposed.

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