Control Method of Flash Memory Controller, Flash Memory Controller, and Storage Device

Abstract

The present invention relates to a control method for a flash memory controller, a flash memory controller, and a storage device. In the control method of the flash memory controller, after receiving a deallocation command from a host device, the flash memory controller updates a valid page count table, a detailed valid page count table, and / or a region valid page count table according to the deallocation command, so that the flash memory controller can effectively and quickly determine whether any region has no valid data, enabling the flash memory controller to recommend to the host device to transmit a reset command to reset the region.

Description

Technical Field

[0001] The present invention relates to a flash memory, and more particularly to a flash memory controller and related control methods. Background Art

[0002] In the Non-Volatile Memory Express (NVMe), a zoned namespace is standardized. However, since the zoned namespace and each zone therein are purely from the perspective of the host device, how to provide an effective memory management method to properly and quickly process the commands of the host device is an important issue. Summary of the Invention

[0003] Therefore, an object of the present invention is to provide a flash memory controller capable of effectively managing a flash memory module according to a deallocation command from a host device to solve the above problems.

[0004] According to an embodiment of the present invention, a control method for a flash memory controller is provided, wherein the flash memory controller is used to access a flash memory module. The flash memory module includes a plurality of blocks, and the control method includes: receiving a setting command from a host device, wherein the setting command configures at least a part of the flash memory module into a partitioned namespace. The partitioned namespace logically includes a plurality of regions. The host device performs a data writing operation based on regions on the partitioned namespace. Each region has the same size, and a plurality of logical addresses corresponding to each region are consecutive, and the plurality of logical addresses do not overlap between regions; writing the data of a first region into a plurality of first blocks; establishing a region-block mapping table, wherein the region-block mapping table includes information about the first region, the corresponding plurality of first blocks, and a shared block; after the data is written into the plurality of first blocks, establishing or updating a valid page count table, wherein the valid page count table records each block and the corresponding valid page count; receiving at least one deallocation command from the host device, wherein each deallocation command includes a logical address range to be deallocated; updating the valid page count table according to the at least one deallocation command to generate an updated valid page count table; judging whether the plurality of valid page counts of all the plurality of first blocks corresponding to the first region are zero according to the updated valid page count table; if the plurality of valid page counts of all the plurality of first blocks corresponding to the first region are zero, then monitoring the shared block to judge whether the first region does not have any valid data in the shared block; and if the first region is judged not to have any valid data in the shared block, then suggesting to the host device to transmit a reset command, wherein the reset command is used to reset the first region.

[0005] According to an embodiment of the present invention, a flash memory controller is provided, wherein the flash memory controller is used to access a flash memory module. The flash memory module includes a plurality of blocks, and the flash memory controller includes a read-only memory for storing a program code, a microprocessor for executing the program code to control the access of the flash memory module, and a buffer memory. The microprocessor is configured to: receive a setup command from a host device, wherein the setup command configures at least a part of the flash memory module into a partitioned namespace, the partitioned namespace logically includes a plurality of regions, the host device performs a data writing operation based on regions on the partitioned namespace, each region has the same size, a plurality of logical addresses corresponding to each region are consecutive, and the plurality of logical addresses do not overlap between regions; write the data of a first region into a plurality of first blocks; establish a region-block mapping table, wherein the region-block mapping table includes information about the first region, the corresponding plurality of first blocks, and a shared block; after the data is written into the plurality of first blocks, establish or update a valid page count table, wherein the valid page count table records each block and the corresponding valid page count; receive at least one deallocation command from the host device, wherein each deallocation command includes a logical address range to be deallocated; update the valid page count table according to the at least one deallocation command to generate an updated valid page count table; determine whether the plurality of valid page counts of all the plurality of first blocks corresponding to the first region are zero according to the updated valid page count table; if the plurality of valid page counts of all the plurality of first blocks corresponding to the first region are zero, then monitor the shared block to determine whether the first region does not have any valid data in the shared block; and if the first region is determined not to have any valid data in the shared block, then recommend to the host device to transmit a reset command, wherein the reset command is used to reset the first region.

[0006] According to an embodiment of the present invention, a storage device is provided, which includes a flash memory module and a flash memory controller. The flash memory module includes a plurality of blocks, and the flash memory controller is used to access the flash memory module. The flash memory controller is configured to: receive a setting command from a host device, wherein the setting command configures at least a part of the flash memory module into a partitioned namespace, the partitioned namespace logically includes a plurality of regions, the host device performs a data writing operation based on regions on the partitioned namespace, each region has the same size, the plurality of logical addresses corresponding to each region are continuous, and the plurality of logical addresses do not overlap between regions; write the data of a first region into a plurality of first blocks; establish a region-block mapping table, wherein the region-block mapping table includes information about the first region, the corresponding plurality of first blocks, and a shared block; after the data is written into the plurality of first blocks, establish or update a valid page count table, wherein the valid page count table records each block and the corresponding valid page count; receive at least one deallocation command from the host device, wherein each deallocation command includes a logical address range to be deallocated; update the valid page count table according to the at least one deallocation command to generate an updated valid page count table; determine whether the plurality of valid page counts of all the plurality of first blocks corresponding to the first region are zero according to the updated valid page count table; if the plurality of valid page counts of all the plurality of first blocks corresponding to the first region are zero, then monitor the shared block to determine whether the first region does not have any valid data in the shared block; and if the first region is determined not to have any valid data in the shared block, then recommend to the host device to transmit a reset command, wherein the reset command is used to reset the first region.

[0007] In summary, in the control method of the flash memory controller of the present invention, by establishing a valid page count table, a detailed valid page count table, and / or a region valid page count table according to the deallocation command from the host device, the flash memory controller can effectively and quickly determine whether any region has no valid data, so that the flash memory controller can recommend to the host device to transmit a reset command to reset the region. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 Schematic diagram of an electronic device according to an embodiment of the present invention.

[0009] Figure 2 Schematic diagram of a flash memory controller in a storage device according to an embodiment of the present invention.

[0010] Figure 3 Schematic diagram of a block in a flash memory module according to an embodiment of the present invention.

[0011] Figure 4 Schematic diagram of a flash memory module including a general storage space and a partitioned namespace.

[0012] Figure 5 Schematic diagram of a partitioned namespace divided into multiple regions.

[0013] Figure 6 Flowchart for writing data from a host device to a partitioned namespace according to an embodiment of the present invention.

[0014] Figure 7 Schematic diagram of regional data of a block written into a flash memory module.

[0015] Figure 8 Schematic diagram of a logical-to-physical address mapping table according to an embodiment of the present invention.

[0016] Figure 9 Schematic diagram of a valid page count table according to an embodiment of the present invention.

[0017] Figure 10 Flowchart for a control method of a flash memory controller according to an embodiment of the present invention.

[0018] Figure 11 Flowchart for writing data from a host device to a partitioned namespace according to another embodiment of the present invention.

[0019] Figure 12 Schematic diagram of a partitioned namespace divided into multiple regions.

[0020] Figure 13 Schematic diagram of a logical-to-physical address mapping table and a shared block table according to an embodiment of the present invention.

[0021] Figure 14 Schematic diagram of a valid page count table according to an embodiment of the present invention.

[0022] Figure 15 Schematic diagram of a detailed valid page count table according to an embodiment of the present invention.

[0023] Figure 16 Flowchart for a control method of a flash memory controller according to an embodiment of the present invention.

[0024] Figure 17 Schematic diagram of a regional valid page count table according to an embodiment of the present invention.

[0025] Figure 18 Flowchart for a control method of a flash memory controller according to an embodiment of the present invention.

[0026] Figure 19 Schematic diagram of a region-valid page mapping table according to an embodiment of the present invention.

[0027] Figure 20 Schematic diagram of an updated region-valid page mapping table according to an embodiment of the present invention.

[0028] Figure 21 Flowchart of a control method for a flash memory controller according to an embodiment of the present invention.

[0029]

Symbol description

[0030] 100: Electronic device

[0031] 110: Host device

[0032] 120_1~120_N: Storage device

[0033] 122: Flash memory controller

[0034] 124: Flash memory module

[0035] 212: Microprocessor

[0036] 212C: Program code

[0037] 212M: Read-only memory

[0038] 214: Control logic

[0039] 216: Buffer memory

[0040] 218: Interface logic

[0041] 232: Encoder

[0042] 234: Decoder

[0043] 240: Dynamic random access memory

[0044] 200, B3, B7, B8, B12, B99, B6: Blocks

[0045] 202: Floating gate transistor

[0046] BL1~BL3: Bit lines

[0047] WL0, WL1, WL2, WL4, WL5, WL6: Word lines

[0048] 410_1, 410_2: Partitioned namespaces

[0049] 420_1, 420_2: General storage spaces

[0050] 600~608, 1000~1008, 1100~1106, 1600~1608, 1800~1810, 2100~2108: Steps

[0051] 800, 1300: Logic to Physical Address Mapping Table

[0052] 900, 1400: Valid Page Count Table

[0053] 1330: Shared Block Table

[0054] 1500: Detailed Valid Page Count Table

[0055] 1700: Region Valid Page Count Table

[0056] 1900: Region Valid Page Mapping Table Detailed implementation manners

[0057] Figure 1 Schematic diagram of an electronic device 100 according to an embodiment of the present invention. As Figure 2 shown, the electronic device 100 may include a host device 110 and a plurality of storage devices 120_1 to 120_N. Each storage device (e.g., storage device 120_1) may include a flash memory controller 122 and a flash memory module 124. In this embodiment, each of the storage devices 120_1 to 120_N may be a solid-state drive (SSD) or any storage device having a flash memory module. The host device 110 may be a central processing unit (CPU) or other electronic devices or components capable of accessing the storage devices 120_1 to 120_N. The electronic device 100 may be a server, a personal computer, a laptop (notebook) computer, or any portable electronic device. It should be noted that although Figure 1 the storage devices 120_1 to 120_N are illustrated, in some embodiments, the electronic device 100 may have only a single storage device 120_1.

[0058] Figure 2 Schematic diagram of the storage device 120_1 according to an embodiment of the present invention. As Figure 2As shown, the flash memory controller 122 may include a microprocessor 212, a read only memory (ROM) 212M, control logic 214, a buffer memory 216, and interface logic 218. The read only memory 212M can be used to store program code 212C, and the microprocessor 212 can be used to execute the program code 212C to control access to the flash memory module 124. The control logic 214 may include an encoder 232 and a decoder 234. The encoder 232 can be used to encode data written to the flash memory module 124 to generate a corresponding check code (i.e., error correction code (ECC)), and the decoder 234 can be used to decode data read from the flash memory module 124.

[0059] In general, the flash memory module 124 may include a plurality of flash memory chips, and each flash memory chip may include a plurality of blocks. The flash memory controller 122 can perform a block-based erase operation on the flash memory module 124. In addition, a block can record a specific number of pages, and the flash memory controller 122 can perform a page-based write operation on the flash memory module 124. In this embodiment, the flash memory module 124 can be a 3D-NAND type flash memory module.

[0060] In fact, by executing the program code 212C through the microprocessor 212, the flash memory controller 122 can use its own internal components to perform many control operations. For example, the flash memory controller 122 can use the control logic 214 to control the access to the flash memory module 124 (in particular, the access to at least one block or at least one page), use the buffer memory 216 to perform the required buffering operations, and use the interface logic 218 to communicate with the host device 110. The buffer memory 216 can be implemented by a random access memory (RAM). For example, the buffer memory 216 can be a static random access memory (SRAM), but the present invention is not limited thereto. In addition, the flash memory controller 122 can be coupled to a dynamic random access memory (DRAM) 240. It should be noted that the dynamic random access memory 240 can be included in the flash memory controller 122. For example, the dynamic random access memory 240 and the flash memory controller 122 can coexist in the same package.

[0061] In one embodiment, the storage device 120_1 can comply with the Non-Volatile Memory Host Controller Interface Specification (NVMe). That is, the interface logic 218 can comply with a specific communication specification, such as the Peripheral Component Interconnect (PCI) specification or the Peripheral Component Interconnect Express (PCIe) specification, and can communicate according to the specific communication specification. For example, the interface logic 218 can communicate with the host device 110 through a connector.

[0062] Figure 3 FIG. is a schematic diagram of a block 200 in the flash memory module 124 according to an embodiment of the present invention, where the flash memory module 124 can be a 3D NAND flash memory module. As Figure 3 shown, the block 200 can include a plurality of memory cells, such as Figure 3 the floating gate transistor 202 shown or other charge trapping components. A 3D NAND flash memory architecture can be implemented through a plurality of bit lines (in Figure 3Only bit lines BL1 to BL3 are shown, and a plurality of word lines (in Figure 3 Only word lines WL0 to WL2 and word lines WL4 to WL6 are shown to form, taking Figure 3 the uppermost plane as an example, all the floating gate transistors on word line WL0 form at least one page, all the floating gate transistors on word line WL1 form at least another page, and all the floating gate transistors on word line WL2 form at least yet another page, and so on. In addition, the definition between word line WL0 and a page (such as a logic page) may vary according to the writing method of the flash memory. Specifically, when storing data in the single-level cell (SLC) manner, all the floating gate transistors on word line WL0 only correspond to a single logic page; when storing data in the multi-level cell (MLC) manner, all the floating gate transistors on word line WL0 correspond to two logic pages; when storing data in the triple-level cell (TLC) manner, all the floating gate transistors on word line WL0 correspond to three logic pages; and when storing data in the quad-level cell (QLC) manner, all the floating gate transistors on word line WL0 correspond to four logic pages. The 3D NAND flash memory architecture and the relationship between the word line and the page are well known to those of ordinary skill in the art. For the sake of brevity, the relevant details will not be repeated here.

[0063] In this embodiment, the host device 110 can configure at least a part of the flash memory module 124 into a zoned namespace by transmitting a settling command set (such as a zoned namespace command set), please refer to Figure 4, the host device 110 can transmit a set of setting commands to the flash memory controller 122, so that the flash memory module 124 has at least one partitioned namespace (in this embodiment, taking partitioned namespace 410_1 and partitioned namespace 410_2 as examples) and at least one general storage space (general storage space; in this embodiment, taking general storage space 420_1 and general storage space 420_2 as examples). The partitioned namespace 410_1 can be divided into multiple zones for access, and the host device 110 must perform a data writing operation based on a logical block address (LBA) in the partitioned namespace 410_1. A logical block address (abbreviated as logical address) can represent a piece of 512-byte data or a piece of 4-kilobyte (KB) data, and the host device 110 needs to continuously write data into a zone. Specifically, please refer to Figure 5 , the partitioned namespace 410_1 can be divided into multiple zones (such as zone Z0 to zone Z3), where the logical addresses in each zone must be continuous, and there are no overlapping logical addresses between zones (that is, a logical address can only exist in one zone). For example, if the size of each zone is "x" logical addresses and the starting logical address of zone Z3 is logical address LBA_k, then zone Z3 uses logical addresses LBA_k, LBA_(k + 1), LBA_(k + 2), LBA_(k + 3)… and logical address LBA_(k + x - 1) to store data. In one embodiment, the logical addresses of adjacent zones can also be continuous. For example, zone Z0 uses logical addresses LBA_1 to LBA_2000 to store data, zone Z1 uses logical addresses LBA_2001 to LBA_4000 to store data, zone Z2 uses logical addresses LBA_4001 to LBA_6000 to store data, zone Z3 uses logical addresses LBA_6001 to LBA_8000 to store data, and so on. In addition, the amount of data corresponding to a logical address can be determined by the host device 110. For example, the amount of data corresponding to a logical address can be 4 kilobytes.

[0064] In addition, when data is written to each region, the data is written according to the order of multiple logical addresses of the data. Specifically, the flash memory controller 122 can set a writepoint according to the written data to control the data writing sequence. Assume that region Z1 is used to store data using logical addresses LBA_2001 to LBA_4000. After the host device 110 transfers data corresponding to logical addresses LBA_2001 to LBA_2051 to the flash memory controller 122, the flash memory controller 122 can set the writepoint to the next logical address LBA_2052. If the host device 110 subsequently transfers data that belongs to the same region but does not have the logical address LBA_2052 (for example, the host device 110 transfers data with the logical address LBA_3000), then the flash memory controller 122 can reject the data write operation and send a write failure message back to the host device 110; in other words, only when the logical address of the received data is the same as the logical address pointed to by the writepoint, the flash memory controller 122 will allow the data write operation. In addition, if data in multiple regions is written alternately, each region can have its own writepoint.

[0065] In addition, the Non-Volatile Memory Host Controller Interface Specification provides a deallocate command that is sent from the host device 110 to request deletion of data corresponding to a logical address range, and the Non-Volatile Memory Host Controller Interface Specification also indicates that a flash memory controller can recommend to the host device 110 to issue a reset command to control a region from a full state to an empty state. Therefore, the following embodiments are proposed to enable the flash memory controller 122 to effectively and correctly recommend to the host device 110 to issue a reset command.

[0066] Figure 6Flowchart for writing data from host device 110 to partitioned namespace 410_1 according to an embodiment of the present invention. In this embodiment, it is assumed that the data volume corresponding to each region is greater than the size of each physical block in flash memory module 124, and the data volume corresponding to each region is not an integer multiple of the size of each physical block in flash memory module 124. In step 600, the process starts, and the power supplies of host device 110 and storage device 120_1 are turned on and an initialization operation is completed. Host device 110 sets basic settings (such as the size of each region, the number of regions, and the logical block address size) for at least a part of the storage regions of storage device 120_1 by using a partitioned namespace command set. In step 602, host device 110 transmits a write command and corresponding data to flash memory controller 122, where the above data is data corresponding to one or more regions, such as data corresponding to logical addresses LBA_k to logical address LBA_(k + x - 1) in region Z3 shown in Figure 5 The data of the logical addresses LBA_k to LBA_(k + x - 1) in region Z3 shown. In step 604, flash memory controller 122 selects at least one block (such as a blank block, that is, a spare block) from flash memory module 124, and sequentially writes the data from host device 110 to the at least one block. Since it is difficult to match the size of the region set by host device 110 with the size of the physical block, after host device 110 transmits the write command to all logical addresses in region Z3, the data to be written by host device 110 usually cannot completely fill the storage space of the physical block. In other words, the data storage capacity corresponding to a region is usually not an integer multiple of the size of the physical block used to store the data written by host device 110. In step 606, after writing the data to the last block and completing the data writing, flash memory controller 122 writes invalid data to the remaining pages of the last block, or directly keeps the remaining pages blank. It should be noted that each block usually reserves multiple pages to store system management information, which includes a write schedule, a physical-to-logical mapping table, check bits of error correction codes, and redundant array of independent disks parity (RAID parity), etc. The above remaining pages represent the pages remaining after the system management information and the data to be stored by host device 110 have been written to the last block.

[0067] For example, please refer to Figure 7, assume that the amount of data corresponding to each region is between two and three blocks in the flash memory module 124. In response to the write command transmitted by the host device 110 for region Z1, the flash memory controller 122 can sequentially write the data of region Z1 to block B3, block B7, and block B8. It should be noted that, in one embodiment, the write command transmitted by the host device 110 for region Z1 may include the starting logical address of region Z1, and the flash memory controller 122 can map the starting logical address of region Z1 to the starting physical storage space (such as the first physical page) of physical block B3, and store the data corresponding to the starting logical address of region Z1 to the starting physical storage space (such as the first physical page) of physical block B3. Blocks B3, B7, and B8 all contain pages P1 to PM, and starting from the first page P1 of block B3 to the last page PM of block B3, the data in region Z1 is sequentially written according to the logical address. After the data in block B3 is written, the writing operation continues from the first page P1 of block B7 to the last page PM of block B7. It should be noted that even if the host device 110 continues to perform the write operation for the logical address in region Z1, the flash memory controller 122 can still select non - consecutive blocks B3 and B7 to store the data that is consecutive in the logical address. After the data in block B7 is written, the data is continuously written to the first page P1 of block B8 until the data of region Z1 ends; in addition, the remaining pages of block B8 remain blank or have invalid data written therein. Similarly, the flash memory controller 122 can sequentially write the data of region Z3 to block B12, block B99, and block B6, where blocks B12, B99, and B6 all contain pages P1 to PM, and starting from the first page P1 of block B12 to the last page PM of block B12, the data of region Z3 is sequentially written according to the logical address. After the data in block B12 is written, the data is continuously written from the first page P1 of block B99 to the last page PM of block B99, and after the data in block B99 is written, the data is continuously written starting from the first page P1 of block B6 until the data of region Z3 ends. In addition, the remaining pages of block B6 remain blank or have invalid data written therein. It should be noted that the flash memory controller 122 may not establish a logical page - to - physical page mapping relationship for the physical pages storing invalid data. The flash memory controller 122 usually sets the physical block with blank physical pages or the physical block with physical pages having invalid data as the last part corresponding to each region. In other words, the flash memory controller 122 stores the data corresponding to the last logical address of the region into the physical block with blank pages or invalid data.

[0068] In step 608, the flash memory controller 122 establishes or updates a logical to physical (L2P) address mapping table to record the mapping relationship between the logical address and the physical address for subsequent data reading of the partition namespace 410_1. Figure 8 FIG. is a schematic diagram of a logical to physical address mapping table 800 according to an embodiment of the present invention. The logical to physical address mapping table 800 may include two fields. One field records the starting logical address of the region, and the other field records the physical block address of the block. Please refer to Figure 7 and Figure 8 Since the data in region Z1 is sequentially written to block B3, block B7, and block B8, and the data in region Z3 is sequentially written to block B12, block B99, and block B6, the logical to physical address mapping table 800 records the starting logical address Z1_LBA_S of region Z1, the physical block address PBA3 of block B3, the physical block address PBA7 of block B7, and the physical block address PBA8 of block B8, and records the starting logical address Z3_LBA_S of region Z3, the physical block address PBA12 of block B12, the physical block address PBA99 of block B99, and the physical block address PBA6 of block B6. For example, assume that region Z1 is used to store data with logical addresses from LBA_2001 to LBA_4000, region Z3 is used to store data with logical addresses from LBA_6001 to LBA_8000, the starting logical address Z1_LBA_S of region Z1 is logical address LBA_2001, and the starting logical address Z3_LBA_S of region Z3 is logical address LBA_6001. It should be noted that as long as the same purpose can be achieved, the steps in the flowchart for writing data from the host device 110 to the partition namespace 410_1 do not have to be performed in a fixed order. For example, step 608 can be performed after step 602, which can be understood by those of ordinary skill in the art under the teaching of the present invention. It should be noted that in this embodiment, each physical block corresponds to only a single region. For example, block B3, block B7, and block B8 only correspond to region Z1, and block B12, block B99, and block B6 only correspond to region Z3. In other words, a single block stores only the data in a single region. For example, block B3, block B7, and block B8 only store the data corresponding to region Z1, and block B12, block B99, and block B6 only store the data corresponding to region Z3.

[0069] Note that Figure 8The logical-to-physical address mapping table 800 shown is for illustrative purposes only, and the present invention is not limited thereto. In other embodiments of the present invention, the logical-to-physical address mapping table may include each logical address and the corresponding physical address, or the logical-to-physical address mapping table may include multiple physical addresses and the corresponding logical address ranges.

[0070] In addition, the flash memory controller 122 may establish a valid page count table that records the number of valid pages in a block, where a valid page represents data that is not old data (i.e., the flash memory module 124 does not have other data with the same logical address for updating the old data). Figure 9 It is a schematic diagram of the valid page count table 900 according to an embodiment of the present invention. As Figure 9 shown, assuming that the valid page count table 900 contains the immediate information after the data in area Z1 and area Z3 is completely written to the flash memory module 12, the valid page counts of physical blocks B3, B7, and B8 corresponding to area Z1 are "128", "128", and "60" respectively, and the valid page counts of physical blocks B12, B99, and B6 corresponding to area Z3 are "128", "128", and "60" respectively. In one embodiment, the valid page count table 900 is temporarily stored in the buffer memory 216.

[0071] Next, if the flash memory controller 122 receives a deallocation command from the host device 110 to deallocate the data corresponding to a logical address range, the microprocessor 212 will update the logical-to-physical address mapping table to remove the information of that logical address range, so that the data corresponding to that logical address range can be regarded as invalid data. For example, the logical-to-physical address mapping table is updated to remove the corresponding physical address of that logical address range, or the logical-to-physical address mapping table is updated to indicate that that logical address range does not have a corresponding physical address. After that, the microprocessor 212 updates the valid page count table 900 based on the page number corresponding to that logical address range. For example, if the deallocation command from the host device 110 indicates a logical address range corresponding to 30 pages of data within block B3, the valid page count of block B3 in the valid page count table 900 is updated to become "98".

[0072] In addition, the microprocessor 212 may check the valid page count table 900 and a zone-block mapping table to determine whether any area does not have any valid data, where the zone-block mapping table may include information about each area and the corresponding physical block. Figure 7For example, region Z1 corresponds to block B3, block B7, and block B8, and region Z3 corresponds to block B12, block B99, and block B6. In one embodiment, the logic-to-physical address mapping table 800 can serve as the region-block mapping table. Specifically, if the microprocessor 212 detects that there is no valid data in blocks B3, B7, and B8 corresponding to region Z1 (i.e., the valid page count of each of blocks B3, B7, and B8 is equal to 0), then the microprocessor 212 can actively notify the host device 110 to suggest that the host device 110 issue a reset command to control region Z1 from a full state to an empty state. Only after receiving the reset command can the microprocessor 212 erase blocks B3, B7, and B8 and set blocks B3, B7, and B8 as spare blocks (e.g., blank blocks) for storing other data.

[0073] In one embodiment, the flash memory controller 122 may further have a plurality of registers, where each register is used to store a reset zone recommended attribute of a region, and the reset zone recommended attribute is used to indicate whether the flash memory controller 122 detects that there is no valid data in the region. Specifically, if the microprocessor 212 detects that there is no valid data in blocks B3, B7, and B8 corresponding to region Z1, then the microprocessor 212 can set the register corresponding to region Z1 to "1", and once the host device 110 detects that the register corresponding to region Z1 has a value of "1", then the host device 110 can consider whether to transmit a reset command to the flash memory controller 122.

[0074] In another embodiment, if the microprocessor 212 detects that there is no valid data in blocks B3, B7, and B8 corresponding to region Z1, then the flash memory controller 122 can actively transmit a zone descriptor changed event to the host device 110 for region Z1 to suggest that the host device 110 transmit a reset command to reset the region.

[0075] Figure 10 It is a flowchart of a control method of the flash memory controller 122 according to an embodiment of the present invention. Please refer to the above Figures 6 to 9 embodiment, and the process is described as follows.

[0076] In step 1000, the process starts.

[0077] In step 1002, the flash memory controller determines whether a deallocation command is received from the host device. If so, it proceeds to step 1004; if not, it returns to step 1002.

[0078] In step 1004, the flash memory controller updates the logical-to-physical address mapping table and the valid page count table.

[0079] In step 1006, the flash memory controller refers to the valid page count table to determine whether any region has no valid data. If so, it proceeds to step 1008; if not, it returns to step 1002.

[0080] In step 1008, the flash memory controller advises the host device to resend a reset command to reset the regions that have no valid data.

[0081] Figure 11 A flowchart for writing data from the host device 110 to the partitioned namespace 410_1 according to another embodiment of the present invention. In this embodiment, it is assumed that the data volume corresponding to each region is greater than the size of each block in the flash memory module 124, and the data volume corresponding to each region is not an integer multiple of the size of each block in the flash memory module 124. In step 1100, the process starts, the power supplies of the host device 110 and the storage device 120_1 are activated and the initialization operations are completed. The host device 110 uses the partitioned namespace command set to configure the storage device 120_1 to have basic settings (such as the size of each region, the number of regions, and the logical block address size). In step 1102, the host device 110 transmits a write command and the corresponding data to the flash memory controller 122, where the above data is data corresponding to one or more regions (such as the data corresponding to the logical addresses LBA_k to LBA_(k + x - 1) of the region Z3 shown). In step 1104, the flash memory controller 122 selects at least one block (such as a blank block, i.e., a spare block) from the flash memory module 124, or selects at least one blank block or at least one shared block, to sequentially write the data from the host device 110 to these blocks. For example, please refer to Figure 5 the region Z3) of the logical addresses LBA_k to LBA_(k + x - 1) shown. In step 1104, the flash memory controller 122 selects at least one block (such as a blank block, that is, a spare block) from the flash memory module 124, or selects at least one blank block or at least one shared block, to sequentially write the data from the host device 110 to these blocks. For example, please refer to Figure 12, assume that the data volume corresponding to each region is between two and three blocks in the flash memory module 124, and the flash memory controller 122 can sequentially write the data of region Z1 into blocks B3, B7, and B8, where block B3 records the first part of the data Z1_0 of region Z1, block B7 records the second part of the data Z1_1 of region Z1, and block Z8 records the third part of the data Z1_2 of region Z1. In this embodiment, since all the data stored in blocks B3 and B7 are the data in region Z1, and only some pages in region B8 store the data in region Z1, in order to utilize the remaining pages in block B8, the microprocessor 212 can set block B8 as a shared block, that is to say, the remaining pages of block B8 can be used to store the data of other regions.

[0082] Please refer to Figure 12 , the flash memory controller 122 is ready to write the data of region Z3 into the partitioned namespace 410_1. Since there is a remaining space in the shared block B8, the microprocessor 212 can select the blank block B12, the blank block B99, and the shared block B8 to store the data in region Z3. Specifically, the flash memory controller 122 sequentially writes the data of region Z3 into block B12, block B99, and block B8, where block B12 records the first part of the data Z3_0 of region Z3, block B99 records the second part of the data Z3_1 of region Z3, and region B8 records the third part of the data Z3_2 of region Z3. In this embodiment, all the data stored in blocks B12 and B99 are the data of region Z3, and block B8 records the third part of the data Z1_2 of region Z1 and the third part of the data Z3_2 of region Z3. It should be noted that for the convenience of management, since it will increase the complexity of establishing the logical-to-physical address mapping table through the flash memory controller 122, the flash memory controller 122 will not store the first data of any region in the shared block. The flash memory controller 122 stores the first data of each region in an exclusive block (such as blocks B3 and B12), and these exclusive blocks only store the data belonging to the same region, so they are called exclusive blocks. The last data of any region (the data corresponding to the last logical address of the region) will be stored in a shared block (such as block B8), and the last data of another region will also be stored in this shared block. In this embodiment, the shared block stores the data in multiple regions. In other words, the shared block stores the last data of multiple regions, while the exclusive block only stores the data in a single region.

[0083] In step 1106, the flash memory controller 122 establishes or updates a logical-to-physical address mapping table to record the mapping relationship between the logical address and the physical address, and establishes a shared block table for subsequent data reading of the partitioned namespace 410_1. Figure 13 FIG. is a schematic diagram of a logical-to-physical address mapping table 1300 and a shared block table 1330 according to an embodiment of the present invention. The logical-to-physical address mapping table 1300 may include two fields, one field recording the logical address and the other field recording the physical address of the block. Please refer to Figure 12 and Figure 13 , since the data in region Z1 is sequentially written into blocks B3, B7, and B8, and the data in region Z3 is sequentially written into blocks B12, B99, and B8, the logical-to-physical address mapping table 1300 records the starting logical address Z1_LBA_S of region Z1, the physical block address PBA3 of block B3, the logical address (Z1_LBA_S + y) of region Z1, the physical block address PBA7 of block B7, the logical address (Z1_LBA_S + 2*y) of region Z1, and the physical block address PBA8 of block B8, where the logical address (Z1_LBA_S + y) can be used as the first logical address of the data written into block B7 (i.e., the first logical address of the second part of data Z1_1), and the logical address (Z1_LBA_S + 2*y) can be used as the first logical address of the data written into block B8 (i.e., the first logical address of the third part of data Z1_2).

[0084] Similarly, the logical-to-physical address mapping table 1300 records the starting logical address Z3_LBA_S of region Z3, the physical block address PBA12 of block B12, the logical address (Z3_LBA_S + y) of region Z3, the physical block address PBA99 of block B99, the logical address (Z3_LBA_S + 2 * y) of region Z3, and the physical block address PBA8 of block B8, where the logical address (Z3_LBA_S + y) can be used as the first logical address of the data written to block B99 (i.e., the first logical address of the second part of data Z3_1, which corresponds to the logical address of the first page P1 of block B99), and the logical address (Z3_LBA_S + 2 * y) can be used as the first logical address of the data written to block B8 (i.e., the first logical address of the third part of data Z3_2). It should be noted that the above "y" can represent the number of data with different logical addresses from the host device 110 that can be stored in a block. It should be noted that after the host device 110 sets the region size and the number of regions, the starting logical address of each region is determined, and the starting logical address of each sub-region is also determined, such as the starting logical address Z1_LBA_S, the logical address (Z1_LBA_S + y), the logical address (Z1_LBA_S + 2 * y), the starting logical address Z3_LBA_S, the logical address (Z3_LBA_S + y), and the logical address (Z3_LBA_S + 2 * y). Therefore, the logical-to-physical address mapping table 1300 can be further simplified to have one field, that is, only one field of physical block address, and the logical address field can be represented by the entries of the table without actually storing the starting logical addresses of multiple sub-regions.

[0085] In addition, the shared block table 1330 can include two fields, one field records the logical address, and the other field records the physical block address and the physical page address corresponding to the logical address. Figure 13In it, the shared block table 1330 records the first logical address (Z1_LBA_S + 2 * y) of the third part of data Z1_2 in area Z1, the corresponding physical block address PBA8, and the physical page address P1. That is to say, the data corresponding to the first logical address in the third part of data Z1_2 is written into the first page P1 of block B8. In addition, the shared block table 1330 records the first logical address (Z3_LBA_S + 2 * y) of the third part of data Z3_2 in area Z3, the corresponding physical block address PBA8, and the physical page address P61. In other words, the data corresponding to the first logical address in the third part of data Z3_2 is written into the sixty-first page P61 of block B8. It should be noted that the above assumes that each page in the block can only store data of a single logical address. However, depending on how many data with different logical addresses can be stored in a page, the actual situation can be adjusted.

[0086] In addition, it should be noted that during the process of writing data into area Z1 and area Z3, the write operation may not start writing the data in area Z3 into the partition namespace 410_1 only after all the data in area Z1 has been written into the partition namespace 410_1. In other words, when the data in area Z1 has not been completely written, the flash memory controller 122 may need to start writing the data in area Z3 into the partition namespace 410_1. Therefore, in another embodiment of the present invention, the shared block table 1330 may additionally include a completion indicator field, which is used to indicate whether the data in an area has been completely written into the shared block. The microprocessor 212 can refer to the completion indicator corresponding to area Z1 to determine whether the data in area Z3 can be written into block B8.

[0087] It should be noted that Figure 13 The shown logical-to-physical address mapping table 1300 and the shared block table 1330 are only for illustration purposes. In other embodiments of the present invention, the logical-to-physical address mapping table 1300 and the shared block table 1330 may include each logical address and the corresponding physical address, or the logical-to-physical address mapping table 1300 and the shared block table 1330 may include multiple physical addresses and the corresponding logical address ranges.

[0088] In addition, the flash memory controller 122 can establish a valid page count table, which records the number of valid pages in the block, where a valid page represents that the data is not old data (that is, the flash memory module 124 does not have other data with the same logical address for updating the old data). Figure 14 Schematic diagram of the valid page count table 1400 according to an embodiment of the present invention. As Figure 14As shown, assume that the valid page count table 1400 contains the up-to-date information after the data in area Z1 has been completely written into the flash memory module 124, but the data in area Z3 has not been completely written into block B8. The valid page counts of blocks B3, B7, and B8 corresponding to area Z1 are "128", "128", and "86" respectively, and the valid page counts of blocks B12, B99, and B8 corresponding to area Z3 are "128", "128", and "86" respectively. Among them, the third part of the data Z1_2 in area Z1 has 60 pages in block B8, and the third part of the data Z3_2 in area Z3 temporarily has 26 pages in block B8. In one embodiment, the valid page count table 1400 is temporarily stored in the buffer memory 126.

[0089] In addition, each shared block further has a detailed valid page count table for clearly indicating the valid page count of the area. Figure 15 FIG. is a schematic diagram of a detailed valid page count table 1500 according to an embodiment of the present invention, where the detailed valid page count table 1500 is for Figures 12 to 14 the shared block B8 to use. As Figure 15 shown, the detailed valid page count table 1500 has 4 fields: zone number, starting physical page address, full information, and valid page count. The starting physical page address field records the starting physical page address of each area. For example, page P1 corresponding to the third part of the data Z1_2 in area Z1 and page P61 corresponding to the third part of the data Z3_2 in area Z3. The full information field records whether all the data in the area has been completely written into block B8. In this example, the data in area Z1 has been completely written into the flash memory module 124, while the data in area Z3 has not been completely written into block B8. The valid page count field records the current valid page count of each area. For example, the valid page count of the third part of the data Z1_2 in area Z1 is "60", and the valid page count of the third part of the data Z3_2 in area Z3 is "26".

[0090] Next, if the flash memory controller 122 receives a deallocation command from the host device 110 to deallocate data corresponding to a logical address range, the microprocessor 212 updates the logical-to-physical address mapping table to remove the information of the logical address range, so that the data corresponding to the logical address range can be regarded as invalid data. For example, the logical-to-physical address mapping table is updated to remove the corresponding physical address of the logical address range, or the logical-to-physical address mapping table is updated to indicate that the logical address range does not have a corresponding physical address. After that, the microprocessor 212 updates the valid page count table 1400 and / or the detailed valid page count table 1500 based on the page numbers corresponding to the logical address range. For example, if the deallocation command from the host device 110 indicates a logical address range of data corresponding to 30 pages in block B8, and the logical address range corresponds to area Z1, the valid page count table 1400 is updated so that the valid page count of block B8 becomes "56", and the detailed valid page count table 1500 is updated so that the valid page count of the third part of data Z1_2 in area Z1 becomes "30".

[0091] In addition, the microprocessor 212 can check the valid page count table 1400, the detailed valid page count table 1500, and a region-block mapping table to determine whether any region has no valid data. The region-block mapping table may contain information about each region and the corresponding physical block, so as to Figure 12 For example, area Z1 corresponds to blocks B3, B7, and B8, and area Z3 corresponds to blocks B12, B99, and B8. In one embodiment, the logical-to-physical address mapping table 1300 can be used as the region-block mapping table. Specifically, if the microprocessor 212 detects that there is no valid data in blocks B3 and B7 corresponding to area Z1 (i.e., the valid page counts of blocks B3 and B7 are both equal to 0), there is no valid data in pages P1 to P60 in block B8 (i.e., the valid page count of the third part of data Z1_2 in area Z1 is equal to 0), and the detailed valid page count table 1500 indicates that all the data in area Z1 has been completely written to the flash memory module 124, then the microprocessor 212 can actively notify the host device 110 to suggest that it issue a reset command to control area Z1 from a full state to an empty state. Only after receiving the reset command, the microprocessor 212 can erase blocks B3 and B7 and set blocks B3 and B7 as spare blocks (i.e., blank blocks) for storing other data. It should be noted that since block B8 has the data of area Z3, even if area Z1 is reset, block B8 cannot be released as a spare block.

[0092] Note that, in order to avoid misjudging that a region has no valid data, the microprocessor 212 may suggest to the host device 110 to perform a reset command only when Figure 15 the full information field shown indicates that all data in the region has been completely written into the flash memory module 124. Specifically, if the host device 110 transmits one or more deallocation commands to deallocate the logical addresses corresponding to all the written data in region Z3 (for example, the logical addresses corresponding to all the pages in block B12 and block B99 and 26 pages in block B8), but Figure 15 the full information field shown indicates that all data in region Z3 has not been completely written into the flash memory module 124 (that is, it means that the remaining data in region Z3 can be written into block B8 after one cycle), then the microprocessor 212 shall not suggest to the host device 100 to perform a reset command to reset region Z3.

[0093] In one embodiment, the flash memory controller 122 may further have a plurality of registers, where each register is used to store a reset region suggestion attribute of a region, and the reset region suggestion attribute indicates whether the flash memory controller 122 detects that there is no valid data in the region. In another embodiment, if the microprocessor 212 detects that there is no valid data in blocks B3, B7, and B8 corresponding to region Z1, then the flash memory controller 122 may actively transmit a region descriptor change event to the host device 110 for region Z1 to suggest to the host device 110 to transmit a reset command to reset the region.

[0094] Figure 16 It is a flowchart of a control method of the flash memory controller 122 according to an embodiment of the present invention. Please refer to Figures 11 to 15 the above embodiments, and the process is described as follows.

[0095] In step 1600, the process starts.

[0096] In step 1602, the flash memory controller determines whether a deallocation command is received from the host device. If yes, it proceeds to step 1604; if no, it returns to step 1602.

[0097] In step 1604, the flash memory controller updates the logical-to-physical address mapping table, the valid page count table, and / or the detailed valid page count table.

[0098] In step 1606, the flash memory controller refers to the valid page count table and the detailed valid page count table to determine whether any region has no valid data. If yes, it proceeds to step 1608; if no, it returns to step 1602.

[0099] In step 1608, the flash memory controller advises the host device to transmit a reset command to reset areas that do not have valid data.

[0100] In Figures 6 to 10 the illustrated embodiment, each block corresponds to only a single area, and the microprocessor 212 checks the valid page count table 900 and an area-block mapping table to determine whether any area has no valid data, so as to determine whether to advise the host device 110 to transmit a reset command. In Figures 11 to 16 the illustrated embodiment, since a block can correspond to multiple areas, the microprocessor 212 checks the valid page count table 1400, the detailed valid page count table 1500, and an area-block mapping table to determine whether any area has no valid data, so as to determine whether to advise the host device 110 to transmit a reset command. In another embodiment, the microprocessor 212 can establish an area valid page count table based on the valid page count table 900 or based on the valid page count table 1400 and the detailed valid page count table 1500, so as to facilitate determining whether any area has no valid data.

[0101] Figure 17 FIG. is a schematic diagram of an area valid page count table 1700 according to an embodiment of the present invention. As Figure 17 shown, the area valid page count table 1700 contains information about the valid page counts of each area. In this embodiment, when the valid page count table 900 is updated, the area valid page count table 1700 is immediately updated, or when the valid page count table 1400 and / or the detailed valid page count table 1500 are updated, the area valid page count table 1700 is immediately updated. For example, if all the data of each area is written to 282 pages of the flash memory module 124, and due to a first deallocation command, the valid page count table 900 is updated to reduce the valid page count corresponding to area Z1, then the area valid page count table 1700 is immediately updated based on the updated valid page count table 900 (for example, the valid page count of area Z1 is updated from "282" to "100"). Then, if due to a second deallocation command, the valid page count table 900 is further updated to reduce the valid page count corresponding to area Z1, the area valid page count table 1700 is immediately updated based on the updated valid page count table 900 (for example, the valid page count of area Z1 is updated from "100" to "0"). After that, the microprocessor 212 can determine whether any area has no valid data based on the area valid page count table 1700 without referring to other tables (such as the valid page count table 900 or the valid page count table 1400).

[0102] Figure 18 A flowchart of a control method for a flash memory controller 122 according to an embodiment of the present invention. Please refer to the above Figure 17 embodiment, and the process is described as follows.

[0103] In step 1800, the process starts.

[0104] In step 1802, the flash memory controller determines whether a deallocation command is received from the host device. If so, it proceeds to step 1804; if not, it returns to step 1802.

[0105] In step 1804, the flash memory controller updates the logical-to-physical address mapping table, the valid page count table, and / or the detailed valid page count table.

[0106] In step 1806, the flash memory controller updates the region valid page count table based on the updated valid page count table and / or the updated detailed valid page count table.

[0107] In step 1808, the flash memory controller refers to the region valid page count table to determine whether any region has no valid data. If so, it proceeds to step 1810; if not, it returns to step 1802.

[0108] In step 1810, the flash memory controller advises the host device to transmit a reset command to reset the region without valid data.

[0109] In the above embodiment, if the host device 110 transmits an incorrect deallocation command, the valid page count table 900, the valid page count table 1400, and the region valid page count table 1700 may be incorrect, which will cause the microprocessor 212 to make an incorrect decision. For example, if the host device 110 transmits a first deallocation command indicating a first logical address range, and then the host device 110 transmits a second deallocation command indicating a second logical address range that partially overlaps with the first logical address range, the calculation of the valid page count may be incorrect. To solve this problem, the region valid page count table can be modified to have a deallocate command history field to record the status of each page. Specifically, please refer to Figure 19 , Figure 19Schematic diagram of a region valid page mapping table 1900 according to an embodiment of the present invention. The region valid page mapping table 1900 may include a deallocation command history field, where the deallocation command history field may include a plurality of bits, and each bit is used to indicate whether the data of a corresponding page is valid or invalid. For example, if a region has 282 pages, the deallocation command history field includes 282 bits, and each bit corresponds to a page. If the bit is equal to "1", it means that the data in the corresponding page is valid; and if the bit is equal to "0", it means that the data in the corresponding page is invalid. In Figure 19 In the illustrated embodiment, since all the data in regions Z1 to Z3 is rewritten into the flash memory module 124 and no deallocation commands are received, the bits in the deallocation command history field are all equal to "1", and the valid page count for each of regions Z1 to Z3 is equal to "282".

[0110] Next, if the flash memory controller 122 receives a deallocation command from the host device 110 to deallocate a logical address range, the microprocessor 212 may refer to the logical address range in the deallocation command to flip the corresponding bits in the deallocation command history field. Specifically, referring to Figure 20 , if the flash memory controller 122 receives a deallocation command from the host device 110 to deallocate a logical address range corresponding to 100 pages, the microprocessor 212 may update the bits corresponding to the 100 pages in the deallocation command history field from "1" to "0".

[0111] Note that the region valid page mapping table 1900 can be updated only based on the deallocation command from the host device 110, without referring to the valid page count table 900, the valid page count table 1400, and the detailed valid page count table 1500.

[0112] In Figure 19 the illustrated embodiment, the term "page" may indicate a logical address range corresponding to a physical page (e.g., 16 kilobytes) or a logical address unit (e.g., a logical block address, 4 kilobytes) corresponding to a block.

[0113] Figure 21 Flowchart of a control method for a flash memory controller 122 according to an embodiment of the present invention. Please refer to the above Figure 19 and Figure 20 embodiments, and the process is described as follows.

[0114] In step 2100, the process starts.

[0115] In step 2102, the flash memory controller determines whether a deallocation command is received from the host device. If so, it proceeds to step 2104; if not, it returns to step 2102.

[0116] In step 2104, the flash memory controller updates the region valid page count table based on the logical address range of the deallocation command.

[0117] In step 2106, the flash memory controller refers to the region valid page count table to determine whether any region has no valid data. If so, it proceeds to step 2018; if not, it returns to step 2102.

[0118] In step 2108, the flash memory controller advises the host device to transmit a reset command to reset the region without valid data.

[0119] In summary, in the control method of the flash memory controller of the present invention, by establishing a valid page count table, a detailed valid page count table, and / or a region valid page count table according to the deallocation command from the host device, the flash memory controller can effectively and quickly determine whether any region has no valid data, so that the flash memory controller can advise the host device to transmit a reset command to reset the region.

[0120] The above are only the preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

Claims

1. A control method for a flash memory controller, wherein the flash memory controller is used to access a flash memory module, the flash memory module includes a plurality of blocks, and the control method includes: Receiving a setup command from a host device, wherein the setup command configures at least a part of the flash memory module into a partitioned namespace, the partitioned namespace logically includes a plurality of regions, the host device performs a data writing operation based on regions on the partitioned namespace, each region has the same size, a plurality of logical addresses corresponding to each region are consecutive, and the plurality of logical addresses do not overlap between the plurality of regions; Writing the data of a first region into a plurality of first blocks; Establishing a region-block mapping table, wherein the region-block mapping table includes information about the first region, the corresponding plurality of first blocks, and a shared block; After the data is written into the plurality of first blocks, establishing or updating a valid page count table, wherein the valid page count table records each block and its corresponding valid page count; Receiving at least one deallocation command from the host device, wherein each deallocation command includes a logical address range to be deallocated; Updating the valid page count table according to the at least one deallocation command to generate an updated valid page count table; Judging whether the plurality of valid page counts of all the plurality of first blocks corresponding to the first region are zero according to the updated valid page count table; If the plurality of valid page counts of all the plurality of first blocks corresponding to the first region are zero, then monitoring the shared block to judge whether the first region does not have any valid data in the shared block; And If the first region is determined not to have any valid data in the shared block, then suggesting to the host device to transmit a reset command, wherein the reset command is used to reset the first region.

2. The control method according to claim 1, characterized in that The step of suggesting to the host device to transmit the reset command includes: Setting a reset region suggestion attribute corresponding to the first region from a first logical value to a second logical value, wherein the reset region suggestion attribute with the first logical value is used to indicate that not all the data corresponding to the first region becomes invalid, the reset region suggestion attribute with the second logical value is used to indicate that all the data corresponding to the first region becomes invalid, and the reset region suggestion attribute is read by the host device to judge whether to transmit the reset command to the flash memory controller.

3. The control method according to claim 1, wherein Another thing included is: After the data is written into the shared block, establishing or updating a detailed valid page count table, wherein the detailed valid page count table records the first region, at least one second region, and their respective corresponding valid page counts.

4. The control method according to claim 3, characterized in that The detailed valid page count table further records the full information of each of the first region and the at least one second region, and the full information indicates whether all the data of the corresponding first / second region is completely written into the shared block.

5. The control method according to claim 4, characterized in that, The step of monitoring the shared block to determine whether the first region has no valid data within the shared block includes: If the detailed valid page count table indicates that all the data of the corresponding first region has been completely written into the shared block and the valid page count of the first region is equal to zero, then it is determined that the first region has no valid data within the shared block.

6. The control method according to claim 5, wherein The step of monitoring the shared block to determine whether the first region has no valid data within the shared block includes: If the detailed valid page count table indicates that the valid page count of the first region is equal to zero, but the detailed valid page count table also indicates that not all the data of the corresponding first region has been completely written into the shared block, then it is not determined that the first region has no valid data within the shared block.

7. A flash memory controller, wherein the flash memory controller is used to access a flash memory module, the flash memory module includes a plurality of blocks, and the flash memory controller includes: A read-only memory for storing a program code; A microprocessor for executing the program code to control access to the flash memory module; And A buffer memory; Wherein the microprocessor is used to: Receive a setting command from a host device, wherein the setting command configures at least a part of the flash memory module into a partitioned namespace, the partitioned namespace logically includes a plurality of regions, the host device performs a region-based data writing operation on the partitioned namespace, each region has the same size, a plurality of logical addresses corresponding to each region are continuous, and the logical addresses do not overlap between the plurality of regions; Write the data of a first region into a plurality of first blocks; Establish a region-block mapping table, wherein the region-block mapping table includes information about the first region, the corresponding plurality of first blocks, and a shared block; After the data is written into the plurality of first blocks, establish or update a valid page count table, wherein the valid page count table records each block and its corresponding valid page count; Receive at least one deallocation command from the host device, wherein each deallocation command includes a logical address range to be deallocated; Update the valid page count table according to the at least one deallocation command to generate an updated valid page count table; Judge whether the plurality of valid page counts corresponding to all the plurality of first blocks corresponding to the first region are zero according to the updated valid page count table; If the plurality of valid page counts corresponding to all the plurality of first blocks corresponding to the first region become zero, then monitor the shared block to determine whether the first region has no valid data within the shared block; And If the first region is determined to have no valid data within the shared block, then recommend that the host device transmit a reset command, wherein the reset command is used to reset the first region.

8. The flash memory controller according to claim 7, wherein, The step of recommending that the host device transmit the reset command includes: Set a reset area suggestion attribute corresponding to the first area from a first logical value to a second logical value, where the reset area suggestion attribute with the first logical value is used to indicate that not all data corresponding to the first area becomes invalid, the reset area suggestion attribute with the second logical value is used to indicate that all data corresponding to the first area becomes invalid, and the reset area suggestion attribute is read by the host device to determine whether to send the reset command to the flash memory controller.

9. The flash memory controller according to claim 7, wherein Further comprising: After the data is written into the shared block, establish or update a detailed valid page count table, where the detailed valid page count table records the first area, at least one second area, and their respective corresponding valid page counts.

10. The flash memory controller according to claim 9, wherein The detailed valid page count table further records the full information of each of the first area and the at least one second area, and the full information indicates whether all the data of the corresponding first / second area is completely written into the shared block.

11. The flash memory controller according to claim 10, characterized in that, The step of monitoring the shared block to determine whether the first area has no valid data in the shared block includes: If the detailed valid page count table indicates that all the data of the corresponding first area is completely written into the shared block, and the valid page count of the first area is equal to zero, then it is determined that the first area has no valid data in the shared block.

12. The flash memory controller according to claim 11, wherein The step of monitoring the shared block to determine whether the first area has no valid data in the shared block includes: If the detailed valid page count table indicates that the valid page count of the first area is equal to zero, but the detailed valid page count table further indicates that not all the data of the corresponding first area is completely written into the shared block, then it is not determined that the first area has no valid data in the shared block.

13. A storage device, comprising: A flash memory module, where the flash memory module includes a plurality of blocks; and A flash memory controller for accessing the flash memory module; Wherein the flash memory controller is configured to: Receive a setting command from a host device, where the setting command configures at least a part of the flash memory module into a partitioned namespace, the partitioned namespace logically includes a plurality of areas, the host device performs a data writing operation based on areas on the partitioned namespace, each area has the same size, a plurality of logical addresses corresponding to each area are continuous, and the plurality of logical addresses do not overlap between the plurality of areas; Write the data of a first area into a plurality of first blocks; Establish a region-block mapping table, where the region-block mapping table includes information about the first area, the corresponding plurality of first blocks, and a shared block; After the data is written into the plurality of first blocks, establish or update a valid page count table, where the valid page count table records each block and its corresponding valid page count; Receive at least one deallocation command from the host device, where each deallocation command includes a range of logical addresses to be deallocated; Update the valid page count table according to the at least one deallocation command to generate an updated valid page count table; Judge whether the valid page counts of all the multiple first blocks corresponding to the first area are zero according to the updated valid page count table; If the valid page counts of all the multiple first blocks corresponding to the first area are zero, then monitor the shared block to judge whether the first area has no valid data in the shared block; And If the first area is determined to have no valid data in the shared block, then suggest that the host device transmit a reset command, where the reset command is used to reset the first area.

14. The storage device according to claim 13, characterized in that, The step of suggesting that the host device transmit the reset command includes: Set a reset area suggestion attribute corresponding to the first area from a first logical value to a second logical value, where the reset area suggestion attribute with the first logical value is used to indicate that not all the data corresponding to the first area becomes invalid, the reset area suggestion attribute with the second logical value is used to indicate that all the data corresponding to the first area becomes invalid, and the reset area suggestion attribute is read by the host device to judge whether to transmit the reset command to the flash memory controller.

15. The storage device according to claim 13, wherein Another includes: After the data is written into the shared block, establish or update a detailed valid page count table, where the detailed valid page count table records the first area, at least one second area, and their respective corresponding valid page counts.

16. The storage device according to claim 15, wherein The detailed valid page count table further records the full information of each of the first area and the at least one second area, and the full information indicates whether all the data of the corresponding first / second area is completely written into the shared block.

17. The storage device according to claim 16, wherein The step of monitoring the shared block to judge whether the first area has no valid data in the shared block includes: If the detailed valid page count table indicates that all the data of the corresponding first area is completely written into the shared block, and the valid page count of the first area is equal to zero, then determine that the first area has no valid data in the shared block.

18. The storage device according to claim 17, wherein The step of monitoring the shared block to judge whether the first area has no valid data in the shared block includes: If the detailed valid page count table indicates that the valid page count of the first area is equal to zero, but the detailed valid page count table further indicates that not all the data of the corresponding first area is completely written into the shared block, then do not determine that the first area has no valid data in the shared block.

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