Interpolation acceleration in the processor memory interface

Abstract

This application relates to interpolation acceleration in a processor memory interface. Linear interpolation is performed within a memory system. The memory system receives floating-point indices into an integer-indexed memory array. The memory system accesses two values ​​from two adjacent integer indices, performs the linear interpolation, and provides the resulting interpolated value. In many system architectures, a critical limitation to system performance is the data transfer rate between memory and processing elements. Therefore, reducing the amount of data transferred can improve overall system performance and reduce power consumption.

Description

[0001] Statement regarding government support

[0002] This invention was made with government support under DARPA Agreement No. HR0011-19-3-0002. The government has certain rights to this invention.

[0003] Priority application

[0004] This application claims priority to U.S. Provisional Application No. 63 / 168,085, filed on March 30, 2021, which is incorporated herein by reference in its entirety. Technical Field

[0005] Embodiments of this disclosure generally relate to processor memory interfaces, and more specifically, to interpolation acceleration in processor memory interfaces. Background Technology

[0006] For example, various computer architectures, such as the von Neumann architecture, typically use shared memory, buses for accessing shared memory, arithmetic units, and program control units. However, moving data between the processor and memory can be time-consuming and labor-intensive, which in turn constrains the performance and capacity of the computer system. Given these limitations, new computing architectures and devices are needed to improve computing performance beyond the practical limitations of transistor scaling (i.e., Moore's Law). Summary of the Invention

[0007] In one aspect, this application provides a system comprising: a memory array; and a memory controller coupled to the memory array and configured to perform operations including: receiving a command via a bus, the command including a floating-point index in a value array stored in the memory array; determining, based on the floating-point index, a first address of a first value of the value array and a second address of a second value of the value array; accessing, from the memory array, the first value from the first address and the second value from the second address; determining, based on the floating-point index, a first weight for the first value and a second weight for the second value; determining, based on the first weight, the first value, the second weight, and the second value, an interpolated value; and providing the interpolated value in response to the command.

[0008] On the other hand, this application provides a non-transitory machine-readable medium for storing instructions that, when executed by a system, cause the system to perform operations including: receiving a command via a bus, the command including a floating-point index in a value array stored in a memory array; determining a first address of a first value of the value array and a second address of a second value of the value array based on the floating-point index; accessing the first value from the first address and the second value from the second address from the memory array; determining a first weight for the first value and a second weight for the second value based on the floating-point index; determining an interpolated value based on the first weight, the first value, the second weight, and the second value; and providing the interpolated value in response to the command.

[0009] In another aspect, this application provides a method comprising: receiving a command via a bus, the command including a floating-point index in a value array stored in a memory array; determining a first address of a first value of the value array and a second address of a second value of the value array based on the floating-point index; accessing the first value from the first address and the second value from the second address from the memory array; determining a first weight for the first value and a second weight for the second value based on the floating-point index; determining an interpolated value based on the first weight, the first value, the second weight, and the second value; and providing the interpolated value in response to the command. Attached Figure Description

[0010] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments thereof. However, the drawings should not be construed as limiting this disclosure to the specific embodiments, but are for explanation and understanding only.

[0011] For ease of identification of any particular element or action being discussed, one or more of the most significant bits in the reference numerals refer to the drawing number in which the element is first introduced.

[0012] Figure 1 This generally illustrates a first instance of a first memory computing device in the context of a memory computing system according to an embodiment.

[0013] Figure 2 An example of a memory subsystem of a memory computing device according to an embodiment is generally shown.

[0014] Figure 3 An example of a programmable atomic unit for a memory controller according to an embodiment is generally shown.

[0015] Figure 4 An example of a hybrid thread processor (HTP) accelerator for a memory computing device according to an embodiment is shown.

[0016] Figure 5 An example of a representation of a hybrid thread structure (HTF) of a memory computing device according to an embodiment is shown.

[0017] Figure 6A An example of a chiplet system according to an embodiment is shown in general.

[0018] Figure 6B A general block diagram is shown, illustrating the sources... Figure 6A Examples of various components in a chiplet system.

[0019] Figure 7 Examples of chiplet-based implementation schemes for memory computing devices according to embodiments are generally shown.

[0020] Figure 8 An example of chipletization of a memory computing device according to an embodiment is shown.

[0021] Figure 9 It is a block diagram of an instance memory system suitable for performing interpolation within a memory system.

[0022] Figure 10 This is a flowchart illustrating the operation of a method performed by a circuit during interpolation according to some embodiments of the present disclosure.

[0023] Figure 11 This is a flowchart illustrating the operation of a method performed by a circuit during interpolation according to some embodiments of the present disclosure.

[0024] Figure 12 This is a flowchart illustrating the operation of a method performed by a circuit when controlling a vehicle according to some embodiments of the present disclosure.

[0025] Figure 13 This is a block diagram illustrating single instruction / multiple data (SIMD) inputs and SIMD outputs for commands that cause interpolation to be performed within a memory system, according to some embodiments of the present disclosure.

[0026] Figure 14 A block diagram of an example machine is shown, which may be used, in, or through which any one or more of the techniques (e.g., methods) discussed herein may be implemented. Detailed Implementation

[0027] Recent advances in materials, devices, and integration technologies can be leveraged to provide memory-centric computing topologies. Such topologies enable advancements in computational efficiency and workload handling for applications constrained by size, weight, or power requirements. Topologies can facilitate low-latency computing in or near memory or other data storage elements. These methods are particularly well-suited for a variety of computationally intensive operations utilizing sparse lookups, such as transform computations (e.g., Fast Fourier Transform (FFT) computations), or applications such as neural networks or artificial intelligence (AI), financial analysis, or simulation or modeling, for example, for computational fluid dynamics (CFD), engineer-as-a-system (EASE) augmented acoustic simulators, integrated circuit-centric simulation programs (SPICE), etc.

[0028] The systems, apparatuses, and methods discussed herein may include or utilize memory computing systems with processors or processing capabilities provided in, near, or integrated with memory or data storage components. Such systems are generally referred to herein as near-memory computing (CNM) systems. CNM systems can be node-based systems, where individual nodes in the system are coupled using a system-scale architecture. Especially in environments where high cache miss rates are expected, each node may include or utilize a dedicated or general-purpose processor and user-accessible accelerators (with custom computational architectures to facilitate intensive operations).

[0029] In this example, each node in a CNM system may have one or more host processors. Within each node, a dedicated hybrid-threaded processor may occupy discrete endpoints of the on-chip network. The hybrid-threaded processor may access some or all of the memory in a specific node of the system, or it may access memory across a network of multiple nodes via a system-scale architecture. Custom compute architectures or hybrid-threaded architectures at each node may have their own processors or accelerators and may operate at higher bandwidths than the hybrid-threaded processors. Different nodes in a CNM system may be configured differently, for example, with different compute capabilities, different types of memory, different interfaces, or other variations. However, nodes may be coupled together to share data and compute resources within a defined address space.

[0030] In this example, the CNM system or nodes within it can be configured by the user for custom operations. The user can provide instructions using a high-level programming language (e.g., C / C++), which can be compiled and directly mapped to the dataflow architecture of one or more nodes in the system or CNM system. That is, nodes in the system can contain hardware blocks (e.g., memory controllers, atomic units, other client accelerators, etc.) that can be configured to directly implement or support user instructions to thereby enhance system performance and reduce latency.

[0031] In practice, CNM systems are particularly well-suited for implementing hierarchical structures of instructions and nested loops (e.g., two, three, or more deep loops, or multidimensional loops). Standard compilers can be used to accept high-level language instructions and compile them directly into one or more dataflow architectures within a node. For example, nodes in the system can contain hybrid threading accelerators. These hybrid threading accelerators can execute in the user space of the CNM system and can initiate their own threads or sub-threads that can operate in parallel. Each thread can be mapped to a different loop iteration, thereby supporting multidimensional loops. Leveraging the ability to initiate such nested loops, along with other capabilities, CNM systems can achieve significant time savings and latency improvements for computationally intensive operations.

[0032] CNM systems, or nodes or components of CNM systems, may include or utilize various memory devices, controllers, and interconnects. In examples, the system may include various interconnect nodes, and these nodes or groups of nodes may be implemented using chiplets. Chiplets are an emerging technology for integrating various processing functions. Typically, a chiplet system consists of discrete chiplets (e.g., integrated circuits (ICs) on different substrates or dies) integrated on an interposer and packaged together. This arrangement differs from a single chiplet (e.g., an IC) containing different device blocks (e.g., intellectual property (IP) blocks) on a substrate (e.g., a single die), such as a system-on-a-chip (SoC), or a discretely packaged device integrated on a board. Generally, chiplets offer greater manufacturing efficiency than a single die chip, including higher throughput or lower development costs. The following discussion... Figure 6A and Figure 6B This section broadly illustrates an example of a chiplet system, which may include a CNM system.

[0033] Linear interpolation constructs new data points within a set of discrete, known data points. For example, measurements can be taken in regular time units (e.g., per second, per .01 seconds, etc.), and the values ​​can be estimated as a continuous function of the time values ​​between measurements using linear interpolation. To perform linear interpolation, two adjacent measurements of the intermediate point to be estimated are retrieved. These two adjacent measurements are combined using a weighted average to generate the interpolated value of the intermediate point.

[0034] One application of linear interpolation is processing data generated by Synthetic Aperture Radar (SAR). A radar antenna transmits radar pulses and receives their reflections. SAR is commonly used on mobile platforms such as aircraft, drones, or spacecraft. Because the antenna's position changes between the time it takes to transmit and receive the reflected pulse, the radar's synthetic aperture is increased, resulting in higher accuracy for radars of the same (physical) size compared to conventional beam-scanning radars. SAR wavelengths can range from 1 to 1000 mm.

[0035] Pulse data is processed using a back-projection algorithm to generate a two-dimensional image, where each pixel value indicates the distance between the corresponding scan point and the SAR. Therefore, the flight device can use the SAR to generate terrain images of the area it has flown over. This image can be used for navigation. For example, landmarks can be identified in the image and compared to landmarks along a pre-planned route. As another example, image recognition can identify targets to attack, track, or avoid.

[0036] Fourier transforms (e.g., FFTs) can be used to expand discrete pulse data collected by SAR to generate intermediate values. The collected data, the generated data, or both can be used for linear interpolation, thus providing approximate pulse values ​​for any index within the pulse range. For example, if 1000 pulses are transmitted and data is obtained for each of those 1000 pulses, an FFT can be used to expand the data by a factor of 10, making indices in the range 0.0–999.0 valid in increments of 0.1 units. Using linear interpolation, any floating-point index in the range 0.0–999.0 yields a valid value.

[0037] When performing linear interpolation on the processor using data stored in memory, the processor determines the measurement to retrieve, retrieves the measurement, and performs the interpolation calculation. Conversely, when retrieving a measurement, the processor retrieves only a single measurement. Therefore, the amount of data transferred from memory to the processor for interpolation is twice the amount of data transferred for the measurement.

[0038] As discussed herein, linear interpolation is performed within the memory system. The processor provides floating-point indices to an integer-indexed memory array. The memory system accesses two values ​​from two adjacent integer indices, performs linear interpolation, and provides the resulting interpolated value to the processor. Therefore, according to some example embodiments, the data transferred from memory to the processor for the interpolated value is the same as the data transferred for the measurement value.

[0039] In many system architectures, a key limiting factor for system performance is the data transfer rate between memory and the processor. Therefore, reducing the amount of data transferred can improve overall system performance. Furthermore, the power consumed in transferring data from the memory system to the processor is not negligible, especially in battery-powered devices such as drones, autonomous electric vehicles, smartphones, tablets, and laptops. Therefore, battery life can be extended by using the systems and methods described in this paper.

[0040] Figure 1A first instance of CNM system 102 is shown in general. The instance of CNM system 102 comprises multiple different memory computing nodes, each of which may contain various CNM devices. Each node in the system can operate within its own operating system (OS) domain (e.g., in particular Linux). In this instance, the nodes may coexist in a common OS domain of CNM system 102.

[0041] Figure 1 Examples include instances of the first memory compute node 104 of the CNM system 102. The CNM system 102 may have multiple nodes, for example, including different examples of the first memory compute node 104 coupled using a scaling structure 106. In the examples, the architecture of the CNM system 102 may support a scale with up to n different memory compute nodes (e.g., n = 4096) using the scaling structure 106. As discussed further below, each node in the CNM system 102 may be a component of multiple devices.

[0042] CNM system 102 may include a global controller for various nodes in the system, or a specific memory compute node in the system may optionally act as a host or controller for one or more other memory compute nodes in the same system. The various nodes in CNM system 102 may therefore be configured similarly or differently.

[0043] In this example, each node in CNM system 102 may include a host system using a specified operating system. The operating system may be common or different across the various nodes in CNM system 102. Figure 1 In this example, the first memory computing node 104 includes a host system 108, a first switch 110, and a first memory computing device 112. The host system 108 may include a processor, such as an x86, ARM, RISC-V, or other type of processor. The first switch 110 may be configured to facilitate communication between or between devices of the first memory computing node 104 or devices of the CNM system 102, for example, using a dedicated or other communication protocol (generally referred to herein as the Chip-to-Chip Protocol Interface (CTCPI)). That is, CTCPI may include a dedicated interface unique to the CNM system 102, or may include or use other interfaces, such as a Compute High-Speed ​​Link (CXL) interface, a Peripheral Component Interconnect High-Speed ​​(PCIe) interface, or a Chiplet Protocol Interface (CPI) interface, etc. The first switch 110 may include a switch configured to use CTCPI. For example, the first switch 110 may include a CXL switch, a PCIe switch, a CPI switch, or other types of switches. In this example, the first switch 110 may be configured to couple dissimilarly configured endpoints. For example, the first switch 110 can be configured to convert packet formats between, for example, PCIe and CPI formats.

[0044] The CNM system 102 is described herein with various example configurations (e.g., systems including nodes), and each node may include various chips (e.g., processors, switches, memory devices, etc.). In an example, the first memory computing node 104 in the CNM system 102 may include various chips implemented using chiplets. In the chiplet-based configuration of the CNM system 102 discussed below, inter-chiplet communication and additional intra-system communication may use a CPI network. The CPI network described herein is an example of CTCPI, that is, a chiplet-specific implementation of CTCPI. Therefore, the structure, operation, and functionality described below for CPI are equally applicable to structures, operations, and functions that may be implemented using non-chiplet-based CTCPI implementations. Unless otherwise expressly indicated, any discussion of CPI herein applies equally to CTCPI.

[0045] The CPI interface includes a packet network that supports virtual channels to enable flexible and high-speed interaction between chiplets, such as portions of the first memory compute node 104 or the CNM system 102. CPI enables bridging from intra-chiplet networks to wider chiplet networks. For example, the Advanced Extensible Interface (AXI) is a specification for intra-chip communication. However, the AXI specification covers various physical design options, such as the number of physical channels, signal timing, power, etc. Within a single chip, these options are typically selected to meet design goals, such as power consumption, speed, etc. However, to achieve flexibility in chiplet-based memory compute systems, adapters using CPI can intersect between various AXI design options that can be implemented in various chiplets. By utilizing packetized protocols to enable physical-to-virtual channel mapping and encapsulating time-based signaling, CPI can be used to bridge intra-chiplet networks (e.g., within a specific memory compute node) across wider chiplet networks (e.g., across the first memory compute node 104 or across the CNM system 102).

[0046] CNM system 102 is scalable to accommodate multi-node configurations. That is, multiple different examples of the first memory compute node 104 or other differently configured memory compute nodes can be coupled using scaling structure 106 to provide a scalable system. Each of the memory compute nodes can run its own operating system and can be configured to jointly coordinate the use of wide system resources.

[0047] exist Figure 1In one example, a first switch 110 of the first memory compute node 104 is coupled to a scaling structure 106. The scaling structure 106 can provide switches (e.g., CTCPI switches, PCIe switches, CPI switches, or other switches) that facilitate communication among and between different memory compute nodes. In this example, the scaling structure 106 can facilitate communication between various nodes in a partitioned global address space (PGAS).

[0048] In this example, a first switch 110 from a first memory computing node 104 is coupled to one or more different memory computing devices, such as a first memory computing device 112. The first memory computing device 112 may include a chiplet-based architecture, referred to herein as a CNM chiplet. A packaged version of the first memory computing device 112 may include, for example, one or more CNM chiplets. The chiplets can be coupled using CTCPI communication to achieve high bandwidth and low latency.

[0049] exist Figure 1 In an example, the first memory computing device 112 may include an on-chip network (NOC) or a first NOC 118. Typically, an NOC is an interconnect network within a device that connects a specific set of endpoints. Figure 1 In this context, the first NOC 118 can provide communication and connectivity between various memories, computing resources and ports of the first memory computing device 112.

[0050] In an example, the first NOC 118 may include a folded Clos topology within each instance of a memory computing device, or as a grid coupling multiple memory computing devices in a node. The Clos topology, for example, can use multiple smaller cardinality cross switches to provide the functionality associated with a higher cardinality cross switch topology, thus offering various benefits. For instance, the Clos topology can present consistent latency and equally distributed bandwidth across the NOC.

[0051] The first NOC 118 can include various types of switches, including hub switches, edge switches, and endpoint switches. Each switch can be configured as a crossbar switch that provides substantially uniform latency and bandwidth between input and output nodes. In an example, endpoint switches and edge switches can contain two separate crossbar switches, one for traffic destined for the hub switch and the other for traffic destined for the hub switch. A hub switch can be configured as a single crossbar switch that switches all inputs to all outputs.

[0052] In this example, hub switches may each have multiple ports (e.g., four or six ports each) depending on whether a particular hub switch participates in inter-chip communication. The number of hub switches participating in inter-chip communication can be set according to inter-chip bandwidth requirements.

[0053] The first NOC 118 can support a variety of payloads between computing elements and memory (e.g., 8 to 64-byte payloads; other payload sizes can be used similarly). In some instances, the first NOC 118 can be optimized for relatively small payloads (e.g., 8–16 bytes) to efficiently handle access to sparse data structures.

[0054] In this example, the first NOC 118 may be coupled to an external host via a first physical layer interface 114, a PCIe slave module 116 or endpoint, and a PCIe master module 126 or root port. That is, the first physical layer interface 114 may include an interface to allow an external host processor to couple to the first memory computing device 112. The external host processor may optionally couple to one or more different memory computing devices, for example, using a PCIe switch or other native protocol switch. Communication with the external host processor via a PCIe-based switch limits device-to-device communication to device-to-device communication supported by the switch. In contrast, communication via a memory computing device native protocol switch, such as using CTCPI, allows for more complete communication between or between different memory computing devices, including support for partitioned global address spaces, such as for generating worker threads and sending events.

[0055] In this example, the CTCPI protocol may be used by a first NOC 118 in a first memory computing device 112, and a first switch 110 may include a CTCPI switch. The CTCPI switch may allow CTCPI packets to be transmitted, for example, from a source memory computing device of the first memory computing device 112 to (e.g., on the same or another node) different destination memory computing devices without being converted to another packet format.

[0056] In one example, the first memory computing device 112 may include an internal host processor 122. The internal host processor 122 may be configured to communicate with the first NOC 118 or other components or modules of the first memory computing device 112, for example, using an internal PCIe master module 126, which can help eliminate the time- and energy-consuming physical layer. In one example, the internal host processor 122 may be based on a RISC-VISA processor and may communicate outside the first memory computing device 112 using a first physical layer interface 114, for example, with other storage devices, networking devices, or other peripheral devices of the first memory computing device 112. The internal host processor 122 may control the first memory computing device 112 and may act as a proxy for operating system-related functionalities. The internal host processor 122 may include a relatively small number of purpose processing cores (e.g., 2 to 4 cores) and a host memory device 124 (e.g., including dynamic random access memory (DRAM) modules).

[0057] In this example, the internal host processor 122 may include PCI root ports. When the internal host processor 122 is in use, one of its root ports may be connected to a PCIe slave module 116. Another root port of the internal host processor 122 may be connected to a first physical layer interface 114 to provide communication with external PCI peripherals. When the internal host processor 122 is deactivated, the PCIe slave module 116 may be coupled to the first physical layer interface 114 to allow an external host processor to communicate with a first NOC 118. In an example of a system with multiple memory computing devices, the first memory computing device 112 may be configured to act as a system host or controller. In this example, the internal host processor 122 may be in use, and other examples of internal host processors in corresponding other memory computing devices may be deactivated.

[0058] The internal host processor 122 can be configured when the first memory computing device 112 is powered on, for example, to allow host initialization. In an example, the internal host processor 122 and its associated data paths (e.g., including the first physical layer interface 114, PCIe slave module 116, etc.) can be configured to the first memory computing device 112 from input pins. One or more of these pins can be used to enable or disable the internal host processor 122 and configure the PCI (or other) data paths accordingly.

[0059] In this example, the first NOC 118 may be coupled to scale structure 106 via scale structure interface module 136 and second physical layer interface 138. Scale structure interface module 136 or SIF facilitates communication between the first memory computing device 112 and a device space such as a Partitioned Global Address Space (PGAS). The PGA may be configured to allow a particular memory computing device, such as the first memory computing device 112, to access memory or other resources on different memory computing devices (e.g., on the same or different nodes) using a load / store paradigm, for example. Various scalable architecture technologies may be used, including CTCPI, CPI, Gen-Z, PCI, or Ethernet bridged via CXL. Scale structure 106 may be configured to support various packet formats. In this example, scale structure 106 supports out-of-order packet communication or ordered packets, for example, by using path identifiers to extend bandwidth across multiple equivalent paths. Scale structure 106 typically supports remote operations such as remote memory reads, writes, and other built-in atoms, remote memory atoms, remote memory computing device send events, and remote memory computing device call and return operations.

[0060] In this example, the first NOC 118 may be coupled to one or more different memory modules, such as including a first memory device 128. The first memory device 128 may include various types of memory devices, such as low-power dual data rate 5 (LPDDR5) SDRAM or graphics dual data rate 6 (GDDR6) DRAM, etc. Figure 1 In one example, the first NOC 118 may coordinate communication with the first memory device 128 via a memory controller 130, which may be dedicated to a specific memory module. In this example, the memory controller 130 may include a memory module cache and an atomic operation module. The atomic operation module may be configured to provide relatively high-volume atomic operators, such as integer and floating-point operators. The atomic operation module may be configured to apply its operators to data within a memory module cache (e.g., including a static random access memory (SRAM) memory-side cache), thereby allowing back-to-back atomic operations using the same memory location with minimal reduction in processing power.

[0061] The memory module cache can provide storage for frequently accessed memory locations, such as the first memory device 128, without requiring re-access to it. In one example, the memory module cache can be configured to cache data only for a specific instance of the memory controller 130. In another example, the memory controller 130 includes a DRAM controller configured to interface with, for example, the first memory device 128 containing a DRAM device. The memory controller 130 can provide access scheduling and bit error management, among other functions.

[0062] In this example, the first NOC 118 may be coupled to a hybrid thread processor (HTP 140), a hybrid thread architecture (HTF 142), and a host interface and dispatch module (HIF 120). HIF 120 may be configured to facilitate access to host-based command request and response queues. In this example, HIF 120 may dispatch new execution threads on the processors or compute elements of the HTP 140 or HTF 142. In this example, HIF 120 may be configured to maintain workload balancing across the HTP 140 and HTF 142 modules.

[0063] The hybrid-threaded processor, or HTP 140, may include accelerators, such as those based on the RISC-V instruction set. The HTP 140 may contain a highly threaded event-driven processor, where threads can execute in a single instruction round to maintain high instruction throughput. The HTP 140 includes relatively few custom instructions to support low-overhead threading capabilities, event send / receive, and shared-memory atomic operators.

[0064] The hybrid thread architecture or HTF 142 may include accelerators, such as non-von Neumann coarse-grained reconfigurable processors. The HTF 142 may be optimized for high-level language operations and data types (e.g., integers or floating-point). In some instances, the HTF 142 may support dataflow computation. The HTF 142 may be configured to utilize substantially all memory bandwidth available on the first memory computing device 112, for example, when executing a memory-bound computational core.

[0065] The HTP and HTF accelerators of the CNM system 102 can be programmed using various high-level structured programming languages. For example, the HTP and HTF accelerators can be programmed using C / C++ (e.g., using the LLVM compiler framework). The HTP accelerator can leverage the open-source compiler environment, for example, through various additional custom instruction sets configured to improve memory access efficiency, provide message passing mechanisms, and manage events, etc. In an example, the HTF accelerator can be designed to be programmed using a high-level programming language, and the compiler can generate simulator configuration files or binaries that run on the HTF 142 hardware. The HTF 142 provides a mid-level language for precise and concise expression of algorithms while hiding the configuration details of the HTF accelerator itself. In an example, the HTF accelerator toolchain can use an LLVM front-end compiler and an LLVM intermediate representation (IR) to interface with the HTF accelerator back-end.

[0066] Figure 2An example of a memory subsystem 200 of a memory computing device according to an embodiment is generally illustrated. The example of memory subsystem 200 includes a controller 202, a programmable atom unit 208, and a second NOC 206. The controller 202 may include or use the programmable atom unit 208 to perform operations using information in the memory device 204. In this example, the memory subsystem 200 includes components from… Figure 1 A portion of the first memory computing device 112, such as a portion of the first NOC 118 or memory controller 130.

[0067] exist Figure 2 In this example, the second NOC 206 is coupled to the controller 202, and the controller 202 may include a memory control module 210, a local cache module 212, and a built-in atom module 214. In this example, the built-in atom module 214 may be configured to handle relatively simple single-loop integer atoms. The built-in atom module 214 can perform atoms with the same processing power as, for example, a normal memory read or write operation. In this example, an atomic memory operation may include a combination of: storing data into memory, performing an atomic memory operation, and then responding by loading data from memory.

[0068] A local cache module 212, for example, that may include an SRAM cache, can be provided to help reduce latency for frequently accessed memory locations. In an example, the local cache module 212 may provide a read buffer for sub-memory line access. The local cache module 212 may be particularly advantageous for computing elements with relatively small or no data cache. In some example embodiments, the local cache module 212 is a 2-kilobyte read-only cache.

[0069] For example, a memory control module 210, which may include a DRAM controller, can provide low-level request buffering and scheduling to provide efficient access to memory device 204 (e.g., which may include a DRAM device). In an example, memory device 204 may include or use a GDDR6 DRAM device, for example, with a density of 16 Gb and a peak bandwidth of 64 Gb / s. Other devices may be used similarly.

[0070] In this example, programmable atomic unit 208 may include single-loop or multi-loop operators, such as being configurable to perform integer addition or more complex multi-instruction operations, such as Bloom filter insertion. In this example, programmable atomic unit 208 may be configured to perform load and store-to-memory operations. Programmable atomic unit 208 may be configured to utilize a dedicated instruction set, such as RISC-V ISA, to facilitate interaction with controller 202 to atomically execute user-defined operations.

[0071] Programmable atomic requests received, for example, from a host on or outside the node, can be routed to programmable atomic units 208 via a second NOC 206 and controller 202. In an example, custom atomic operations (e.g., performed by programmable atomic units 208) can be identical to built-in atomic operations (e.g., performed by built-in atomic modules 214), except that the programmable atomic operations can be defined or programmed by a user rather than a system architect. In an example, programmable atomic request packets can be sent to controller 202 via the second NOC 206, and controller 202 can recognize the requests as custom atoms. Controller 202 can then forward the recognized requests to programmable atomic units 208.

[0072] Figure 3 An example of a programmable atom unit 302 for use with a memory controller, according to an embodiment, is generally shown. In this example, the programmable atom unit 302 may include or correspond to data from... Figure 2 The instance is a programmable atomic unit 208. That is to say, Figure 3 The components shown are examples of programmable atom units (PAUs) 302, such as those described above relative to... Figure 2 (e.g., in programmable atom unit 208) or relative to Figure 1 (For example, in the atomic operation module of memory controller 130) the mentioned components. Figure 3 As shown, the programmable atomic unit 302 includes a PAU processor or PAU core 306, a PAU thread control 304, an instruction SRAM 308, a data cache 310, and a memory interface 312 for interfacing with a memory controller 314. In this example, the memory controller 314 includes components from... Figure 2 An instance of controller 202.

[0073] In this example, the PAU core 306 is a pipelined processor, allowing multiple stages of different instructions to execute together per clock cycle. The PAU core 306 may contain a barrel-shaped multithreaded processor, where the thread control 304 circuitry switches between different register files (e.g., a set of registers containing the current processing state) after each clock cycle. This enables efficient context switching between currently executing threads. In this example, the PAU core 306 supports eight threads, resulting in eight register files. In this example, some or all of the register files are not integrated into the PAU core 306, but instead actually reside in the local data cache 310 or instruction SRAM 308. This reduces the circuit complexity of the PAU core 306 by eliminating the traditional flip-flops used for registers in such memories.

[0074] The local PAU memory may contain instruction SRAM 308, such as instructions for various atoms. These instructions include instruction sets to support atomic operators loaded by various applications. When an atomic operator is requested, for example, by an application chiplet, the instruction set corresponding to the atomic operator is executed by the PAU core 306. In this example, the instruction SRAM 308 can be partitioned to establish the instruction set. In this example, a specific programmable atomic operator requested by the request process can be identified by a partition number. The partition number can be established when a programmable atomic operator is registered (e.g., loaded onto) using programmable atomic unit 302. Other metadata for the programmable instructions may be stored in the local memory of programmable atomic unit 302 (e.g., in a partition table).

[0075] In this example, atomic operators manipulate data cache 310, which is typically synchronized (e.g., flushed) when the thread used for the atomic operator completes. Therefore, latency can be reduced for most memory operations during the execution of the programmable atomic operator thread, except for initial loads from external memory such as memory controller 314.

[0076] If a potentially dangerous condition would prevent a memory request, the pipelined processor (e.g., PAU core 306) may encounter problems when an execution thread attempts to make such a request. Here, the memory request retrieves data from memory controller 314, whether it comes from cache on memory controller 314 or off-die memory. To address this, PAU core 306 is configured to deny memory requests to threads. Typically, PAU core 306 or thread control 304 may contain circuitry to enable one or more thread rescheduling points in the pipeline. Here, the denial occurs at a point in the pipeline outside (e.g., after) these thread rescheduling points. In this instance, the danger occurs outside the rescheduling point. Here, the danger arises after the memory request instruction passes through the last thread rescheduling point before the pipeline stage where the memory request can be made.

[0077] In this example, to reject a memory request, the PAU core 306 is configured to determine (e.g., detect) the presence of a danger on the memory indicated in the memory request. Here, a danger represents any condition that would cause an inconsistent state of the thread if the memory request were allowed (e.g., executed). In this example, the danger is an ongoing memory request. Here, the existence of an ongoing memory request makes it uncertain what the data at that address in the data cache 310 should be, regardless of whether the data cache 310 contains data at the requested memory address. Therefore, the thread must wait for the ongoing memory request to complete before operating on the current data. The danger is cleared when the memory request completes.

[0078] In this example, the danger lies in a dirty cache line in data cache 310 used for the requested memory address. While a dirty cache line typically indicates that the data in the cache is current but the memory controller version of such data is not current, problems can arise with thread instructions that do not operate from the cache. Instances of such instructions utilize the built-in atomic operators of memory controller 314 or other separate hardware blocks. In the context of the memory controller, the built-in atomic operators are decoupled from programmable atomic units 302 and do not have access to the data cache 310 or instruction SRAM 308 within the PAU. If a cache line is dirty, the built-in atomic operators will not operate on the latest data until data cache 310 is flushed to synchronize the cache with another or off-die memory. This same situation can occur using other hardware blocks of the memory controller, such as cryptographic blocks, encoders, etc.

[0079] Figure 4 An example of an HTP accelerator or HTP accelerator 400 is shown. HTP accelerator 400 may include a portion of a memory computing device according to an embodiment. In the example, HTP accelerator 400 may include or include components from… Figure 1 The HTP 140 is an example of this. The HTP accelerator 400 includes, for example, an HTP core 402, an instruction cache 404, a data cache 406, a translation block 408, a memory interface 410, and a thread controller 412. The HTP accelerator 400 may further include, for example, a dispatch interface 414 and an NOC interface 416 for interfacing with a NOC, the NOC being, for example, from... Figure 1 The first NOC 118 instance, from Figure 2 The second NOC 206 or any other NOC.

[0080] In this example, the HTP accelerator 400 includes modules based on the RISC-V instruction set and may include a relatively small number of other or additional custom instructions to support low-overhead, thread-enabled hybrid threading (HT) languages. The HTP accelerator 400 may include a highly threaded processor core, namely the HTP core 402, in which threads can execute in a single instruction round-robin to maintain high instruction throughput. In this example, threads can pause while waiting for other pending events to complete. This allows computational resources to be used efficiently for related work, rather than polling. In this example, multithreaded barrier synchronization can utilize efficient HTP-to-HTP and HTP-to / from host message passing, allowing thousands of threads to initialize or wake up in, for example, tens of clock cycles.

[0081] In an example, dispatch interface 414 may include function blocks for handling hardware-based thread management of HTP accelerator 400. That is, dispatch interface 414 can manage the dispatch of work to HTP core 402 or other accelerators. However, non-HTP accelerators are typically unable to dispatch work. In an example, work dispatched from the host may use dispatch queues residing in, for example, host main memory (e.g., DRAM-based memory). On the other hand, work dispatched from HTP accelerator 400 may use dispatch queues residing in SRAM, for example, within a dispatch for a target HTP accelerator 400 within a specific node.

[0082] In an example, HTP core 402 may include one or more cores that execute instructions on behalf of threads. That is, HTP core 402 may contain instruction processing blocks. HTP core 402 may further include or be coupled to thread controller 412. Thread controller 412 may provide thread control and state for each active thread within HTP core 402. Data cache 406 may include a cache for the host processor (e.g., for local and remote memory computing devices, including caches for HTP core 402), and instruction cache 404 may include a cache for use by HTP core 402. In an example, data cache 406 may be configured for both read and write operations, and instruction cache 404 may be configured for read-only operations.

[0083] In this example, data cache 406 is a small cache provided per hardware thread. Data cache 406 can temporarily store data for use by its assigned thread. Data cache 406 can be managed by hardware or software within the HTP accelerator 400. For example, the hardware can be configured to automatically allocate or evict lines as needed when load and store operations are performed by the HTP core 402. Software, for example, using RISC-V instructions, can determine which memory accesses should be cached and when lines should be invalidated or written back to other memory locations.

[0084] Cached data on the HTP accelerator 400 offers various benefits, including making memory controller access more efficient, thus allowing execution threads to avoid stalling. However, situations that lead to inefficiency exist when using caches. Examples include accesses where data is accessed only once and causes cache lines to be scrambled. To help address this issue, the HTP accelerator 400 can use a custom load instruction set to prompt load instructions to check for cache hits and, if a cache miss occurs, issue a memory request for the requested operand without placing the acquired data in the data cache 406. Therefore, the HTP accelerator 400 includes various types of load instructions, including non-cached and cache line loads. Non-cached load instructions use cached data if dirty data exists in the cache. Non-cached load instructions ignore clean data in the cache and do not write the accessed data to the data cache. For cache line load instructions, a complete data cache line (e.g., including 64 bytes) can be loaded from memory into the data cache 406, and the addressed memory can be loaded into a specified register. If clean or dirty data is in data cache 406, these loads can use the cached data. If the referenced memory location is not in data cache 406, the entire cache line can be accessed from memory. The use of cache line load instructions when referencing sequential memory locations (e.g., memory copy operations) can reduce cache misses, but it can also waste memory and bandwidth at NOC interface 416 if the referenced memory data is not used.

[0085] In this example, the HTP accelerator 400 includes non-cached custom store instructions. These non-cached store instructions help avoid disrupting the data cache 406 by utilizing write data that is not sequentially written to memory.

[0086] In this example, the HTP accelerator 400 further includes a translation block 408. Translation block 408 may include a virtual-to-physical translation block for the local memory of the memory computing device. For example, a host processor in HTP core 402 may execute load or store instructions, and these instructions may generate virtual addresses. A translation table from translation block 408 may be used, for example, to translate the virtual addresses into physical addresses for the host processor. For example, memory interface 410 may include an interface between HTP core 402 and NOC interface 416.

[0087] Figure 5 An example of a representation of an HTF 500 of a memory computing device according to an embodiment is shown. In this example, the HTF 500 may include or include components from... Figure 1The HTF 142 is an example of this. The HTF 500 is a coarse-grained, reconfigurable computational architecture optimized for high-level language operand types and operators (e.g., using C / C++ or other high-level languages). In an instance, the HTF 500 may contain a configurable n-bit-wide (e.g., 512-bit-wide) data path for interconnect-hardened SIMD arithmetic units.

[0088] In an instance, HTF 500 includes HTF cluster 502, which contains multiple HTF tiles, including instance tile 504 or tile N. Each HTF tile may contain one or more compute elements with local memory and arithmetic capabilities. For example, each tile may contain a compute pipeline with support for integer and floating-point operations. In an instance, data paths, compute elements, and other infrastructure may be implemented as hardened IP to provide maximum performance while minimizing power consumption and reconfiguration time.

[0089] exist Figure 5 In this example, the tiles of HTF cluster 502 are arranged linearly, and each tile in the cluster can be coupled to one or more other tiles in HTF cluster 502. Figure 5 In this example, instance tile 504 or tile N is coupled to four other tiles, including coupling to base tile 510 (e.g., tile N-2) via a port labeled SF IN N-2, coupling to adjacent tile 512 (e.g., tile N-1) via a port labeled SF IN N-1, and coupling to tile N+1 via a port labeled SF IN N+1 and to tile N+2 via a port labeled SF IN N+2. Instance tile 504 may be coupled to the same or other tiles via corresponding output ports (e.g., ports labeled SF OUT N-1, SF OUT N-2, SF OUT N+1, and SF OUT N+2). In this example, the ordered list of names of the various tiles is a conceptual indication of the tile's location. In other examples, tiles, including HTF cluster 502, may be arranged in a grid or other configuration, where each tile is similarly coupled to one or more of its nearest neighbors in the grid. Tiles positioned at the edge of a cluster may optionally have fewer connections to adjacent tiles. For example, tiles N-2 or Figure 5 In one instance, the base tile 510 may be coupled only to the adjacent tile 512 (tile N-1) and to the instance tile 504 (tile N). Similarly, fewer or additional inter-tile connections may be used.

[0090] HTF cluster 502 may further include a memory interface module, which includes a first memory interface module 506. The memory interface module couples HTF cluster 502 to a NOC, such as a first NOC 118. In an example, the memory interface module allows tiles within the cluster to request other locations in the memory computing system (e.g., within the same or different nodes in the system). That is, the representation of HTF 500 may include part of a larger structure that can be distributed across multiple nodes, such as having one or more HTF tiles or HTF clusters at each of the nodes. Requests can be made between tiles or nodes within the context of the larger structure.

[0091] exist Figure 5 In this example, a synchronous structure (SF) is used to couple the tiles in the HTF cluster 502. The synchronous structure provides communication between a specific tile in the HTF cluster 502 and its neighboring tiles, as described above. Each HTF cluster 502 may further include an asynchronous structure (AF), which provides communication, for example, between tiles in the cluster, between memory interfaces in the cluster, and between dispatch interfaces 508 in the cluster.

[0092] In this example, the synchronization structure can exchange messages containing data and control information. Control information may include, among other things, instruction RAM address information or thread identifiers. Control information can be used to set the data path, and data message fields can be selected as the source of the path. Typically, control fields can be provided or received earlier, making them available for configuring the data path. For example, to help minimize any delays in the pipeline through the synchronization domain in the tile, control information may arrive at the tile several clock cycles before the data fields. Various registers can be provided to help coordinate the timing of data flow in the pipeline.

[0093] In this example, each tile in the HTF cluster 502 may contain multiple memories. Each memory may have the same width as the data path (e.g., 512 bits) and a specified depth, for example, ranging from 512 to 1024 features. The tile memory can be used to store data that supports data path operations. For example, the stored data may contain constants that are part of the cluster configuration of the kernel, or variables that are computed as part of a data stream. In this example, the tile memory may be written from an asynchronous structure as a data transfer from another synchronization domain, or may contain the result of a load operation initiated by another synchronization domain. Reading from the tile memory can be performed via synchronous data path instructions in the synchronization domain.

[0094] In the example, each tile in the HTF cluster 502 may have a dedicated instruction RAM (INST RAM). In an example of an HTF cluster 502 with sixteen tiles and an instruction RAM with sixty-four entries, the cluster may allow the use of up to 1024 multiply-shift and / or ALU operation mapping algorithms. Various tiles may be optionally pipelined together, for example, using a synchronous structure to allow dataflow computation with minimal memory access, thus minimizing latency and reducing power consumption. In the example, an asynchronous structure may allow memory referencing and computation to continue in parallel, thereby providing a more efficient streaming kernel. In the example, various tiles may include built-in support for loop-based constructions and may support nested loop kernels.

[0095] Synchronization structures allow for the pipelined use of multiple tiles, eliminating the need for data queues. Tiles participating in a synchronization domain can, for example, act as a single pipelined data path. The first or base tile of the synchronization domain (e.g., tile N-2, in...) Figure 5 In this example, worker threads can be initiated via pipelined tiles. The base tile is responsible for initiating work on a predefined cadence, referred to in this document as the SpokeCount. For instance, if the SpokeCount is 3, the base tile can initiate work every two clock cycles.

[0096] In this example, the synchronization domain comprises a set of connected tiles in the HTF cluster 502. Thread execution can begin at the base tile of the domain and can proceed from the base tile to other tiles within the same domain via the synchronization structure. The base tile provides instructions to be executed against the first tile. The first tile may by default provide the same instructions for another connected tile to be executed. However, in some instances, the base tile or subsequent tiles may conditionally specify or use alternative instructions. Alternative instructions are selected by causing the tile's data path to produce a Boolean condition value, and then the Boolean value can be used to select between the instruction set of the current tile and the alternative instructions.

[0097] Asynchronous structures can be used to perform operations that occur asynchronously relative to synchronous domains. Each tile in the HTF cluster 502 may contain an interface to an asynchronous structure. The inbound interface may contain, for example, a FIFO buffer or a queue (e.g., AF IN QUEUE) to provide storage for messages that cannot be processed immediately. Similarly, the outbound interface of the asynchronous structure may contain a FIFO buffer or a queue (e.g., AF OUT QUEUE) to provide storage for messages that cannot be sent immediately.

[0098] In this example, messages in the AF can be categorized as data messages or control messages. Data messages may contain SIMD-width data values ​​written to tile memory 0 (MEM_0) or memory 1 (MEM_1). Control messages can be configured to control threads to create, release resources, or issue external memory references.

[0099] Tiles in an HTF cluster 502 can perform various computational operations for HTF. These operations can be performed by configuring the data paths within the tiles. In this instance, a tile contains two function blocks that perform computational operations for the tile: a multiplication and shift operation block (MS OP) and an arithmetic, logical, and bit operation block (ALB OP). Both blocks can be configured to perform pipelined operations, such as multiplication and addition, or shift and addition, etc.

[0100] In one instance, each example of a memory computing device in the system may have a full set of supported instructions for its operator blocks (e.g., MSOP and ALB OP). In this case, binary compatibility can be achieved across all devices in the system. However, in some instances, it may be helpful to maintain a basic set of functionalities and optional instruction set categories to accommodate various design trade-offs, such as die size. The approach can be similar to how the RISC-V instruction set has a basic set and multiple optional instruction subsets.

[0101] In this example, instance tile 504 may contain spoke-type RAM. The spoke-type RAM can be used to specify which input (e.g., from four SF tile inputs and a base tile input) is the master input for each clock cycle. The spoke-type RAM read address input may originate from a counter counting from zero to the spoke count minus one. In this example, different spoke counts may be used for different tiles, for example, within the same HTF cluster 502, to allow the performance of a particular application or instruction set to be determined by several tiles or unique tile examples used in the inner loop. In this example, the spoke-type RAM may specify when synchronous inputs will be written to the tile memory, for example, using multiple inputs for a particular tile instruction and the time when one of the inputs arrives before the others. The earlier arriving input may be written to the tile memory and may be read later when all inputs are available. In this example, the tile memory may be accessed as a FIFO memory, and the FIFO read and write pointers may be stored in register-based memory areas or structures within the tile memory.

[0102] Figure 6A and Figure 6BExamples of chiplet systems that can be used to implement one or more aspects of CNM system 102 are generally illustrated. As similarly mentioned above, nodes in CNM system 102 or devices within nodes in CNM system 102 may contain chiplet-based architectures or CNM chiplets. Packaged memory computing devices may contain, for example, one, two, or four CNM chiplets. Chipslets may be interconnected using high-bandwidth, low-latency interconnects (e.g., using CPI interfaces). Typically, a chiplet system consists of discrete modules (each referred to as a “chiplet”) integrated on an interposer layer and, in many instances, interconnected as needed via one or more established networks to provide the desired functionality to the system. The interposer layer and the contained chiplets may be packaged together to facilitate interconnection with other components of a larger system. Each chiplet may contain one or more individual integrated circuits (ICs) or “chips”, which may be combined with discrete circuit components and may be coupled to a corresponding substrate for attachment to the interposer layer. Most or all of the chiplets in the system may be individually configured for communication via established networks.

[0103] Chiplets, configured as individual modules within a system, differ from such systems implemented on a single chip containing different blocks of devices (e.g., intellectual property (IP) blocks) on a substrate (e.g., a single die), such as a system-on-a-chip (SoC) or multiple discrete packaged devices integrated on a printed circuit board (PCB). Generally, chiplets offer better performance (e.g., lower power consumption, reduced latency, etc.) than discrete packaged devices, and offer greater manufacturing benefits than a single die chip. These manufacturing benefits may include higher yields or reduced development costs and time.

[0104] A chiplet system may comprise, for example, one or more application (or processor) chiplets and one or more support chiplets. Here, the distinction between application chiplets and support chiplets is merely a reference to possible design scenarios for chiplet systems. Thus, for example, a synthetic vision chiplet system may comprise (by way of example only) application chiplets for generating synthetic vision output, and support chiplets such as memory controller chiplets, sensor interface chiplets, or communication chiplets. In typical use cases, a synthetic vision designer may design the application chiplets and obtain the support chiplets from other sources. Therefore, design costs (e.g., in terms of time or complexity) are reduced by avoiding the design and manufacture of the functionality embodied in the support chiplets.

[0105] Chiplets also support the tight integration of IP blocks that might otherwise be difficult, such as IP blocks manufactured using different processing technologies or with different feature sizes (or utilizing different contact technologies or spacing). Therefore, multiple ICs or IC components with different physical, electrical, or communication characteristics can be assembled in a modular manner to provide a component with the desired functionality. Chiplet systems also facilitate adaptation to the needs of different larger systems that will be incorporated into chiplet systems. In examples, ICs or other components can be optimized for power, speed, or heat generation for specific functions, as might be the case with sensors, and can be integrated with other devices more easily than attempting integration on a single die. Furthermore, by reducing the overall die size, chiplet yields are often higher than those of more complex single-die devices.

[0106] Figure 6A and Figure 6B An example of a chiplet system according to an embodiment is shown in general. Figure 6A This is an illustration of a chiplet system 602 mounted on a peripheral board 604, which can be connected to a wider computer system, for example, via PCIe. The chiplet system 602 includes a package substrate 606, an interposer 608, and four chips: an application chiplet 610, a host interface chiplet 612, a memory controller chiplet 614, and a memory device chiplet 616. Other systems may include numerous additional chipsets to provide additional functionality, as will be apparent from the following discussion. The package of the chiplet system 602 is shown as a cap or cover plate 618, but other packaging techniques and structures used for chiplet systems may be used. Figure 6B This is a block diagram illustrating the components in a chiplet system for clarity.

[0107] Application chip 610 is shown as a chip system NOC 620 including a chip network 622 for supporting inter-chip communication. In an example embodiment, the chip system NOC 620 may be included on application chip 610. In an example, the chip network 622 may be defined in response to selected supporting chips (e.g., host interface chip 612, memory controller chip 614, and memory device chip 616). Figure 1 The first NOC 118 in this example allows designers to select an appropriate number of chiplet network connections or switches for the chiplet system NOC 620. In this example, the chiplet system NOC 620 may reside on a single chiplet or within the interposer 608. In the example discussed herein, the chiplet system NOC 620 implements a CPI network.

[0108] In this example, the chiplet system 602 may include or comprise a portion of the first memory computing node 104 or the first memory computing device 112. That is, various blocks or components of the first memory computing device 112 may include chiplets that can be mounted on the peripheral board 604, the package substrate 606, and the interposer 608. The interface components of the first memory computing device 112 may typically include a host interface chiplet 612. The memory and memory control-related components of the first memory computing device 112 may typically include a memory controller chiplet 614. The various accelerator and processor components of the first memory computing device 112 may typically include an application chiplet 610 or examples thereof.

[0109] For example, the CPI interface, which can be used for communication between or within chiplets in a system, is a packet network that supports virtual channels to enable flexible and high-speed interaction between chiplets. CPI bridges the chiplet network 622 from the chiplet intranet. For instance, AXI is a widely used specification for designing intranet communication. However, the AXI specification covers a large number of physical design options, such as the number of physical channels, signal timing, and power. Within a single chip, these options are typically selected to meet design goals, such as power consumption and speed. However, to achieve flexibility in chiplet systems, adapters such as CPI are used to intersect between various AXI design options that can be implemented in various chiplets. By implementing a mapping from physical channels to virtual channels and encapsulating time-based signaling using packetization protocols, CPI bridges the chiplet intranet 622.

[0110] CPI can utilize various physical layers to transmit packets. A physical layer can contain simple conductive connections, drivers for increasing voltage, or other mechanisms to facilitate signal transmission over longer distances. Examples of such physical layers include an Advanced Interface Bus (AIB), which in various instances can be implemented within the intermediate layer 608. The AIB uses source-synchronous data transfer with a forwarding clock to transmit and receive data. Packets are transmitted across the AIB at Single Data Rate (SDR) or Double Data Rate (DDR) relative to the transmitted clock. The AIB supports various channel widths. Channels can be configured with a symmetrical number of transmit (TX) and receive (RX) inputs / outputs (I / O), or an asymmetrical number of transmitters and receivers (e.g., all transmitters or all receivers). A channel can act as either the AIB body or slave depending on which chip provides the master clock. The AIB I / O unit supports three clock modes: asynchronous (i.e., non-timing), SDR, and DDR. In various instances, the non-timing mode is used for clocking and some control signals. SDR mode can use a dedicated SDR-only I / O unit or a dual-purpose SDR / DDR I / O unit.

[0111] In this example, CPI packet protocols (e.g., point-to-point or routable) can use symmetrical receive and transmit I / O units within an AIB channel. CPI streaming protocols allow for more flexible utilization of AIB I / O units. In this example, a streaming AIB channel can be configured with I / O units as all TX, all RX, or half TX and half RX. CPI packet protocols can use AIB channels in SDR or DDR operating modes. In this example, AIB channels are configured in increments of 80 I / O units (i.e., 40 TX and 40 RX) for SDR mode and in increments of 40 I / O units for DDR mode. CPI streaming protocols can use AIB channels in SDR or DDR operating modes. Here, in this example, AIB channels are configured in increments of 40 I / O units for both SDR and DDR modes. In this example, a unique interface identifier is assigned to each AIB channel. This identifier is used during CPI reset and initialization to determine paired AIB channels across neighboring chiplets. In this example, the interface identifier is a 20-bit value comprising a seven-bit chiplet identifier, a seven-bit column identifier, and a six-bit link identifier. The AIB physical layer uses an AIB out-of-band shift register to transmit the interface identifier. Bits 32 to 51 of the shift register are used to transmit the 20-bit interface identifier in both directions across the AIB interface.

[0112] AIB defines a stacked group of AIB channels as an AIB channel column. An AIB channel column has a certain number of AIB channels plus auxiliary channels. The auxiliary channels contain signals used for AIB initialization. All AIB channels within a column (except for the auxiliary channels) have the same configuration (e.g., all TX, all RX, or half TX and half RX) and the same number of data I / O signals. In this example, AIB channels are numbered sequentially in ascending order, starting with the AIB channel adjacent to the AUX channel. The AIB channel adjacent to the AUX channel is defined as AIB channel zero.

[0113] Typically, the CPI interface on a single chiplet may include serialization-deserialization (SERDES) hardware. SERDES interconnects are well-suited for scenarios requiring high-speed signaling and low signal counts. However, SERDES can introduce additional power consumption and longer latency for multiplexing and demultiplexing, error detection or correction (e.g., using block-level cyclic redundancy check (CRC)), link-level retries, or forward error correction. However, when low latency or power consumption is a primary concern for ultra-short-range chiplet-to-chiplet interconnects, parallel interfaces that allow data transmission with minimal latency can be utilized. CPIs contain elements designed to minimize both latency and power consumption in these ultra-short-range chiplet interconnects.

[0114] For flow control, CPI employs a credit-based technique. For example, the sender side of chip 614, such as the receiver side of chip 610, provides credits indicating available buffers. In this example, the CPI receiver contains buffers for each virtual channel for a given transmission time unit. Therefore, if the CPI receiver supports five messages and a single virtual channel in time, the receiver has five buffers arranged in five rows (e.g., one row per unit time). If four virtual channels are supported, the receiver has twenty buffers arranged in five rows. Each buffer holds the payload of one CPI packet.

[0115] When a sender transmits data to a receiver, the sender decrements its available credits based on the transmission. Once the receiver has used up all its credits, the sender stops sending packets to the receiver. This ensures that the receiver always has an available buffer to store transmissions.

[0116] When the receiver processes the received packet and releases the buffer, it sends the available buffer space back to the sender. The sender can then use this credit return to allow the transmission of additional information.

[0117] Figure 6A An example is a chiplet mesh network 624 that uses direct chiplet-to-chiplet technology without requiring a chiplet system NOC 620. The chiplet mesh network 624 can be implemented in a CPI or another chiplet-to-chiplet protocol. The chiplet mesh network 624 typically implements a chiplet pipeline, where one chiplet acts as an interface to the pipeline, while other chipslets in the pipeline interface only interface with themselves.

[0118] Alternatively, a dedicated device interface can be used to connect devices to the chiplet, such as one or more industry-standard memory interfaces (e.g., synchronous memory interfaces, such as DDR5, DDR6). Connections from the chiplet system or individual chiplets to external devices (e.g., larger systems) can be made via the desired interface (e.g., a PCIe interface). In this example, such an external interface can be implemented via a host interface chiplet 612, which, in the depicted example, provides a PCIe interface external to the chiplet system. This type of interface is typically used when industry practice or standards have converged on such a dedicated chiplet interface 626. The illustrated example of connecting a memory controller chiplet 614 to the DDR interface of a DRAM memory device chiplet 616 exemplifies this industry practice.

[0119] Among the various possible supporting chiplets, the memory controller chiplet 614 is likely to be present in chiplet systems due to the ubiquitous use of storage devices for computer processing and the current level of technological sophistication of memory devices. Therefore, using the memory device chiplet 616 and the memory controller chiplet 614, produced through other technologies, allows chiplet system designers to obtain robust products manufactured by established companies. Typically, the memory controller chiplet 614 provides a memory device-specific interface for reading, writing, or erasing data. Typically, the memory controller chiplet 614 can provide additional functionality such as error detection, error correction, maintenance operations, or atomic operator execution. For some types of memory, maintenance operations are often specific to the memory device chiplet 616, such as garbage collection in NAND flash or storage-class memory, or temperature regulation (e.g., cross-temperature management) in NAND flash memory. In instances, maintenance operations may involve logic-to-physical (L2P) mapping or management to provide an indirection hierarchy between the physical and logical representations of data. In other types of memory, such as DRAM, some memory operations, such as refresh, may be controlled at some times by the host processor or memory controller, and at other times by the DRAM memory device or logic associated with one or more DRAM devices, such as interface chips (in this example, buffers).

[0120] Atomic operators are data manipulations that can be performed, for example, by the memory controller chiplet 614. In other chiplet systems, atomic operators can be performed by other chipsets. For example, an application chiplet 610 can specify an "increment" atomic operator in a command that includes a memory address and may include an increment value. Upon receiving the command, the memory controller chiplet 614 retrieves a number from the specified memory address, increments the number by the amount specified in the command, and stores the result. Upon successful completion, the memory controller chiplet 614 provides the application chiplet 610 with an indication that the command was successful. Atomic operators avoid transferring data across the chiplet mesh network 624, thereby reducing latency in executing such commands.

[0121] Atomic operators can be categorized into built-in atoms or programmable (e.g., custom) atoms. Built-in atoms are a limited set of operations that are implemented invariantly in the hardware. Programmable atoms are small programs that can be executed on the PAU (e.g., custom atomic unit (CAU)) of the memory controller chip 614.

[0122] The memory device chip 616 may be or include any combination of volatile memory devices or non-volatile memory. Examples of volatile memory devices include, but are not limited to, RAM, such as DRAM, synchronous DRAM (SDRAM), and GDDR6 SDRAM. Examples of non-volatile memory devices include, but are not limited to, NAND flash memory and memory-type memories (e.g., phase-change memory or memristor-based technology, ferroelectric RAM (FeRAM), etc.). The illustrated example includes the memory device chip 616 as a chip; however, the device may reside elsewhere, such as in different packages on peripheral board 604. For many applications, multiple memory device chips may be provided. In examples, these memory device chips may each implement one or more memory technologies and may include an integrated computing host. In examples, the memory chip may include multiple stacked memory dies of different technologies (e.g., one or more SRAM devices stacked with one or more DRAM devices or their respective stacks). (It communicates in other ways). In an example, the memory controller chip 614 can be used to coordinate the operation between multiple memory chips in the chiplet system 602 (e.g., using one or more memory chips in one or more tiers of cache memory, and using one or more additional memory chips as main memory). The chiplet system 602 may include multiple examples of memory controller chips 614, such as those used to provide memory control functions for individual hosts, processors, sensors, networks, etc. For example, the chiplet architecture in the illustrated system offers advantages in allowing adaptation to different memory storage technologies and provides different memory interfaces through updated chiplet configurations, for example, without requiring redesign of the rest of the system architecture.

[0123] Figure 7 This section generally illustrates an example of a chiplet-based implementation for a memory computing device according to an embodiment. The example includes an implementation having four CNM chiplets, each of which may include or include components from… Figure 1 This refers to a portion of the first memory computing device 112 or the first memory computing node 104. Various portions may contain or include corresponding chiplets. Chiplet-based implementations may include or utilize CPI-based intra-system communication, as described above in [the context of...]. Figure 6A and Figure 6B The example chip system 602 is discussed similarly.

[0124] Figure 7An example includes a first CNM package 700, which comprises multiple chiplets. The first CNM package 700 includes a first chiplet 702, a second chiplet 704, a third chiplet 706, and a fourth chiplet 708, all coupled to the CNM NOC hub 710. Each of the first through fourth chiplets may include examples of the same or substantially the same components or modules. For example, each chiplet may each contain a corresponding example of an HTP accelerator, an HTF accelerator, and a memory controller for accessing internal or external memory.

[0125] exist Figure 7 In one example, the first chiplet 702 includes a first NOC hub edge 714 coupled to the CNM NOC hub 710. Other chipslets in the first CNM package 700 similarly include NOC hub edges or endpoints. Switches in the NOC hub edges facilitate communication within the chiplet or within the chiplet system via the CNM NOC hub 710.

[0126] The first chiplet 702 may further include one or more memory controllers 716. The memory controllers 716 may correspond to different NOC endpoint switches that interface with the first NOC hub edge 714. In examples, the memory controllers 716 include memory controller chiplet 614, memory controller 130, memory subsystem 200, or other memory computing implementations. The memory controllers 716 may be coupled to different memory devices, such as a first external memory module 712a or a second external memory module 712b. The external memory modules may include, for example, GDDR6 memory that can be selectively accessed by different chipsets in the system.

[0127] The first chiplet 702 may further include, for example, a first HTP chiplet 718 and a second HTP chiplet 720 coupled to the edge 714 of the first NOC hub via a corresponding different NOC endpoint switch. The HTP chipsets may correspond to an HTP accelerator, for example, from... Figure 1 The instance of HTP 140 or from Figure 4 An example of an HTP accelerator 400. The HTP chiplet can communicate with the HTF chiplet 722. The HTF chiplet 722 can correspond to an HTF accelerator, for example, from... Figure 1 The instance of HTF 142 or from Figure 5 The HTF 500 instance.

[0128] The CNM NOC hub 710 can be coupled to other chiplets or other CNM packages via various interfaces and switches. For example, the CNM NOC hub 710 can be coupled to a CPI interface via multiple different NOC endpoints on the first CNM package 700. Each of the multiple different NOC endpoints can be coupled to a different node, for example, outside the first CNM package 700. In an example, the CNM NOC hub 710 can be coupled to other peripheral devices, nodes, or devices using CTCPI or other non-CPI protocols. For example, the first CNM package 700 may include a PCIe-scale interface (PCIe / SFI) or a CXL interface configured to interface the first CNM package 700 with other devices. In an example, devices coupled to the first CNM package 700 using various CPI, PCIe, CXL, or other architectures can form a common global address space.

[0129] exist Figure 7 In this example, the first CNM package 700 includes a host interface 724 (HIF) and a host processor (R5). The host interface 724 may correspond to, for example, a source... Figure 1 The instance is HIF 120. The host processor or R5 can correspond to the one from... Figure 1 The instance includes an internal host processor 122. Host interface 724 may include a PCI interface for coupling the first CNM package 700 to other external devices or systems. In this instance, work can be initiated via host interface 724 on the first CNM package 700 or on a cluster of tiles within the first CNM package 700. For example, host interface 724 may be configured to command individual HTF tile clusters (e.g., within various chiplets in the first CNM package 700) to enter and exit power / clock gate modes.

[0130] Figure 8 An example of tiled storage of a memory computing device according to an embodiment is shown. Figure 8 In the example 800 of the tiled chiplet instance, there are four different CNM clusters of chiplets, where the clusters are coupled together. Each CNM chiplet instance may contain one or more constituent chiplets (e.g., host processor chiplets, memory device chiplets, interface chiplets, etc.).

[0131] 800 tiled chiplet instances contain data from Figure 7An example of the first CNM package 700 is one or more of its CNM clusters. For example, the tiled chiplet instance 800 may include a first CNM cluster 802, which includes a first chiplet 810 (e.g., corresponding to the first chiplet 702), a second chiplet 812 (e.g., corresponding to the second chiplet 704), a third chiplet 814 (e.g., corresponding to the third chiplet 706), and a fourth chiplet 816 (e.g., corresponding to the fourth chiplet 708). The chipsets in the first CNM cluster 802 may be coupled to a common NOC hub, which may in turn be coupled to one or more NOC hubs in adjacent clusters (e.g., in the second CNM cluster 804 or the fourth CNM cluster 808).

[0132] exist Figure 8 In this example, the tiled chiplet instance 800 includes a first CNM cluster 802, a second CNM cluster 804, a third CNM cluster 806, and a fourth CNM cluster 808. The various CNM chipsets can be configured in a common address space, allowing chipsets to allocate and share resources across different tiles. In this example, chipsets within a cluster can communicate with each other. For instance, the first CNM cluster 802 can be communicatively coupled to the second CNM cluster 804 via an inter-chiplet CPI interface 818, and the first CNM cluster 802 can be communicatively coupled to the fourth CNM cluster 808 via another or the same CPI interface. The second CNM cluster 804 can be communicatively coupled to the third CNM cluster 806 via the same or another CPI interface, and so on.

[0133] In this example, one of the CNM chipsets in the tiled chiplet example 800 may contain a host interface (e.g., corresponding to a source from...). Figure 7 The host interface 724 of the instance is responsible for workload balancing across the chiplet instance 800. The host interface can facilitate, for example, access to host-based command request queues and response queues from outside the chiplet instance 800. The host interface can use hybrid thread processors and hybrid thread architectures in one or more CNM chipsets in the chiplet instance 800 to dispatch new execution threads.

[0134] Figure 9 This is a block diagram 900 of an instance memory system 910 suitable for performing interpolation within a memory system. The memory system 910 includes a memory controller 130 and a memory device 128, both of which are also... Figure 1 As shown in the diagram. Memory controller 130 is configured to process host commands 925 received from host 920 via a bus. Processing host commands 925 may include interpolating memory addresses (operation 950), accessing data from a cache (operation 960), and interpolating samples (operation 970). If the data is in a cache (e.g., ...), ... Figure 2If the local cache module 212 is unavailable, data can be loaded from the memory device 128.

[0135] The host command can be an interpolated access initialization command. The interpolated access initialization command identifies an integer-indexed memory array stored in memory device 128. For example, the interpolated access initialization command may include the address of a first element of the memory array and multiple elements in the memory array. The addresses and numbers of the elements may be stored in local cache module 212 or in another memory element (e.g., a register file) in memory controller 130.

[0136] Host commands can be requests to access interpolated data, including floating-point indices in an integer-indexed memory array. For example, a data array (e.g., integer data, floating-point single-precision real data, floating-point double-precision complex data, vector data, or any suitable combination thereof) can have ten elements, indexed by integer values ​​from 0 to 9. Requests can be values ​​of floating-point indices in the range 0-9. For illustration, a floating-point index of 1.7 can be accepted.

[0137] In operation 950, memory controller 130 determines one or more addresses within memory device 128 to be accessed to process the request. If an index is not equal to one of the indices used for the memory array, two adjacent indices (and their corresponding addresses) are identified. For example, if the base address of the array is 0x1000, each element is 8 bytes in size, and the index is 1.7, then two adjacent addresses are 0x1008 and 0x1010. As used herein, the prefix 0x indicates that the following number is in hexadecimal representation.

[0138] Retrieve the data value from the identified address from the local cache module 212 (operation 960). If the local cache module 212 does not yet store the value (e.g., in the case of a cache miss), retrieve the data value from the local cache module 212. Figure 1 memory device 128 or Figure 2 The memory device 204 reads data from these two addresses and stores it in the local cache module 212.

[0139] In operation 970, the memory controller 130 interpolates a sample. For example, if the value of index 1 is 20 and the value of index 2 is 30, then the interpolated value of index 1.7 is 27. The interpolated value can be found using the following pseudocode:

[0140]

[0141] In the above example, the `numElements` and `dataP0` parameters are defined by the initialization command, `bin` is the index provided with the interpolation read request, and `sample` is the interpolated output. The `linearInterpolateFloat` function determines the interpolated floating output value of the binary array, indicated by the types of `sample` and `dataP0`, respectively. Values ​​generated using interpolation may be less accurate than measurements stored in the array. Therefore, reducing the precision of the output value saves memory bandwidth and storage, with almost no reduction in computational accuracy. The `linearInterpolateFloat` function performs a bounds check on the floating-point index (after converting it to the integer `bin_floor`) to avoid accessing data values ​​outside the array. If the bounds check fails, a zero value is provided. Therefore, a processing element that calls the linear interpolation function on memory controller 130 does not need to perform its own bounds check before calling the linear interpolation function to avoid potentially invalid memory accesses.

[0142] Linear interpolation is performed by determining the first weight (w) of the first value (dataP0[bin_floor]) and the second weight (1.0fw, where the "f" suffix indicates that 1.0 is treated as a single-precision floating-point value) of the second value (dataP0[bin_floor+1]). The two values ​​are then multiplied by their respective weights, and the results are summed to obtain the linearly interpolated value.

[0143] The following pseudocode can also be used to perform linear interpolation on complex values:

[0144]

[0145] The `linearInterpolateComplex` function is similar to the `linearInterpolateReal` function, but the array and output values ​​are complex data types, not real numbers. Since complex numbers can be considered vectors of length two, it can be seen that the above method can be extended to provide linear interpolation for vectors of arbitrary length (e.g., three-dimensional, four-dimensional, ten-dimensional, or one-hundred-dimensional). The `complex_float` data type is a single-precision complex number (e.g., consisting of two floating-point numbers, each stored using 32 bits). The `complex_double` data type is a double-precision complex number (e.g., consisting of two double-precision floating-point numbers, each stored using 64 bits).

[0146] In some implementations, the interpolated data is stored in a two-dimensional array. A request for interpolated data may contain an integer index of one of the two dimensions (or N-1 dimensions of an N-dimensional array) and a floating-point index of the remaining dimensions. Pseudocode for this scenario is presented below.

[0147]

[0148] In some implementations, pIdx is provided as part of the initialization command. In other implementations, pIdx is provided as part of the interpolation request. Two-dimensional data is stored in sConsts2 (provided as part of the initialization command). The size of the interpolated dimension is stored in sConsts1->numElements. In some implementations, the input index (bin in the above example) uses a different range than the integer index in the array. In these implementations, the index can be transformed after calculating the weights and before accessing the two data values. For example, if the input index ranges from 0 to 1, rows can be added.

[0149] bin_floor*=sConsts1->dataElements–1;

[0150] Convert bin_floor to a range of the number of data elements. As another example, if the input index ranges from -size / 2 to size / 2, rows can be added.

[0151] bin_floor+=sConsts1->dataElements>>2;

[0152] The bin_floor is shifted upwards by half the number of data elements in the interpolation array, thus making the range from 0 to the size. Other transformations of the input index are also envisioned.

[0153] Figure 10 This is a flowchart illustrating the operation of a method 1000 performed by circuitry during interpolation according to some embodiments of the present disclosure. Method 1000 includes operations 1010, 1020, 1030, 1040, 1050, and 1060. Operations 1010-1060 are described by, and not by, circuitry according to, some embodiments of the present disclosure. Figure 1 and 9 The memory controller 130 executes pseudocode to execute the linearInterpolateFloat function.

[0154] In operation 1010, memory controller 130 (e.g., from host processor 122) receives a command including a floating-point index in a value array stored in the memory array. Memory controller 130 determines a first address of a first value in the memory array and a second address of a second value in the memory array based on the floating-point index (operation 1020). In the `linearInterpolateFloat` function, the first address is the address of `dataP0[bin_floor]`, and the second address is the address of `dataP0[bin_floor+1]`.

[0155] In operation 1030, memory controller 130 accesses a first value from a first address and a second value from a second address. Furthermore, in operation 1040, the memory controller determines a first weight for the first value and a second weight for the second value based on floating-point indices. In the `linearInterpolateFloat` function, the first weight is (1.0fw) and the second weight is w.

[0156] In operation 1050, memory controller 130 determines an interpolated value (e.g., a sample value in linearInterpolateFloat) based on a first weight, a first value, a second weight, and a second value. Memory controller 130 provides the interpolated value in response to a command received in operation 1010.

[0157] Interpolation is performed within memory controller 130, rather than by host processor 122, using method 1000. Method 1000 can be executed simultaneously by multiple memory controllers 130 operating on multiple memories 128. Each of the memories 128 can store a separate portion of the dataset to be manipulated. One use of linear interpolation is to generate images suitable for use as input to algorithms (e.g., trained machine learning models) when processing SAR data for autonomous navigation of autonomous vehicles (e.g., flying unmanned aerial vehicles (also known as drones (UAVs) or autonomous land vehicles (e.g., cars, tanks, or towing trailers)). For example, SAR pulse data can be divided into physical regions, and all pulses of a single region are stored in one memory 128. In various example embodiments, data is divided into memories 128 with larger or smaller granularities.

[0158] Since the interpolation performed by the host processor 122 involves (at least) two data values ​​that need to be interpolated between them, the amount of data transferred from the memory controller 130 to the host processor 122 using method 1000 is reduced by at least two times. The power consumed by the data transfer is also reduced by a similar factor, thereby extending the battery life of battery-powered devices (e.g., drones). Therefore, the CNM system 102 can be integrated into autonomous vehicles, whereby performing linear interpolation using method 1000 helps extend the vehicle's battery life, increase its driving range, allow the use of smaller and lighter batteries, or any suitable combination thereof.

[0159] Figure 11 This is a flowchart illustrating the operation of method 1100 performed by circuitry during interpolation according to some embodiments of the present disclosure. Method 1100 includes operations 1110, 1120, and 1130. By way of example and not limitation, operations 1110-1130 are performed by... Figure 1 and 9 The memory controller 130 executes.

[0160] In operation 1110, the memory controller 130 receives a command indicating the starting address of the value array and the number of values ​​in the value array. For example, it may receive pointers to numElements and dataP0 used in the linearInterpolateFloat function. Alternatively, the command may include pointers to a data structure from which the starting address of the value array and the number of values ​​in the array are derived. An example of this is shown in the linearInterpolate2D function, where numElements originates from the sConsts1 pointer and dataP0 originates from the sConsts2 pointer and the pIdx parameter.

[0161] In response to the command, in operation 1120, the memory controller stores the address and value number in the cache memory (e.g., Figure 2 In the cache (212). In operation 1130, the memory controller executes method 1000 to access the value stored in the cache memory.

[0162] By separating the provision of linear interpolation function parameters between initialization commands and interpolation requests, the communication overhead of repeated interpolation requests within the same value array is reduced. Initialization commands are only repeated when the value array changes. Therefore, compared to providing all parameters for each interpolation request, this results in reduced communication between the processor and memory controller, reduced latency, increased throughput, and lower power consumption.

[0163] Figure 12 This is a flowchart illustrating the operation of a method performed by circuitry when controlling a vehicle according to some embodiments of the present disclosure. By way of example and not limitation, method 1200 may comprise... Figure 1-9 The autonomous vehicle executes one or more memory systems. Method 1200 includes operations 1210, 1220, 1230, 1240, 1250, and 1260.

[0164] In Operation 1210, the vehicle uses SAR to collect pulse data. For example, a flying drone may carry an antenna subsystem mounted under the drone's fuselage. The antenna subsystem generates radar pulses and receives radar reflections (pulse data).

[0165] In operation 1220, the vehicle uses a Fourier transform to generate intermediate data points. Each pulse generates discrete data points. To improve the resolution of the image generated by backprojection, additional intermediate data points are needed. For this purpose, the FFT generates intermediate data points with appropriate accuracy. In some example embodiments, the HTP 140 of the CNM system 102 performs operation 1220. As another example, Figure 7The CNM packaged HTP chiplets 718 and 720 (optionally organized as) Figure 8 The tiled chiplet instance 800) performs operation 1220. For each pulse data sequence or different parts of a single pulse data sequence, the generation of intermediate data points can be performed in parallel.

[0166] In operation 1230, the collected and generated data points are stored in memory. For example, the data can be stored in... Figure 1 and 9 Memory device 128 Figure 7 Memory modules 712a and 712b Figure 8 The chiplet memory device or any suitable combination thereof in the chiplet cluster 802. Using FFT interpolation instead of using more radar pulses allows for a simpler radar antenna, reducing the energy consumed in generating pulses and detecting reflections, or both.

[0167] In operation 1240, the vehicle generates an image by performing backprojection, where additional intermediate data points are generated using linear interpolation within the memory controller. For example, method 1100 can be repeated when iterating over stored pulse data during the execution of the backprojection algorithm. Using linear interpolation instead of a higher-resolution FFT to generate additional intermediate data points saves computation and memory storage, thus saving energy and weight (because a larger memory device is not required). Performing linear interpolation within the memory controller, rather than in different processing elements, saves energy and memory bandwidth.

[0168] Similar to generating interpolated data using FFT in operation 1220, this can be achieved by using multiple HTPs 140 of CNM system 102. Figure 7 The CNM packaged HTP chiplets 718 and 720 (optionally organized as) Figure 8 (e.g., a tiled chiplet instance 800) or any suitable combination thereof to perform operations 1240 substantially in parallel.

[0169] The vehicle feeds the generated images as input to a trained machine learning model or other control algorithm (operation 1250). For example, a machine learning model can be trained on a training set of labeled images to learn how to control the vehicle. The resulting model is loaded into the vehicle (e.g., into the memory of the tiled chip instance 800 for evaluation by the processing elements of the tiled chip instance 800) and used to generate control signals for the vehicle. For example, the model can be trained to avoid obstacles while maintaining a forward direction toward a pre-programmed destination. Thus, when an obstacle is detected ahead, the model generates signals to turn left, right, up, or down to avoid the obstacle, even if the path length to the destination increases. Therefore, periodically feeding images generated by SAR to the trained machine learning module allows for dynamic control of the autonomous vehicle.

[0170] In Operation 1260, the vehicle is controlled based on the output of a trained machine learning model. For example, the output of the trained machine learning model can be connected to the control signals of the autonomous vehicle to make the vehicle turn left or right, increase or decrease speed, or (for UAVs) adjust altitude, direction, yaw, pitch, or roll.

[0171] Figure 13 This is a block diagram illustrating a SIMD interpolation initialization input 1310, a SIMD interpolation request input 1340, and a SIMD interpolation output 1360 for causing interpolation to be performed within a memory system, according to some embodiments of the present disclosure. Each SIMD command includes multiple data inputs and a single control input. The processing element receiving the SIMD command executes the same command for each data input. Compared to single-input, single-data commands, this reduces the overhead of command signaling. SIMD commands can be used in machine learning and image processing applications, as well as other uses.

[0172] SIMD interpolation initialization input 1310 includes two or more addresses 1320A-1320B and an equal number of element counts 1330A-1330B (e.g., for use with...). Figure 11 (SIMD processing in operations 1110 and 1120). Each pair of inputs provides initialization data for subsequent SIMD interpolation requests. In some example embodiments, eight pairs of inputs are included in the SIMD interpolation initialization input 1310. As an alternative to providing both the address and the number of elements in a single SIMD command, the initialization parameters can be divided across multiple SIMD commands. For example, a first SIMD command may be received including a 64-bit address of each of the multiple data channels, and a second SIMD command may be received including a 64-bit integer of each of the multiple data channels.

[0173] SIMD interpolation request input 1340 includes options suitable for... Figure 10The operation 1010 uses two or more floating-point indices 1350A and 1350B. Index 1350A is used as an offset from address 1320A, and index 1350B is used as an offset from address 1320B. In some example embodiments, eight indices are included in the SIMD interpolation request input 1340.

[0174] The SIMD interpolation output 1360 includes two or more interpolated result values. Figure 13 In this example, the interpolated value is a complex number. Therefore, the SIMD interpolation output 1360 includes a first real part 1370A, a first imaginary part 1380A, a second real part 1370B, and a second imaginary part 1380B. If more inputs are provided, the first input is used to generate the first complex output, the second input is used to generate the second complex output, and so on.

[0175] In some example embodiments and such Figure 2 As shown, the size of each output value is the same as the size of each input value. For example, 64-bit double-precision floating-point numbers can be accepted as indices 1350A and 1350B, and each of the result portions 1370A-1380B can be a 32-bit single-precision floating-point number, making each complex number result a 64-bit value. As another example, 64-bit double-precision floating-point numbers can be accepted as indices 1350A-1350B, and the result can be a 64-bit double-precision real (non-complex) floating-point number.

[0176] Matching the sizes of input and output values ​​maximizes the efficiency of the memory controller's memory interface. If the output size is larger than the input size, either the input is loosely packaged (e.g., a 128-bit interface carrying only 64 input bits to accommodate the doubled output size) or multiple data transfers are used to receive the output (e.g., two 128-bit transfers to receive 256 bits generated from the 128-bit input). If the output size is smaller than the input size, the output is loosely packaged. This may be harmless, but reducing the output size without reducing the number of memory transfers is unlikely to be beneficial.

[0177] Since complex numbers (or other two-dimensional results) contain two values, the size of the input and output can be matched by using the precision of each component of the result (which is half the precision of the input index). In this example, a 64-bit input is used, and two 32-bit outputs are generated. Other possibilities include a 16-bit input and two 8-bit outputs, a 32-bit input and two 16-bit outputs, a 128-bit input and two 64-bit outputs, and so on.

[0178] SIMD commands can be piped so that at least one data value begins processing in each clock cycle. Alternatively, multiple data values ​​can begin processing in parallel.

[0179] Figure 14 A block diagram of an example machine 1400 is shown, which may be used, in, or through which any one or more techniques (e.g., methods) discussed herein be implemented. As described herein, the example may contain, or be operated by, logic or multiple components or mechanisms in machine 1400. A circuit system (e.g., a processing circuit system) is a collection of circuits implemented in the tangible entity of machine 1400, which includes hardware (e.g., simple circuits, gates, logic, etc.). The membership of the circuit system may be flexible over time. The circuit system includes components that, when operated, can perform a specified operation individually or in combination. In the example, the hardware of the circuit may be immutably designed to perform a specific operation (e.g., hardwiring). In the example, the hardware of the circuit system may include physically connected components (e.g., execution units, transistors, simple circuits, etc.) and machine-readable media that are physically modified (e.g., magnetic, electrical, movable placement of particles of fixed mass, etc.) to encode instructions for a specific operation. When connecting the physical components, the underlying electrical properties of the hardware may change, for example, from an insulator to a conductor, or vice versa. These instructions enable embedded hardware (e.g., execution units or loading mechanisms) to create components of a circuit system within the hardware via variable connections so that, during operation, parts of the circuit system perform specific operations. Thus, in this example, a machine-readable media element is either part of the circuit system or another component communicatively coupled to the circuit system during device operation. In this example, any of the physical components can be used in more than one component of more than one circuit system. For example, during operation, an execution unit can be used at one point in time for a first circuit of a first circuit system and reused by a second circuit of the first circuit system, or reused at different times by a third circuit of the second circuit system. Further examples of these components of machine 1400 are given below.

[0180] In alternative embodiments, machine 1400 may operate as a standalone device or may be connected (e.g., networked) to other machines. In a networked deployment, machine 1400 may operate as a server machine, a client machine, or both in a server-client network environment. In an example, machine 1400 may act as a peer-to-peer (P2P) (or other distributed) network environment. Machine 1400 may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, network device, network router, switch, or bridge, or any machine capable of executing instructions (sequential instructions or other instructions) specifying the actions to be taken by said machine. Furthermore, although only a single machine is shown, the term "machine" should also be considered as any collection of machines that individually or jointly execute a set (or more) of instructions to perform any one or more methods discussed herein, such as cloud computing, Software as a Service (SaaS), or other computer cluster configurations.

[0181] Machine 1400 (e.g., a computer system) may include a hardware processor 1402 (e.g., a central processing unit (CPU), graphics processing unit (GPU), hardware processor core, or any combination thereof), main memory 1404, static memory 1406 (e.g., memory or storage device for firmware, microcode, basic input / output (BIOS), unified extensible firmware interface (UEFI), etc.), and mass storage device 1408 (e.g., hard disk drive, tape drive, flash memory, or other block device), some or all of which may communicate with each other via interconnect 1430 (e.g., a bus). Machine 1400 may further include a display device 1410, an alphanumeric input device 1412 (e.g., a keyboard), and a user interface (UI) navigation device 1414 (e.g., a mouse). In an example, the display device 1410, the input device 1412, and the UI navigation device 1414 may be a touchscreen display. Machine 1400 may also include a signal generation device 1418 (e.g., a speaker), a network interface device 1420, and one or more sensors 1416, such as a Global Positioning System (GPS) sensor, a compass, an accelerometer, or other sensors. Machine 1400 may include an output controller 1428, for example, serial (e.g., Universal Serial Bus (USB), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection, to communicate with or control one or more peripheral devices (e.g., a printer, a card reader, etc.).

[0182] The registers of the hardware processor 1402, main memory 1404, static memory 1406, or mass storage device 1408 may be or contain a machine-readable medium 1422 on which one or more sets of data structures or instructions 1424 (e.g., software) are stored, embodying or used by any one or more of the technologies or functions described herein. During execution of the instructions 1424 by the machine 1400, the instructions may also reside wholly or at least partially in any register of the hardware processor 1402, main memory 1404, static memory 1406, or mass storage device 1408. In this example, one or any combination of the hardware processor 1402, main memory 1404, static memory 1406, or mass storage device 1408 may constitute the machine-readable medium 1422. Although machine-readable media 1422 is shown as a single media, the term "machine-readable media" can include a single media or multiple media (e.g., a centralized or distributed database, or associated caches and servers) configured to store one or more instructions 1424.

[0183] The term "machine-readable media" can include any medium capable of storing, encoding, or carrying instructions executable by machine 1400 and causing machine 1400 to perform any one or more of the technologies disclosed herein, or any medium capable of storing, encoding, or carrying data structures used by or associated with such instructions. Examples of non-limiting machine-readable media may include solid-state memory, optical media, magnetic media, and signals (e.g., radio frequency signals, other photon-based signals, sound signals, etc.). In examples, non-transitory machine-readable media includes machine-readable media having a plurality of particles with constant mass (e.g., stationary) and thus being a component of matter. Therefore, non-transitory machine-readable media is machine-readable media that does not contain transiently propagating signals. Specific examples of non-transitory machine-readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable hard disks; magneto-optical disks; and CD-ROMs and DVD-ROMs.

[0184] In this example, information stored or otherwise provided on machine-readable medium 1422 may represent instructions 1424, such as instructions 1424 itself or a format from which instructions 1424 may be derived. Such a format from which instructions 1424 may be derived may include source code, encoded instructions (e.g., in compressed or encrypted form), encapsulated instructions (e.g., split into multiple encapsulations), etc. The information representing instructions 1424 on machine-readable medium 1422 may be processed by a processing circuitry system into instructions to perform any of the operations discussed herein. For example, deriving instructions 1424 from information (e.g., processed by a processing circuitry system) may include: compiling (e.g., from source code, object code, etc.), interpreting, loading, organizing (e.g., dynamic or static linking), encoding, decoding, encrypting, decrypting, encapsulating, decapsulating, or otherwise manipulating information into instructions 1424.

[0185] In an example, the derivation of instruction 1424 may involve (e.g., by processing circuitry) the assembly, compilation, or interpretation of information to create instruction 1424 from some intermediate or preprocessed format provided by machine-readable medium 1422. When information is provided in multiple parts, it can be combined, decapsulated, and modified to create instruction 1424. For example, information may be contained in multiple compressed source code packages (or object code, or binary executable code, etc.) on one or more remote servers. The source code packages may be encrypted during transmission over a network and, if necessary, decrypted, decompressed, assembled (e.g., linked), compiled or interpreted at the local machine (e.g., into a stand-alone executable library, etc.), and executed by the local machine.

[0186] Using any of several transport protocols (e.g., Frame Relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc.), instructions 1424 can also be transmitted or received on the communication network 1426 via the network interface device 1420 using a transport medium. Example communication networks can include local area networks (LANs), wide area networks (WANs), packet data networks (e.g., the Internet), mobile phone networks (e.g., cellular networks), conventional telephone (POTS) networks, and wireless data networks (e.g., the IEEE 802.11 standard series, known as...). The IEEE 802.16 standard series is known as This includes standards such as the IEEE 802.15.4 series and point-to-point (P2P) networks. In an example, network interface device 1420 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas for connection to network 1426. In an example, network interface device 1420 may include multiple antennas to perform wireless communication using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) technologies. The term "transmission medium" should be considered as any intangible medium capable of storing, encoding, or carrying instructions for execution by machine 1400, and containing digital or analog communication signals or other intangible media to facilitate communication of such software. The transmission medium is a machine-readable medium.

[0187] To better illustrate the methods and apparatus described herein, a set of non-limiting example embodiments are described below with numbered examples.

[0188] Example 1 is a system comprising: a memory array; and a memory controller coupled to the memory array and configured to perform operations including: receiving a command via a bus, the command including a floating-point index in a value array stored in the memory array; determining, based on the floating-point index, a first address of a first value of the value array and a second address of a second value of the value array; accessing, from the memory array, the first value from the first address and the second value from the second address; determining, based on the floating-point index, a first weight for the first value and a second weight for the second value; determining, based on the first weight, the first value, the second weight, and the second value, an interpolated value; and providing the interpolated value in response to the command.

[0189] In Example 2, the subject matter according to Example 1 includes: circuitry for controlling a vehicle; and one or more processing elements configured to perform operations including: generating an image from synthetic aperture radar (SAR) pulse data using the interpolated data; providing the image to a trained machine learning model; and generating inputs to the circuitry for controlling the vehicle using the results from the trained machine learning model.

[0190] In Example 3, the subject matter according to Example 2 includes: wherein the one or more processing elements are further configured such that the interpolated values ​​used to generate the image are determined by a plurality of memory controllers connected in a hybrid thread structure.

[0191] In Example 4, the subject matter described in Examples 1 to 3 includes: wherein the bus is part of a network on-chip (NOC); and the command is received from a host processor.

[0192] In Example 5, the subject matter according to Examples 1 to 4 includes: wherein providing the interpolated value includes providing the interpolated value to the hybrid thread processor (HTP) via the edge of the network on-chip (NOC) hub.

[0193] In Example 6, the subject matter described in Examples 1 to 5 includes: wherein the memory controller is a memory controller chip of a computer near memory (CNM) system.

[0194] In Example 7, the subject matter according to Examples 1 to 6 includes: wherein the system further includes a cache memory; and the operation further includes: receiving a second command prior to receiving the command, the second command indicating the address of the beginning of the value array and the number of values ​​in the value array; and in response to the second command, storing the address and the number of values ​​in the cache memory.

[0195] In Example 8, the subject matter according to Examples 1 to 7 includes: wherein the received command is a single instruction / multiple data (SIMD) command, the command including multiple floating-point indices in a plurality of value arrays stored in the memory array, the plurality of floating-point indices including the floating-point index.

[0196] In Example 9, the subject matter according to Example 8 includes: wherein the SIMD commands are piped such that at least one of the plurality of floating-point indices is processed in each clock cycle.

[0197] In Example 10, the subject matter according to Examples 1 to 9 includes: wherein the floating-point index has a value between a first integer index of the value array and a second integer index of the value array; and the first address corresponds to the first integer index, and the second address corresponds to the second integer index.

[0198] In Example 11, the subject matter according to Example 10 includes: wherein the operation further includes performing a bound check on the floating-point index.

[0199] In Example 12, the subject matter according to Examples 1 to 11 includes: wherein the floating-point index is a real number stored using a first number of bits; and the provided interpolated value is a complex number comprising a real part stored using a second number of bits and an imaginary part stored using a second number of bits, the second number of bits being half the first number of bits.

[0200] In Example 13, the subject matter according to Example 12 includes: the first number of bits is 64 bits; and the second number of bits is 32 bits.

[0201] In Example 14, the subject matter according to Examples 1 to 13 includes: wherein determining the interpolated value includes: determining a first product of the first value and the first weight; determining a second product of the second value and the second weight; and determining the interpolated value as the sum of the first product and the second product.

[0202] Example 15 is a non-transitory machine-readable medium storing instructions that, when executed by a system, cause the system to perform operations including: receiving a command via a bus, the command including a floating-point index in a value array stored in a memory array; determining, based on the floating-point index, a first address of a first value in the value array and a second address of a second value in the value array; accessing, from the memory array, the first value from the first address and the second value from the second address; determining, based on the floating-point index, a first weight for the first value and a second weight for the second value; determining, based on the first weight, the first value, the second weight, and the second value, an interpolated value; and providing the interpolated value in response to the command.

[0203] In Example 16, the subject matter described in Example 15 includes: said operation is for a memory controller chip for a computer near memory (CNM) system.

[0204] In Example 17, the subject matter according to Examples 15 and 16 includes: wherein the operation further includes: generating an image from synthetic aperture radar (SAR) pulse data using the interpolated data; providing the image to a trained machine learning model; and generating inputs to circuitry for controlling the vehicle using the results from the trained machine learning model.

[0205] In Example 18, the subject matter according to Examples 15 to 17 includes: wherein the operation further includes: receiving a second command prior to receiving the command, the second command indicating the address of the beginning of the value array and the number of values ​​in the value array; and in response to the second command, storing the address and the number of values ​​in a cache memory.

[0206] In Example 19, the subject matter according to Examples 15 to 18 includes: wherein the received command is a Single Instruction / Multiple Data (SIMD) command, the command including multiple floating-point indices in a plurality of value arrays stored in the memory array, the plurality of floating-point indices including the floating-point index.

[0207] In Example 20, the subject matter according to Example 19 includes: wherein the SIMD commands are piped such that at least one of the plurality of floating-point indices is processed in each clock cycle.

[0208] In Example 21, the subject matter according to Examples 15 to 20 includes: wherein the floating-point index has a value between a first integer index of the value array and a second integer index of the value array; and the first address corresponds to the first integer index, and the second address corresponds to the second integer index.

[0209] In Example 22, the subject matter according to Example 21 includes: wherein the operation further includes performing a bound check on the floating-point index.

[0210] In Example 23, the subject matter according to Examples 15 to 22 includes: wherein the floating-point index is a real number stored using a first number of bits; and the provided interpolated value is a complex number comprising a real part stored using a second number of bits and an imaginary part stored using a second number of bits, the second number of bits being half the first number of bits.

[0211] In Example 24, the subject matter according to Example 23 includes: the first number of bits is 64 bits; and the second number of bits is 32 bits.

[0212] Example 25 is a method comprising: receiving a command via a bus, the command including a floating-point index in a value array stored in a memory array; determining a first address of a first value of the value array and a second address of a second value of the value array based on the floating-point index; accessing the first value from the first address and the second value from the second address from the memory array; determining a first weight for the first value and a second weight for the second value based on the floating-point index; determining an interpolated value based on the first weight, the first value, the second weight, and the second value; and providing the interpolated value in response to the command.

[0213] In Example 26, the subject matter according to Example 25 includes: generating an image from synthetic aperture radar (SAR) pulse data using the interpolated data via one or more processing elements; providing the image to a trained machine learning model via the one or more processing elements; and generating inputs to circuitry for controlling a vehicle via the results from the trained machine learning model via the one or more processing elements.

[0214] In Example 27, the subject matter according to Example 26 includes: the interpolated values ​​used to generate the image are determined by a plurality of memory controllers connected in a hybrid thread structure via the one or more processing elements.

[0215] In Example 28, the subject matter described according to Examples 25 through 27 includes: wherein the bus is part of a network on-chip (NOC); and the command is received from a host processor.

[0216] In Example 29, the subject matter according to Examples 25 through 28 includes: wherein providing the interpolated value includes providing the interpolated value to a hybrid thread processor (HTP) via the edge of a network on-chip (NOC) hub.

[0217] In Example 30, the subject matter according to Examples 25 to 29 includes: receiving a second command prior to receiving the first command, the second command indicating the address of the beginning of the value array and the number of values ​​in the value array; and in response to the second command, storing the address and the number of values ​​in a cache memory.

[0218] In Example 31, the subject matter according to Examples 25 to 30 includes: wherein the received command is a Single Instruction / Multiple Data (SIMD) command, the command including multiple floating-point indices in a plurality of value arrays stored in the memory array, the plurality of floating-point indices including the floating-point index.

[0219] In Example 32, the subject matter according to Example 31 includes: wherein the SIMD commands are piped such that at least one of the plurality of floating-point indices is processed in each clock cycle.

[0220] In Example 33, the subject matter according to Examples 25 to 32 includes: wherein the floating-point index has a value between a first integer index of the value array and a second integer index of the value array; and the first address corresponds to the first integer index, and the second address corresponds to the second integer index.

[0221] In Example 34, the topic described in Example 33 includes: performing a bounds check on the floating-point index.

[0222] In Example 35, the subject matter according to Examples 25 to 34 includes: wherein the floating-point index is a real number stored using a first number of bits; and the provided interpolated value is a complex number comprising a real part stored using a second number of bits and an imaginary part stored using a second number of bits, the second number of bits being half the first number of bits.

[0223] In Example 36, the subject matter according to Example 35 includes: the first number of bits is 64 bits; and the second number of bits is 32 bits.

[0224] Example 37 is at least one machine-readable medium containing instructions that, when executed by a processing circuitry system, cause the processing circuitry system to perform operations to implement any of Examples 1 to 36.

[0225] Example 38 is a device that includes components for implementing any of Examples 1 through 36.

[0226] Example 39 is a system for implementing any of Examples 1 through 36.

[0227] Example 40 is a method for implementing any of Examples 1 through 36.

[0228] The above detailed description includes reference to the accompanying drawings, which form part of the detailed description. The drawings illustrate specific embodiments in which the invention can be practiced. These embodiments are also referred to herein as "examples." Such examples may include elements other than those shown or described. However, the inventors of the present invention have also contemplated examples where only those elements shown or described are provided. Furthermore, the inventors of the present invention have contemplated examples of any combination or arrangement of those elements (or aspects thereof) shown or described herein, either with respect to a particular example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0229] In this document, the term "a" is used as is common in patent literature to include one or more, independent of any other example or use of "at least one" or "one or more". In this document, the term "or" is used to refer to a non-exclusive "or", such that unless otherwise indicated, "A or B" may include "A but not B", "B but not A", and "A and B". In the appended claims, the terms "comprising" and "in which" are used as concise equivalents to the corresponding terms "including" and "wherein". Furthermore, in the appended claims, the terms "comprising" and "including" are open-ended, meaning that a system, apparatus, article, or process that includes elements other than those listed after such terms is still considered to be within the scope of the claims. Additionally, in the appended claims, the terms "first", "second", and "third", etc., are used only as designations and are not intended to impose numerical requirements on their objects.

[0230] The above description is intended to be illustrative and not restrictive. For example, the above examples (or one or more aspects thereof) can be used in combination with each other. Other embodiments may be used by those skilled in the art upon review of the above description. It is submitted on the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the above detailed description, various features may be grouped together to simplify this disclosure. This should not be construed as expecting that any unclaimed disclosed features are necessary for any claim. In fact, the subject matter of the invention may lie in less than all the features of a particular disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, wherein each claim exists independently as a separate embodiment, and these embodiments can be combined or arranged in various ways. The scope of the invention should be determined by reference to the appended claims and the full scope of the equivalents to which these claims are given.

Claims

1. A memory system comprising: Memory array; as well as A memory controller, coupled to the memory array and configured to perform operations including the following: The command is received via a bus, the command including a floating-point index in a value array stored in the memory array, the floating-point index having a value between a first integer index and a second integer index of the value array; Based on the floating-point index, the first address of the first value of the value array and the second address of the second value of the value array are determined, wherein the first address corresponds to the first integer index and the second address corresponds to the second integer index; Access the first value from the first address and the second value from the second address from the memory array; A first weight for the first value and a second weight for the second value are determined based on the floating-point index; The interpolated value is determined based on the first weight, the first value, the second weight, and the second value; as well as The interpolated value is provided in response to the command.

2. The memory system according to claim 1, further comprising: Circuits used to control the vehicle; as well as One or more processing elements configured to perform operations including the following: The image is generated from synthetic aperture radar (SAR) pulse data using the interpolated values; The image is fed into a trained machine learning model; as well as The results from the trained machine learning model are used to generate inputs to the circuitry used to control the vehicle.

3. The memory system according to claim 2, wherein: The one or more processing elements are further configured such that the interpolated values ​​used to generate the image are determined by a plurality of memory controllers connected in a hybrid threaded architecture.

4. The memory system according to claim 1, wherein: The bus is part of the on-chip network NOC; and The command is received from the host processor.

5. The memory system of claim 1, wherein providing the interpolated value includes providing the interpolated value to the hybrid thread processor HTP via the edge of the on-chip network NOC hub.

6. The memory system according to claim 1, wherein the memory controller is a memory controller chip of a computer near memory (CNM) system.

7. The memory system according to claim 1, wherein: The system further includes a cache memory; and The operation further includes: Before receiving the first command, a second command is received, the second command indicating the starting address of the value array and the number of values ​​in the value array; and In response to the second command, the address and the number of values ​​are stored in the cache memory.

8. The memory system according to claim 1, wherein: The received command is a Single Instruction / Multiple Data (SIMD) command, which includes multiple floating-point indices in multiple value arrays stored in the memory array, and the multiple floating-point indices include the floating-point index.

9. The memory system according to claim 8, wherein: The SIMD commands are piped so that at least one of the plurality of floating-point indices is processed in each clock cycle.

10. The memory system of claim 1, wherein the operation further comprises: Perform a bounds check on the floating-point index.

11. The memory system according to claim 1, wherein: The floating-point index is a real number stored using a first number of bits; and The provided interpolated value is a complex number, which includes a real part stored using a second number of bits and an imaginary part stored using a second number of bits, the second number of bits being half the first number of bits.

12. The memory system according to claim 11, wherein: The first number of bits is 64 bits; and The second number of bits is 32 bits.

13. The memory system of claim 1, wherein determining the interpolated value comprises: Determine the first product of the first value and the first weight; Determine the second product of the second value and the second weight; as well as The interpolated value is determined as the sum of the first product and the second product.

14. A non-transitory machine-readable medium storing instructions, which, when executed by a system, cause the system to perform operations including: The command is received via a bus, the command including a floating-point index in a value array stored in a memory array, the floating-point index having a value between a first integer index and a second integer index of the value array; Based on the floating-point index, the first address of the first value of the value array and the second address of the second value of the value array are determined, wherein the first address corresponds to the first integer index and the second address corresponds to the second integer index; Access the first value from the first address and the second value from the second address from the memory array; A first weight for the first value and a second weight for the second value are determined based on the floating-point index; The interpolated value is determined based on the first weight, the first value, the second weight, and the second value; as well as The interpolated value is provided in response to the command.

15. The non-transitory machine-readable medium of claim 14, wherein the operation is for a memory controller chip of a computer near memory (CNM) system.

16. The non-transitory machine-readable medium of claim 14, wherein the operation further comprises: The image is generated from synthetic aperture radar (SAR) pulse data using the interpolated values; The image is fed into a trained machine learning model; as well as The results from the trained machine learning model are used to generate inputs to the circuitry used to control the vehicle.

17. The non-transitory machine-readable medium of claim 14, wherein the operation further comprises: A second command is received before the first command is received, the second command indicating the starting address of the value array and the number of values ​​in the value array; as well as In response to the second command, the address and the number of values ​​are stored in the cache memory.

18. The non-transitory machine-readable medium according to claim 14, wherein: The received command is a Single Instruction / Multiple Data (SIMD) command, which includes multiple floating-point indices in multiple value arrays stored in the memory array, and the multiple floating-point indices include the floating-point index.

19. The non-transitory machine-readable medium according to claim 18, wherein: The SIMD commands are piped so that at least one of the plurality of floating-point indices is processed in each clock cycle.

20. The non-transitory machine-readable medium of claim 14, wherein the operation further comprises: Perform a bounds check on the floating-point index.

21. The non-transitory machine-readable medium according to claim 14, wherein: The floating-point index is a real number stored using a first number of bits; and The provided interpolated value is a complex number, which includes a real part stored using a second number of bits and an imaginary part stored using a second number of bits, the second number of bits being half the first number of bits.

22. The non-transitory machine-readable medium according to claim 21, wherein: The first number of bits is 64 bits; and The second number of bits is 32 bits.

23. A method for performing interpolation, the method comprising: The command is received via a bus, the command including a floating-point index in a value array stored in a memory array, the floating-point index having a value between a first integer index and a second integer index of the value array; Based on the floating-point index, the first address of the first value of the value array and the second address of the second value of the value array are determined, wherein the first address corresponds to the first integer index and the second address corresponds to the second integer index; Access the first value from the first address and the second value from the second address from the memory array; A first weight for the first value and a second weight for the second value are determined based on the floating-point index; The interpolated value is determined based on the first weight, the first value, the second weight, and the second value; as well as The interpolated value is provided in response to the command.

24. The method of claim 23, further comprising: An image is generated from synthetic aperture radar (SAR) pulse data using the interpolated values ​​through one or more processing elements; The image is fed to a trained machine learning model via one or more processing elements; as well as The one or more processing elements use the results from the trained machine learning model to generate inputs to the circuitry used to control the vehicle.

25. The method of claim 24, further comprising: The interpolated values ​​used to generate the image are determined by a plurality of memory controllers connected in a hybrid threaded architecture via one or more processing elements.

26. The method according to claim 23, wherein: The bus is part of the on-chip network NOC; and The command is received from the host processor.

27. The method of claim 23, wherein providing the interpolated value comprises providing the interpolated value to the hybrid thread processor HTP via the edge of the on-chip network (NOC) hub.

28. The method of claim 23, further comprising: A second command is received before the first command is received, the second command indicating the starting address of the value array and the number of values ​​in the value array; as well as In response to the second command, the address and the number of values ​​are stored in the cache memory.

29. The method according to claim 23, wherein: The received command is a Single Instruction / Multiple Data (SIMD) command, which includes multiple floating-point indices in multiple value arrays stored in the memory array, and the multiple floating-point indices include the floating-point index.

30. The method according to claim 29, wherein: The SIMD commands are piped so that at least one of the plurality of floating-point indices is processed in each clock cycle.

31. The method of claim 23, further comprising: Perform a bounds check on the floating-point index.

32. The method according to claim 23, wherein: The floating-point index is a real number stored using a first number of bits; and The provided interpolated value is a complex number, which includes a real part stored using a second number of bits and an imaginary part stored using a second number of bits, the second number of bits being half the first number of bits.

33. The method according to claim 32, wherein: The first number of bits is 64 bits; and The second number of bits is 32 bits.

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