A flash memory data read architecture, method, apparatus, chip, and storage medium
By improving the flash data read architecture and utilizing read mode selection and current comparison modules, the problem of storage space limitation has been solved, enabling more efficient data representation in dual split-gate memory cells, and improving the upgradeability of system products and user experience.
Patent Information
- Application Number
- CN202210976432.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-08-15
- Publication Date
- 2025-12-02
- Estimated Expiration
- 2042-08-15
AI Technical Summary
Existing flash memory encounters storage space limitations during data upgrades, resulting in reduced functionality in system product upgrades and a poor user experience, especially since it is difficult to replace system-in-package products with larger capacity flash memory products.
A flash memory data read architecture is provided, which controls the normal and composite data read modes through a read mode selection signal. Combined with current comparison and logic operation modules, it realizes multiple data representation methods for dual split-gate memory cells, including normal data read and composite data read.
Within a limited storage space, by optimizing data distribution, more data representation was achieved, improving the flexibility of the system product and reducing costs.
Smart Images
Figure CN115148264B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of memory technology, such as a flash memory data reading architecture, method and apparatus, chip and storage medium. Background Technology
[0002] Currently, flash memory retains its stored data even when power is off, making it a type of non-volatile memory. Flash memory is characterized by its ability to retain data even when power is off, without requiring special high voltages for electrical erasure and reprogramming, its low manufacturing cost, and its high storage density, making it the mainstream non-volatile semiconductor memory technology. Among them, dual-gate flash memory boasts high transfer efficiency and is highly cost-effective for small capacities of 1MB to 4MB, thus making it one of the main non-volatile memory technologies on the market today.
[0003] However, as system products are upgraded, the data stored in the flash memory needs to be updated. The upgrade process increases the amount of data stored in the flash memory. If the amount of data required for the upgrade exceeds the maximum capacity of the flash memory product, a larger capacity flash memory product must be replaced. Typically, it is difficult to change the firmware of the flash memory product after the system product has been manufactured, especially for System-in-a-Package (SIP) products. When encountering such bottlenecks, the only option is to reduce the upgrade content and abandon some upgrade functions, resulting in a poor user experience. Summary of the Invention
[0004] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.
[0005] This disclosure provides a flash memory data reading architecture, method, apparatus, chip, and storage medium to enable the representation of more data with limited storage bits.
[0006] In some embodiments, the flash data read architecture includes:
[0007] The read operation control module is used to generate the read mode selection signal read_c. When the read_c signal is high, it enters the normal data read mode, and when the read_c signal is low, it enters the composite data read mode.
[0008] The first current comparison module is used to compare the current Icell output by the dual split-gate memory cell with the reference current Iref1 in the composite data reading mode, and generate the first composite data reading result Dout1.
[0009] The second current comparison module is used to compare the current Icell output by the dual split-gate memory cell with the reference current Iref1 and the reference current Iref_com in the composite data read mode, and generate the second composite data read result Dout2.
[0010] The logic operation module is used to perform an XOR logic operation on the first composite data reading result Dout1 and the second composite data reading result Dout2 to obtain the mixed composite data reading result Dout_mix;
[0011] The data output selection module is used to output the normal data reading result Dout0 in normal data reading mode and the mixed composite data reading result Dout_mix in composite data reading mode.
[0012] The read operation control module is electrically connected to the input terminal of the second current comparison module and the data output selection module, respectively. The output terminal of the first current comparison module is electrically connected to the input terminal of the logic operation module and the input terminal of the data output selection module, respectively. The output terminal of the second current comparison module is electrically connected to the input terminal of the logic operation module, and the output terminal of the logic operation module is electrically connected to the input terminal of the data output selection module.
[0013] In some embodiments, this application provides a flash memory data reading method, including:
[0014] Based on the read mode selection signal read_c, the normal data read mode and the composite data read mode are executed respectively;
[0015] In the normal data reading mode, the first normal data reading result Dout01 of the first storage unit bit1 of the dual split-gate memory cell and the second normal data reading result Dout02 of the second storage unit bit2 of the dual split-gate memory cell are obtained respectively.
[0016] In composite data read mode, obtain the mixed composite data read result Dout_mix of the first storage cell bit1 and the second storage cell bit2 of the dual split gate memory cell;
[0017] The first regular data read result Dout01, the second regular data read result Dout02, and the mixed composite data read result Dout_mix are combined to generate the final data read result.
[0018] In some embodiments, this application provides a flash memory data reading device, including a processor and a memory storing program instructions, wherein the processor is configured to execute the flash memory data reading method as described in this application when running the program instructions.
[0019] In some embodiments, this application provides an SPI NOR Flash chip, including the flash data read architecture as described in this application.
[0020] In some embodiments, this application provides a storage medium storing program instructions that, when executed, perform the flash memory data reading method as described in this application.
[0021] The flash memory data reading architecture, method, apparatus, chip, and storage medium provided in this disclosure can achieve the following technical effects:
[0022] This application incorporates a data reading mode selection, allowing users to choose between a conventional data reading mode and / or a composite data reading mode based on their data representation needs. The conventional data reading mode can read data from a single storage cell in a dual-separated gate memory cell, while the composite data reading mode can read data from the combined storage state of two storage cells in a dual-separated gate memory cell and has certain data processing capabilities. Thus, when limited by storage space, the distribution of stored data can be optimized to represent more data with limited storage bits.
[0023] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description
[0024] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein:
[0025] Figure 1 This is a schematic diagram of the structure of a dual-separated gate memory cell in related technologies;
[0026] Figure 2 This is a schematic diagram of a flash memory data reading architecture in related technologies;
[0027] Figure 3 This is a schematic diagram of a flash memory data reading architecture provided in an embodiment of this disclosure;
[0028] Figure 4 This is a schematic diagram of current distribution under conventional data reading mode provided in the embodiments of this disclosure;
[0029] Figure 5This is a schematic diagram of the current distribution under the composite data reading mode provided in the embodiments of this disclosure;
[0030] Figure 6 This is a specific application illustration provided by an embodiment of the present disclosure;
[0031] Figure 7 This is a schematic diagram of a flash memory data reading method provided in an embodiment of this disclosure;
[0032] Figure 8 This is a schematic diagram of another flash memory data reading method provided in an embodiment of this disclosure;
[0033] Figure 9 This is a schematic diagram of another flash memory data reading method provided in an embodiment of this disclosure;
[0034] Figure 10 This is a schematic diagram of a flash memory data reading device provided in an embodiment of this disclosure. Detailed Implementation
[0035] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.
[0036] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.
[0037] Unless otherwise stated, the term "multiple" means two or more.
[0038] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.
[0039] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.
[0040] The term "correspondence" can refer to an association or binding relationship. The correspondence between A and B means that there is an association or binding relationship between A and B.
[0041] Combination Figure 1 As shown, a dual-separated gate memory cell in the related technology includes two memory cells (memory bits), namely bit1 and bit2, which can store 2 bits of data.
[0042] Combination Figure 2 As shown, in a data reading architecture of a dual-separated-gate memory cell in related technologies, a dual-separated-gate memory cell is divided into four states according to the different data stored in bit1 and bit2, namely:
[0043] State 1: Both bit1 and bit2 store 0 data, i.e., bit1, bit2 = 0, 0.
[0044] State 2: bit1 stores data as 1, bit2 stores data as 0, that is, bit1, bit2 = 1, 0.
[0045] State 3: bit1 stores data 0, bit2 stores data 1, that is, bit1, bit2 = 0, 1.
[0046] State 4: Both bit1 and bit2 store data of 1, that is, bit1, bit2 = 1, 1.
[0047] By controlling the currents in states one and three to be less than the reference current iref_nor, states one and three are identified as data 0. By controlling the currents in states two and four to be greater than the reference current iref_nor, states two and four are identified as data 1.
[0048] It is evident that the existing data reading architecture can only represent 2 bits of data, namely bit1 storage bit and bit2 storage bit. If more data is to be represented, the number of dual-separated gate memory cells must be increased. However, it is usually difficult to change the firmware of flash memory products after the system products have been manufactured, especially system-in-package products. When encountering such a bottleneck, the upgrade content can only be reduced and some upgrade functions can be abandoned.
[0049] Therefore, in combination Figure 3 As shown, this disclosure provides a flash memory data reading architecture, including:
[0050] The read operation control module is used to generate the read mode selection signal read_c. When the read_c signal is high, the system enters the normal data read mode, and when the read_c signal is low, the system enters the composite data read mode.
[0051] The first current comparison module is used to compare the current Icell output by the dual split-gate memory cell with the reference current Iref0 in the normal data read mode, and generate the normal data read result Dout0. The first current comparison module is also used to compare the current Icell output by the dual split-gate memory cell with the reference current Iref1 in the composite data read mode, and generate the first composite data read result Dout1.
[0052] The second current comparison module is used to compare the current Icell output by the dual split-gate memory cell with the reference current Iref1 and the reference current Iref_com in the composite data read mode, and generate the second composite data read result Dout2.
[0053] The logic operation module is used to perform an XOR logic operation on the first composite data reading result Dout1 and the second composite data reading result Dout2 to obtain the mixed composite data reading result Dout_mix.
[0054] The data output selection module is used to output the normal data reading result Dout0 in normal data reading mode and the mixed composite data reading result Dout_mix in composite data reading mode.
[0055] The read operation control module is electrically connected to the input terminal of the second current comparison module and the data output selection module, respectively. The output terminal of the first current comparison module is electrically connected to the input terminal of the logic operation module and the input terminal of the data output selection module, respectively. The output terminal of the second current comparison module is electrically connected to the input terminal of the logic operation module, and the output terminal of the logic operation module is electrically connected to the input terminal of the data output selection module.
[0056] The flash memory data reading architecture provided in this disclosure allows users to select a conventional data reading mode and / or a composite data reading mode according to the data representation requirements. The conventional data reading mode can read the data of a single storage cell in a dual-split-gate memory cell, while the composite data reading mode can read the data of two storage cells in a dual-split-gate memory cell in a combined storage state and has certain data processing functions. Thus, when limited by storage space, the distribution of stored data can be optimized to represent more data with limited storage bits.
[0057] Furthermore, it should be noted that in order to represent more data, this invention adds some control modules, although these new control modules account for a very small proportion of the memory product. In a memory chip, 80% of the area is the memory cell array. Intuitively, using the read architecture of this invention, it is theoretically possible to achieve data representation equivalent to 120% of the original memory cell array area.
[0058] In the embodiments of this application, combined with Figure 3 As shown, the flash memory data reading architecture further includes:
[0059] Read the voltage generation module, which is used to generate voltages Vr1, Vr2, Vr3 and Vr3.
[0060] The first read voltage selection module is used to set the read control voltage Vc1 of the first storage cell bit1 in the dual split-gate memory cell to voltage Vr1 in the normal data read mode, and to set the read control voltage Vc1 of the first storage cell bit1 in the dual split-gate memory cell to voltage Vr2 in the composite data read mode.
[0061] The second read voltage selection module is used to set the read control voltage Vc2 of the second memory cell bit2 in the dual split-gate memory cell to voltage Vr3 in the normal data read mode, and to set the read control voltage Vc2 of the second memory cell bit2 in the dual split-gate memory cell to voltage Vr4 in the composite data read mode.
[0062] The reference current generation module is used to generate reference currents Iref0, Iref1, and Iref_com.
[0063] The reference current selection module is used to set the reference current Iref_nor of the first current comparison module to the reference current Iref0 in the normal data reading mode, and to set the reference current Iref_nor of the first current comparison module and the second current comparison module to the reference current Iref1 in the composite data reading mode.
[0064] The read voltage generation module is electrically connected to the input terminals of the first read voltage selection module and the second read voltage selection module, respectively. The output terminal of the first read voltage selection module is electrically connected to the first storage cell bit1 in the dual split-gate memory cell. The output terminal of the second read voltage selection module is electrically connected to the second storage cell bit2 in the dual split-gate memory cell. The output terminal of the reference current generation module is electrically connected to the input terminals of the reference current selection module and the second current comparison module, respectively. The output terminal of the reference current selection module is electrically connected to the input terminal of the first current comparison module.
[0065] In the embodiments of this application, combined with Figure 3 As shown, the read operation control module generates a read mode selection signal read_c. If the read_c signal is high ("1"), it enters the normal data read mode and reads the data of the first storage cell bit1 or the second storage cell bit2 in the dual split-gate memory cell. If the read_c signal is low ("0"), it enters the composite data read mode and reads the total data composed of the first storage cell bit1 and the second storage cell bit2 in the dual split-gate memory cell, i.e., composite data. Furthermore, normal data read and composite data read are two independent read modes.
[0066] If the read operation control module selects to enter the normal data read mode, the read control voltage Vc1 of the first memory cell bit1 in the dual split-gate memory cell is voltage Vr1, and the read control voltage Vc2 of the second memory cell bit2 is voltage Vr3, as shown in Table 1 below:
[0067] Table 1 Reading Voltage Control Selection
[0068]
[0069] At this time, the current in the dual-gate memory cell is as follows: Figure 4 Distribution, combination Figure 4 As shown, the reference current Iref_nor of the first current comparison module is the reference current Iref0. Meanwhile, in normal data reading mode, the read_c signal controls the second current comparison module to be inactive. Simultaneously, the data output selection module MUX selects the data reading result from the first current comparison module as the normal data reading result Dout0.
[0070] If the read operation control module selects to enter the composite data read mode, the read control voltage Vc1 of bit1 in the first memory cell of the dual split-gate memory cell is voltage Vr2, as shown in Table 1 above. At this time, the first current comparison module and the second current comparison module are simultaneously operating. The reference current Iref_nor of the first current comparison module is reference current Iref1, and the reference current Iref_nor of the second current comparison module is also reference current Iref1. The current in the dual split-gate memory cell is then as follows: Figure 5 Distribution, combination Figure 5 As shown, the first composite data read result Dout1 from the first current comparison module and the second composite data read result Dout2 from the second current comparison module are XORed to obtain the mixed composite data read result Dout_mix. Furthermore, the data output selection module MUX selects "mixed composite data read result Dout_mix" as the final data output, as shown in Table 2 below:
[0071] Table 2 Reference Current Selection for Conventional Current Comparison Module
[0072]
[0073] In this way, data can be represented through two data modes, and when limited by storage space, more data can be represented with limited storage space by optimizing the distribution of stored data.
[0074] In the embodiments of this application, as shown in Table 3, in the composite data reading mode, when the data stored in the first storage cell bit1 and the second storage cell bit2 in the dual split-gate storage cell are both 0, the current Icell output by the dual split-gate storage cell is simultaneously less than the reference current Iref1 and the reference current Iref_com. Then, the first composite data reading result Dout1 is 0, the second composite data reading result Dout2 is 0, and the mixed composite data reading result Dout_mix is 0.
[0075] Meanwhile, in composite data reading mode, if the data stored in the first storage unit bit1 of the dual split-gate storage unit is 0 and the data stored in the second storage unit bit2 is 1, or if the data stored in the first storage unit bit1 is 1 and the data stored in the second storage unit bit2 is 0, and the current Icell output by the dual split-gate storage unit is greater than the reference current Iref_com and less than the reference current Iref1, then the first composite data reading result Dout1 is 0, the second composite data reading result Dout2 is 1, and the mixed composite data reading result Dout_mix is 1.
[0076] Meanwhile, in composite data reading mode, when the data stored in the first storage unit bit1 and the second storage unit bit2 in the dual split-gate storage unit are both 1, the current Icell output by the dual split-gate storage unit is greater than both the reference current Iref1 and the reference current Iref_com. Then, the first composite data reading result Dout1 is 1, the second composite data reading result Dout2 is 1, and the mixed composite data reading result Dout_mix is 1.
[0077] In the embodiments of this application, in the data reading mode, only two current distribution intervals are generated: one is a very small current interval (representing data 0), and the other is a very large current interval (representing data 1). In the composite data reading mode, three current distribution intervals can be generated: one very small current interval, one current interval with an intermediate value, and a last very large current interval.
[0078] This allows for a better reflection of the complexity and diversity of the data.
[0079] Table 3 Truth Table for Composite Current Reading Mode Data Output
[0080]
[0081] In practical applications, combined with Figure 6 As shown, the flash memory data reading architecture includes four sets of dual-separated gate memory cells, totaling eight data storage bits. When the data stored in the four sets of dual-separated gate memory cells are (0,0), (1,0), (0,1) and (1,1) respectively, the normal data reading result Dout0 is 0101_0011, the mixed composite data reading result Dout_mix is 0011, and the final combined data reading result Dout_final is 0101_0011-0110.
[0082] In this way, by combining the results of conventional data reading with the results of mixed composite data reading, this application can represent a total of 12 bits of data. This increases the amount of data representation by 50% compared to traditional reading schemes, thereby greatly expanding the amount of data representation within limited storage space.
[0083] Combination Figure 7 As shown, this disclosure provides a flash memory data reading method, including:
[0084] Step 701: Select the read_c signal according to the read mode and execute the normal data read mode and the composite data read mode respectively.
[0085] Step 702: In the normal data reading mode, obtain the first normal data reading result Dout01 of the first storage cell bit1 of the dual split-gate memory cell and the second normal data reading result Dout02 of the second storage cell bit2 of the dual split-gate memory cell.
[0086] Step 703: In composite data read mode, obtain the composite data read result Dout_mix of the first storage cell bit1 and the second storage cell bit2 of the dual split gate memory cell.
[0087] Step 704: Combine the first regular data reading result Dout01, the second regular data reading result Dout02, and the mixed composite data reading result Dout_mix to generate the final data reading result.
[0088] In the embodiments of this application, the Nord flash memory product has two data reading modes: a conventional data reading mode, which reads data from two storage bits in a Nord cell separately, and a composite data reading mode, which reads composite data from two storage bits in a Nord cell. Specifically, the conventional data reading mode reads data from two storage bits in a Nord cell, resulting in a first data reading result and a second data reading result; the composite data reading mode reads composite data from two storage bits in a Nord cell, resulting in a mixed composite data reading result. The first and second data reading results from the conventional data reading mode, combined with the mixed composite data reading result from the composite data reading mode, constitute the final data reading result, which is equivalent to three data representations.
[0089] The flash memory data reading method provided in this disclosure adds a data reading mode selection, allowing users to choose a conventional data reading mode and / or a composite data reading mode according to the data representation requirements. The conventional data reading mode can read the data of a single storage cell in a dual-split-gate memory cell, while the composite data reading mode can read the data of the combined storage state of two storage cells in a dual-split-gate memory cell and has certain data operation functions. Thus, when limited by storage space, the distribution of stored data can be optimized to represent more data with limited storage bits.
[0090] In the embodiments of this application, combined with Figure 8 As shown, the step of obtaining the first normal data read result Dout01 of the first storage cell bit1 of the dual split-gate memory cell and the second normal data read result Dout02 of the second storage cell bit2 of the dual split-gate memory cell includes:
[0091] Step 801: Generate the reference current Iref0.
[0092] Step 802: Compare the current Icell output by the dual split-gate memory cell with the reference current Iref0 to generate the first normal data read result Dout01 and the second normal data read result Dout02 respectively.
[0093] In the embodiments of this application, combined with Figure 9 As shown, the process of obtaining the mixed composite data read result Dout_mix of the first storage cell bit1 and the second storage cell bit2 of the dual-separated gate memory cell includes:
[0094] Step 901: Generate the reference current Iref1 and the reference current Iref_com.
[0095] Step 902: Compare the current Icell output by the dual split-gate memory cell with the reference current Iref1 to generate the first composite data read result Dout1.
[0096] Step 903: Compare the current Icell output by the dual-separated gate memory cell with the reference current Iref1 and the reference current Iref_com to generate the second composite data read result Dout2.
[0097] Step 904: Perform an XOR operation on the first composite data reading result Dout1 and the second composite data reading result Dout2 to obtain the mixed composite data reading result Dout_mix.
[0098] The flash memory data reading method provided in this disclosure adds a composite data reading mode unique to dual-split-gate flash memory products to the conventional data reading mode, resulting in corresponding hybrid composite data reading results. This achieves the goal of representing more data using existing storage space, making system product development more flexible and significantly reducing system product costs. For example, a 2Mbits (2048bits) dual-split-gate flash memory product can add an additional 1024 bits of data representation using the composite data reading mode.
[0099] Combination Figure 10As shown, this disclosure provides a flash memory data reading device, including a processor 100 and a memory 101. Optionally, the device may further include a communication interface 102 and a bus 103. The processor 100, communication interface 102, and memory 101 can communicate with each other via the bus 103. The communication interface 102 can be used for information transmission. The processor 100 can invoke logical instructions in the memory 101 to execute the flash memory data reading method of the above embodiment.
[0100] Furthermore, the logic instructions in the aforementioned memory 101 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.
[0101] The memory 101, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of this disclosure. The processor 100 executes functional applications and data processing by running the program instructions / modules stored in the memory 101, that is, it implements the flash memory data reading method in the above embodiments.
[0102] The memory 101 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 101 may include high-speed random access memory and may also include non-volatile memory.
[0103] The flash memory data reading device provided in this application adds a composite data reading mode to the conventional data reading mode. The conventional data reading mode reads data from two storage bits in the Nord cell separately, achieving 2-bit data representation; the composite data reading mode reads composite data determined by the two storage bits in the Nord cell, achieving an additional 1-bit data representation. The final read data consists of both conventional and composite data, ultimately increasing the amount of representation data.
[0104] This disclosure provides an SPI NOR Flash chip, including the flash data readout architecture as described in this application.
[0105] In the embodiments of this application, the SPI NOR Flash chip utilizes a data readout architecture composed of a data readout control module, a readout voltage generation module, a readout voltage selection module, a reference current generation module, a reference current selection module, a conventional current comparison module, and a composite current comparison module to achieve the goal of representing more data with limited storage units. Simultaneously, the composite current readout mode allows for the simultaneous implementation of certain logical operations during data readout.
[0106] The SPI NOR Flash chip implemented in this application, through an architecture of conventional data reading mode and composite data reading mode, can increase the number of data representations without increasing the size of the flash memory array. At the same time, the composite data reading mode of the SPI NOR Flash chip in this application can realize data reading and data operation output simultaneously.
[0107] This disclosure provides a storage medium storing computer-executable instructions configured to execute the flash memory data reading method described in this application.
[0108] The aforementioned storage medium can be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.
[0109] The technical solutions of this disclosure can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes one or more instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in this disclosure. The aforementioned storage medium can be a non-transitory storage medium, including: a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and other media capable of storing program code; it can also be a transient storage medium.
[0110] The foregoing description and accompanying drawings fully illustrate embodiments of this disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terminology used in this application is for describing embodiments only and is not intended to limit the claims. As used in the description of embodiments and claims, the singular forms “a,” “an,” and “the” are intended to equally include the plural forms unless the context clearly indicates otherwise. Similarly, the term “and / or” as used in this application means including one or more of the associated listed items and all possible combinations thereof. Additionally, when used in this application, the term "comprise" and its variations "comprises" and / or "comprising" refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Without further limitations, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes said element. In this document, each embodiment may focus on the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, the relevant parts can be referred to the description of the method section.
[0111] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this disclosure. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.
[0112] The methods and products disclosed in the embodiments herein (including but not limited to devices and equipment) can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units may be merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to implement this embodiment according to actual needs. In addition, the functional units in the embodiments of this disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
[0113] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than that shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different blocks may also occur in a different order than disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. Each block in a block diagram and / or flowchart, and combinations of blocks in a block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.
Claims
1. A flash memory data reading architecture, characterized in that, include: The read operation control module is used to generate the read mode selection signal read_c. When the read_c signal is high, it enters the normal data read mode, and when the read_c signal is low, it enters the composite data read mode. The first current comparison module is used to compare the current Icell output by the dual split-gate memory cell with the reference current Iref1 in the composite data reading mode, and generate the first composite data reading result Dout1. The second current comparison module is used to compare the current Icell output by the dual split-gate memory cell with the reference current Iref1 and the reference current Iref_com in the composite data reading mode, and generate the second composite data reading result Dout2. The logic operation module is used to perform an XOR logic operation on the first composite data reading result Dout1 and the second composite data reading result Dout2 to obtain the mixed composite data reading result Dout_mix; The data output selection module is used to output the normal data reading result Dout0 in normal data reading mode and the mixed composite data reading result Dout_mix in composite data reading mode. The read operation control module is electrically connected to the input terminal of the second current comparison module and the data output selection module, respectively. The output terminal of the first current comparison module is electrically connected to the input terminal of the logic operation module and the input terminal of the data output selection module, respectively. The output terminal of the second current comparison module is electrically connected to the input terminal of the logic operation module, and the output terminal of the logic operation module is electrically connected to the input terminal of the data output selection module.
2. The flash memory data reading architecture according to claim 1, characterized in that, The first current comparison module is used to compare the current Icell output by the dual split-gate memory cell with the reference current Iref0 in the normal data reading mode, and generate the normal data reading result Dout0.
3. The flash memory data reading architecture according to claim 1, characterized in that, In composite data read mode, when the data stored in the first storage cell bit1 and the second storage cell bit2 in the dual split-gate storage cell are both 0, the current Icell output by the dual split-gate storage cell is simultaneously less than the reference current Iref1 and the reference current Iref_com. Then, the first composite data read result Dout1 is 0, the second composite data read result Dout2 is 0, and the mixed composite data read result Dout_mix is 0.
4. The flash memory data reading architecture according to claim 1, characterized in that, In composite data read mode, if the data stored in the first storage cell bit1 of the dual split-gate storage cell is 0 and the data stored in the second storage cell bit2 is 1, or if the data stored in the first storage cell bit1 is 1 and the data stored in the second storage cell bit2 is 0, and the current Icell output by the dual split-gate storage cell is greater than the reference current Iref_com and less than the reference current Iref1, then the first composite data read result Dout1 is 0, the second composite data read result Dout2 is 1, and the mixed composite data read result Dout_mix is 1.
5. The flash memory data reading architecture according to claim 1, characterized in that, In composite data read mode, when the data stored in the first storage cell bit1 and the second storage cell bit2 in the dual split-gate storage cell are both 1, the current Icell output by the dual split-gate storage cell is greater than the reference current Iref1 and the reference current Iref_com at the same time. Then, the first composite data read result Dout1 is 1, the second composite data read result Dout2 is 1, and the mixed composite data read result Dout_mix is 1.
6. The flash memory data read architecture according to any one of claims 1 to 5, characterized in that, Also includes: Read the voltage generation module, which is used to generate voltages Vr1, Vr2, Vr3, and Vr4; The first read voltage selection module is used to set the read control voltage Vc1 of the first storage cell bit1 in the dual split-gate memory cell to voltage Vr1 in the normal data read mode, and to set the read control voltage Vc1 of the first storage cell bit1 in the dual split-gate memory cell to voltage Vr2 in the composite data read mode. The second read voltage selection module is used to set the read control voltage Vc2 of the second memory cell bit2 in the dual split-gate memory cell to voltage Vr3 in the normal data read mode, and to set the read control voltage Vc2 of the second memory cell bit2 in the dual split-gate memory cell to voltage Vr4 in the composite data read mode. The read voltage generation module is electrically connected to the input terminals of the first read voltage selection module and the second read voltage selection module, respectively. The output terminal of the first read voltage selection module is electrically connected to the first storage cell bit1 in the dual split-gate memory cell, and the output terminal of the second read voltage selection module is electrically connected to the second storage cell bit2 in the dual split-gate memory cell.
7. The flash memory data read architecture according to any one of claims 1 to 5, characterized in that, Also includes: The reference current generation module is used to generate reference currents Iref0, Iref1, and Iref_com; The reference current selection module is used to set the reference current Iref_nor of the first current comparison module to the reference current Iref0 in the normal data reading mode, and to set the reference current Iref_nor of the first current comparison module and the second current comparison module to the reference current Iref1 in the composite data reading mode. The output terminal of the reference current generation module is electrically connected to the input terminal of the reference current selection module and the input terminal of the second current comparison module, respectively, and the output terminal of the reference current selection module is electrically connected to the input terminal of the first current comparison module.
8. The flash memory data read architecture according to any one of claims 1 to 5, characterized in that, It includes four sets of dual-separated gate storage cells: Nord cell0, Nord cell1, Nord cell2, and Nord cell3, totaling eight data storage bits. When the data stored in the four sets of dual-separated gate storage cells are (0,0), (1,0), (0,1), and (1,1), respectively, the normal data read result Dout0 is 0101_0011, the mixed composite data read result Dout_mix is 0011, and the final combined data read result Dout_final is 0101_0011-0110.
9. A flash memory data reading method, characterized in that, include: Based on the read mode selection signal read_c, the normal data read mode and the composite data read mode are executed respectively; In the normal data reading mode, the first normal data reading result Dout01 of the first storage unit bit1 of the dual split-gate memory cell and the second normal data reading result Dout02 of the second storage unit bit2 of the dual split-gate memory cell are obtained respectively. In composite data read mode, obtain the mixed composite data read result Dout_mix of the first storage cell bit1 and the second storage cell bit2 of the dual split gate memory cell; The first regular data read result Dout01, the second regular data read result Dout02, and the mixed composite data read result Dout_mix are combined to generate the final data read result.
10. The flash memory data reading method according to claim 9, characterized in that, The step of obtaining the first normal data read result Dout01 of the first storage cell bit1 of the dual split-gate memory cell and the second normal data read result Dout02 of the second storage cell bit2 of the dual split-gate memory cell includes: Generate a reference current Iref0; The current Icell output by the dual-separated gate memory cell is compared with the reference current Iref0 to generate the first normal data read result Dout01 and the second normal data read result Dout02 respectively.
11. The flash memory data reading method according to claim 9, characterized in that, The process of obtaining the mixed composite data read result Dout_mix of the first storage cell bit1 and the second storage cell bit2 of the dual-separated gate memory cell includes: Generate the reference current Iref1 and the reference current Iref_com; The current Icell output by the dual-separated gate memory cell is compared with the reference current Iref1 to generate the first composite data read result Dout1; The current Icell output by the dual-separated gate memory cell is compared with the reference current Iref1 and the reference current Iref_com to generate the second composite data read result Dout2; Perform an XOR operation on the first composite data read result Dout1 and the second composite data read result Dout2 to obtain the mixed composite data read result Dout_mix.
12. A flash memory data reading device, comprising a processor and a memory storing program instructions, characterized in that, The processor is configured to execute the flash memory data reading method as described in any one of claims 9 to 11 when running the program instructions.
13. An SPI NOR Flash chip, characterized in that, Includes the flash data read architecture as described in any one of claims 1 to 8.
14. A storage medium storing program instructions, characterized in that, When the program instructions are executed, they perform the flash memory data reading method as described in any one of claims 9 to 11.
Citation Information
Patent Citations
Reading method and device of memory unit
CN108109660A
Sensitive amplifier circuit and memory
CN113555042A