Memory device and operating method thereof, memory system

Abstract

The embodiment of the present disclosure provides a memory device, including a memory array, a peripheral circuit coupled with the memory array; the memory array includes a plurality of memory pieces coupled with an Nth word line, each memory piece includes a plurality of memory cells; the peripheral circuit is configured to: apply a first programming start voltage to the memory cells of at least one first memory piece coupled with the Nth word line, and perform a first programming operation; during the first programming operation, perform a programming operation with a target state being a first state on the basis of gradually increasing a step voltage from the first programming start voltage; obtain a number P of memory cells whose threshold voltage exceeds an upper limit of a threshold voltage of the first state; when P is greater than a first preset value for the first time, obtain a number M of the increased step voltage; N, P and M are all positive integers; determine a second programming start voltage according to P and M; and apply the second programming start voltage to the memory cells of the memory pieces coupled with the Nth word line except the first memory piece, and perform a second programming operation.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a memory device and its operation method, and a memory system. Background Technology

[0002] Memory is a storage device used to store information in modern information technology. As a typical non-volatile semiconductor memory, NAND (Not-And) flash memory has become the mainstream product in the memory market due to its high storage density, controllable production cost, suitable erasure speed, and retention characteristics.

[0003] With the increasing demands on memory, reducing programming time and improving programming efficiency has become one of the most pressing technical problems to be solved in this field. Summary of the Invention

[0004] This disclosure provides a memory device, its operation method, and a memory system.

[0005] In a first aspect, embodiments of this disclosure provide a memory device, the memory device including a memory array and peripheral circuitry coupled to the memory array;

[0006] The memory array includes multiple memory chips coupled to the Nth word line, and each memory chip includes multiple memory cells;

[0007] The peripheral circuit is configured as follows:

[0008] A first programming start voltage is applied to the memory cell of at least one first memory chip coupled to the Nth word line to perform a first programming operation; wherein, during the first programming operation, a programming operation with the target state as the first state is performed by successively increasing the first programming start voltage by one step voltage.

[0009] Obtain the number P of memory cells whose threshold voltage exceeds the upper limit of the first-state threshold voltage;

[0010] When P first exceeds a first preset value, the number M of the increased step voltages is obtained; N, P, and M are all positive integers.

[0011] The second programming start voltage is determined based on P and M;

[0012] A second programming start voltage is applied to the memory cells of the memory chips other than the first memory chip that are coupled to the Nth word line, and a second programming operation is performed.

[0013] In the above scheme, the peripheral circuit is configured as follows:

[0014] A first compensation value is determined based on the interval to which P belongs; the larger the value of the interval to which P belongs, the smaller the first compensation value, and the first compensation value is a negative voltage; the larger the average number of memory cells in the interval, the larger the value of the interval.

[0015] The sum of the first programming start voltage, M times the step voltage, and the first compensation value is used as the second programming start voltage.

[0016] In the above scheme, the peripheral circuit is configured as follows:

[0017] Based on the interval to which P belongs, and in conjunction with the first mapping table, the first compensation value is determined; the first mapping table stores the correspondence between different intervals of P and different first compensation values.

[0018] In the above scheme, the storage bits of the storage unit include multiple bits; the first state is the programming state in which the threshold voltage distribution is closest to the threshold voltage distribution of the erase state.

[0019] In the above scheme, the peripheral circuit is configured as follows:

[0020] After programming to the first state by successively increasing the voltage step by step based on the first programming start voltage, a programming verification voltage is applied to the memory cells of at least one first memory chip coupled to the Nth word line to obtain the number P of memory cells whose threshold voltage exceeds the upper limit of the first state threshold voltage.

[0021] In the above scheme, the peripheral circuit is configured as follows:

[0022] When P is less than a first preset value, the programming operation of the first state is continued by increasing the voltage step by step until P is greater than the first preset value for the first time.

[0023] In the above scheme, the peripheral circuit is configured as follows:

[0024] After applying a second programming start voltage to the memory cells of the memory chips other than the first memory chips coupled to the Nth word line, a third programming start voltage is applied to the memory cells of at least one first memory chip coupled to the N+1th word line to perform a third programming operation; wherein, during the third programming operation, a programming operation with the target state as the first state is performed by successively increasing a step voltage based on the third programming start voltage.

[0025] Obtain the number Q of memory cells whose threshold voltage exceeds the upper limit of the first state threshold voltage;

[0026] When Q is greater than the first preset value for the first time, the number of additional step voltages S is obtained; Q and S are both positive integers.

[0027] The fourth programming start voltage is determined based on S and Q;

[0028] A fourth programming start voltage is applied to the memory cells of the memory chips other than the first memory chip that are coupled to the N+1th word line, and a fourth programming operation is performed.

[0029] In the above scheme, the peripheral circuit is configured as follows:

[0030] During the first programming operation, after completing the programming operation with the target state of the first state for the memory cell of at least one first memory chip coupled to the Nth word line, the programming operation with the target state of other states begins for the memory cell of at least one first memory chip coupled to the Nth word line.

[0031] During the second programming operation, after applying a second programming start voltage to the memory cells of the memory chips (excluding the first memory chip) coupled to the Nth word line to complete the programming operation with the target state as the first state, programming operations with the target state as other states are started on the memory cells of the memory chips (excluding the first memory chip) coupled to the Nth word line.

[0032] In the above scheme, the memory device includes a three-dimensional NAND type memory.

[0033] In a second aspect, embodiments of this disclosure provide a memory system, including:

[0034] One or more memory devices as described in any of the above embodiments; and

[0035] A memory controller, which is coupled to and controls the memory device.

[0036] Thirdly, embodiments of this disclosure provide a method for operating a memory device, including:

[0037] A first programming start voltage is applied to the memory cell of at least one first memory chip coupled to the Nth word line to perform a first programming operation; wherein, during the first programming operation, a programming operation with the target state as the first state is performed by successively increasing the first programming start voltage by one step voltage.

[0038] Obtain the number P of memory cells whose threshold voltage exceeds the upper limit of the first-state threshold voltage;

[0039] When P first exceeds a first preset value, the number M of the increased step voltages is obtained; N, P, and M are all positive integers.

[0040] The second programming start voltage is determined based on P and M;

[0041] A second programming start voltage is applied to the memory cells of the memory chips other than the first memory chip that are coupled to the Nth word line, and a second programming operation is performed.

[0042] In the above scheme, determining the second programming start voltage based on P and M includes:

[0043] A first compensation value is determined based on the interval to which P belongs; the larger the value of the interval to which P belongs, the smaller the first compensation value, and the first compensation value is a negative voltage; the larger the average number of memory cells in the interval, the larger the value of the interval.

[0044] The sum of the first programming start voltage, M times the step voltage, and the first compensation value is used as the second programming start voltage.

[0045] In the above scheme, determining the first compensation value based on the interval to which P belongs includes:

[0046] Based on the interval to which P belongs, and in conjunction with the first mapping table, the first compensation value is determined; the first mapping table stores the correspondence between different intervals of P and different first compensation values.

[0047] In the above scheme, the storage bits of the storage unit include multiple bits; the first state is the programming state in which the threshold voltage distribution is closest to the threshold voltage distribution of the erase state.

[0048] In the above scheme, obtaining the number P of memory cells whose threshold voltage exceeds the upper limit of the first-state threshold voltage includes:

[0049] After programming to the first state by successively increasing the voltage step by step based on the first programming start voltage, a programming verification voltage is applied to the memory cells of at least one first memory chip coupled to the Nth word line to obtain the number P of memory cells whose threshold voltage exceeds the upper limit of the first state threshold voltage.

[0050] The method in the above scheme further includes:

[0051] When P is less than a first preset value, the programming operation of the first state is continued by increasing the voltage step by step until P is greater than the first preset value for the first time.

[0052] The method in the above scheme further includes:

[0053] After applying a second programming start voltage to the memory cells of the memory chips other than the first memory chips coupled to the Nth word line, a third programming start voltage is applied to the memory cells of at least one first memory chip coupled to the N+1th word line to perform a third programming operation; wherein, during the third programming operation, a programming operation with the target state as the first state is performed by successively increasing a step voltage based on the third programming start voltage.

[0054] Obtain the number Q of memory cells whose threshold voltage exceeds the upper limit of the first state threshold voltage;

[0055] When Q is greater than the first preset value for the first time, the number of additional step voltages S is obtained; Q and S are both positive integers.

[0056] The fourth programming start voltage is determined based on S and Q;

[0057] A fourth programming start voltage is applied to the memory cells of the memory chips other than the first memory chip that are coupled to the N+1th word line to perform a fourth programming operation.

[0058] The method in the above scheme further includes:

[0059] During the first programming operation, after completing the programming operation with the target state of the first state for the memory cell of at least one first memory chip coupled to the Nth word line, the programming operation with the target state of other states begins for the memory cell of at least one first memory chip coupled to the Nth word line.

[0060] During the second programming operation, after applying a second programming start voltage to the memory cells of the memory chips (excluding the first memory chip) coupled to the Nth word line to complete the programming operation with the target state as the first state, a programming operation with the target state as another state is started on the memory cells of the memory chips (excluding the first memory chip) coupled to the Nth word line.

[0061] This disclosure provides a memory device and its operation method, a memory system, wherein the memory device includes a memory array and peripheral circuitry coupled to the memory array; the memory array includes a plurality of memory chips coupled to an Nth word line, each memory chip including a plurality of memory cells; the peripheral circuitry is configured to: apply a first programming start voltage to the memory cells of at least one first memory chip coupled to the Nth word line to perform a first programming operation; wherein, during the first programming operation, a programming operation with a target state of a first state is performed by successively increasing a step voltage based on the first programming start voltage; obtain the number P of memory cells whose threshold voltage exceeds the upper limit of the first state threshold voltage; when P first exceeds a first preset value, obtain the number M of the increased step voltages; wherein N, P, and M are all positive integers; determine a second programming start voltage based on P and M; and apply the second programming start voltage to the memory cells of memory chips other than the first memory chips coupled to the Nth word line to perform a second programming operation. In this embodiment of the disclosure, when performing a second programming operation on the memory cells of the memory chips other than the first memory chip coupled to the Nth word line, the second programming start voltage is dynamically adjusted according to P and M. That is, the value of the second programming start voltage is not a fixed value, but a value that is dynamically adjusted according to the programming verification result of the memory cells of at least one first memory chip coupled to the Nth word line. This enables each word line to be programmed to the target state at a faster speed, thereby improving the overall programming speed and thus improving programming efficiency. Attached Figure Description

[0062] Figure 1 This is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0063] Figure 2a This is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0064] Figure 2b This is a schematic diagram of an exemplary solid-state drive with a memory system according to an embodiment of the present disclosure;

[0065] Figure 3a This is a schematic diagram showing the distribution of storage cells in a three-dimensional NAND type memory according to an embodiment of the present disclosure;

[0066] Figure 3b This is a schematic diagram of an exemplary memory device including peripheral circuitry according to an embodiment of the present disclosure;

[0067] Figure 4 This is a schematic cross-sectional view of a memory array including NAND memory strings according to an embodiment of the present disclosure.

[0068] Figure 5This is a schematic diagram of an exemplary memory device including a memory array and peripheral circuitry according to an embodiment of the present disclosure;

[0069] Figure 6 A schematic diagram of the framework flow during programming operations according to an embodiment of this disclosure;

[0070] Figure 7 This is a schematic diagram illustrating the relationship between the number of memory cells and the threshold voltage during programming operations for two types of memory cells in one embodiment of this disclosure.

[0071] Figure 8 This is a schematic diagram of the word line voltage applied to the memory cell during programming operations using a step-pulse programming method according to an embodiment of the present disclosure;

[0072] Figure 9 This is a schematic diagram illustrating the correspondence between the interval and the first compensation value in one embodiment of this disclosure;

[0073] Figure 10 This is a schematic diagram of data storage in a three-level cell of a three-dimensional NAND type memory according to an embodiment of the present disclosure;

[0074] Figure 11 This is a schematic diagram illustrating the implementation flow of an operation method for a memory device according to an embodiment of the present disclosure;

[0075] Figure 12 A schematic diagram of the framework flow during programming operations for another embodiment of this disclosure. Detailed Implementation

[0076] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0077] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0078] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0079] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0080] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0081] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0082] To gain a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this disclosure.

[0083] The memory devices in the embodiments of this disclosure include, but are not limited to, three-dimensional NAND type memory. For ease of understanding, three-dimensional NAND type memory will be used as an example for explanation.

[0084] As the density requirements of 3D NAND flash memory continue to increase, the manufacturing process becomes more difficult. This results in differences in programming speed between memory cells coupled to different word lines, as well as differences in programming speed between memory cells of different blocks. Applying a fixed programming voltage to a single word line can lead to significant differences in programming time, affecting programming efficiency.

[0085] To address one or more of the aforementioned problems, embodiments of this disclosure introduce a solution in which the programming start voltage can be dynamically adjusted during programming operations on a memory cell coupled to a word line of a memory device to achieve an adaptive programming speed, thereby improving the overall programming speed and efficiency.

[0086] Figure 1 A block diagram of an exemplary system 100 having a memory device according to some aspects of this disclosure is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1 As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the memory device 104.

[0087] According to some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs), which are used as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays.

[0088] The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) relating to data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with external devices (e.g., host 108) according to specific communication protocols. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Devices (IDE) protocol, Firewire protocol, etc.

[0089] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2aIn one example shown, the memory controller 106 and a single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The memory card connector 204 is coupled to the host 108. In such a way... Figure 2b In another example shown, the memory controller 106 and multiple memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include components for connecting the SSD 206 to a host computer (e.g., Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0090] Figure 3a An exemplary schematic diagram of a three-dimensional NAND flash memory array is provided, such as... Figure 3a As shown, the memory array of a three-dimensional NAND flash memory consists of several rows of parallel, staggered rows of memory cells parallel to the gate isolation structure. Each two rows of memory cells are separated by a gate isolation structure and an up-select gate isolation structure. Each row of memory cells includes multiple memory cells. The gate isolation structure may include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure divides the memory array into multiple blocks. Multiple second gate isolation structures can divide the blocks into multiple finger regions. An up-select gate isolation structure located in the middle of each finger region can divide the finger region into two parts, thus dividing the finger region into two strings. Figure 3a The memory block shown contains 6 memory slices; however, in practical applications, the number of memory slices in a memory block is not limited to this. A memory cell within a memory slice coupled to a single word line can be called a memory page.

[0091] It should be noted that, Figure 3a The number of cell rows between the gate isolation structure and the top-select gate isolation structure given is merely an exemplary example and is not intended to limit the number of cell rows contained in a single memory region of the three-dimensional NAND memory in this disclosure. In practical applications, the number of cell rows contained in a single memory region can be adjusted according to actual conditions, such as 2, 4, 8, 16, etc.

[0092] Figure 3b A schematic circuit diagram of an exemplary memory device 300, including peripheral circuitry, is shown according to some aspects of this disclosure. The memory device 300 may be... Figure 1 An example of memory device 104 is provided. Memory device 300 may include memory array 301 and peripheral circuitry 302 coupled to memory array 301. Taking memory array 301 as an example of a three-dimensional NAND-type memory array, memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0093] In some implementations, each memory cell 306 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 306 is a multi-level cell capable of storing more than a single bit of data in more than two memory states. For example, an MLC may store two bits per cell (also known as a two-level cell), a TLC may store three bits per cell (also known as a three-level cell), and a QLC may store four bits per cell (also known as a four-level cell). Each multi-level cell can be programmed to take a range of possible nominal memory values. In one example, if each multi-level cell stores two bits of data, the multi-level cell can be programmed to take one of three possible programming levels from the erase state by writing one of the three possible nominal memory values ​​to the cell. A fourth nominal memory value may be used for the erase state.

[0094] like Figure 3bAs shown, each NAND memory string 308 may include a lower select gate (BSG) 310 at its source end and an upper select gate (TSG) 312 at its drain end. BSG 310 and TSG 312 may be configured to activate a selected NAND memory string 308 during read and program operations. In some embodiments, the sources of NAND memory strings 308 within the same memory block 304 are coupled via a common source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 308 within the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each NAND memory string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having TSG 312) or a deselection voltage (e.g., 0V) to the corresponding TSG 312 via one or more TSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having BSG 310) or a deselection voltage (e.g., 0V) to the corresponding BSG 310 via one or more BSG lines 315.

[0095] like Figure 3bAs shown, NAND memory strings 308 can be organized into multiple memory blocks 304, each of which may have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block 304a, an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)) can be used to bias and couple the source line 314 of the selected memory block 304a and the unselected memory block 304b on the same face as the selected memory block 304a. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent NAND memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some implementations, each word line 318 is coupled to a page 320 of memory cell 306, where page 320 is the basic data unit used for programming operations. The size of a page 320, in bits, can be related to the number of NAND memory strings 308 coupled by word lines 318 in a memory block 304. Each word line 318 may include multiple control gates (gate electrodes) at each memory cell 306 in the corresponding page 320, as well as gate lines coupling the control gates. (This is in conjunction with the preceding...) Figure 3a A page 320 contains multiple memory cells 306, which are separated by an up-select gate isolation structure and a gate isolation structure. The memory cells between the up-select gate isolation structure and the gate isolation structure are arranged into multiple memory cell rows, each of which is parallel to the gate isolation structure and the up-select gate isolation structure. The memory cells in the memory chip that share the same word line form a programmable (read / write) page.

[0096] Figure 4 A schematic cross-sectional view of an exemplary memory array 301 including NAND memory strings 308 is shown, according to some aspects of this disclosure. Figure 4 As shown, the NAND memory string 308 may include a stacked structure 410, which includes multiple gate layers 411 and multiple insulating layers 412 stacked alternately in sequence, and a memory string 308 perpendicularly penetrating the gate layers 411 and insulating layers 412. The gate layers 411 and insulating layers 412 may be stacked alternately, with adjacent gate layers 411 separated by an insulating layer 412. The number of pairs of gate layers 411 and insulating layers 412 in the stacked structure 410 determines the number of memory cells included in the memory array 301.

[0097] The constituent materials of the gate layer 411 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stack 410 may extend laterally as an upper select gate line, the gate layer 411 at the bottom of the stack 410 may extend laterally as a lower select gate line, and the gate layer 411 extending laterally between the upper and lower select gate lines may serve as a word line layer.

[0098] In some embodiments, the stacked structure 410 may be disposed on the substrate 401. The substrate 401 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0099] In some embodiments, the NAND memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes channel vias filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0100] Return to reference Figure 3bThe peripheral circuitry 302 can be coupled to the memory array 301 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory array 301 by applying voltage and / or current signals to each target memory cell 306 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313, and by sensing voltage and / or current signals from each target memory cell 306. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuitry is shown. Peripheral circuitry 302 includes a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic unit 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 5 Additional peripheral circuitry not shown.

[0101] Page buffer / sensor amplifier 504 can be configured to read data from memory array 301 and program (write) data to memory array 301 according to control signals from control logic unit 512. In one example, page buffer / sensor amplifier 504 can store a page of programming data (write data) to be programmed into a page 320 of memory array 301. In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 506 can be configured to be controlled by control logic unit 512 and select one or more NAND memory strings 308 by applying a bit line voltage generated from voltage generator 510.

[0102] The row decoder / word line driver 508 can be configured to be controlled by the control logic unit 512 and to select / deselect memory blocks 304 of the memory array 301 and to select / deselect word lines 318 of the memory blocks 304. The row decoder / word line driver 508 can also be configured to drive word lines 318 using word line voltages generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive BSG lines 315 and TSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform programming operations on memory cells 306 coupled to one or more selected word lines 318. The voltage generator 510 can be configured to be controlled by the control logic unit 512 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 301.

[0103] In some specific embodiments, the programming operation may include multiple steps. For example, the programming operation may include a bit line setting step, a programming execution step, and a programming recovery step. After the programming operation, a programming verification operation is also required; after the programming verification operation, a programming verification recovery operation is also required. During the bit line setting step of the programming operation, the voltage for unselected word lines can be maintained at ground (GND). During the programming execution step of the programming operation, a pass voltage (Vpass) can be applied to the unselected word lines, and a programming voltage (Vpgm) can be applied to the selected word lines. Therefore, the memory cells connected to the selected word lines can be programmed. During the programming recovery step of the programming operation, the voltage applied to all word lines can be reduced to ground (GND).

[0104] During the programming verification operation, a verification voltage Vvrf can be applied to the selected word line, and a read voltage Vread can be applied to the unselected word line.

[0105] During the execution of the programming verification recovery operation, a recovery operation that drops the voltage to ground (GND) can be performed on both unselected and selected word lines.

[0106] In other words, the programming execution step mainly involves applying a programming voltage to the word line coupled to the memory cell being programmed. The application of the programming voltage can be done by first applying a programming start voltage and then gradually increasing it by one step voltage. Furthermore, during the programming execution step, a disable voltage can be applied to the bit line coupled to the unselected memory cell.

[0107] Control logic unit 512 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 514 can be coupled to control logic unit 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic unit 512 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic unit 512, as well as to buffer status information received from control logic unit 512 and relay it to the host. Interface 516 can also be coupled to column decoder / bitline driver 506 via data bus 518 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 301.

[0108] This disclosure provides a memory device, the peripheral circuit of which is configured to: firstly perform a first programming operation on the memory cells of the first memory chip coupled to the Nth word line; during the first programming operation, gradually increase a step voltage based on the first programming start voltage to perform a programming operation with the target state as the first state; when the number of memory cells exceeding the upper limit of the first state threshold voltage is greater than a first preset value for the first time, obtain the number M of the increased step voltages, and obtain a second programming start voltage based on the number of increased step voltages and a fixed compensation value; the second programming start voltage is used to perform programming operations on the memory cells of the remaining memory chips coupled to the Nth word line.

[0109] In some specific examples, the second programming start voltage is the sum of the first programming start voltage, M times the step voltage, and a fixed compensation value.

[0110] It is understood that in the solution provided by the above embodiments, by first performing a programming operation on the memory cell of the first memory chip coupled to the Nth word line to the target state of the first state, when P is greater than the first preset value for the first time, the number M of the increased step voltage is obtained. Based on the obtained M, the programming start voltage is adjusted when programming the memory cells of the memory chips coupled to the Nth word line other than the first memory chip, so that when programming the memory cells of the remaining memory chips coupled to the Nth word line to the target state of the first state, it is not necessary to apply multiple pulses to increase one step voltage at a time to perform the programming operation to the target state of the first state, thereby saving programming time and improving programming efficiency.

[0111] The following is combined with Figure 6The embodiments of this disclosure are described in detail below. When programming the memory cell coupled to the Nth word line, a first programming operation is first performed on the memory cell of the first memory chip coupled to the Nth word line. When P first exceeds a first preset value, the number M of the increase step voltages is obtained. A fixed compensation value is added to the first programming start voltage and the M times the step voltage to adjust the second programming start voltage. The second programming start voltage is then applied to the second to fifth memory chips for a second programming operation. After the programming operation of the memory cell coupled to the Nth word line is completed, the programming operation of the memory cell coupled to the N+1th word line continues according to the programming method for the Nth word line.

[0112] Further research found that, for example Figure 7 As shown, the initial threshold voltage of memory cells with different word lines varies, resulting in different programming speeds. Figure 7 The first storage unit represents the set of storage units with slow programming speed, and the second storage unit represents the set of storage units with fast programming speed. Figure 7 It can be seen that the initial threshold voltage of the first memory cell is lower than that of the second memory cell, resulting in a faster programming speed for the second memory cell. Since the initial threshold voltages of memory cells coupled to different word lines differ, when this difference is less than a step voltage, the minimum adjustment increment of the Dynamic Start Voltage (DSV) is one step voltage. In this case, finer adjustments cannot be made using the DSV. Furthermore, the fixed compensation value is a globally fixed value. For different initial threshold voltages, although the verification failure count standard for the DSV can be met, the actual final threshold voltages will still differ. Since overprogramming is undesirable, the fixed compensation value is chosen to account for faster-programming memory cells, assigning them a larger absolute compensation value. This causes other slower memory cells to lose some of their programming start voltage, resulting in a decrease in programming time. In other words, the fixed compensation value is the same during programming operations on memory cells with different word lines, but the programming speed of memory cells with different word lines varies. The fixed compensation value cannot meet the different needs of memory cells with different word lines, thus affecting the programming speed.

[0113] In view of one or more of the above problems, embodiments of this disclosure provide another memory device, the memory device including a memory array and peripheral circuitry coupled to the memory array;

[0114] The memory array includes multiple memory chips coupled to the Nth word line, and each memory chip includes multiple memory cells;

[0115] The peripheral circuit is configured as follows:

[0116] A first programming start voltage is applied to the memory cell of at least one first memory chip coupled to the Nth word line to perform a first programming operation; wherein, during the first programming operation, a programming operation with the target state as the first state is performed by successively increasing the first programming start voltage by one step voltage.

[0117] Obtain the number P of memory cells whose threshold voltage exceeds the upper limit of the first-state threshold voltage;

[0118] When P first exceeds a first preset value, the number M of the increased step voltages is obtained; N, P, and M are all positive integers.

[0119] The second programming start voltage is determined based on P and M;

[0120] A second programming start voltage is applied to the memory cells of the memory chips other than the first memory chip that are coupled to the Nth word line, and a second programming operation is performed.

[0121] Here, the Nth word line can be any word line among multiple word lines in the memory array.

[0122] Here, P is acquired after each application of the programming voltage during the first programming operation, while M is acquired only when the acquired P is greater than a first preset value.

[0123] Here, the upper limit of the first-state threshold voltage can be referenced. Figure 10 To understand, Figure 10 The second threshold voltage Vt1 corresponds to logic bit 100, which corresponds to the first programming state. The second threshold voltage Vt1 corresponds to a range of voltage values, and the upper limit of this range is the upper limit of the first-state threshold voltage. The value of the upper limit of the first-state threshold voltage is related to the type of memory cell. Different types of memory cells have different upper limits of the first-state threshold voltage. For example, the types of memory cells include, but are not limited to, SLC, MLC, TLC, and QLC.

[0124] Here, at least one storage cell of the first storage chip can be a portion of the multiple storage chips coupled to the Nth word line, extracted based on three considerations: first, it can reflect the overall programming speed of the storage cells coupled to the Nth word line; second, it can effectively improve the programming speed; and third, it can be programmed independently.

[0125] In this embodiment of the present disclosure, in addition to performing a first programming operation on the storage cells of at least one first storage chip coupled to the Nth word line and then performing a second programming operation on the storage cells of the storage chips other than the first storage chip coupled to the Nth word line, it is also possible to first perform a first programming operation on the storage cells of any area coupled to the Nth word line that can be independently programmed, and then perform a second programming operation on the storage cells of other areas coupled to the Nth word line.

[0126] In some specific examples, at least one first storage slice can be one of a plurality of storage slices coupled to the Nth word line. For example, if one word line is coupled to six storage slices, at least one first storage slice can be one of the six storage slices, such as String0. Correspondingly, the storage slices other than the first storage slice can be the remaining storage slices coupled to the Nth word line, such as String1-5. At least one first storage slice can also be two storage slices of a plurality of storage slices coupled to the Nth word line, such as String0-String1. Correspondingly, the storage slices other than the first storage slice can be the remaining storage slices, such as String2-String5.

[0127] Here, the value of the first preset value can be set according to specific circumstances. The standard for setting the first preset value is to avoid window loss (Margin Loss). The window here mainly refers to the upper edge of the first-state peak. The first preset value should not be set too large, otherwise over-programming may occur, resulting in window loss. In some specific examples, different first preset values ​​can be set, and the window data under different settings can be compared to ensure that there is no loss of window data. In some specific examples, the first preset value can be 200. It should be noted that the first preset value given here is only an exemplary demonstration and is not intended to limit the value of the first preset value in this disclosure.

[0128] Here, when performing a programming operation with the target state as the first state on at least one memory cell of the first memory chip coupled to the Nth word line, the programming can be performed using Incremental Step Pulse Program (ISPP). Figure 8 This is a schematic diagram of the word line voltage applied to the word line during programming operations using the ISPP method according to an embodiment of this disclosure.

[0129] For NAND flash memory, write operations using step-pulse programming are performed on a page-by-page basis. Taking a specific cell within a page as an example, after programming begins, a starting programming voltage Vpgm is applied to the word line coupled to that cell. Then, a programming verification voltage Vvf_0 is applied to the word line to verify if the target threshold voltage has been reached. If the target threshold voltage has not been reached, a voltage Vispp, higher than the starting programming voltage, is applied, followed by another programming verification voltage Vvf_1 to verify if the target threshold voltage has been reached. This process is repeated until the threshold voltage of the cell is found to have reached the target threshold voltage during the verification step. At this point, the programming of that cell is complete. Subsequently, a programming suppression voltage is applied to the bit line coupled to the cell to prevent further programming. The entire page writing process ends when the threshold voltages of all cells in the page have reached the target threshold voltage. This step-pulse programming method allows for a narrower final threshold voltage distribution.

[0130] Each programming cycle includes a programming operation and a programming verification operation. For example, during the programming operation of a memory cell of a first memory chip coupled to the Nth word line, a first programming start voltage Vpgm is applied to the selected word line, and a pass voltage Vpass is applied to the unselected word lines. During the programming verification operation, a verification voltage Vvfy is applied to the selected word line, and a read voltage Vread is applied to the unselected word lines. The next programming cycle then begins, applying a second programming voltage Vpgm+Vispp to the selected word line, and a pass voltage Vpass is applied to the unselected word lines. Here, for each programming cycle, the programming voltage is greater than the programming voltage in the previous programming cycle by the amount of Vispp.

[0131] It is understood that in this embodiment of the present disclosure, a dynamic programming start voltage is applied during the programming process. The method performs programming operations on the memory cells coupled to the Nth word line in two stages: first, a first programming operation is performed on the memory cells of at least one first memory chip coupled to the Nth word line, using a default start voltage during this first programming operation; then, a second programming operation is performed on the memory cells of the memory chips coupled to the Nth word line (excluding the first memory chips). During the second programming operation, the programming start voltage is adjusted based on the programming verification results of the first programming operation, thereby achieving adaptive adjustment of the programming speed. Therefore, when programming memory cells coupled to different word lines, different programming start voltages can be provided for different word line coupled memory cells, thereby improving the overall programming speed and efficiency.

[0132] In some embodiments, the peripheral circuit is configured as follows:

[0133] A first compensation value is determined based on the interval to which P belongs; the larger the value of the interval to which P belongs, the smaller the first compensation value, and the first compensation value is a negative voltage; the larger the average number of memory cells in the interval, the larger the value of the interval.

[0134] The sum of the first programming start voltage, M times the step voltage, and the first compensation value is used as the second programming start voltage.

[0135] It is understandable that the value of an interval can be represented by the average number of storage units in the interval. The larger the average number of storage units in the interval, the larger the value of the interval, and the larger the absolute value of the given first compensation value, that is, the greater the compensation.

[0136] Understandably, when P first exceeds the first preset value, the larger the value within the range of P, the faster the programming speed of at least one memory cell in the first memory chip. This means the faster the programming speed of other memory cells in the memory chips connected to the Nth word line (excluding the first memory chip). Therefore, a compensation value with a large absolute value is needed to prevent over-programming of the memory cells in the memory chips connected to the Nth word line (excluding the first memory chip). This first compensation value is not a fixed value, but rather dynamically adjusted based on the programming verification results of the memory cells in the at least one first memory chip connected to the Nth word line—that is, the programming speed of the memory cells. This dynamically adjusts the programming start voltage of the memory cells in the memory chips connected to the Nth word line (excluding the first memory chip), thereby improving the overall programming speed.

[0137] The first compensation value here, being a negative voltage, can be understood as follows: During the programming operation of at least one memory cell of the first memory chip coupled to the Nth word line, when the applied programming voltage causes P to exceed the first preset value for the first time, the number of step voltages increased is M. In the programming operation of increasing one step voltage at a time, it means that the programming voltage at this time is a suitable voltage that can program the memory cell to a low failure bit rate count. However, at this time, the threshold voltage of some memory cells is still greater than the upper limit of the threshold voltage of the first state. Therefore, when programming the memory cells of memory chips other than the first memory chip, the programming start voltage needs to be appropriately reduced (increased to the first compensation value of negative voltage) on the basis of increasing M step voltages. This allows the second programming start voltage to be adjusted directly according to the programming status of the memory cells of at least one first memory chip during the programming operation of the memory cells of memory chips other than the first memory chip. This reduces the number of programming pulses when programming the memory cells of memory chips other than the first memory chip, thereby shortening the programming operation time and improving programming efficiency.

[0138] In some embodiments, the peripheral circuit is configured as follows:

[0139] Based on the interval to which P belongs, and in conjunction with the first mapping table, the first compensation value is determined; the first mapping table stores the correspondence between different intervals of P and different first compensation values.

[0140] Here, according to the combination Figure 9 To understand, Figure 9 An exemplary first mapping table is shown, which reflects the relationship between intervals and first compensation values. Different intervals correspond to different first compensation values. During programming, the specific value of the first compensation value can be determined based on which interval P falls within when P first exceeds the first preset value. For example, when P first exceeds the first preset value, if P falls within the interval N1 to N2, the first compensation value is first compensation value -1; if P first exceeds the first preset value, if P falls within the interval N2 to N3, the first compensation value is first compensation value -2; and if P first exceeds the first preset value, if P falls within the interval N3 to N4, the first compensation value is first compensation value -3. The first compensation values ​​-1, -2, and -3 are different.

[0141] In some specific examples, the memory device further includes a register for storing a first mapping table, the register being located in the peripheral circuitry.

[0142] In some embodiments, the storage bits of the storage unit include multiple bits; the first state is the programming state in which the threshold voltage distribution is closest to the threshold voltage distribution of the erase state.

[0143] Here, the number of bits in the storage unit can include 1 bit, 2 bits, 3 bits, or 4 bits, but is not limited to these. When the number of bits in the storage unit is 1 bit, each storage unit is a single-level cell (SLC) that can store one bit of data; when the number of bits in the storage unit is 2 bits, each storage unit is a multi-level cell (MLC) that can store two bits of data; when the number of bits in the storage unit is 3 bits, each storage unit is a three-level cell (TLC) that can store three bits of data; and when the number of bits in the storage unit is 4 bits, each storage unit is a four-level cell (QLC) that can store four bits of data.

[0144] The following is a simple explanation using TLC as an example. Figure 10 This is a schematic diagram of data storage in the TLC of a 3D-NAND device. For example... Figure 10 As shown, a TLC can have eight threshold voltages Vt0-Vt7, and each of these eight threshold voltages Vt0-Vt7 can represent three corresponding logic bits. For example, the first threshold voltage Vt0 corresponds to logic bit 000, and the second threshold voltage Vt1 corresponds to logic bit 100, where logic bit 000 corresponds to the erase state. Therefore, by adjusting the threshold voltages of the TLC to the target threshold voltage, the TLC can be programmed with corresponding logic bits. When the programming operation of the TLC is completed, a subsequent verification operation can be performed to verify whether the threshold voltages of the TLC meet the target threshold voltage. The logic bits stored in the TLC can be further divided into three logic pages: the next page, the middle page, and the previous page. For example, the logic bit 100 of the second threshold voltage Vt1 of the TLC can be further stored in the next page, the middle page, and the previous page, where logic bit 1 can be stored in the previous page, the first logic bit 0 can be stored in the middle page, and the second logic bit 0 can be stored in the next page. Here, the target threshold voltage is the programming state of Vt1 corresponding to the first state.

[0145] In some embodiments, the peripheral circuit is configured as follows:

[0146] After programming the target state to the first state by successively increasing the voltage step by step based on the first programming start voltage, a programming verification voltage is applied to the memory cells of the at least one first memory chip to obtain the number P of memory cells whose threshold voltage exceeds the upper limit of the first state threshold voltage.

[0147] In some embodiments, the peripheral circuit is configured as follows:

[0148] When P is less than a first preset value, the programming operation of the first state is continued by increasing the voltage step by step until P is greater than the first preset value for the first time.

[0149] It is understandable that when P is less than the first preset value, the voltage is increased by one step at a time until P is greater than the first preset value for the first time. At this time, the total number of steps increased is M. Then, the second programming start voltage is determined based on P and M.

[0150] In some embodiments, the peripheral circuit is configured as follows:

[0151] After applying a second programming start voltage to the memory cells of the memory chips other than the first memory chips coupled to the Nth word line, a third programming start voltage is applied to the memory cells of at least one first memory chip coupled to the N+1th word line to perform a third programming operation; wherein, during the third programming operation, a programming operation with the target state as the first state is performed by successively increasing a step voltage based on the third programming start voltage.

[0152] Obtain the number Q of memory cells whose threshold voltage exceeds the upper limit of the first state threshold voltage;

[0153] When Q is greater than the first preset value for the first time, the number of additional step voltages S is obtained; Q and S are both positive integers.

[0154] The fourth programming start voltage is determined based on S and Q;

[0155] A fourth programming start voltage is applied to the memory cells of the memory chips other than the first memory chip that are coupled to the N+1th word line to perform a fourth programming operation.

[0156] Here, the (N+1)th word line can be a word line adjacent to the Nth word line. For example, when the programming operations are performed in a forward programming order, the (N+1)th word line can be a word line located above the Nth word line; when the programming operations are performed in a reverse programming order, the (N+1)th word line can be a word line located below the Nth word line. The terms "upper" and "lower" can be referenced here. Figure 4To understand this, the forward programming sequence starts from the memory cell closest to the lower select gate (BSG) and proceeds upwards to the memory cell closest to the upper select gate (TSG). In other words, programming proceeds sequentially from the memory cell adjacent to the lower select gate (BSG) to the memory cell adjacent to the upper select gate (TSG). The reverse programming sequence starts from the memory cell closest to the upper select gate (TSG) and proceeds downwards to the memory cell closest to the lower select gate (BSG). In some specific examples, during a first programming operation where the target state is the first state is achieved for at least one memory cell coupled to the Nth word line, the number of step voltages increased is M. During a third programming operation where the target state is the first state is achieved for at least one memory cell coupled to the N+1th word line, the number of step voltages increased is S. The values ​​of M and S can be the same or different, depending on the specific programming speed of the Nth word line and the N+1th word line.

[0157] In some specific examples, determining the fourth programming start voltage based on S and Q includes:

[0158] The second compensation value is determined based on the interval to which Q belongs; when P and Q belong to the same interval, the first compensation value and the second compensation value are the same; when P and Q belong to different intervals, the first compensation value and the second compensation value are different.

[0159] The fourth programming start voltage is equal to the sum of the third programming start voltage, S times the step voltage, and the second compensation value.

[0160] It is understood that the programming speed of memory cells with different word lines is different. In this embodiment of the present disclosure, when programming memory cells with different word lines, when the number of memory cells with different word lines that exceed the upper limit of the first state threshold voltage is greater than the first preset value for the first time, the second programming start voltage and the fourth programming start voltage are determined according to the intervals to which P and Q belong respectively.

[0161] In some embodiments, the peripheral circuit is configured as follows:

[0162] During the first programming operation, after completing the programming operation with the target state of the first state for the memory cell of at least one first memory chip coupled to the Nth word line, the programming operation with the target state of other states begins for the memory cell of at least one first memory chip coupled to the Nth word line.

[0163] During the second programming operation, after applying a second programming start voltage to the memory cells of the memory chips (excluding the first memory chip) coupled to the Nth word line to complete the programming operation with the target state as the first state, programming operations with the target state as other states are started on the memory cells of the memory chips (excluding the first memory chip) coupled to the Nth word line.

[0164] In some embodiments, the memory device includes a three-dimensional NAND type memory.

[0165] However, the memory device in this disclosure is not limited to three-dimensional NAND type memory. In this disclosure, the memory device can be a semiconductor memory, including but not limited to three-dimensional NAND flash memory, vertical NAND flash memory, NOR flash memory, dynamic random access memory (DRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), phase change random access memory (PCRAM), resistive random access memory (RRAM), or nano random access memory (NRAM), etc.

[0166] In this embodiment of the disclosure, when performing programming operations using a dynamic programming start voltage mode, the compensation value is dynamically adjusted based on the number of memory cells whose threshold voltage exceeds the upper limit of the first state threshold voltage when the programming verification result of the first programming operation on at least one memory cell of the first memory chip satisfies the condition that P is greater than a first preset value for the first time. This achieves a more precise adjustment of the second programming start voltage. Because a dynamically adjusted compensation value is used, the situation where a large compensation value is required to account for memory cells with faster programming speeds without programming them is avoided, thereby improving the overall programming speed.

[0167] In this embodiment of the disclosure, in the first programming operation, based on the judgment criterion that P is greater than the first preset value for the first time, a dynamic compensation value is then performed based on the P value. The larger the P value, the larger the absolute value of the compensation value, thereby preventing overprogramming.

[0168] This disclosure provides a memory device including a memory array and peripheral circuitry coupled to the memory array. The memory array includes a plurality of memory chips coupled to an Nth word line, each memory chip including a plurality of memory cells. The peripheral circuitry is configured to: apply a first programming start voltage to the memory cells of at least one first memory chip coupled to the Nth word line to perform a first programming operation; wherein, during the first programming operation, a programming operation with a target state of a first state is performed by successively increasing a step voltage based on the first programming start voltage; obtain the number P of memory cells whose threshold voltage exceeds the upper limit of the first state threshold voltage; when P first exceeds a first preset value, obtain the number M of the increased step voltages; where N, P, and M are all positive integers; determine a second programming start voltage based on P and M; and apply the second programming start voltage to the memory cells of memory chips other than the first memory chips coupled to the Nth word line to perform a second programming operation. In this embodiment of the disclosure, when performing a second programming operation on the memory cells of the memory chips other than the first memory chip coupled to the Nth word line, the second programming start voltage is dynamically adjusted according to P and M. That is, the value of the second programming start voltage is not a fixed value, but a value that is dynamically adjusted according to the programming verification result of the memory cells of at least one first memory chip coupled to the Nth word line. This enables each word line to be programmed to the target state at a faster speed, thereby improving the overall programming speed and thus improving programming efficiency.

[0169] This disclosure also provides a memory system, the memory system comprising:

[0170] One or more memory devices as described in any of the above embodiments; and

[0171] A memory controller, which is coupled to and controls the memory device.

[0172] Here, the specific structure and composition of the memory system can be referred to the foregoing. Figure 1 , Figure 2a , Figure 2b The relevant structure and composition of the memory system are described below. For the sake of brevity, they will not be elaborated here.

[0173] In some embodiments, the memory system includes a memory card or a solid-state drive.

[0174] Based on the above-described memory device, this disclosure also provides a method for operating the memory device, such as... Figure 11 As shown, the method includes:

[0175] Step 1101: Apply a first programming start voltage to the memory cell of at least one first memory chip coupled to the Nth word line to perform a first programming operation; wherein, during the first programming operation, a programming operation with the target state as the first state is performed by successively increasing a step voltage based on the first programming start voltage.

[0176] Step 1102: Obtain the number P of memory cells whose threshold voltage exceeds the upper limit of the first-state threshold voltage;

[0177] Step 1103: When P first exceeds the first preset value, obtain the number M of the increased step voltages; N, P, and M are all positive integers;

[0178] Step 1104: Determine the second programming start voltage based on P and M;

[0179] Step 1105: Apply a second programming start voltage to the memory cells of the memory chips other than the first memory chip coupled to the Nth word line, and perform a second programming operation.

[0180] In some embodiments, determining the second programming start voltage based on P and M includes:

[0181] A first compensation value is determined based on the interval to which P belongs; the larger the value of the interval to which P belongs, the smaller the first compensation value, and the first compensation value is a negative voltage; the larger the average number of memory cells in the interval, the larger the value of the interval.

[0182] The sum of the first programming start voltage, M times the step voltage, and the first compensation value is used as the second programming start voltage.

[0183] In some embodiments, determining the first compensation value based on the interval to which P belongs includes:

[0184] Based on the interval to which P belongs, and in conjunction with the first mapping table, the first compensation value is determined; the first mapping table stores the correspondence between different intervals of P and different first compensation values.

[0185] In some specific examples, the method further includes: establishing the first mapping table before performing the first programming operation.

[0186] In some embodiments, the storage bits of the storage unit include multiple bits; the first state is the programming state in which the threshold voltage distribution is closest to the threshold voltage distribution of the erase state.

[0187] In some embodiments, obtaining the number P of memory cells whose threshold voltage exceeds the upper limit of the first-state threshold voltage includes:

[0188] After programming to the first state by successively increasing the voltage step by step based on the first programming start voltage, a programming verification voltage is applied to the memory cells of at least one first memory chip coupled to the Nth word line to obtain the number P of memory cells whose threshold voltage exceeds the upper limit of the first state threshold voltage.

[0189] In some embodiments, the method further includes:

[0190] When P is less than a first preset value, the programming operation of the first state is continued by increasing the voltage step by step until P is greater than the first preset value for the first time.

[0191] In some embodiments, the method further includes:

[0192] After applying a second programming start voltage to the memory cells of the memory chips other than the first memory chips coupled to the Nth word line, a third programming start voltage is applied to the memory cells of at least one first memory chip coupled to the N+1th word line to perform a third programming operation; wherein, during the third programming operation, a programming operation with the target state as the first state is performed by successively increasing a step voltage based on the third programming start voltage.

[0193] Obtain the number Q of memory cells whose threshold voltage exceeds the upper limit of the first state threshold voltage;

[0194] When Q is greater than the first preset value for the first time, the number of additional step voltages S is obtained; Q and S are both positive integers.

[0195] The fourth programming start voltage is determined based on S and Q;

[0196] A fourth programming start voltage is applied to the memory cells of the memory chips other than the first memory chip that are coupled to the N+1th word line to perform a fourth programming operation.

[0197] In some specific examples, determining the fourth programming start voltage based on S and Q includes:

[0198] The second compensation value is determined based on the interval to which Q belongs; when P and Q belong to the same interval, the first compensation value and the second compensation value are the same; when P and Q belong to different intervals, the first compensation value and the second compensation value are different.

[0199] The fourth programming start voltage is equal to the sum of the third programming start voltage, S times the step voltage, and the second compensation value.

[0200] In some embodiments, the method further includes:

[0201] During the first programming operation, after completing the programming operation with the target state of the first state for the memory cell of at least one first memory chip coupled to the Nth word line, the programming operation with the target state of other states begins for the memory cell of at least one first memory chip coupled to the Nth word line.

[0202] During the second programming operation, after applying a second programming start voltage to the memory cells of the memory chips (excluding the first memory chip) coupled to the Nth word line to complete the programming operation with the target state as the first state, programming operations with the target state as other states are started on the memory cells of the memory chips (excluding the first memory chip) coupled to the Nth word line.

[0203] The following is combined with Figure 12 Understanding the above embodiments of this disclosure, when programming a memory cell coupled to the Nth word line, a first programming operation is first performed on the memory cell of the first memory chip coupled to the Nth word line. When P first exceeds a first preset value, the number M of the increased step voltages is obtained, and the compensation value is updated according to the value of P. The updated compensation value is added to the first programming start voltage and the step voltage of M times, thereby adjusting the second programming start voltage. The second programming start voltage is then applied to the second to fifth memory chips for a second programming operation. After the programming operation of the memory cell coupled to the Nth word line is completed, the programming operation of the memory cell coupled to the N+1th word line continues according to the programming method for the Nth word line.

[0204] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0205] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0206] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A memory device, comprising: The memory device includes a memory array and peripheral circuitry coupled to the memory array. The memory array includes multiple memory chips coupled to the Nth word line, and each memory chip includes multiple memory cells; The peripheral circuit is configured as follows: A first programming start voltage is applied to the memory cell of at least one first memory chip coupled to the Nth word line to perform a first programming operation; wherein, during the first programming operation, a programming operation with the target state as the first state is performed by successively increasing the first programming start voltage by one step voltage. Obtain the number P of memory cells whose threshold voltage exceeds the upper limit of the first-state threshold voltage; When P first exceeds a first preset value, the number M of the increased step voltages is obtained; N, P, and M are all positive integers. Determine the first compensation value based on the interval to which P belongs; The second programming starting voltage is determined based on the first programming starting voltage, M times the step voltage, and the first compensation value; A second programming start voltage is applied to the memory cells of the memory chips other than the first memory chip that are coupled to the Nth word line, and a second programming operation is performed.

2. The memory device of claim 1, wherein, The larger the value of the interval to which P belongs, the smaller the first compensation value, and the first compensation value is a negative voltage; the larger the average number of memory cells in the interval, the larger the value of the interval; the peripheral circuit is configured as follows: The sum of the first programming start voltage, M times the step voltage, and the first compensation value is used as the second programming start voltage.

3. The memory device of claim 2, wherein, The peripheral circuit is configured as follows: Based on the interval to which P belongs, and in conjunction with the first mapping table, the first compensation value is determined; the first mapping table stores the correspondence between different intervals of P and different first compensation values.

4. The memory device according to claim 1, characterized in that, The storage bits of the storage unit include multiple bits; the first state is the programming state in which the threshold voltage distribution is closest to the threshold voltage distribution of the erase state.

5. The memory device of claim 1, wherein, The peripheral circuit is configured as follows: After programming to the first state by successively increasing the voltage step by step based on the first programming start voltage, a programming verification voltage is applied to the memory cells of at least one first memory chip coupled to the Nth word line to obtain the number P of memory cells whose threshold voltage exceeds the upper limit of the first state threshold voltage.

6. The memory device of claim 1, wherein, The peripheral circuit is configured as follows: When P is less than a first preset value, the programming operation of the first state is continued by increasing the voltage step by step until P is greater than the first preset value for the first time.

7. The memory device according to claim 1, characterized in that, The peripheral circuit is configured as follows: After applying a second programming start voltage to the memory cells of the memory chips other than the first memory chips coupled to the Nth word line, a third programming start voltage is applied to the memory cells of at least one first memory chip coupled to the N+1th word line to perform a third programming operation; wherein, during the third programming operation, a programming operation with the target state as the first state is performed by successively increasing a step voltage based on the third programming start voltage. The number Q of memory cells whose threshold voltage exceeds the upper limit of the first state threshold voltage is obtained; When Q first exceeds the first preset value, the number S of the increased step voltages is obtained; Q and S are both positive integers. The fourth programming start voltage is determined based on S and Q; A fourth programming start voltage is applied to the memory cells of the memory chips other than the first memory chip that are coupled to the N+1th word line to perform a fourth programming operation.

8. The memory device according to claim 1, characterized in that, The peripheral circuit is configured as follows: During the first programming operation, after completing the programming operation with the target state of the first state for the memory cell of at least one first memory chip coupled to the Nth word line, the programming operation with the target state of other states begins for the memory cell of at least one first memory chip coupled to the Nth word line. During the second programming operation, after applying a second programming start voltage to the memory cells of the memory chips (excluding the first memory chip) coupled to the Nth word line to complete the programming operation with the target state as the first state, programming operations with the target state as other states are started on the memory cells of the memory chips (excluding the first memory chip) coupled to the Nth word line.

9. The memory device according to claim 1, characterized in that, The memory device includes a three-dimensional NAND type memory.

10. A memory system, comprising: One or more memory devices as described in any one of claims 1 to 9; as well as A memory controller, which is coupled to and controls the memory device.

11. A method of operating a memory device, characterized in that, include: A first programming start voltage is applied to the memory cell of at least one first memory chip coupled to the Nth word line to perform a first programming operation; wherein, during the first programming operation, a programming operation with the target state as the first state is performed by successively increasing the first programming start voltage by one step voltage. Obtain the number P of memory cells whose threshold voltage exceeds the upper limit of the first-state threshold voltage; When P first exceeds a first preset value, the number M of the increased step voltages is obtained; N, P, and M are all positive integers. Determine the first compensation value based on the interval to which P belongs; The second programming starting voltage is determined based on the first programming starting voltage, M times the step voltage, and the first compensation value; A second programming start voltage is applied to the memory cells of the memory chips other than the first memory chip that are coupled to the Nth word line, and a second programming operation is performed.

12. The operating method according to claim 11, characterized in that, The larger the value of the interval to which P belongs, the smaller the first compensation value, and the first compensation value is a negative voltage; the larger the average number of memory cells in the interval, the larger the value of the interval; determining the second programming start voltage based on the first programming start voltage, M times the step voltage, and the first compensation value includes: The sum of the first programming start voltage, M times the step voltage, and the first compensation value is used as the second programming start voltage.

13. The method of operation of claim 12, wherein, Determining the first compensation value based on the interval to which P belongs includes: Based on the interval to which P belongs, and in conjunction with the first mapping table, the first compensation value is determined; the first mapping table stores the correspondence between different intervals of P and different first compensation values.

14. The operating method according to claim 11, characterized in that, The storage bits of the storage unit include multiple bits; the first state is the programming state in which the threshold voltage distribution is closest to the threshold voltage distribution of the erase state.

15. The operating method according to claim 11, characterized in that, The number P of memory cells whose threshold voltage exceeds the upper limit of the first-state threshold voltage includes: After programming to the first state by successively increasing the voltage step by step based on the first programming start voltage, a programming verification voltage is applied to the memory cells of at least one first memory chip coupled to the Nth word line to obtain the number P of memory cells whose threshold voltage exceeds the upper limit of the first state threshold voltage.

16. The operating method according to claim 11, characterized in that, The method further includes: When P is less than a first preset value, the programming operation of the first state is continued by increasing the voltage step by step until P is greater than the first preset value for the first time.

17. The operating method according to claim 11, characterized in that, The method further includes: After applying a second programming start voltage to the memory cells of the memory chips other than the first memory chips coupled to the Nth word line, a third programming start voltage is applied to the memory cells of at least one first memory chip coupled to the N+1th word line to perform a third programming operation; wherein, during the third programming operation, a programming operation with the target state as the first state is performed by successively increasing a step voltage based on the third programming start voltage. Obtain the number Q of memory cells whose threshold voltage exceeds the upper limit of the first state threshold voltage; When Q first exceeds the first preset value, the number S of the increased step voltages is obtained; Q and S are both positive integers. The fourth programming start voltage is determined based on S and Q; A fourth programming start voltage is applied to the memory cells of the memory chips other than the first memory chip that are coupled to the N+1th word line to perform a fourth programming operation.

18. The operating method according to claim 11, characterized in that, The method further includes: During the first programming operation, after completing the programming operation with the target state of the first state for the memory cell of at least one first memory chip coupled to the Nth word line, the programming operation with the target state of other states begins for the memory cell of at least one first memory chip coupled to the Nth word line. During the second programming operation, after applying a second programming start voltage to the memory cells of the memory chips (excluding the first memory chip) coupled to the Nth word line to complete the programming operation with the target state as the first state, programming operations with the target state as other states are started for the memory cells of the memory chips (excluding the first memory chip) coupled to the Nth word line.

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