A method for preparing an epitaxial wafer, an epitaxial wafer, and a high electron mobility transistor

Abstract

The present invention discloses a method for preparing an epitaxial wafer, an epitaxial wafer, and a high electron mobility transistor. The preparation method includes providing a substrate; carbonizing the substrate by introducing n-hexane with nitrogen as a carrier gas to grow a first thin film layer on the substrate, and continuously introducing n-hexane and silane to grow a second thin film layer on the first thin film layer; successively growing a nucleation layer, a high-resistance buffer layer, a channel layer, an insertion layer, a barrier layer, and a cap layer on the second thin film layer; wherein, both the first thin film layer and the second thin film layer are SiC layers. The present invention solves the problem of poor crystal quality of the epitaxial wafer in the prior art.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a method for preparing an epitaxial wafer, an epitaxial wafer, and a high electron mobility transistor. Background Art

[0002] As a third-generation semiconductor material, GaN-based materials have advantages such as a large bandgap, a high electron saturation drift velocity, good chemical stability, high radiation resistance and high temperature resistance, and easy formation of heterojunctions, and have become the preferred materials for manufacturing high electron mobility transistor (HEMT) structures with high temperature, high frequency, high power, and radiation resistance. The GaN-based heterostructure has a very high carrier concentration and electron mobility, a small on-resistance, and the advantage of the bandgap enables it to withstand a very high operating voltage. Therefore, GaN-based HEMTs are widely used in application fields such as high-temperature high-frequency high-power devices and low-loss rate switching devices.

[0003] Currently, the common substrates for growing GaN thin films in this field are sapphire (Al2O3), silicon carbide (SiC), and silicon (Si). Among them, the epitaxial growth of GaN thin films on sapphire and SiC substrates is very mature, but their prices are relatively high, especially the price of SiC is expensive, which greatly increases the production cost. Moreover, sapphire itself has poor heat dissipation effect and it is difficult to achieve large-size epitaxial growth. Therefore, Si substrates are usually used for epitaxial growth of GaN thin films, which have good thermal conductivity and can achieve large-size epitaxy, especially 6-inch, 8-inch, and 12-inch epitaxial wafers, which can reduce production costs and have great market competitiveness. However, there are large lattice mismatches and thermal mismatches between the Si substrate and the GaN epitaxial thin film. The film stress generated by the large lattice mismatch during the epitaxial growth process will cause the crystal quality of the epitaxial thin film to decline. In addition, the thermal stress generated by the large thermal mismatch during the cooling process will cause cracks on the surface of the epitaxial thin film, which also reduces the crystal quality of the epitaxial layer. Therefore, in order to prepare high electron mobility transistors with more excellent performance, a large amount of in-depth research is still required.

[0004] In the prior art, due to the relatively large lattice mismatch and thermal mismatch between the Si substrate and GaN, cracks are easily formed on the epitaxial surface, resulting in crazing, which limits the development of this technology. In order to reduce cracks and improve the quality of the epitaxial layer, common methods include setting a low-temperature AlN insertion layer / high-temperature AlN insertion layer, and using methods such as a graded layer AlGaN, an AlN / AlGaN superlattice, etc. to gradually release the stress caused by the lattice mismatch to solve the problems of cracks on the surface of the epitaxial layer and crystal quality. However, these conventional methods all consider from the perspective of lattice mismatch, reducing the stress generated by the lattice mismatch and resulting in the generation of cracks on the surface of the epitaxial thin film and the decline of crystal quality, but do not solve the stress generated by the thermal mismatch. There is still a large thermal mismatch between the Si substrate and the GaN thin film, which in turn leads to poor crystal quality of the epitaxial wafer. Summary of the Invention

[0005] Based on this, the object of the present invention is to provide a method for preparing an epitaxial wafer, an epitaxial wafer and a high electron mobility transistor, aiming at solving the problem that the crystal quality is poor due to the thermal mismatch not being considered when reducing the lattice matching in the prior art epitaxial wafer.

[0006] The embodiments of the present invention are implemented as follows:

[0007] A method for preparing an epitaxial wafer, the method comprising:

[0008] Providing a substrate;

[0009] Using nitrogen as a carrier gas to introduce n-hexane to carbonize the substrate, so as to grow a first thin film layer on the substrate, and continuing to introduce n-hexane and silane to grow a second thin film layer on the first thin film layer;

[0010] Sequentially growing a nucleation layer, a high-resistance buffer layer, a channel layer, an insertion layer, a barrier layer and a capping layer on the second thin film layer;

[0011] Wherein, both the first thin film layer and the second thin film layer are SiC layers.

[0012] In addition, according to the method for preparing an epitaxial wafer proposed by the present invention, the following additional technical features may also be included:

[0013] Further, in the above method for preparing an epitaxial wafer, the growth temperature of both the first thin film layer and the second thin film layer is 1100°C - 1300°C.

[0014] Further, in the above method for preparing an epitaxial wafer, the growth pressure of both the first thin film layer and the second thin film layer is 30 - 70 mbar.

[0015] Further, in the above method for preparing an epitaxial wafer, the growth thickness of the first thin film layer is less than the growth thickness of the second thin film layer.

[0016] Further, in the above method for preparing an epitaxial wafer, the growth thickness of the first thin film layer is 10 - 20 nm, and the growth thickness of the second thin film layer is 100 - 300 nm.

[0017] Further, in the above method for preparing an epitaxial wafer, before the step of using hydrogen as a carrier gas to introduce n-hexane to carbonize the substrate to grow a first thin film layer on the substrate and continuing to introduce n-hexane and silane to grow a second thin film layer on the first thin film layer, it further includes:

[0018] Subjecting the substrate to a high-temperature treatment at a temperature of 1000 - 1200°C in an H2 atmosphere for 5 - 10 min, and then introducing N2 for purging for 1 - 5 min.

[0019] Furthermore, in the above method for preparing an epitaxial wafer, the steps of successively growing a nucleation layer, a high-resistance buffer layer, a channel layer, an insertion layer, a barrier layer, and a cap layer on the second thin film layer include:

[0020] Controlling the temperature to be adjusted to 1100°C - 1300°C and the growth pressure to be 30 - 70 mbar, using nitrogen as the carrier gas, and introducing ammonia and trimethylaluminum to grow the nucleation layer on the second thin film layer;

[0021] Controlling the temperature to be 1000°C - 1200°C and the pressure to be 40 - 70 mbar, and introducing a preset carrier gas, a precursor, and a gallium source to grow the high-resistance buffer layer on the nucleation layer;

[0022] Controlling the temperature to be 1000°C - 1150°C and the pressure to be 100 - 300 mbar, and introducing a preset carrier gas, a precursor, and a gallium source to grow the channel layer on the high-resistance buffer layer;

[0023] Controlling the temperature to be 1050°C - 1150°C and the pressure to be 40 - 70 mbar, and introducing a preset carrier gas, a precursor, and a gallium source to successively grow the insertion layer, the barrier layer, and the cap layer on the channel layer.

[0024] Another object of the present invention is to provide an epitaxial wafer, which is prepared by the method for preparing an epitaxial wafer described in any one of the above, and the epitaxial wafer includes:

[0025] A substrate;

[0026] A first thin film layer, a second thin film layer, a nucleation layer, a high-resistance buffer layer, a channel layer, an insertion layer, a barrier layer, and a cap layer that are successively stacked on the substrate.

[0027] Furthermore, in the above epitaxial wafer, the substrate is a Si substrate, the first thin film layer and the second thin film layer are both SiC layers, the nucleation layer and the insertion layer are both AlN layers, the high-resistance buffer layer and the barrier layer are both AlGaN layers, and the channel layer and the cap layer are both GaN layers.

[0028] Another object of the present invention is to provide a high electron mobility transistor, which includes the above epitaxial wafer.

[0029] Compared with the prior art: Due to the large thermal mismatch between the Si substrate and the GaN epitaxial layer, the epitaxial layer will be subjected to great thermal stress during the cooling process, which easily causes cracks on the surface of the epitaxial layer. Growing an SiC thin film on the surface of the Si substrate can relieve the thermal stress brought during the cooling process, reduce the surface defects of the epitaxial layer, and the first thin film layer only introduces n-hexane. At this time, the surface of the formed SiC thin film is relatively rough, which is beneficial to releasing the stress between the Si substrate, the second thin film, and the epitaxial layer. The second SiC thin film is an SiC thin film formed by the reaction of n-hexane and silane. At this time, the surface of the formed SiC thin film is relatively flat and the crystal quality is relatively good, which can reduce the thermal stress brought by the epitaxial layer during the cooling process. Secondly, the lattice mismatch between the GaN epitaxial layer and SiC is 3.5%, which is much smaller than the lattice mismatch of 17% between the GaN epitaxial layer and Si. Inserting an SiC thin film on the Si substrate can also reduce the lattice mismatch degree during the GaN epitaxial growth process, reduce the lattice mismatch of the epitaxial wafer while reducing the thermal mismatch, thereby ultimately improving the crystal quality of the epitaxial layer. Description of the Drawings

[0030] Figure 1 It is a flowchart of the method for preparing an epitaxial wafer in an embodiment of the present invention;

[0031] Figure 2 It is the edge crack situation of the epitaxial wafer prepared by the traditional method;

[0032] Figure 3 It is the edge crack situation of the epitaxial wafer prepared by the method for preparing an epitaxial wafer proposed in an embodiment of the present invention.

[0033] The following specific embodiments will further illustrate the present invention in conjunction with the above-mentioned drawings. Specific Embodiments

[0034] For the convenience of understanding the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. Several embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present invention more thorough and comprehensive.

[0035] It should be noted that when an element is referred to as being "fixed on" another element, it can be directly on the other element or there can also be a middle element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be a middle element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are only for the purpose of illustration.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this invention belongs. The terms used in the description of this invention herein are for the purpose of describing specific embodiments only and are not intended to limit the invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0037] In view of the problem of poor crystal quality of current epitaxial wafers, the present invention provides a method for preparing an epitaxial wafer, an epitaxial wafer, and a high electron mobility transistor, wherein:

[0038] Please refer to Figure 1 , which shows the method for preparing an epitaxial wafer proposed in an embodiment of the present invention, including:

[0039] Step S10, providing a substrate.

[0040] In this embodiment, the substrate is a P-type doped Si substrate. Additionally, in some alternative embodiments of the present invention, in order to improve the epitaxial growth effect on the substrate, before epitaxial growth on the substrate, the substrate is heat-treated at a temperature of 1000 - 1200 °C in an H2 atmosphere for 5 - 10 min, and then N2 is introduced for purging for 1 - 5 min; specifically, the substrate is placed in an MOCVD system, the chamber temperature is raised to 1000 - 1200 °C, and it is heat-treated in an H2 atmosphere for 5 - 10 min to remove oxide impurities on the surface of the Si-based substrate, then N2 is introduced for purging for 1 - 5 min to remove H2 in the chamber, and the chamber pressure is maintained at 50 - 100 mbar.

[0041] Step S11, using nitrogen as a carrier gas to introduce n-hexane to carbonize the substrate, so as to grow a first thin film layer on the substrate, and continuing to introduce n-hexane and silane to grow a second thin film layer on the first thin film layer.

[0042] Specifically, after the Si substrate is heat-treated, at a temperature of 1100 - 1200 °C and a chamber pressure of 30 - 70 mbar, using N2 as a carrier gas, n-hexane is introduced to carbonize the Si substrate to generate a SiC layer to form a first thin film layer, wherein the growth thickness is 10 - 20 nm; after the growth of the first thin film layer is completed, at a temperature of 1100 - 1200 °C and a chamber pressure of 30 - 70 mbar, using N2 as a carrier gas, n-hexane and silane are introduced to grow a second thin film layer, wherein the growth thickness is 100 - 300 nm. Further, the growth thickness of the first thin film layer is less than that of the second thin film layer.

[0043] It is understandable that only n-hexane is introduced into the first thin film layer, and the Si substrate is carbonized at high temperature to form a SiC thin film with the Si atoms on the surface of the Si substrate. At this time, the surface of the formed SiC thin film is relatively rough, which is beneficial to releasing the stress between the Si substrate, the second thin film layer and the epitaxial layer. Moreover, the thickness of the first thin film layer is relatively thin, and the influence on the crystal quality is very small. The second thin film layer is formed by reacting n-hexane and silane to generate a SiC thin film. At this time, the surface of the formed SiC thin film is relatively flat and the crystal quality is relatively good. In addition, the thickness of the second thin film layer is relatively thick, which can reduce the thermal stress brought by the epitaxial layer during the cooling process, thereby reducing the surface defects of the epitaxial layer. And the thermal mismatch between the epitaxial layer and SiC is 25%, and the thermal expansion coefficient of SiC is 3.8*10 -6 / K, which is between the thermal expansion coefficient of GaN of 5.59*10 -6 / K and the thermal expansion coefficient of Si of 2.59*10 -6 / K; Secondly, the lattice mismatch between the GaN epitaxial layer and SiC is 3.5%, which is much smaller than the lattice mismatch of 17% between the GaN epitaxial layer and Si. Inserting a SiC thin film on the Si substrate can reduce the lattice mismatch degree during the GaN epitaxial growth process, and finally improve the crystal quality of the GaN epitaxial layer.

[0044] Step S12, grow a nucleation layer, a high-resistance buffer layer, a channel layer, an insertion layer, a barrier layer and a cap layer on the second thin film layer in sequence.

[0045] Specifically, control the temperature to be adjusted to 1100°C - 1300°C, the growth pressure to be 30 - 70 mbar, use nitrogen as the carrier gas, and introduce ammonia and trimethylaluminum to grow a nucleation layer on the second thin film layer. Then, grow a high-resistance buffer layer, a channel layer, an insertion layer, a barrier layer and a cap layer epitaxially on the nucleation layer in sequence. Specifically, control the temperature to be 1000°C - 1200°C, the pressure to be 40 - 70 mbar, and introduce a preset carrier gas, a precursor and a gallium source to grow a high-resistance buffer layer on the nucleation layer; control the temperature to be 1000°C - 1150°C, the pressure to be 100 - 300 mbar, and introduce a preset carrier gas, a precursor and a gallium source to grow a channel layer on the high-resistance buffer layer; control the temperature to be 1050°C - 1150°C, the pressure to be 40 - 70 mbar, and introduce a preset carrier gas, a precursor and a gallium source to grow an insertion layer, a barrier layer and a cap layer on the channel layer in sequence.

[0046] Exemplarily, the high-resistance buffer layer is a carbon-doped AlGaN layer with a thickness of 2.0 - 4.0 μm and a C doping concentration of 10 19 cm -3 -10 20 cm -3Between them, the Al component ranges from 0.2 to 0.8; the channel layer is a GaN layer with a thickness of 300 to 600 nm; the insertion layer is an AlN layer with a thickness of 1 nm; the barrier layer is an AlGaN layer with a thickness of 20 to 25 nm and an Al component of 0.20 to 0.25; the cap layer is a GaN layer with a thickness of 3 to 10 nm; trimethylaluminum (TMAl), trimethylgallium or triethylgallium (TMGa or TEGa), and NH3 are used as precursors for group III and group V sources respectively, carbon tetrabromide (CBr4) is used as a precursor for the carbon (C) source, n-hexane (C6H 14 ) and silane (SiH4) are used as precursors for growing the SiC film, and N2 and H2 are used as carrier gases.

[0047] It should be noted that since SiC easily adsorbs H2, N2 should be used as the carrier gas during both the growth and post-growth stages of the SiC film. It is not advisable to use H2 as the carrier gas to avoid affecting the crystal quality of the SiC film and the subsequent AlN layer and epitaxial layer films. After the growth of the high-temperature AlN nucleation layer is completed, a subsequent epitaxial layer structure can use a mixed gas of H2, N2, or H2 / N2 as the carrier gas.

[0048] On the other hand, the present invention also provides an epitaxial wafer, which is prepared by the above-described epitaxial wafer preparation method. The epitaxial wafer includes:

[0049] A substrate;

[0050] A first thin film layer, a second thin film layer, a nucleation layer, a high-resistance buffer layer, a channel layer, an insertion layer, a barrier layer, and a cap layer that are sequentially stacked on the substrate.

[0051] Exemplarily, the substrate is a Si substrate, the first thin film layer and the second thin film layer are both SiC layers, the nucleation layer and the insertion layer are both AlN layers, the high-resistance buffer layer and the barrier layer are both AlGaN layers, and the channel layer and the cap layer are both GaN layers.

[0052] On the other hand, the present invention also provides a high electron mobility transistor including the above-described epitaxial wafer.

[0053] To facilitate understanding of the present invention, the present invention will be described more comprehensively below with reference to related embodiments. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0054] Example 1

[0055] Provide a substrate;

[0056] Using nitrogen as the carrier gas, hexane is introduced, and the substrate is carbonized under the conditions of a growth pressure of 50 mbar and a growth temperature of 1100 °C to grow a first thin film layer with a thickness of 10 nm on the substrate. Then, hexane and silane are continuously introduced, and under the conditions of a growth pressure of 30 mbar and a growth temperature of 1200 °C, a second thin film layer with a thickness of 300 nm is grown on the first thin film layer;

[0057] An AlN nucleation layer, an AlGaN high-resistance buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer, and a GaN cap layer are successively grown on the second thin film layer.

[0058] Example 2

[0059] This example also proposes a method for preparing an epitaxial wafer. The difference between this example and the method for preparing an epitaxial wafer proposed in Example 1 is that:

[0060] The growth thickness of the first thin film layer is 15 nm.

[0061] Example 3

[0062] This example also proposes a method for preparing an epitaxial wafer. The difference between this example and the method for preparing an epitaxial wafer proposed in Example 1 is that:

[0063] The growth thickness of the first thin film layer is 20 nm.

[0064] Example 4

[0065] This example also proposes a method for preparing an epitaxial wafer. The difference between this example and the method for preparing an epitaxial wafer proposed in Example 1 is that:

[0066] The growth thickness of the first thin film layer is 15 nm, and the growth thickness of the second thin film layer is 100 nm.

[0067] Example 5

[0068] This example also proposes a method for preparing an epitaxial wafer. The difference between this example and the method for preparing an epitaxial wafer proposed in Example 1 is that:

[0069] The growth thickness of the first thin film layer is 15 nm, and the growth thickness of the second thin film layer is 200 nm.

[0070] Example 6

[0071] This example also proposes a method for preparing an epitaxial wafer. The difference between this example and the method for preparing an epitaxial wafer proposed in Example 1 is that:

[0072] The growth thickness of the first thin film layer is 15 nm, and the growth thickness of the second thin film layer is 400 nm.

[0073] Example 7

[0074] This example also proposes a method for preparing an epitaxial wafer. The difference between this example and the method for preparing an epitaxial wafer proposed in Example 1 is that:

[0075] The growth thickness of the first thin film layer is 15 nm, and the growth pressure of the second thin film layer is 20 mbar.

[0076] Example 8

[0077] This example also proposes a method for preparing an epitaxial wafer. The difference between this example and the method for preparing an epitaxial wafer proposed in Example 1 is that:

[0078] The growth thickness of the first thin film layer is 15 nm, and the growth pressure of the second thin film layer is 40 mbar.

[0079] Example 9

[0080] This example also proposes a method for preparing an epitaxial wafer. The difference between this example and the method for preparing an epitaxial wafer proposed in Example 1 is that:

[0081] The growth thickness of the first thin film layer is 15 nm, and the growth pressure of the second thin film layer is 50 mbar.

[0082] Example 10

[0083] This example also proposes a method for preparing an epitaxial wafer. The difference between this example and the method for preparing an epitaxial wafer proposed in Example 1 is that:

[0084] The growth thickness of the first thin film layer is 15 nm, and the growth temperature of the second thin film layer is 1100 °C.

[0085] Example 11

[0086] This example also proposes a method for preparing an epitaxial wafer. The difference between this example and the method for preparing an epitaxial wafer proposed in Example 1 is that:

[0087] The growth thickness of the first thin film layer is 15 nm, and the growth temperature of the second thin film layer is 1150 °C.

[0088] Example 12

[0089] This example also proposes a method for preparing an epitaxial wafer. The difference between this example and the method for preparing an epitaxial wafer proposed in Example 1 is that:

[0090] The growth thickness of the first thin film layer is 15 nm, and the growth temperature of the second thin film layer is 1250 °C.

[0091] To compare with the above embodiments of the present invention, the present invention also provides the following comparative examples.

[0092] Comparative Example 1

[0093] The present invention also provides a method for preparing an epitaxial wafer in a comparative example. The difference between this comparative example and Embodiment 1 of the present invention is as follows:

[0094] In Comparative Example 1, it is a traditional method for preparing an epitaxial wafer, in which an AlN nucleation layer is directly grown on a substrate, and no first thin film layer and second thin film layer are inserted between the substrate and the AlN nucleation layer.

[0095] Please refer to Table 1 below, which shows the parameters corresponding to Embodiments 1-12 and Comparative Example 1 of the present invention.

[0096] Table 1

[0097]

[0098] In Table 1 above, both the first thin film layer and the second thin film layer are SiC layers. In practical applications, the corresponding epitaxial wafers are prepared by using the preparation methods and parameters corresponding to Embodiments 1-12 and Comparative Example 1 of the present invention respectively, and then X-ray diffraction tests (XRD) are carried out to test the half-width (XRD-002, XRD-102) of the preset plane and breakdown voltage and other test experiments. The test data are shown in Table 2 below. It should be noted that in order to ensure the reliability of the verification results, in the preparation of the corresponding epitaxial wafers in Embodiments 1-12 and Comparative Example 1 of the present invention, except for the above different parameters, other aspects should be the same, that is, the preparation processes and parameters of other layers should be kept consistent.

[0099] Table 2:

[0100]

[0101] Combining the data in Table 1 and Table 2 above, it can be clearly seen that the present invention grows a SiC thin film on the surface of the Si substrate to relieve the thermal stress during the cooling process, reduce the surface defects of the epitaxial layer, and the first thin film layer only introduces n-hexane. At this time, the surface of the formed SiC thin film is relatively rough, which is beneficial to releasing the stress between the Si substrate, the second thin film and the epitaxial layer. The second SiC thin film is a SiC thin film formed by the reaction of n-hexane and silane. At this time, the surface of the formed SiC thin film is relatively flat and the crystal quality is relatively good, which can reduce the thermal stress brought by the epitaxial layer during the cooling process. At the same time, inserting a SiC thin film on the Si substrate can also reduce the lattice mismatch during the GaN epitaxial growth process, and finally improve the crystal quality of the epitaxial layer.

[0102] In addition, it can be clearly seen by combining Examples 1 to 3 and Examples 4 to 6 that the reasonable growth thicknesses of the first thin film layer and the second thin film layer both promote the improvement of the crystal quality of the epitaxial wafer. And the best performance is achieved when the thickness of the first thin film layer is 15 and the thickness of the second thin film layer is 300. This is because the first thin film layer is mainly used to release the stress between the Si substrate, the second thin film layer, and the epitaxial layer. Therefore, the thickness of the first thin film layer is relatively thin and has little impact on the crystal quality. While the thickness of the second thin film layer with good crystal quality is set relatively thick, which can reduce the thermal stress brought by the epitaxial layer during the cooling process, thereby reducing the surface defects of the epitaxial layer.

[0103] It can be clearly seen by combining Examples 7 to 12 that the reasonable growth conditions of the first thin film layer and the second thin film layer both promote the improvement of the crystal quality of the epitaxial wafer. And the best performance is achieved when the growth pressure is 30 mbar and the growth temperature is 1200 °C.

[0104] Please refer to Figures 2 to 3 , which shows the surface edge conditions of the traditional epitaxial wafer and the epitaxial wafer prepared in this application. It can be clearly seen from the figure that the surface flatness of the epitaxial wafer prepared in this application is higher than that of the epitaxial wafer prepared by the traditional method, thereby significantly improving the crystal quality of the epitaxial wafer.

[0105] The above-described embodiments only represent several implementation manners of the present invention. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the appended claims.

Claims

1. A method for preparing an epitaxial wafer, characterized in that, The method includes: providing a substrate; using nitrogen as a carrier gas to introduce n-hexane to carbonize the substrate, so as to grow a first thin film layer on the substrate, and continuously introducing n-hexane and silane to grow a second thin film layer on the first thin film layer; successively growing a nucleation layer, a high-resistance buffer layer, a channel layer, an insertion layer, a barrier layer, and a cap layer on the second thin film layer; wherein, both the first thin film layer and the second thin film layer are SiC layers.

2. The method for preparing an epitaxial wafer according to claim 1, wherein The growth temperatures of both the first thin film layer and the second thin film layer are 1100°C - 1300°C.

3. The method for preparing an epitaxial wafer according to claim 1, wherein The growth pressures of both the first thin film layer and the second thin film layer are 30 - 70 mbar.

4. The method for preparing an epitaxial wafer according to claim 1, wherein The growth thickness of the first thin film layer is less than that of the second thin film layer.

5. The method for preparing an epitaxial wafer according to claim 4, wherein The growth thickness of the first thin film layer is 10 - 20 nm, and the growth thickness of the second thin film layer is 100 - 300 nm.

6. The method for preparing an epitaxial wafer according to claim 1, wherein The step of successively growing a nucleation layer, a high-resistance buffer layer, a channel layer, an insertion layer, a barrier layer, and a cap layer on the second thin film layer includes: controlling the temperature to be adjusted to 1100°C - 1300°C and the growth pressure to be 30 - 70 mbar, using nitrogen as a carrier gas, and introducing ammonia and trimethylaluminum to grow a nucleation layer on the second thin film layer; controlling the temperature to be 1000°C - 1200°C and the pressure to be 40 - 70 mbar, and introducing a preset carrier gas, a precursor, and a gallium source to grow a high-resistance buffer layer on the nucleation layer; controlling the temperature to be 1000°C - 1150°C and the pressure to be 100 - 300 mbar, and introducing a preset carrier gas, a precursor, and a gallium source to grow a channel layer on the high-resistance buffer layer; controlling the temperature to be 1050°C - 1150°C and the pressure to be 40 - 70 mbar, and introducing a preset carrier gas, a precursor, and a gallium source to successively grow an insertion layer, a barrier layer, and a cap layer on the channel layer.

7. The method for preparing an epitaxial wafer according to any one of claims 1 to 6, characterized in that Before the step of using nitrogen as a carrier gas to introduce n-hexane to carbonize the substrate, so as to grow a first thin film layer on the substrate, and continuously introducing n-hexane and silane to grow a second thin film layer on the first thin film layer, it further includes: treating the substrate at a temperature of 1000 - 1200°C in an H2 atmosphere for 5 - 10 min, and then introducing N2 to purge for 1 - 5 min.

8. An epitaxial wafer, characterized in that, The epitaxial wafer is prepared by the epitaxial wafer preparation method according to any one of claims 1 to 7, and the epitaxial wafer includes: a substrate; a first thin film layer, a second thin film layer, a nucleation layer, a high-resistance buffer layer, a channel layer, an insertion layer, a barrier layer, and a cap layer that are successively stacked on the substrate.

9. The epitaxial wafer according to claim 8, characterized in that, The substrate is a Si substrate, both the first thin film layer and the second thin film layer are SiC layers, both the nucleation layer and the insertion layer are AlN layers, both the high-resistance buffer layer and the barrier layer are AlGaN layers, and both the channel layer and the cap layer are GaN layers.

10. A high electron mobility transistor, characterized in that, including the epitaxial wafer according to any one of claims 8 to 9.

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