Semiconductor device with electrical components built into a circuit board

Abstract

A semiconductor device includes a substrate body (12) having a first surface (12a) and a second surface (12b); an electrical component (21, 22, 31, 32) disposed in the substrate body; a surface conductor pattern (70) disposed in a first circuit layer (L6) on the second surface; a first internal conductor pattern (68) and a second internal conductor pattern (69) disposed in a second circuit layer (L5) between the electrical component and the second surface and insulated from each other; at least one first thermal conductor via (77) extending from the electrical component to the first internal conductor pattern; and at least one second thermal conductor via (78a, 78b) extending from the surface conductor pattern to the second internal conductor pattern.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device having electrical components built into a circuit board. Background Technology

[0002] Patent Document 1 discloses a semiconductor device. The semiconductor device includes a substrate body (as a core substrate) and electrical components disposed within the substrate body. A surface conductor pattern is provided on the lower surface of the substrate body, and an internal conductor pattern is provided between the electrical components and a second surface. The electrical components and the first internal conductor pattern are then connected through a plurality of thermally conductive vias. According to this configuration, heat from the electrical components is transferred through the plurality of thermally conductive vias to the internal conductor pattern, further from the internal conductor pattern to the surface conductor pattern, and radiated to the outside of the substrate body.

[0003] Existing technical documents

[0004] [Patent Literature]

[0005] Patent Document 1: JP-2020-9879-A Summary of the Invention

[0006] In the aforementioned semiconductor device, an insulating layer made of the substrate body material is provided between the inner conductor pattern and the surface conductor pattern. This configuration provides electrical insulation between the inner and surface conductor patterns. However, a challenge arises because the insulating layer may suppress heat conduction from the inner conductor pattern to the surface conductor pattern. Furthermore, although multiple thermally conductive vias are arranged in the layer located on one side of the inner conductor pattern, these vias are not arranged in the insulating layer located on the other side of the inner conductor pattern. Consequently, there is a significant difference in mechanical properties between the two layers adjacent to the inner conductor pattern. As a result, a potential problem when the temperature of the substrate body rises is the induction of non-uniform thermal deformation of the substrate body, such as warping or corrugation.

[0007] In view of the above, this embodiment provides a technology that can improve the thermal conductivity and mechanical properties of the substrate body while maintaining the insulation properties of electrical components in a semiconductor device having electrical components built into the circuit board.

[0008] The semiconductor device disclosed in this embodiment includes: a substrate body having a first surface and a second surface; an electrical component disposed in the substrate body; a surface conductor pattern disposed in a circuit layer located on the second surface; a first internal conductor pattern and a second internal conductor pattern disposed in the circuit layer between the electrical component and the second surface, and insulated from each other; at least one first thermal conductor via extending from the electrical component to the first internal conductor pattern; and at least one second thermal conductor via extending from the surface conductor pattern to the second internal conductor pattern.

[0009] In the above configuration, the circuit layer located between the electrical component and the second surface has a first internal conductor pattern and a second internal conductor pattern that are insulated from each other. The first internal conductor pattern is connected to the electrical component through at least one first thermal conductor via. The second internal conductor pattern is connected to the surface conductor pattern on the second surface through at least one second thermal conductor via. As a result, heat generated in the electrical component is transferred to the first internal conductor pattern through the first thermal conductor via and further to the second internal conductor pattern. Then, the heat of the second internal conductor pattern is transferred to the surface conductor pattern through the second thermal conductor via and radiated from the surface conductor pattern to the outside of the substrate body. Although the first and second internal conductor patterns are isolated from each other, they are located in the same circuit layer, so the heat transfer between them is relatively high. Furthermore, since the first and second thermal conductor vias are arranged in two layers adjacent to the circuit layer, there is no significant difference in the mechanical properties between the two layers. As described above, the thermal conductivity and mechanical properties of the substrate body can be improved while maintaining the insulation performance of the electrical component. Attached Figure Description

[0010] The above and other objects, features, and advantages of this disclosure will become more apparent from the following detailed description with reference to the accompanying drawings. In the drawings:

[0011] Figure 1 This is a plan view showing the semiconductor device of the first embodiment;

[0012] Figure 2 This is a circuit diagram illustrating the circuit structure of the semiconductor device according to the first embodiment;

[0013] Figure 3 It is along Figure 1 The cross-sectional view taken by line III-III in the figure; for clarity, the cross-sectional lines of the substrate body are omitted, and further, some overlapping configurations are shown by intentionally changing their positions;

[0014] Figure 4 This is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment; and

[0015] Figure 5 This is a cross-sectional view showing the structure of a semiconductor device according to a third embodiment. Detailed Implementation

[0016] In one embodiment of this invention, at least one second thermally conductive via may include an internal thermally conductive via 78a located in the region where the electrical component and the second surface face each other, and an external thermally conductive via 78b located outside the facing region. With this configuration, the second thermally conductive via can be effectively positioned within a range where heat generated in the electrical component diffuses through the substrate body.

[0017] In one embodiment of this invention, the semiconductor device may include: a third inner conductor pattern 66 disposed in a circuit layer 14 and electrically insulated from the electrical component, the circuit layer 14 being located at the same depth as the electrical component; and at least one third via 79 extending from the second conductor pattern to the third inner conductor pattern. According to this configuration, heat generated by the electrical component can be directed to the second surface of the substrate body from more directions relative to the electrical component.

[0018] In one embodiment of this invention, the substrate body may include a first layer 13 made of a first material and a second layer 15 made of a second material having a higher thermal conductivity than the first material. In this case, the second layer may be located between the electrical components and the second surface. According to this configuration, heat generated by the electrical components can be diffused over a wide area of ​​the substrate body through the second layer.

[0019] In the above embodiment, the second layer may be exposed on the second surface. With this configuration, heat diffused within the substrate body through the second layer can radiate from the second surface of the substrate body to the outside of the substrate body.

[0020] In the above embodiments, the second material may include at least one selected from the group consisting of paper, glass cloth, glass nonwoven fabric, glass woven fabric, and glass fiber, and at least one selected from the group consisting of phenolic resin, epoxy resin, polyimide resin, and Teflon (registered trademark). According to this configuration, the thermal conductivity of the second layer can be effectively enhanced while maintaining the original properties required by the substrate body.

[0021] In one embodiment of this disclosure, the semiconductor device may further include a surface electrical component disposed on a first surface and controlling the operation of electrical components. According to the configuration of this embodiment, most of the heat generated by the electrical components can be directed to a second surface of the substrate body, and the temperature rise of the first surface of the substrate body is suppressed. By disposing the surface electrical component on the first surface, the temperature rise of the surface electrical component can be suppressed.

[0022] In one embodiment, the material constituting the first thermally conductive via can be the same as the material constituting the first internal conductor pattern. With this configuration, for example, during the fabrication of a semiconductor device, the first thermally conductive via and the first internal conductor pattern can be formed simultaneously or sequentially.

[0023] In one embodiment, the material constituting the second thermally conductive via can be the same as the material constituting the surface conductor pattern. With this configuration, for example, during the fabrication of a semiconductor device, the second thermally conductive via and the surface conductor pattern can be formed simultaneously or sequentially.

[0024] In one embodiment of this disclosure, the electrical components may include power semiconductor devices 21, 22 and heat sinks 31, 32 to which the power semiconductor devices are bonded. Because the power semiconductor devices carry relatively large currents, the heat generated is also relatively large. The configuration disclosed herein is applicable to semiconductor devices including such power semiconductor devices.

[0025] (Example 1)

[0026] The semiconductor device 10 of the first embodiment will be described with reference to the accompanying drawings. The semiconductor device 10 of this embodiment is used, for example, in a power control unit of an electric vehicle and can form part of a power conversion circuit for power conversion between a power source and a drive motor. In this embodiment, "electric vehicle" broadly refers to a vehicle having a motor for driving wheels, and includes, for example, electric vehicles charged by external power, hybrid electric vehicles having an engine in addition to a motor, fuel cell vehicles having a fuel cell as a power source, etc. However, the application of the semiconductor device 10 according to this embodiment is not limited to electric vehicles and can be applied to various electrical devices.

[0027] like Figures 1 to 3 As shown, the semiconductor device 10 includes a substrate body 12, two semiconductor elements 21 and 22, and two heat sinks 31 and 32. The substrate body 12 has a plate-like or sheet-like shape. The substrate body 12 has an upper surface 12a and a lower surface 12b. The lower surface 12b is disposed on the side opposite to the upper surface 12a. The substrate body 12 is made of an insulator such as epoxy resin or other resin material. The substrate body 12 includes an upper layer 14, an intermediate layer 16, and a lower layer 18 in order from the upper surface 12a to the lower surface 12b. The upper layer 14 is the layer that includes the upper surface 12a of the substrate body 12. The lower layer 18 is the layer that includes the lower surface 12b of the substrate body 12. The intermediate layer 16 is the layer disposed between the upper layer 14 and the lower layer 18.

[0028] In the attached figures, the X and Y directions are parallel to the upper surface 12a and lower surface 12b of the substrate body 12, and are perpendicular to each other. The Z direction is perpendicular to the upper surface 12a and lower surface 12b of the substrate body 12, and is perpendicular to each of the X and Y directions. That is, the upper layer 14, the middle layer 16, and the lower layer 18 are stacked along the Z direction.

[0029] Semiconductor elements 21 and 22, and heat sinks 31 and 32, are electrical components forming part of the circuitry in the semiconductor device 10. The two semiconductor elements 21 and 22, together with the two heat sinks 31 and 32, are disposed in the intermediate layer 16 of the substrate body 12. Each of the semiconductor elements 21 and 22 is a power semiconductor element, particularly a switching element. This switching element is, for example, an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor).

[0030] Semiconductor elements 21 to 22 each have upper surface electrodes 21a to 22a and lower surface electrodes 21b to 22b, and conduct or block conduction between the corresponding upper surface electrodes 21a to 22a and the corresponding lower surface electrodes 21b to 22b.

[0031] For example, the two semiconductor elements 21 and 22 include a first semiconductor element 21 and a second semiconductor element 22. The first semiconductor element 21 and the second semiconductor element 22 are electrically connected in series within the substrate body 12. As described above, the two semiconductor elements 21 and 22 are switching elements, such as IGBTs or MOSFETs. The semiconductor device 10 of this embodiment can form part of, for example, an inverter circuit or a DC-DC converter circuit. The number of semiconductor elements 21 and 22 is not limited to two. In addition, the semiconductor device 10 may include at least one other electrical component in place of the semiconductor elements 21 and 22 and the heat sinks 31 and 32.

[0032] Two heat sinks 31 and 32 each have a plate-like shape and are arranged parallel to the substrate body 12. Each heat sink 31, 32 is made of a conductor such as copper or other metal. For example, the two heat sinks 31 and 32 are arranged along the X direction. The two heat sinks 31 and 32 include a first heat sink 31 and a second heat sink 32. A first semiconductor element 21 is disposed on the first heat sink 31, and the lower surface electrode 21b of the first semiconductor element 21 is electrically connected to the first heat sink 31. The first semiconductor element 21 and the first heat sink 31 are integrally bonded to each other and can be interpreted as a single electrical component. Similarly, a second semiconductor element 22 is disposed on the second heat sink 32, and the lower surface electrodes 21b and 22b of the second semiconductor element 22 are electrically connected to the second heat sink 32. The second semiconductor element 22 and the second heat sink 32 are also integrally bonded to each other and can be interpreted as a single electrical component.

[0033] Semiconductor device 10 includes a plurality of terminals 40, 42, and 44. These terminals 40, 42, and 44 are external connection terminals for connection to external circuitry. The plurality of terminals 40, 42, and 44 are made of a conductor such as copper or other metal. For example, the plurality of terminals 40, 42, and 44 include a P terminal 40, an N terminal 42, and an O terminal 44. The plurality of terminals 40, 42, and 44 are disposed on the lower surface 12b of the substrate body 12. Here, some or all of the plurality of terminals 40, 42, and 44 may be disposed on the upper surface 12a of the substrate body 12.

[0034] P terminal 40 is electrically connected to a first heat sink 31 within the substrate body 12, and is electrically connected to the lower surface electrode 21b of the first semiconductor element 21 via the first heat sink 31. N terminal 42 is electrically connected to the upper surface electrode 22a of the second semiconductor element 22 within the substrate body 12. O terminal 44 is electrically connected to the upper surface electrode 21a of the first semiconductor element 21 and the second heat sink 32 within the substrate body 12. That is, O terminal 44 is electrically connected to each of the upper surface electrode 21a of the first semiconductor element 21 and the lower surface electrode 22b of the second semiconductor element 22. As a result, when the first semiconductor element 21 is turned on, P terminal 40 and O terminal 44 are electrically connected to each other. On the other hand, when the second semiconductor element 22 is turned on, N terminal 42 and O terminal 44 are electrically connected to each other.

[0035] The substrate body 12 has multiple circuit layers L1-L6 to form a multilayer substrate structure. The multiple circuit layers L1-L6 include a first circuit layer L1, a second circuit layer L2, a third circuit layer L3, a fourth circuit layer L4, a fifth circuit layer L5, and a sixth circuit layer L6. The first circuit layer L1 is disposed on the upper surface 12a of the substrate body 12. The second circuit layer L2 is disposed in the upper layer 14 of the substrate body 12. The third circuit layer L3 is disposed at the boundary between the upper layer 14 and the intermediate layer 16 of the substrate body 12. The fourth circuit layer L4 is disposed at the boundary between the intermediate layer 16 and the lower layer 18 of the substrate body 12. The fifth circuit layer L5 is disposed in the lower layer 18 of the substrate body 12. The sixth circuit layer L6 is disposed on the lower surface 12b of the substrate body 12.

[0036] The first circuit layer L1 has a first conductor pattern 61. The first conductor pattern 61 is made of a conductor, such as copper or other metal. The first conductor pattern 61 constitutes a control circuit 50 that controls two semiconductor elements 21 and 22. Therefore, a plurality of surface electrical components 52 are mounted on the first conductor pattern 61. The plurality of surface electrical components 52 include, for example, gate drive circuits that control the switching of semiconductor elements 21 and 22.

[0037] The first conductor pattern 61 mentioned here is a general term for one or more conductor patterns required to form the control circuit 50. That is, the first conductor pattern 61 can be a single conductor pattern or a combination of multiple conductor patterns. The same applies to the second conductor patterns 62 to the tenth conductor patterns 70 described below. Each of the second conductor patterns 62 to the tenth conductor patterns 70 is a general term for one or more conductor patterns having a common function, and can be a single conductor pattern or a combination of multiple conductor patterns.

[0038] The second circuit layer L2 has multiple conductor patterns 62, 63, and 64. Each conductor pattern 62, 63, and 64 is made of a conductor such as copper or other metal. The multiple conductor patterns 62, 63, and 64 include a second conductor pattern 62, a third conductor pattern 63, and a fourth conductor pattern 64. Here, the multiple conductor patterns 62, 63, and 64 are actually arranged on the same plane, but... Figure 3 In order to make the illustration clear, the second conductor pattern 62 is intentionally shifted relative to the third conductor pattern 63 and the fourth conductor pattern 64.

[0039] The second conductor pattern 62 extends over a large portion of the second circuit layer L2 and faces the plurality of semiconductor elements 21 and 22. As a result, heat generated in the semiconductor elements 21 and 22 is diffused through the second conductor pattern 62 over a wide area of ​​the substrate body 12. The second conductor pattern 62 also serves as a shielding layer, shielding electromagnetic noise radiated from the semiconductor elements 21 and 22. Although there are no particular limitations, the second conductor pattern 62 can be connected to ground potential, thereby improving its function as a shielding layer.

[0040] The third conductor pattern 63 is connected to the O terminal 44 through the first via 71. Furthermore, the third conductor pattern 63 is connected to the upper surface electrode 21a of the first semiconductor element 21 and the second heat sink 32 through two second vias 72. The first via 71 and the second via 72 are made of a conductor such as copper or another metal. As a result, the two semiconductor elements 21 and 22 are electrically connected in series through the second conductor pattern 62 and electrically connected to the O terminal 44 through the second conductor pattern 62.

[0041] The fourth conductor pattern 64 is connected to the upper surface electrode 22a of the second semiconductor element 22 through the third via 73. Furthermore, the fourth conductor pattern 64 is connected to the N-terminal 42 through the fourth via 74. The third via 73 and the fourth via 74 are made of conductors such as copper or other metals. As a result, the upper surface electrode 22a of the second semiconductor element 22 is electrically connected to the N-terminal 42 through the fourth conductor pattern 64.

[0042] Semiconductor elements 21 and 22, and heat sinks 31 and 32, are disposed in the third circuit layer L3 and the fourth circuit layer L4. The thickness of the heat sinks 31 and 32 is equal to the distance from the third circuit layer L3 to the fourth circuit layer L4. Semiconductor elements 21 and 22 disposed on the heat sinks 31 and 32 are disposed in the third circuit layer L3. Furthermore, the third circuit layer L3 and the fourth circuit layer L4 are respectively provided with a fifth conductor pattern 65 and a sixth conductor pattern 66. The use of the fifth conductor pattern 65 and the sixth conductor pattern 66 is not particularly limited. The fifth conductor pattern 65 and the sixth conductor pattern 66 can be connected to, for example, ground potential.

[0043] The fifth circuit layer L5 has multiple conductor patterns 67, 68, and 69. Each conductor pattern 67, 68, and 69 is made of a conductor such as copper or other metal. The multiple conductor patterns 67, 68, and 69 include a seventh conductor pattern 67, an eighth conductor pattern 68, and a ninth conductor pattern 69. Here, the multiple conductor patterns 67, 68, and 69 are actually arranged on the same plane, but... Figure 3 In order to make the illustration clear, the seventh conductor pattern 67 is intentionally shifted relative to the eighth conductor pattern 68 and the ninth conductor pattern 69.

[0044] The seventh conductor pattern 67 is connected to the first heat sink 31 through the fifth via 75. Furthermore, the seventh conductor pattern 67 is connected to the P-terminal 40 through the sixth via 76. The fifth via 75 and the sixth via 76 are made of conductors such as copper or other metals. As a result, the lower surface electrode 21b of the first semiconductor element 21 is electrically connected to the P-terminal 40 through the first heat sink 31 and the seventh conductor pattern 67.

[0045] An eighth conductor pattern 68 is disposed in the area facing the first heat sink 31 or the second heat sink 32. The eighth conductor pattern 68 is connected to the first heat sink 31 and the second heat sink 32 through a plurality of seventh vias 77. Each seventh via 77 is made of a conductor such as copper or other metal. As a result, the eighth conductor pattern 68 is electrically and thermally connected to the first heat sink 31 and the seventh conductor pattern 67 through the plurality of seventh vias 77. Although there are no particular limitations, the material constituting the plurality of seventh vias 77 can be the same as the material constituting the eighth conductor pattern 68, and can be, for example, copper or aluminum.

[0046] In the ninth conductor pattern 69, the ninth conductor pattern 69 is positioned adjacent to the eighth conductor pattern 68, such that heat from the eighth conductor pattern 68 is effectively transferred to the ninth conductor pattern 69. Here, the eighth conductor pattern 68 and the ninth conductor pattern 69 are separated by the material constituting the substrate body 12, and the eighth conductor pattern 68 and the ninth conductor pattern 69 are electrically insulated from each other. A portion of the ninth conductor pattern 69 is located within the area facing the first heat sink 31 or the second heat sink 32, and another portion of the ninth conductor pattern 69 is located outside this facing area.

[0047] Multiple eighth vias 78a and 78b are connected to the ninth conductor pattern 69. The multiple eighth vias 78a and 78b extend from the ninth conductor pattern 69 to the sixth circuit layer L6 located on the lower surface 12b of the substrate body 12. Each eighth via 78a, 78b is made of a conductor such as copper or other metal. As a result, the ninth conductor pattern 69 is electrically and thermally connected to the sixth circuit layer L6 through the multiple eighth vias 78a and 78b.

[0048] The plurality of eighth vias 78a, 78b include at least one internal via 78a and at least one external via 78b. The internal via 78a is located in the facing region of the first heat sink 31 or the second heat sink 32 opposite to the lower surface 12b of the substrate body 12. On the other hand, the external via 78b is located outside this facing region. The range in which the plurality of eighth vias 78a and 78b are provided is designed to match the area through which heat from the first heat sink 31 or the second heat sink 32 diffuses within the substrate body 12.

[0049] The sixth circuit layer L6 has a tenth conductor pattern 70. The tenth conductor pattern 70 extends over a large portion of the sixth circuit layer L6 and is positioned to face the ninth conductor pattern 69 of the fifth circuit layer L5. The tenth conductor pattern 70 is made of a conductor such as copper or another metal. A plurality of eighth vias 78a and 78b are connected to the tenth conductor pattern 69. As a result, the tenth conductor pattern 70 is electrically and thermally connected to the ninth conductor pattern 69 of the fifth circuit layer L5 through the plurality of eighth vias 78a and 78b. Although not particularly limited, the material constituting the tenth conductor pattern 70 can be the same as the material constituting the eighth vias 78a and 78b, and can be, for example, copper or aluminum.

[0050] As described above, in the semiconductor device 10 of this embodiment, the tenth conductor pattern 70 is disposed in the circuit layer L6 located on the lower surface 12b of the substrate body 12. The mutually insulated eighth conductor pattern 68 and ninth conductor pattern 69 are disposed in the circuit layer L5 located between the heat sinks 31 and 32 and the lower surface 12b of the substrate body 12. The heat sinks 31 and 32 and the eighth conductor pattern 68 are connected to each other through at least one seventh via 77. The ninth conductor pattern 69 and the tenth conductor pattern 70 are connected to each other through at least one eighth via 78a and 78b.

[0051] According to the above configuration, the heat generated in semiconductor elements 21 and 22 and heat sinks 31 and 32 is transferred through the seventh via 77 to the eighth conductor pattern 68, and further to the ninth conductor pattern 69 adjacent to the eighth conductor pattern 68. Then, the heat from the ninth conductor pattern 69 is transferred through the eighth vias 78a and 78b to the tenth conductor pattern 70, and radiated from the tenth conductor pattern 70 to the outside of the substrate body 12. Although the eighth conductor pattern 68 and the ninth conductor pattern 69 are isolated from each other, they are located in the same fifth circuit layer L5, so the heat transfer between them is relatively high. Furthermore, since the seventh via 77 and the eighth vias 78a and 78b are arranged in two adjacent layers above and below the fifth circuit layer L5, there is no significant difference in mechanical properties between the two layers. As described above, while maintaining the insulation properties of semiconductor elements 21 and 22 and heat sinks 31 and 32, the thermal conductivity and mechanical properties of the substrate body 12 can be improved.

[0052] The semiconductor device 10 according to the first embodiment is an embodiment of the technology disclosed in this specification, and the content of this technology is not particularly limited. The substrate body 12 in this embodiment is an example of a substrate in this technology. The upper surface 12a and lower surface 12b of the substrate body 12 in this embodiment are examples of the first surface and the second surface of the substrate body in this technology, respectively. In this embodiment, the combination of the first semiconductor element 21 and the first heat sink 31, and the combination of the second semiconductor element 22 and the second heat sink 32, are examples of electrical components in this disclosure. The tenth conductor pattern 70 in this embodiment is an example of a surface conductor pattern in this disclosure. The eighth conductor pattern 68 in this embodiment is an example of a first internal conductor pattern in this technology. The ninth conductor pattern 69 in this embodiment is an example of a second internal conductor pattern in this disclosure. The ninth via 79 in this embodiment is an example of a thermal conductor via in this disclosure. The seventh via 77 in this embodiment is an example of a first thermal conductor via in this disclosure. The eighth vias 78a and 78b in this embodiment are examples of second thermal conductor vias in this disclosure. In the eighth vias 78a and 78b of this embodiment, the internal via 78a is an example of an internal thermal conductor via in this disclosure, and the external via 78b is an example of an external thermal conductor via in this disclosure. The seventh via 77 of this embodiment is an example of a first thermal conductor via in this disclosure. The surface electrical component 52 of this embodiment is an example of a surface electrical component in this technology.

[0053] (Example 2)

[0054] Reference Figure 4The semiconductor device 110 of the second embodiment is described. The semiconductor device 110 of this embodiment differs from the semiconductor device 10 of the first embodiment in that it includes a plurality of ninth vias 79. In the following description, the differences from the first embodiment will be primarily described, and the same reference numerals will be used for configurations common to the first embodiment, and their descriptions will be omitted.

[0055] Multiple ninth vias 79 extend from the fourth circuit layer L4 to the fifth circuit layer L5, connecting the sixth conductor pattern 66 of the fourth circuit layer L4 and the ninth conductor pattern 69 of the fifth circuit layer L5. Each ninth via 79 is made of a conductor such as copper or other metal. As a result, the sixth conductor pattern 66 is electrically and thermally connected to the ninth conductor pattern 69 through the multiple ninth vias 79.

[0056] The sixth conductor pattern 66, located in the fourth circuit layer L4, lies at the same depth as heat sinks 31 and 32. Therefore, the sixth conductor pattern 66 receives heat diffused from heat sinks 31 and 32 in a direction parallel to the substrate body 12 (i.e., in the X or Y direction). The heat from the sixth conductor pattern 66 is transferred to the ninth conductor pattern through the ninth via 79, and further transferred to the tenth conductor pattern 70 through the external via 78b of the eighth vias 78a and 78b. As a result, heat from semiconductor elements 21 and 22, as well as heat sinks 31 and 32, is radiated from the tenth conductor pattern 70 to the outside of the substrate body 12. The sixth conductor pattern 66 is electrically insulated from semiconductor elements 21 and 22, as well as heat sinks 31 and 32.

[0057] The semiconductor device 110 according to this embodiment is an embodiment of the technology disclosed in this specification, and the content of this technology is not particularly limited. The sixth conductor pattern 66 in this embodiment is an example of the third internal conductor pattern in this technology. The ninth via 79 in this embodiment is an example of the third via in this disclosure.

[0058] (Example 3)

[0059] Reference Figure 5 The semiconductor device 210 of the third embodiment is described. The semiconductor device 210 of this embodiment differs from the semiconductor device 110 of the second embodiment in that the substrate body 12 has two layers 13 and 15 made of different materials. Hereinafter, the differences from the second embodiment will be mainly described, and the same reference numerals will be given for configurations common to the first to second embodiments, and their descriptions will be omitted.

[0060] In this embodiment, the substrate body 12 has a first layer 13 made of a first material and a second layer 15 made of a second material. The first layer 13 includes the aforementioned upper layer 14, intermediate layer 16, and a portion of the lower layer 18. The second layer 15 is the remaining portion of the lower layer 18, particularly the portion filling the space between the fifth circuit layer L5 and the sixth circuit layer L6. That is, the second layer 15 is located at the lowest layer including the lower surface 12b of the substrate body 12. The second material constituting the second layer 15 has a higher thermal conductivity than the first material constituting the first layer 13. By positioning the second layer 15, which has excellent thermal conductivity, between the heat sinks 31 and 32 and the lower surface 12b of the substrate body 12, the temperature rise of the semiconductor elements 21 and 22 and the heat sinks 31 and 32 is further suppressed.

[0061] The first and second materials are not particularly limited. For example, the second material can be a composite material including fibers, and therefore the second material can include, for example, at least one selected from the group consisting of paper, glass cloth, glass nonwoven fabric, glass woven fabric and glass fiber, and at least one selected from the group consisting of phenolic resin, epoxy resin, polyimide resin and Teflon (registered trademark). For example, as the first material, resin materials illustrated herein can be used, and, similarly to the second material, fiber materials can be included. The combination of the first and second materials is not particularly limited as long as the thermal conductivity of the second material is higher than that of the first material.

[0062] Although this disclosure has been described with reference to embodiments thereof, it should be understood that this disclosure is not limited to the embodiments and structures. This disclosure is intended to cover various modifications and equivalent substitutions. Furthermore, while various combinations and configurations exist, other combinations and configurations including more, fewer, or only a single element are also within the spirit and scope of this disclosure.

Claims

1. A semiconductor device comprising: a substrate body having a first surface and a second surface; an electrical component disposed in the substrate body; a surface conductor pattern disposed in a first circuit layer located on the second surface; a first internal conductor pattern and a second internal conductor pattern disposed in a second circuit layer located between the electrical component and the second surface and insulated from each other; at least one first thermal conductor via extending from the electrical component to the first internal conductor pattern; and at least one second thermal conductor via extending from the surface conductor pattern to the second internal conductor pattern, wherein: the at least one second thermal conductor via includes an internal thermal conductor via located in a facing region of the electrical component facing the second surface and an external thermal conductor via located outside the facing region.

2. The semiconductor device of claim 1, further comprising: a third internal conductor pattern disposed in a third circuit layer located within a same depth range as the electrical component and electrically isolated from the electrical component; and at least one third via extending from the second internal conductor pattern to the third internal conductor pattern.

3. The semiconductor device of claim 1, wherein: the substrate body includes a first layer made of a first material and a second layer made of a second material having a higher thermal conductivity than the first material; and the second layer is arranged between the electrical component and the second surface.

4. The semiconductor device of claim 3, wherein: the second layer is exposed on the second surface.

5. The semiconductor device of claim 3, wherein: the second material includes: at least one selected from a group consisting of paper, glass cloth, and glass fiber, and at least one selected from a group consisting of phenol resin, epoxy resin, polyimide resin, and Teflon.

6. The semiconductor device of claim 5, wherein: the second material includes at least one selected from a group consisting of glass nonwoven cloth, glass woven cloth.

7. The semiconductor device of claim 1, further comprising: a surface electrical component disposed on the first surface and controlling operation of the electrical component.

8. The semiconductor device of claim 1, wherein: the first thermal conductor via is made of a same material as a material of the first internal conductor pattern.

9. The semiconductor device of claim 1, wherein: the second thermal conductor via is made of a same material as a material of the surface conductor pattern.

10. The semiconductor device of any one of claims 1 to 9, wherein: the electrical component includes a power semiconductor element bonded to a heat sink. ​ ​

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