Power MOSFET gate structure resistant to single-particle gate damage and preparation method
By using high-dielectric-constant composite gate dielectrics and bird-beak-shaped gate dielectric regions in MOSFET devices, the single-particle gate penetration damage problem is solved, the device's radiation resistance is improved, and it is compatible with existing production processes.
Patent Information
- Application Number
- CN202210712377.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-06-22
- Publication Date
- 2025-09-05
- Estimated Expiration
- 2042-06-22
AI Technical Summary
Existing MOSFET devices are susceptible to single-particle gate penetration damage in space radiation environments, especially in the center of the JFET region, which leads to breakdown of the gate insulating dielectric, and thickening the dielectric will affect the total dose resistance.
A high-dielectric-constant composite gate dielectric structure is adopted, combined with a bird's-beak-shaped gate dielectric region. Radiation protection is enhanced by thickening the gate dielectric in the center of the JFET region and forming a split gate electrode in the channel region.
The single-particle gate punch-through resistance of MOSFET devices is improved, while the total dose degradation caused by dielectric thickening is avoided, and the protection capability against single-particle irradiation is enhanced.
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Figure CN115148819B_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a power MOSFET gate structure. Background Art
[0002] The space radiation environment is a complex one filled with various types of cosmic rays, including galactic cosmic rays (GCRs) composed of protons and alpha particles, solar cosmic rays (SCRs) composed of high-energy, high-flux charged particle streams accelerated by the solar atmosphere, the solar wind formed by hot ionized gases flying from the sun to the earth, and the earth's radiation belts (Van Allen belts) composed of protons, electrons and a small amount of low-energy heavy ions captured by the geomagnetic field. The space nuclear explosion environment composed of nuclear radiation, high-energy electromagnetic pulses and nuclear explosion shock waves generated by ground or high-altitude nuclear weapon explosions, as well as secondary particles generated by the interaction of the above-mentioned high-energy particles with the constituent materials of spacecraft, all have varying degrees of impact on spacecraft.
[0003] Single-Event Gate Rupture (SEGR) refers to the phenomenon in which the gate insulating dielectric is broken down and short-circuited due to high-energy particles incident on the MOSFET device. The failure mechanism is mainly that when high-energy particles are incident, a large number of electron-hole pairs are excited in the semiconductor material. These electron-hole pairs cause an instantaneous short circuit between the drain and the gate, causing the gate dielectric material to be subjected to a large electric field strength, resulting in permanent performance degradation of the gate dielectric or even breakdown and burning. The central area of the JFET region is considered to be a sensitive area for SEGR and requires special protection in radiation hardening. Directly thickening the gate oxide layer has a significant anti-SEGR effect, but it will have a negative effect on the total ionizing dose (TID) resistance of the device, which requires trade-offs and optimization. Summary of the Invention
[0004] To solve the problem of gate damage caused by single particle irradiation in the above-mentioned MOSFET, the present invention proposes a power MOSFET gate structure and preparation method that is resistant to single particle gate damage. The technical solution is as follows:
[0005] A power MOSFET gate structure resistant to single-particle gate damage, comprising:
[0006] a first conductivity type epitaxial layer drift region;
[0007] a second conductivity type well region located on the drift region of the first conductivity type epitaxial layer, wherein a JFET region is formed between adjacent second conductivity type well regions;
[0008] a first conductivity type source region located in the second conductivity type well region, wherein a channel region is formed between the second conductivity type well region and the first conductivity type source region on a side close to the JFET region;
[0009] A second conductivity type heavily doped region located in the second conductivity type well region and away from the JFET region;
[0010] a first isolation gate dielectric layer, the first isolation gate dielectric layer being disposed on top of the drift region of the first conductive type epitaxial layer, the first isolation gate dielectric layer being thick in the middle and thin at both sides, and a portion of the first isolation gate dielectric layer where the thickness varies in the horizontal direction forming a bird's beak region;
[0011] a second isolation gate dielectric layer, the second isolation gate dielectric layer being arranged on top of the first isolation gate dielectric layer;
[0012] a gate electrode, the gate electrode being disposed on top of the second isolation gate dielectric layer;
[0013] a passivation layer, the passivation layer being disposed on the second isolation gate dielectric layer and covering the gate electrode;
[0014] A source metal electrode is arranged on both sides of the first isolation gate dielectric layer and above the passivation layer, and the source metal electrode is arranged above the second conductive type heavily doped region and a portion of the first conductive type source region.
[0015] Furthermore, the thinnest position of the first isolation gate dielectric layer is located above the channel region, and the thickest position is located above the JFET region. The thickness of the thickest position is not less than twice the thickness of the thinnest position, and there is no obvious sudden step from the thinnest position to the thickest position.
[0016] Furthermore, the dielectric constant of the second isolation gate dielectric layer is greater than the dielectric constant of the first isolation gate dielectric layer.
[0017] Furthermore, the average thickness of the second isolation gate dielectric layer is greater than the thickness of the first isolation gate dielectric layer at its thinnest position.
[0018] Furthermore, the second isolation gate dielectric layer covers the entire channel region and is discontinuous above the JFET region. One end of the second isolation gate dielectric layer close to the JFET region is located above the bird's beak region, and one end of the second isolation gate dielectric layer away from the JFET region is located above the first conductive type source region.
[0019] Furthermore, the gate electrode is discontinuous above the JFET region, forming a split gate structure.
[0020] Furthermore, a first conductivity type highly doped substrate and a drain electrode are provided below the first conductivity type epitaxial layer drift region.
[0021] Furthermore, an additional isolation gate dielectric layer exists between the second isolation gate dielectric layer and the gate electrode.
[0022] Furthermore, the drift region of the first conductive type epitaxial layer is made of Si or a wide bandgap semiconductor material; and the gate electrode is made of metal or doped polycrystalline.
[0023] In the above method for preparing the power MOSFET gate structure, if the gate electrode is continuous above the JFET region, the steps are as follows:
[0024] S1, preparing a first conductivity type epitaxial layer drift region;
[0025] S2, forming a second conductivity type well region, a first conductivity type source region, and a second conductivity type heavily doped region on the drift region of the first conductivity type epitaxial layer by processes such as photolithography, implantation, and activation annealing;
[0026] S3, growing a first isolation gate dielectric layer on the drift region of the first conductive type epitaxial layer;
[0027] S4, growing a second isolation gate dielectric layer on the first isolation gate dielectric layer;
[0028] S5. Etching the second isolation gate dielectric layer and a portion of the first isolation gate dielectric layer above the JFET region through photolithography and etching processes to form a gate dielectric thickening window;
[0029] S6. Performing thermal oxidation through a high-temperature process to form a gate dielectric thickening region at the location of the gate dielectric thickening window, and at this time, the first isolation gate dielectric layer forms a bird's beak structure;
[0030] S7, depositing polycrystalline or metal, and etching the polycrystalline or metal above the second conductive type heavily doped region and a portion of the first conductive type source region to form a gate electrode;
[0031] S8, depositing a passivation medium, forming contact holes through multiple photolithography and etching processes, and forming a passivation layer;
[0032] S9, depositing metal and reverse etching to form a source metal electrode;
[0033] If the gate electrode is discontinuous above the JFET region, the above steps S5-S7 are replaced by the following steps S5'-S7':
[0034] S5′, forming an oxide layer on the surface of the second isolation gate dielectric layer, and depositing polycrystalline or metal to form a gate electrode;
[0035] S6′, etching the gate electrode, the oxide layer, the second isolation gate dielectric layer and a portion of the first isolation gate dielectric layer above the JFET region through photolithography and etching processes to form a gate dielectric thickening window;
[0036] S7′, performing thermal oxidation through a high temperature process to form a gate dielectric thickening region at the location of the gate dielectric thickening window. At this time, the first isolation gate dielectric layer forms a bird's beak structure, and the gate electrode forms a self-oxidation layer due to oxidation.
[0037] Beneficial effects of the present invention:
[0038] By utilizing a composite gate dielectric structure with a high dielectric constant, the present invention can improve the single-particle gate punch-through resistance of MOSFET while avoiding the total dose degradation caused by dielectric thickening. At the same time, the additional thickening of the gate dielectric in the center of the JFET region helps to further improve the SEGR resistance of the device. In addition, the bird's beak-shaped gate dielectric region is conducive to suppressing the peak electric field in the source region during the extraction process of electron-hole pairs generated by single-particle irradiation, thereby strengthening radiation protection. The present invention is compatible with existing power MOSFET production processes and can be used in combination with device reinforcement measures such as source region / epitaxial buffer layer to achieve better radiation resistance. BRIEF DESCRIPTION OF THE DRAWINGS
[0039] Figure 1 is a schematic structural diagram of the MOSFET device of Example 1;
[0040] Figure 2 It is a partial enlarged view of the dotted box position in the structure of Example 1;
[0041] Figure 3 1 is a schematic diagram of the preparation process of the MOSFET device of Example 1;
[0042] Figure 4 is a schematic structural diagram of a MOSFET device according to Example 2;
[0043] Figure 5 It is a schematic diagram of the preparation process of the MOSFET device of Example 2.
[0044] Description of labels:
[0045] 1. First conductivity type epitaxial layer drift region; 2. Second conductivity type well region; 3. First conductivity type source region; 4. Second conductivity type heavily doped region; 5. First isolation gate dielectric layer; 6. Second isolation gate dielectric layer; 7. Gate dielectric thickening window; 8. Gate dielectric thickening region; 9. SiO2 layer; 10. Gate electrode; 11. Passivation layer; 12. Source metal electrode; 13. Self-oxidation layer. DETAILED DESCRIPTION
[0046] The present invention is further described below with reference to examples. The examples are only used to illustrate the present invention and do not constitute a limitation to the scope of the claims. Other alternative means that can be thought of by those skilled in the art are all within the scope of the claims of the present invention.
[0047] In addition, in the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are only used to facilitate the description of the present invention and simplify the description. They do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be understood as limiting the invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only and should not be understood as indicating or implying relative importance.
[0048] Example 1
[0049] A power MOSFET gate structure resistant to single-particle gate damage, such as Figure 1-2 As shown, it includes a first conductive type epitaxial layer drift region 1; a second conductive type well region 2 located on the first conductive type epitaxial layer drift region 1, with a JFET region formed between adjacent second conductive type well regions 2; a first conductive type source region 3 located in the second conductive type well region 2, with a channel region formed between the second conductive type well region 2 and the first conductive type source region 3 on the side close to the JFET region; a second conductive type heavily doped region 4 located in the second conductive type well region 2 and away from the JFET region; a first isolation gate dielectric layer 5, which is arranged on top of the first conductive type epitaxial layer drift region 1, The first isolation gate dielectric layer 5 has a structure that is thick in the middle and thin on both sides, and the part where its thickness changes in the horizontal direction forms a bird's beak area; the second isolation gate dielectric layer 6 is arranged on the top of the first isolation gate dielectric layer 5; the gate electrode 10 is arranged on the top of the second isolation gate dielectric layer 6; the passivation layer 11 is arranged on the second isolation gate dielectric layer 6 and covers the gate electrode 10; the source metal electrode 12 is arranged on both sides of the first isolation gate dielectric layer 5 and above the passivation layer 11, and the source metal electrode 12 is arranged above the second conductive type heavily doped region 4 and part of the first conductive type source region 3.
[0050] Preferably, the first isolation gate dielectric layer 5 is SiO2, with the thinnest portion of the first isolation gate dielectric layer 5 located above the channel region and the thickest portion located above the JFET region. The thickness of the thickest portion is not less than twice the thickness of the thinnest portion. Furthermore, the thickness of the first isolation gate dielectric layer 5 has no obvious abrupt step change from the thinnest portion to the thickest portion. Furthermore, the thickness of the first isolation gate dielectric layer 5 at its thinnest portion is typically 1nm-100nm, with a typical thickness of 2nm-50nm, and the thickness at its thickest portion is generally 50nm-500nm, with a typical thickness of 200nm-500nm.
[0051] Preferably, the dielectric constant of the second isolation gate dielectric layer 6 is greater than that of the first isolation gate dielectric layer 5, and the second isolation gate dielectric layer 6 is Si3N4. Furthermore, the average thickness of the second isolation gate dielectric layer 6 is greater than the thickness of the first isolation gate dielectric layer 5 at its thinnest location. Furthermore, the average thickness of the second isolation gate dielectric layer 6 is typically 20nm-400nm, with a typical thickness of 50nm-200nm. Furthermore, when the second isolation gate dielectric layer 6 is Si3N4, a SiO2 layer 9 is formed above the second isolation gate dielectric layer 6.
[0052] Preferably, the second isolation gate dielectric layer 6 covers the entire channel region and is discontinuous above the JFET region. An end of the second isolation gate dielectric layer 6 close to the JFET region is located above the bird's beak region, and an end of the second isolation gate dielectric layer 6 away from the JFET region is located above the first conductivity type source region 3.
[0053] Preferably, the first conductive type epitaxial layer drift region 1 can be Si, or a wide bandgap semiconductor material such as SiC, GaN, etc. Furthermore, there is a first conductive type highly doped substrate and a drain electrode disposed below the substrate below the first conductive type epitaxial layer drift region 1.
[0054] Preferably, the gate electrode 10 is made of metal or doped polysilicon.
[0055] The method for preparing the above-mentioned power MOSFET gate structure resistant to single particle gate damage is as follows: Figure 3 As shown, the following steps are included:
[0056] S1. Figure 3 (a) shows the first conductivity type epitaxial layer drift region 1;
[0057] S2. Figure 3 As shown in (b), a second conductivity type well region 2, a first conductivity type source region 3, and a second conductivity type heavily doped region 4 are formed on the first conductivity type epitaxial layer drift region 1 through processes such as photolithography, implantation, and activation annealing;
[0058] S3. Figure 3 As shown in (c), a first isolation gate dielectric layer 5 is grown on the drift region 1 of the first conductive type epitaxial layer;
[0059] S4. Figure 3 As shown in (d), a second isolation gate dielectric layer 6 is grown on the first isolation gate dielectric layer 5;
[0060] S5. Figure 3 As shown in (e), the second isolation gate dielectric layer 6 and a portion of the first isolation gate dielectric layer 5 above the JFET region are etched by photolithography, etching and other processes to form a gate dielectric thickening window 7;
[0061] S6. Figure 3 As shown in (f), thermal oxidation is performed by a high-temperature process to form a gate dielectric thickening region 8 at the position of the gate dielectric thickening window 7. At this time, the first isolation gate dielectric layer 5 forms a bird's beak structure; when the second isolation gate dielectric layer 6 is Si3N4, the upper portion of the second isolation gate dielectric layer 6 is oxidized to form a SiO2 layer 9;
[0062] S7. Figure 3 As shown in (g), polysilicon is deposited, and the polysilicon above the second conductive type heavily doped region 4 and a portion of the first conductive type source region 3 is etched to form a polysilicon gate electrode 10;
[0063] S8. Figure 3 As shown in (h), a passivation dielectric is deposited, and contact holes are formed through multiple photolithography and etching processes to form a passivation layer 11;
[0064] S9. Figure 3 As shown in (i), metal is deposited and reverse-etched to form a source metal electrode 12.
[0065] Example 2
[0066] A power MOSFET gate structure resistant to single-particle gate damage, such as Figure 4 As shown, it is basically the same as embodiment 1, except that the gate electrode 10 is discontinuous above the JFET, forming a split gate structure, which can further reduce gate damage of the SEGR and reduce gate capacitance.
[0067] The method for preparing the above-mentioned single-particle gate damage-resistant power MOSFET gate structure is substantially the same as the method for preparing the same in Example 1, except for the deposition sequence of the gate electrode 10, specifically steps S5-S7. Steps S5-S7 of this embodiment are as follows:
[0068] S5. Figure 5 (c) and Figure 5As shown in (d), when the second isolation gate dielectric layer 6 is Si3N4, the upper portion of the second isolation gate dielectric layer 6 is oxidized to form a SiO2 layer 9, and a polysilicon gate electrode 10 is deposited;
[0069] S6. Figure 5 As shown in (e), the polysilicon gate electrode 10, the SiO2 layer 9, the second isolation gate dielectric layer 6 and a portion of the first isolation gate dielectric layer 5 above the JFET region are etched by photolithography, etching and other processes to form a gate dielectric thickening window 7;
[0070] S7. Figure 5 As shown in (f), thermal oxidation is performed through a high-temperature process to form a gate dielectric thickening region 8 at the location of the gate dielectric thickening window 7. At this time, the first isolation gate dielectric layer 5 forms a bird's beak structure. At the same time, the polysilicon gate electrode 10 forms a polysilicon self-oxidation layer 13 due to oxidation.
[0071] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.
Claims
1. A power MOSFET gate structure resistant to single-particle gate damage, characterized in that: include: a first conductivity type epitaxial layer drift region; a second conductivity type well region located on the drift region of the first conductivity type epitaxial layer, wherein a JFET region is formed between adjacent second conductivity type well regions; a first conductivity type source region located in the second conductivity type well region, wherein a channel region is formed between the second conductivity type well region and the first conductivity type source region on a side close to the JFET region; A second conductivity type heavily doped region located in the second conductivity type well region and away from the JFET region; a first isolation gate dielectric layer, the first isolation gate dielectric layer being disposed on top of the drift region of the first conductive type epitaxial layer, the first isolation gate dielectric layer being thick in the middle and thin at both sides, and a portion of the first isolation gate dielectric layer where the thickness varies in the horizontal direction forming a bird's beak region; a second isolation gate dielectric layer, the second isolation gate dielectric layer being arranged on top of the first isolation gate dielectric layer; a gate electrode, the gate electrode being disposed on top of the second isolation gate dielectric layer; a passivation layer, the passivation layer being disposed on the second isolation gate dielectric layer and covering the gate electrode; A source metal electrode is provided on both sides of the first isolation gate dielectric layer and above the passivation layer, and the source metal electrode is provided above the second conductive type heavily doped region and a portion of the first conductive type source region; The dielectric constant of the second isolation gate dielectric layer is greater than the dielectric constant of the first isolation gate dielectric layer; The second isolation gate dielectric layer covers the entire channel region and is discontinuous above the JFET region. One end of the second isolation gate dielectric layer close to the JFET region is located above the bird's beak region, and one end of the second isolation gate dielectric layer away from the JFET region is located above the first conductive type source region.
2. The power MOSFET gate structure resistant to single particle gate damage according to claim 1, characterized in that: The thinnest position of the first isolation gate dielectric layer is located above the channel region, and the thickest position is located above the JFET region. The thickness of the thickest position is not less than twice the thickness of the thinnest position, and there is no obvious sudden step from the thinnest position to the thickest position.
3. The power MOSFET gate structure resistant to single particle gate damage according to claim 1, characterized in that: The average thickness of the second isolation gate dielectric layer is greater than the thickness of the thinnest position of the first isolation gate dielectric layer.
4. The power MOSFET gate structure resistant to single particle gate damage according to claim 1, characterized in that: The gate electrode is discontinuous above the JFET region, forming a split-gate structure.
5. The power MOSFET gate structure resistant to single particle gate damage according to claim 1, characterized in that: A first conductivity type highly doped substrate and a drain electrode are provided below the first conductivity type epitaxial layer drift region.
6. The power MOSFET gate structure resistant to single particle gate damage according to claim 1, characterized in that: An additional isolation gate dielectric layer is present between the second isolation gate dielectric layer and the gate electrode.
7. The power MOSFET gate structure resistant to single particle gate damage according to claim 1, characterized in that: The drift region of the first conductive type epitaxial layer is made of Si or a wide bandgap semiconductor material; the gate electrode is made of metal or doped polycrystalline.
8. The method for preparing a power MOSFET gate structure according to any one of claims 1 to 4, characterized in that: If the gate electrode is continuous over the JFET region, the steps are as follows: S1, preparing a first conductivity type epitaxial layer drift region; S2, forming a second conductivity type well region, a first conductivity type source region, and a second conductivity type heavily doped region on the drift region of the first conductivity type epitaxial layer by photolithography, implantation, and activation annealing processes; S3, growing a first isolation gate dielectric layer on the drift region of the first conductive type epitaxial layer; S4, growing a second isolation gate dielectric layer on the first isolation gate dielectric layer; S5. Etching the second isolation gate dielectric layer and a portion of the first isolation gate dielectric layer above the JFET region through photolithography and etching processes to form a gate dielectric thickening window; S6. Performing thermal oxidation through a high-temperature process to form a gate dielectric thickening region at the location of the gate dielectric thickening window, and at this time, the first isolation gate dielectric layer forms a bird's beak structure; S7, depositing polycrystalline or metal, and etching the polycrystalline or metal above the second conductive type heavily doped region and a portion of the first conductive type source region to form a gate electrode; S8, depositing a passivation medium, forming contact holes through multiple photolithography and etching processes, and forming a passivation layer; S9, depositing metal and reverse etching to form a source metal electrode; If the gate electrode is discontinuous above the JFET region, the above steps S5-S7 are replaced by the following S5'-S7': S5', forming an oxide layer on the surface of the second isolation gate dielectric layer, and depositing polycrystalline or metal to form a gate electrode; S6', etching the gate electrode, oxide layer, second isolation gate dielectric layer and part of the first isolation gate dielectric layer above the JFET region through photolithography and etching processes to form a gate dielectric thickening window; S7′, performing thermal oxidation through a high temperature process to form a gate dielectric thickening region at the location of the gate dielectric thickening window. At this time, the first isolation gate dielectric layer forms a bird's beak structure, and the gate electrode forms a self-oxidation layer due to oxidation.
Citation Information
Patent Citations
Step gate dielectric layer structure and manufacturing method thereof
CN113506829A