Vertical light emitting diode and method for preparing the same

Abstract

The present invention provides a vertical light emitting diode and a preparation method thereof. The metal reflection layer and the insulating reflection layer of the ODR reflection layer are used to form a MIS capacitor structure with an epitaxial layer. The second electrode is connected to a relatively high potential and the third electrode is connected to a relatively low potential, so that the light emitting layer in the epitaxial layer emits light. At the same time, the first electrode is connected to a relatively high potential and the third electrode is connected to a relatively low potential, so that electrons gather from the first semiconductor layer of the epitaxial layer to the light emitting layer and holes gather from the second semiconductor layer of the epitaxial layer to the light emitting layer, thereby improving the hole injection efficiency and increasing the radiation recombination efficiency in the light emitting layer. The photoelectric conversion efficiency is improved without reducing the transmission efficiency of the radiation recombination luminescence, and the cost is low. The present invention only slightly improves the existing vertical light emitting diode and will not significantly increase the complexity of the structure and the preparation process.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a vertical light emitting diode and a preparation method thereof. Background Art

[0002] Improving the photoelectric conversion efficiency of light-emitting diodes is a technical focus that has attracted much attention at present, especially for light-emitting diodes based on III-N materials (compound materials formed by III-N materials and nitrogen, such as GaN, AlGaN and other materials). Since P-type doping activation of III-N materials is relatively difficult, the hole concentration of the P-type semiconductor layer of the epitaxial layer is one to two orders of magnitude lower than the electron concentration of the N-type semiconductor layer, and the effective mass of holes is also greater than the effective mass of electrons. At the same time, the mobility of holes is also significantly lower than that of electrons. Therefore, how to obtain a higher hole concentration and a better hole injection effect is one of the key issues in solving the photoelectric conversion efficiency of light-emitting diodes.

[0003] Compared with the light-emitting diode with a normal structure, the vertical light-emitting diode can alleviate the current congestion phenomenon. The vertical light-emitting diode usually prepares an ohmic contact layer and a reflective layer on the P-type semiconductor layer. However, the reflectivity of the metal reflective layer alone is not optimal. For example, the highest reflectivity of Ag is about 90%-95%, and the reflectivity will decrease after heat aggregation. The reflectivity can be further increased to more than 98% by adopting an ODR (Omni-Directional Reflector) structure, but the dielectric layer in the ODR reflector needs to form an array of through holes, and the ODR metal current expansion layer is electrically connected to the ohmic contact layer after passing through the through holes. For the area outside the through hole (the area directly connected to the non-metallic current expansion layer), the carrier transport effect is relatively poor under high current, resulting in poor hole injection effect, which will affect the electro-optical conversion efficiency of the vertical light-emitting diode under high working current density. Summary of the invention

[0004] The object of the present invention is to provide a vertical light emitting diode and a method for preparing the same, so as to solve the problem of low photoelectric conversion efficiency of the existing vertical light emitting diode.

[0005] In order to achieve the above object, the present invention provides a vertical light emitting diode, comprising:

[0006] a first substrate;

[0007] An epitaxial layer, located on the first surface of the first substrate, comprising a first semiconductor layer, a light-emitting layer and a second semiconductor layer arranged in sequence from top to bottom;

[0008] An ODR reflective layer, located between the epitaxial layer and the first surface of the first substrate, includes an insulating reflective layer and a metal reflective layer arranged in sequence from top to bottom, wherein the metal reflective layer, the insulating reflective layer and the epitaxial layer constitute a MIS capacitor structure; and

[0009] The first electrode, the second electrode and the third electrode which are insulated from each other are electrically connected to the metal reflective layer, the second semiconductor layer and the first semiconductor layer respectively.

[0010] Optionally, also include:

[0011] A plurality of grooves, penetrating the second semiconductor layer and the light emitting layer and exposing the first semiconductor layer;

[0012] a plurality of first through holes, penetrating the ODR reflective layer and exposing the second semiconductor layer;

[0013] a plurality of second through holes, penetrating the ODR reflective layer and communicating with the corresponding grooves; and,

[0014] The dielectric layer is located between the ODR reflective layer and the first surface of the first substrate and covers at least the sidewalls of the first through-hole and the second through-hole corresponding to the metal reflective layer, and is at least used to electrically isolate the first electrode and the second electrode.

[0015] Optionally, also include:

[0016] A first step, penetrating the epitaxial layer and exposing the metal reflective layer, wherein the first electrode is located on a lower step surface of the first step and is electrically connected to the metal reflective layer;

[0017] a first current spreading layer, located in the dielectric layer and passing through a portion of the dielectric layer to fill the first through hole so as to be electrically connected to the second semiconductor layer;

[0018] a second step, penetrating the epitaxial layer, the ODR reflective layer and a portion of the dielectric layer and exposing the first current spreading layer, the second electrode being located on a lower step surface of the second step and electrically connected to the first current spreading layer; and

[0019] The second current spreading layer is located between the dielectric layer and the first surface of the first substrate, and is electrically connected to the first semiconductor layer after passing through the dielectric layer and filling the second through-hole and the groove. The third electrode is located on the second surface of the first substrate, and is electrically connected to the second current spreading layer through the first substrate.

[0020] Optionally, the dielectric layer includes a first dielectric layer and a second dielectric layer stacked in sequence on the metal reflective layer, the first current spreading layer is located between the first dielectric layer and the second dielectric layer, penetrates the first dielectric layer and fills the first perforation, and is electrically connected to the second semiconductor layer, and the second current spreading layer is located between the second dielectric layer and the first surface of the first substrate, penetrates the second dielectric layer and the first dielectric layer and fills the second perforation and the groove, and is electrically connected to the first semiconductor layer.

[0021] Optionally, also include:

[0022] The first ohmic contact layer is located on a surface of the second semiconductor layer close to the first substrate and in each of the first through-holes. After the first current spreading layer fills the first through-holes, it is electrically connected to the second semiconductor layer through the first ohmic contact layer.

[0023] Optionally, the material of the first ohmic contact layer is a metal material; and / or the thickness of the first ohmic contact layer is 10 nm to 200 nm.

[0024] Optionally, the material of the first ohmic contact layer is a transparent conductive material, and a surface of the first ohmic contact layer close to the first substrate is further covered with an etching protection layer; and / or the thickness of the first ohmic contact layer is 10 nm to 200 nm.

[0025] Optionally, also include:

[0026] The second ohmic contact layer is located on a surface of the first semiconductor layer close to the first substrate and in each of the grooves. After the second current spreading layer fills the second through-hole and the grooves, it is electrically connected to the first semiconductor layer through the second ohmic contact layer.

[0027] Optionally, a bonding layer is further provided between the second current spreading layer and the first surface of the first substrate.

[0028] Optionally, a first adhesion layer is provided between a surface of the first current spreading layer close to the first substrate and the dielectric layer; and / or a second adhesion layer is provided between a surface of the first current spreading layer and / or the second current spreading layer away from the first substrate and the dielectric layer.

[0029] Optionally, the material of the first adhesion layer and / or the second adhesion layer is at least one of Ti, Cr and Ni; the thickness of the first adhesion layer and / or the second adhesion layer is 5 nm to 50 nm.

[0030] Optionally, also include:

[0031] A passivation layer conformally covers the surface of the epitaxial layer, the sidewall and lower step surface of the first step, and the sidewall and lower step surface of the second step, and at least part of the surface of the first electrode and the second electrode is exposed from the passivation layer.

[0032] Optionally, the passivation layer is a single layer or at least two layers of SiO2 and / or Al2O3.

[0033] Optionally, the materials of the first dielectric layer and the second dielectric layer are SiO2 and SiN x , AlN, BN and diamond; and / or, the thickness of the first dielectric layer and the second dielectric layer are respectively 200nm ~ 2μm.

[0034] Optionally, the insulating reflective layer is a single-layer reflective film or is formed by two layers of reflective films with different refractive indices being alternately distributed.

[0035] Optionally, the material of the reflective film is SiO2, Al2O3, HfO2, SiN x , AlN, BN or MgF2; and / or, the thickness of the reflective film is λ / 4n, wherein λ is the light emitting wavelength of the light emitting layer and n is the refractive index of the reflective film.

[0036] Optionally, when the vertical light emitting diode is in use, the first electrode is connected to a first potential, the second electrode is connected to a second potential, the third electrode is connected to a third potential, and the first potential and the second potential are both greater than the third potential.

[0037] Optionally, the difference between the first potential and the third potential is 3V to 10V.

[0038] The present invention also provides a method for preparing a vertical light emitting diode, comprising:

[0039] providing a first substrate;

[0040] Transferring an epitaxial layer to the first surface of the first substrate, the epitaxial layer comprising a first semiconductor layer, a light-emitting layer and a second semiconductor layer arranged in sequence from top to bottom;

[0041] forming an ODR reflective layer, the ODR reflective layer being located between the epitaxial layer and the first surface of the first substrate, and comprising an insulating reflective layer and a metal reflective layer arranged in sequence from top to bottom, the metal reflective layer, the insulating reflective layer and the epitaxial layer constituting a MIS capacitor structure; and,

[0042] A first electrode, a second electrode and a third electrode which are insulated from each other are formed. The first electrode, the second electrode and the third electrode are electrically connected to the metal reflective layer, the second semiconductor layer and the first semiconductor layer respectively.

[0043] Optionally, the step of forming the epitaxial layer and the ODR reflective layer includes:

[0044] Providing a second substrate, and sequentially forming the first semiconductor layer, the light-emitting layer, and the second semiconductor layer on the second substrate;

[0045] Etching the second semiconductor layer and the light emitting layer to form a plurality of grooves exposing the first semiconductor layer;

[0046] forming the insulating reflective layer on the second semiconductor layer; and,

[0047] The metal reflection layer is formed on a portion of the insulating reflection layer. The metal reflection layer has a plurality of third through holes and a plurality of fourth through holes. The third through holes expose the insulating reflection layer, and the fourth through holes are connected to the groove.

[0048] Optionally, after forming the groove and before forming the insulating reflective layer, the method further includes:

[0049] A first ohmic contact layer is formed on a portion of the second semiconductor layer, and each of the third through holes is aligned with the first ohmic contact layer.

[0050] Optionally, the material of the first ohmic contact layer is a metal material; and / or the thickness of the first ohmic contact layer is 10 nm to 200 nm.

[0051] Optionally, after forming the first ohmic contact layer, an etching protection layer is further formed on the first ohmic contact layer.

[0052] Optionally, the material of the first ohmic contact layer is a transparent conductive material; and / or the thickness of the first ohmic contact layer is 10 nm to 200 nm.

[0053] Optionally, when forming the first ohmic contact layer, a second ohmic contact layer is also formed on the first semiconductor layer in each of the grooves, and each of the fourth through holes exposes the second ohmic contact layer.

[0054] Optionally, the step of forming the first electrode, the second electrode and the third electrode which are insulated from each other includes:

[0055] Forming a first dielectric layer on the metal reflective layer, the first dielectric layer also filling the third through-hole, the fourth through-hole and the groove, the first dielectric layer having a plurality of fifth through-holes and a plurality of sixth through-holes, the fifth through-holes aligning with the third through-holes and exposing the second semiconductor layer, the sixth through-holes aligning with the fourth through-holes and exposing the first semiconductor layer;

[0056] forming a first current spreading layer on a portion of the first dielectric layer, wherein the first current spreading layer fills the fifth through-hole and is electrically connected to the second semiconductor layer;

[0057] forming a second dielectric layer on the first current spreading layer and the first dielectric layer, wherein the second dielectric layer further fills the sixth through-hole, and the second dielectric layer has a plurality of seventh through-holes, wherein the seventh through-holes are aligned with the sixth through-holes and expose the first semiconductor layer;

[0058] forming a second current spreading layer on at least a portion of the second dielectric layer, wherein the second current spreading layer fills the seventh through hole and is electrically connected to the first semiconductor layer;

[0059] bonding the first substrate on the second current spreading layer, and separating the second substrate;

[0060] Sequentially etching the epitaxial layer and the insulating reflective layer to form a first step exposing the metal reflective layer, and sequentially etching the epitaxial layer and the ODR reflective layer to form a second step exposing the first current spreading layer;

[0061] forming a first electrode and a second electrode on lower step surfaces of the first step and the second step, respectively, the first electrode and the second electrode being electrically connected to the metal reflection layer and the first current spreading layer, respectively; and,

[0062] A third electrode is formed on the second surface of the first substrate, and the third electrode is electrically connected to the second current spreading layer through the first substrate.

[0063] Optionally, a first adhesion layer is provided between a surface of the first current spreading layer close to the first substrate and the dielectric layer; and / or a second adhesion layer is provided between a surface of the first current spreading layer and / or the second current spreading layer away from the first substrate and the dielectric layer.

[0064] Optionally, the material of the first adhesion layer and / or the second adhesion layer is at least one of Ti, Cr and Ni; the thickness of the first adhesion layer and / or the second adhesion layer is 5 nm to 50 nm.

[0065] Optionally, the materials of the first dielectric layer and the second dielectric layer are SiO2 and SiNx , AlN, BN and diamond; and / or, the thickness of the first dielectric layer and the second dielectric layer are respectively 200nm ~ 2μm.

[0066] Optionally, the step of bonding the first substrate on the second current spreading layer includes:

[0067] forming a first bonding material layer and a second bonding material layer on the second current spreading layer and the first substrate respectively; and,

[0068] The first bonding material layer and the second bonding material layer are fused to bond the first substrate on the second current spreading layer. After the first bonding material layer and the second bonding material layer are fused, a bonding layer is formed between the first substrate and the second current spreading layer.

[0069] Optionally, the step of bonding the first substrate on the second current spreading layer includes:

[0070] forming a second bonding material layer on the first surface of the first substrate; and,

[0071] The second bonding material layer is fused into the second current spreading layer to bond the first substrate on the second current spreading layer.

[0072] Optionally, after forming the first step and the second step, the method further includes:

[0073] Continue etching along the first step and the second step until a scribe line is formed that exposes the first surface of the first substrate; and,

[0074] After forming the first electrode, the second electrode and the third electrode, the first substrate is cut along the scribe line to form a single vertical light emitting diode.

[0075] Optionally, before or after forming the first electrode and the second electrode, and before forming the third electrode, the method further includes:

[0076] A passivation layer is formed, the passivation layer conformally covers the surface of the epitaxial layer, the sidewall and lower step surface of the first step, and the sidewall and lower step surface of the second step, and at least part of the surface of the first electrode and the second electrode is exposed from the passivation layer.

[0077] Optionally, the passivation layer is a single layer or at least two layers of SiO2 and / or Al2O3.

[0078] Optionally, the insulating reflective layer is a single-layer reflective film or is formed by two layers of reflective films with different refractive indices being alternately distributed.

[0079] Optionally, the material of the reflective film is SiO2, Al2O3, HfO2, SiN x , AlN, BN or MgF2; and / or, the thickness of the reflective film is λ / 4n, wherein λ is the light emitting wavelength of the light emitting layer and n is the refractive index of the reflective film.

[0080] Optionally, when the vertical light emitting diode is in use, the first electrode is connected to a first potential, the second electrode is connected to a second potential, the third electrode is connected to a third potential, and the first potential and the second potential are both greater than the third potential.

[0081] Optionally, the difference between the first potential and the third potential is 3V to 10V.

[0082] In the vertical light-emitting diode and the preparation method thereof provided by the present invention, the metal reflection layer and the insulating reflection layer of the ODR reflection layer are used to form a MIS (Metal-Insulator-Semiconductor) capacitor structure with the epitaxial layer. When the vertical light-emitting diode is in use, the second electrode can be connected to a relatively high potential and the third electrode can be connected to a relatively low potential, so that the light-emitting layer in the epitaxial layer emits light. At the same time, the first electrode is connected to a relatively high potential and the third electrode is connected to a relatively low potential, so that electrons gather from the first semiconductor layer of the epitaxial layer to the light-emitting layer, and holes gather from the second semiconductor layer of the epitaxial layer to the light-emitting layer, thereby improving the hole injection efficiency, increasing the radiation recombination efficiency in the light-emitting layer, and improving the photoelectric conversion efficiency without reducing the transmission efficiency of the radiation recombination luminescence, and the cost is low. In addition, since the ODR reflection layer can improve the light extraction efficiency, the ODR reflection layer is widely used in the current vertical light-emitting diodes. The present invention only slightly improves the existing vertical light-emitting diodes and will not significantly increase the complexity of the structure and the preparation process. BRIEF DESCRIPTION OF THE DRAWINGS

[0083] Figure 1 A flow chart of a method for preparing a vertical light emitting diode provided in Embodiment 1 of the present invention;

[0084] Figure 2 to Figure 14 A schematic structural diagram corresponding to corresponding steps of the method for preparing a vertical light emitting diode provided in the first embodiment of the present invention;

[0085] Figure 15 to Figure 25 A schematic structural diagram corresponding to corresponding steps of a method for preparing a vertical light emitting diode provided in Embodiment 2 of the present invention;

[0086] Wherein, the accompanying drawings are marked as follows:

[0087] 100-second substrate; 101-first substrate; 200-epitaxial layer; 200a-groove; 210a-first step; 210b-second step; 201-buffer layer; 202-low defect density layer; 203-stress adjustment layer; 204-first semiconductor layer; 205-light emitting layer; 206-second semiconductor layer; 214-second ohmic contact layer; 216-first ohmic contact layer; 301-insulating reflective layer; 302-metal reflective layer; 302a-third perforation; 302b-fourth perforation; 401-first dielectric layer; 401a-fifth perforation; 401b-sixth perforation; 402-second dielectric layer; 402a-seventh perforation; 501-first current spreading layer; 502-second current spreading layer; 601-first electrode; 602-second electrode; 603-third electrode; 700-passivation layer. DETAILED DESCRIPTION

[0088] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0089] Embodiment 1

[0090] Fig.14 The schematic diagram of the structure of the vertical light emitting diode provided in this embodiment. Fig.14 As shown, the vertical light emitting diode includes a first substrate 101, an epitaxial layer 200, an ODR reflective layer 300, a dielectric layer, a first electrode 601, a second electrode 602 and a third electrode 603. The ODR reflective layer 300 includes an insulating reflective layer 301 and a metal reflective layer 302.

[0091] Next, this embodiment will be explained using the vertical light emitting diode as a deep ultraviolet vertical light emitting diode (light emitting wavelength of 200nm-320nm), but it should be understood that the vertical light emitting diode is not limited to a deep ultraviolet vertical light emitting diode, but can also be a vertical light emitting diode in other light emitting bands such as ultraviolet and visible light (light emitting wavelength of 320nm-600nm), which will not be explained one by one here.

[0092] Specifically, the first substrate 101 can be made of metal materials such as molybdenum (Mo), copper (Cu), tungsten (W), molybdenum-copper alloy (CuMo), copper-tungsten alloy (CuW) or silicon-aluminum alloy (AlSi), or can be made of conductive semiconductor materials such as Si, Ge, SiC, etc.

[0093] The epitaxial layer 200 is located on the first surface of the first substrate 101 (i.e., the upper surface of the first substrate 101), and includes a first semiconductor layer 204, a light-emitting layer 205, and a second semiconductor layer 206 arranged in sequence from top to bottom. In this embodiment, the first semiconductor layer 204 is an N-type semiconductor layer, and the second semiconductor layer 206 is a P-type semiconductor layer. Among them, the first semiconductor layer 204 is an n-AlGaN layer, the second semiconductor layer 206 is a p-AlGaN layer, and the light-emitting layer 205 is a multi-quantum well layer (MQW), which can be formed by stacking AlGaN structures with a gradient Al component, and the corresponding light-emitting wavelength range is 200nm to 320nm.

[0094] Furthermore, in this embodiment, the epitaxial layer 200 further comprises a low defect density layer 202 and a stress adjustment layer 203 which are sequentially arranged from top to bottom, and the low defect density layer 202 and the stress adjustment layer 203 are stacked and located on the first semiconductor layer 204. The low defect density layer 202 may be a thicker non-intentionally doped AlN layer, and the stress adjustment layer 203 may be a superlattice structure of AlGaN, specifically: an AlGaN layer with a gradual change in Al composition (gradually decreasing) is prepared from the low defect density layer 202 to the first semiconductor layer 204. x Ga 1-x N / A y Ga 1-y N superlattice structure, where 0<y<x<1.

[0095] It should be understood that other film layers may be formed in the epitaxial layer 200, for example, an EBL electron blocking layer may be formed between the light emitting layer 205 and the second semiconductor layer 206, which will not be explained here one by one. The thickness of the epitaxial layer 200 may be 5 μm to 10 μm, but it should not be limited thereto.

[0096] The epitaxial layer 200 has grooves 200a, and the grooves 200a penetrate the second semiconductor layer 206 and the light emitting layer 205 and expose the first semiconductor layer 204. The grooves 200a are arranged in an array.

[0097] Please continue reading Fig.14The second semiconductor layer 206 has a first ohmic contact layer 216 on one side close to the first substrate 101. The first ohmic contact layer 216 is a patterned film layer. The first ohmic contact layer 216 makes ohmic contact with the second semiconductor layer 206, thereby achieving excellent electrical connection. Each of the grooves 200a has a second ohmic contact layer 214 in it. The second ohmic contact layer 214 is a patterned film layer. The second ohmic contact layer 214 makes ohmic contact with the first semiconductor layer 204, thereby achieving excellent electrical connection.

[0098] In this embodiment, the material of the first ohmic contact layer 216 may be a metal material, such as Ag, NiAg, NiAu, NiAl or PdAu, etc., and the thickness may be 10 nm to 200 nm, but it should not be limited thereto.

[0099] In this embodiment, the material of the second ohmic contact layer 214 may be at least one of V, Hf, Ti, Cr, Al, Ni, Au and Pt, and the thickness may be 100 nm to 2 μm, but should not be limited thereto.

[0100] Further, the ODR reflective layer 300 is located between the second semiconductor layer 206 and the first surface of the first substrate 101, and includes an insulating reflective layer 301 and a metal reflective layer 302 arranged in sequence from top to bottom. The insulating reflective layer 301 covers the side of the second semiconductor layer 206 close to the first substrate 101, covers the first ohmic contact layer 216 and extends to cover the sidewall of the groove 200a; the metal reflective layer 302 only covers the part of the side of the insulating reflective layer 301 close to the first substrate 101, specifically covers the area of ​​the insulating reflective layer 301 avoiding the first ohmic contact layer 216, and the metal reflective layer 302 does not enter the groove 200a. The metal reflective layer 302, the insulating reflective layer 301 and the epitaxial layer 200 can form a MIS capacitor structure.

[0101] In this embodiment, the insulating reflective layer 301 enters the groove 200a and covers the side wall of the groove 200a, but there is a gap between the insulating reflective layer 301 and the second ohmic contact layer 214 in the lateral direction, but it should not be limited to this. The insulating reflective layer 301 can also be in close contact with the side wall of the second ohmic contact layer 214; and, as an optional embodiment, the insulating reflective layer 301 can also only cover the second semiconductor layer 206 without entering the groove 200a, and the metal reflective layer 302 can also enter the groove 200a and cover the side wall of the groove 200a, but cannot contact the second ohmic contact layer 214. These optional embodiments do not affect the implementation of the present invention.

[0102] from Fig.14 It can be seen that the ODR reflective layer 300 can be regarded as having a plurality of first perforations and a plurality of second perforations, wherein each of the first perforations is aligned with the first ohmic contact layer 216, and the first perforations penetrate the metal reflective layer 302 and the insulating reflective layer 301 to expose the first ohmic contact layer 216; each of the second perforations is aligned with the second ohmic contact layer 214, and the second perforations penetrate the metal reflective layer 302 and the insulating reflective layer 301 and connect to the groove 200a to expose the second ohmic contact layer 214.

[0103] In this embodiment, the insulating reflective layer 301 can be a single-layer reflective film or a DBR (Distributed Bragg Reflectors) reflective structure formed by alternating two layers of reflective films with different refractive indices. The material of the reflective film can be SiO2, Al2O3, HfO2, SiN x , AlN, BN or MgF2; the thickness of the reflective film is λ / 4n, wherein λ is the light emitting wavelength of the light emitting layer 205, and n is the refractive index of the reflective film.

[0104] In this embodiment, the material of the metal reflective layer 302 may be at least one of Ag, Al, Mg and Rh, and the thickness may be 50-500 nm, but it should not be limited thereto.

[0105] As an optional embodiment, a third adhesion layer and an anti-oxidation layer ( Fig.14 The third adhesion layer is used to adhere the metal reflective layer 302 and the anti-oxidation layer, and the anti-oxidation layer can prevent the metal reflective layer 302 from being oxidized.

[0106] Furthermore, the material of the third adhesion layer may be at least one of Ti, Ni and Cr, and the thickness may be However, it should not be limited thereto; the material of the anti-oxidation layer may be Pt and / or TiW, and the thickness may be But it should not be limited to this.

[0107] Please continue reading Fig.14 A dielectric layer is further provided between the ODR reflective layer 300 and the first surface of the first substrate 101, and the dielectric layer is used to electrically isolate the first electrode, the second electrode, and the third electrode. In this embodiment, the dielectric layer needs to cover a side of the ODR reflective layer 300 close to the first substrate 101 and a portion of the sidewalls of the first through-hole and the second through-hole corresponding to the metal reflective layer 302.

[0108] In this embodiment, since the insulating reflective layer 301 covers the sidewalls of the groove 200a, the dielectric layer can cover the sidewalls of the second perforation and the portion of the insulating reflective layer 301 located in the groove 200a; however, it should be understood that if the insulating reflective layer 301 is only located on one side of the second semiconductor layer 206 close to the first substrate 101 and does not enter the groove 200a, the dielectric layer needs to enter the groove 200a and cover the sidewalls of the groove 200a; or, if the metal reflective layer 302 also enters the groove 200a, the dielectric layer needs to enter the groove 200a and cover the metal reflective layer 302.

[0109] In this embodiment, the dielectric layer has a first current spreading layer 501. The first current spreading layer 501 passes through a portion of the dielectric layer and fills the first through hole, thereby being electrically connected to the first ohmic contact layer 216. A second current spreading layer 502 is provided between the dielectric layer and the first surface of the first substrate 101. The second current spreading layer 502 passes through the dielectric layer and fills the second through hole and the groove 200a, thereby being electrically connected to the second ohmic contact layer 214. The first current spreading layer 501 and the second current spreading layer 502 are electrically isolated by the dielectric layer.

[0110] Furthermore, the vertical light-emitting diode also includes a first step 210a and a second step 210b, the first step 210a penetrates the epitaxial layer 200 and exposes the metal reflective layer 302, the second step 210b penetrates the epitaxial layer 200, the ODR reflective layer 300 and a partial thickness of the dielectric layer and exposes the first current spreading layer 501, and has only one sidewall.

[0111] In this embodiment, the first step 210a and the second step 210b are respectively located on two sides of the edge of the epitaxial layer 200 , but the present invention is not limited thereto. The first step 210a and the second step 210b may also be located on the same side or diagonally of the edge of the epitaxial layer 200 .

[0112] The first electrode 601 is located on the lower step surface of the first step 210a and is electrically connected to the metal reflective layer 302; the second electrode 602 is located on the lower step surface of the second step 210b and is electrically connected to the first current spreading layer 501, and the second electrode 602 is electrically connected to the second semiconductor layer 206 through the first current spreading layer 501 and the first ohmic contact layer 216; the third electrode 603 is located on the second surface of the first substrate 101 and is electrically connected to the second current spreading layer 502 through the first substrate 101, and the third electrode 603 is electrically connected to the first semiconductor layer 204 through the first substrate 101, the second current spreading layer 502 and the second ohmic contact layer 214. In this way, the first electrode 601 can be used as one electrode of the MIS capacitor structure, the second electrode 602 can be used as the P electrode of the vertical light emitting diode, and the third electrode 603 can be used as the other electrode of the MIS capacitor structure and the N electrode of the vertical light emitting diode at the same time. The third electrode 603 can be shared or separated into two separate electrodes.

[0113] In this embodiment, the material of the first current spreading layer 501 and the second current spreading layer 502 may be at least one of Ti, Cr, Ni, Al, Au and Pt, and the thickness may be 300nm-2um, but it should not be limited thereto.

[0114] As an optional embodiment, a first adhesion layer ( Fig.14 The first adhesion layer can improve the adhesion effect between the first current spreading layer 501 and the dielectric layer. The material of the first adhesion layer can be at least one of Ti, Cr and Ni, and the thickness is 5nm to 50nm.

[0115] As an optional embodiment, a second adhesion layer ( ) may be formed between the first current spreading layer 501 and / or the second current spreading layer 502 on a side away from the first substrate 101 and the dielectric layer. Fig.14 The second adhesion layer can improve the adhesion effect between the top surface of the first current spreading layer 501 and / or the second current spreading layer 502 and the dielectric layer. The material of the second adhesion layer can be at least one of Ti, Cr and Ni, and the thickness is 5nm to 50nm.

[0116] In this embodiment, the materials of the first electrode 601 , the second electrode 602 and the third electrode 603 may be Au and / or Sn, and the thickness may be 500 nm to 20 μm, but it should not be limited thereto.

[0117] Specifically, the dielectric layer includes a first dielectric layer 401 and a second dielectric layer 402 which are sequentially stacked from top to bottom between the ODR reflective layer 300 and the first surface of the first substrate 101 .

[0118] Specifically, the first dielectric layer 401 is located on a side of the ODR reflective layer 300 close to the first substrate 101, covers the metal reflective layer 302, the sidewalls of the first through-hole and the second through-hole, and also enters the groove 200a, covers the insulating reflective layer 301 in the groove 200a. The first current spreading layer 501 is located on a side of the first dielectric layer 401 close to the first substrate 101, covers a portion of the surface of the first dielectric layer 401, and the first current spreading layer 501 passes through the first dielectric layer 401 and fills the first through-hole, and the first current spreading layer 501 contacts the first ohmic contact layer 216 to achieve electrical connection.

[0119] The second dielectric layer 402 is located on a side of the first dielectric layer 401 close to the first substrate 101, and covers the first current spreading layer 501 and the first dielectric layer 401. The second current spreading layer 502 is located on a side of the second dielectric layer 402 close to the first substrate 101, and covers the second dielectric layer 402. The second current spreading layer 502 passes through the second dielectric layer 402 and the first dielectric layer 401 and fills the second through-hole and the groove 200a. The second current spreading layer 502 contacts the second ohmic contact layer 214 to achieve electrical connection.

[0120] from Fig.14 As can be seen from the figure, the first electrode 601, the second electrode 602 and the third electrode 603 are insulated from each other by the dielectric layer.

[0121] In this embodiment, the materials of the first dielectric layer 401 and the second dielectric layer 402 can be SiO2, SiN x At least one of AlN, BN and diamond may have a thickness of 200 nm to 2 μm, but should not be limited thereto. Optionally, the materials and thicknesses of the first dielectric layer 401 and the second dielectric layer 402 may be the same or different.

[0122] As an optional embodiment, a bonding layer may be provided between the first surface of the first substrate 101 and the second current spreading layer 502, and the bonding layer is used to achieve bonding between the first substrate 101 and the second current spreading layer 502. The material of the bonding layer may be a metal alloy, such as one of a binary eutectic metal system composed of a high melting point metal such as gold (Au), nickel (Ni), copper (Cu), silver (Ag) and a low melting point metal such as tin (Sn), indium (In).

[0123] Please continue reading Fig.14 The vertical light-emitting diode further includes a passivation layer 700, which conformally covers the first surface of the first substrate 101, the surface of the low defect density layer 202, and extends to cover the sidewalls and lower step surfaces of the first step 210a and the second step 210b, that is, the passivation layer 700 covers the entire surface of the vertical light-emitting diode, thereby protecting the internal structure of the vertical light-emitting diode. It should be noted that at least part of the surface of the first electrode 601 and the second electrode 602 needs to expose the passivation layer 700 to facilitate the application of voltage.

[0124] In this embodiment, the passivation layer 700 can be a single layer or at least two layers of SiO2 and / or Al2O3, for example, it can be a three-layer film composed of SiO2-Al2O3-SiO2, so as to prevent the entry of external water vapor and improve the moisture resistance of the vertical light-emitting diode, but it should not be limited to this.

[0125] In this embodiment, when the vertical light-emitting diode is in use, the second electrode 602 is connected to a second potential, and the third electrode 603 is connected to a third potential, and the second potential is greater than the third potential, thereby providing a forward working current for the vertical light-emitting diode, so that the light-emitting layer 205 emits light; at the same time, the first electrode 601 is connected to a first potential, and the first potential is greater than the third potential, thereby providing a forward working current for the MIS capacitor structure, so that electrons gather from the first semiconductor layer 204 to the light-emitting layer 205, and holes gather from the second semiconductor layer 206 to the light-emitting layer 205, which is equivalent to improving the hole injection efficiency and increasing the radiation recombination efficiency in the light-emitting layer 205. The photoelectric conversion efficiency of the vertical light-emitting diode is improved without reducing the transmission efficiency of the radiation recombination luminescence, and the cost is low, which is of great significance for realizing the industrialization of large-size vertical light-emitting diodes. If there is no MIS capacitor structure, only the holes in the second semiconductor layer 206 at the position of the second ohmic contact layer 216 and its vicinity are injected into the light-emitting layer 205, and the holes in the area far away from the second ohmic contact layer 216 are not effectively utilized. Furthermore, since the ODR reflective layer 300 can improve light extraction efficiency, the ODR reflective layer 300 is widely used in current vertical light emitting diodes. The present invention only slightly improves the existing vertical light emitting diodes and will not significantly increase the complexity of the structure and the manufacturing process.

[0126] Optionally, the difference between the first potential and the third potential may be 3V to 10V, but should not be limited thereto.

[0127] Figure 1 The flowchart of the method for preparing the vertical light emitting diode provided in this embodiment is as follows: Figure 1 As shown, the method for preparing the vertical light emitting diode includes:

[0128] Step S100: providing a first substrate;

[0129] Step S200: transferring an epitaxial layer to the first surface of the first substrate, the epitaxial layer comprising a first semiconductor layer, a light emitting layer and a second semiconductor layer arranged in sequence from top to bottom;

[0130] Step S300: forming an ODR reflective layer, the ODR reflective layer being located between the epitaxial layer and the first surface of the first substrate, and comprising an insulating reflective layer and a metal reflective layer arranged in sequence from top to bottom, the metal reflective layer, the insulating reflective layer and the epitaxial layer forming a MIS capacitor structure; and,

[0131] Step S400: forming a first electrode, a second electrode and a third electrode which are insulated from each other, wherein the first electrode, the second electrode and the third electrode are electrically connected to the metal reflective layer, the second semiconductor layer and the first semiconductor layer respectively.

[0132] Figure 2 to Figure 14 The following is a schematic diagram of the structure corresponding to the corresponding steps of the method for preparing a vertical light emitting diode provided in this embodiment. Figure 2 to Figure 14 The method for preparing the vertical light emitting diode provided in this embodiment is described in detail.

[0133] See also Figure 2 , perform step S100 and step S200 to provide a second substrate 100. The second substrate 100 is one of the heterogeneous substrates, and its material can be any one of Ga2O3, SiC, Si, sapphire, ZnO and LiGaO2. The surface of the second substrate 100 can be prepared with micro-nano patterns, so as to improve the luminous efficiency. The micro-nano patterns can be prepared directly on the surface of the second substrate 100, or a film layer such as AlN film can be deposited on the second substrate 100 in advance. The micro-nano patterns are prepared on the pre-deposited film layer. The characteristic size range of the micro-nano patterns can be from hundreds of nanometers to several microns, and the pattern array mode can be any one of parallel straight lines, curved lines, squares and hexagonal arrangements.

[0134] At this time, the second substrate 100 may be a 1-inch to 8-inch wafer, and may have a thickness of 300 μm to 2 mm, but is not limited thereto.

[0135] Next, a buffer layer 201 is formed on the second substrate 100. The material of the buffer layer 201 can be low-temperature grown AlN, or can be sputtered AlN. The buffer layer 201 serves as a buffer structure between the second substrate 100 and the subsequently formed epitaxial layer 200, which is beneficial to improving the crystal quality of the second substrate 100 and the subsequently formed epitaxial layer 200 through the buffer layer 201 in the subsequent process.

[0136] Next, the epitaxial layer 200 is formed on the second substrate 100. Specifically, the low defect density layer 202, the stress adjustment layer 203, the first semiconductor layer 204, the light emitting layer 205 and the second semiconductor layer 206 are sequentially formed on the second substrate 100. Specifically, the low defect density layer 202, the stress adjustment layer 203, the first semiconductor layer 204, the light emitting layer 205 and the second semiconductor layer 206 can be prepared by a metal chemical vapor deposition process, a laser-assisted molecular beam epitaxy process, a laser sputtering process or a hydride vapor phase epitaxy process.

[0137] See also Figure 3, the second semiconductor layer 206 and the light emitting layer 205 are etched downward until the first semiconductor layer 204 is exposed, so as to form a plurality of the grooves 200a. Specifically, the step of forming the grooves 200a includes: processing the grooves 200a in the second semiconductor layer 206 and the light emitting layer 205 by photolithography and dry etching processes, and the depth of the grooves 200a needs to exceed the light emitting layer 205 and expose the first semiconductor layer 204.

[0138] See also Figure 4 , perform step S300 and step S400, form a second ohmic contact layer 214 in each of the grooves 200a, and form a first ohmic contact layer 216 on the second semiconductor layer 206. The second ohmic contact layer 214 and the first ohmic contact layer 216 may be formed by: forming an ohmic contact material in a corresponding area by electron beam evaporation, sputtering, atomic layer deposition, plasma assisted deposition, ion beam assisted deposition or chemical vapor deposition.

[0139] Optionally, after forming the second ohmic contact layer 214, the second ohmic contact layer 214 may be annealed to enhance the ohmic contact effect between the second ohmic contact layer 214 and the first semiconductor layer 204; after forming the first ohmic contact layer 216, the first ohmic contact layer 216 may also be annealed to enhance the ohmic contact effect between the first ohmic contact layer 216 and the second semiconductor layer 206. The annealing of the second ohmic contact layer 214 and / or the first ohmic contact layer 216 may be performed in an atmosphere of an inert gas such as N2, the annealing temperature of the annealing of the first ohmic contact layer 216 may be 450° C. to 600° C., and the annealing time may be 2 min to 20 min; the annealing temperature of the annealing of the second ohmic contact layer 214 may be 700° C. to 1100° C., and the annealing time may be 30 s to 2 min.

[0140] See also Figure 5 , an insulating reflective layer 301 is formed on the second semiconductor layer 206, and the insulating reflective layer 301 covers the second semiconductor layer 206, the first ohmic contact layer 216 and the sidewall of the groove 200a. The insulating reflective layer 301 can be formed by: using an electron beam evaporation process, a sputtering process, an atomic layer deposition process, a plasma assisted process, an ion beam assisted deposition process or a chemical vapor deposition process to fully deposit an insulating reflective material ( Figure 5(not shown), and then a portion of the insulating reflective material on the second ohmic contact layer 214 and in the groove 200a is removed by an etching process, and the remaining insulating reflective material constitutes the insulating reflective layer 301.

[0141] Please continue reading Figure 5 , a metal reflective layer 302 is formed on the insulating reflective layer 301, and the metal reflective layer 302 has a plurality of third through-holes 302a and a plurality of fourth through-holes 302b. The third through-holes 302a penetrate the metal reflective layer 302 and expose the insulating reflective layer 301, and each of the third through-holes 302a is aligned with the first ohmic contact layer 216; each of the fourth through-holes 302b penetrates the metal reflective layer 302 and is connected to one of the grooves 200a, thereby exposing the second ohmic contact layer 214. The formation process of the metal reflective layer 302 can be: forming a metal reflective material ( Figure 5 (not shown), then a portion of the metal reflective material on the insulating reflective layer 301 and the metal reflective material in the groove 200a are removed by photolithography and etching processes, and the remaining metal reflective material constitutes the metal reflective layer 302.

[0142] The insulating reflective layer 301 and the metal reflective layer 302 constitute the ODR reflective layer 300 .

[0143] See also Figure 6 , forming a first dielectric layer 401 on the metal reflective layer 302, the first dielectric layer 401 also fills the third through-hole 302a, the fourth through-hole 302b and the groove 200a, the first dielectric layer 401 has a plurality of fifth through-holes 401a and a sixth through-hole 401b, the fifth through-hole 401a is aligned with the third through-hole 302a and exposes the first ohmic contact layer 216, the sixth through-hole 401b is aligned with the fourth through-hole 302b and exposes the second ohmic contact layer 214. The formation process of the first dielectric layer 401 can be: using an electron beam evaporation process, a sputtering process, an atomic layer deposition process, a plasma assisted process, an ion beam assisted deposition process or a chemical vapor deposition process to fully deposit the first dielectric material ( Figure 6 (not shown), then the third through-hole 302a, the fourth through-hole 302b and part of the first dielectric material in the groove 200a are removed by photolithography and etching processes, and the remaining first dielectric material constitutes the first dielectric layer 401.

[0144] See also Figure 7, forming a first current spreading layer 501 on the first dielectric layer 401, wherein the first current spreading layer 501 covers a portion of the first dielectric layer 401 and fills the fifth through-hole 401a. The first current spreading layer 501 may be formed by: using an electron beam evaporation process, a sputtering process, an atomic layer deposition process, a plasma assisted process, an ion beam assisted deposition process or a chemical vapor deposition process to deposit a first current spreading material ( Figure 7 (not shown), then a portion of the first current spreading material on the first dielectric layer 401 and the first current spreading material in the sixth through-hole 401b are removed by photolithography and etching processes, and the remaining first current spreading material constitutes the first current spreading layer 501.

[0145] See also Figure 8 , forming a second dielectric layer 402 on the first current spreading layer 501 and the first dielectric layer 401, the second dielectric layer 402 also fills the sixth through-hole 401b, and the second dielectric layer 402 has a plurality of seventh through-holes 402a, the seventh through-holes 402a are aligned with the sixth through-holes 401b and expose the second ohmic contact layer 214. The formation process of the second dielectric layer 402 can be: using an electron beam evaporation process, a sputtering process, an atomic layer deposition process, a plasma assisted process, an ion beam assisted deposition process or a chemical vapor deposition process to fully deposit a second dielectric material ( Figure 8 (not shown), then a portion of the second dielectric material in the sixth through hole 401 b is removed by photolithography and etching processes, and the remaining second dielectric material constitutes the second dielectric layer 402.

[0146] See also Fig. 9 , forming a second current spreading layer 502 on the second dielectric layer 402, the second current spreading layer 502 covers the second dielectric layer 402 and fills the seventh through hole 402a. The second current spreading layer 502 can be formed by: using an electron beam evaporation process, a sputtering process, an atomic layer deposition process, a plasma assisted process, an ion beam assisted deposition process or a chemical vapor deposition process to fully deposit a second current spreading material ( Fig. 9 ), thereby forming the second current spreading layer 502.

[0147] See also Fig.10, providing a first substrate 101, and bonding the first surface of the first substrate 101 to the second current spreading layer 502. Specifically, the method for bonding the first substrate 101 may be: forming a second bonding material layer on the first surface of the first substrate 101, and then bonding the second current spreading layer 502 and the second bonding material layer together, and then at a certain temperature, using a liquid phase transient bonding process, the second bonding material layer is fused into the second current spreading layer 502 ( Fig.10 As can be seen in the figure, the thickness of the second current spreading layer 502 is increased), thereby achieving permanent bonding between the first substrate 101 and the second current spreading layer 502.

[0148] As an optional embodiment, the method for bonding the first substrate 101 may also be: forming a first bonding material layer and a second bonding material layer on the second current spreading layer 502 and the first surface of the first substrate 101, respectively, and then laminating the first bonding material layer and the second bonding material layer together, and then at a certain temperature, using a liquid phase transient bonding process, the first bonding material layer and the second bonding material layer are fused together to achieve permanent bonding of the first substrate 101 and the second current spreading layer 502. After the first bonding material layer and the second bonding material layer are fused, a bonding layer is formed between the second current spreading layer 502 and the first substrate 101.

[0149] The materials of the first bonding material layer (or the second current spreading layer 502) and the second bonding material layer can be the same, for example, both are binary bonding layers composed of an alloy of a high melting point metal and a low melting point metal; of course, the materials of the first bonding material layer (or the second current spreading layer 502) and the second bonding material layer can also be different, for example, one is a high melting point metal layer and the other is a low melting point metal layer.

[0150] Optionally, before forming the first bonding material layer and the second bonding material layer on the second current spreading layer 502 and the first surface of the first substrate 101, respectively, a fourth adhesion layer may be formed on the second current spreading layer 502 and the first surface of the first substrate 101 to enhance the adhesion between the first bonding material layer and the second current spreading layer 502 and between the second bonding material layer and the first surface of the first substrate 101 to avoid delamination. The material of the fourth adhesion layer may be titanium.

[0151] See also Fig.11, separating the second substrate 100. In this embodiment, an ultraviolet laser with a certain wavelength (for example, 193 nm) is used to irradiate the buffer layer 201 on the second substrate 100 with a small spot of a certain size (for example, 200 μm). Under the irradiation of the ultraviolet laser, the buffer layer 201 is decomposed into Al and N2, and then the second substrate 100 and the epitaxial layer 200 are separated by heating.

[0152] It should be understood that since the buffer layer 201 in this embodiment is made of AlN material, ultraviolet laser irradiation is used to separate the second substrate 100. When the material of the second substrate 100 changes, other methods such as etching can also be used to separate the second substrate 100. For example, the second substrate 100 is replaced with a silicon substrate, and the second substrate 100 is removed by a grinding process.

[0153] See also Fig.12 , etching the epitaxial layer 200 and the insulating reflective layer 301 to form a first step 210a exposing the metal reflective layer 302; etching the epitaxial layer 200, the insulating reflective layer 301 and the metal reflective layer 302 to form a second step 210b exposing the first current spreading layer 501.

[0154] Furthermore, after forming the first step 210a and the second step 210b, etching can be continued along the first step 210a and the second step 210b until the first substrate 101 is exposed. After etching is completed, horizontal and vertical scribe grooves are formed. The scribe grooves can be used to define the area of ​​a single vertical light-emitting diode, which is convenient for subsequent scribe.

[0155] Please continue reading Fig.12 The low defect density layer 202 is etched with a hot KOH solution (eg, 50° C. to 70° C.) of a certain concentration (eg, 2 mol / L to 6 mol / L) to roughen the surface of the low defect density layer 202 , thereby improving the luminous efficiency.

[0156] Please continue reading Fig.13, a first electrode 601 and a second electrode 602 are formed on the lower step surfaces of the first step 210a and the second step 210b respectively. The first electrode 601 contacts the metal reflective layer 302 to achieve electrical connection; the second electrode 602 contacts the first current spreading layer 501, thereby being electrically connected to the second semiconductor layer 206 through the first current spreading layer 501 and the first ohmic contact layer 216. The steps of forming the first electrode 601 and the second electrode 602 include: forming a photoresist mask to cover the area where the electrode does not need to be formed, then forming a conductive material by an electron beam evaporation process, and then removing the photoresist mask and the conductive material on the photoresist mask by a stripping process, and the conductive material in the area not covered by the photoresist mask is retained, thereby forming the first electrode 601 and the second electrode 602.

[0157] Next, a passivation material may be deposited on the entire surface to form a passivation layer 700. The passivation layer 700 may cover the entire surface of the low defect density layer 202 and cover the sidewalls and lower step surfaces of the first step 210a and the second step 210b, as well as the inner wall of the scribe groove, thereby isolating the epitaxial layer 200 from the outside to protect the epitaxial layer 200. It should be understood that at least a portion of the top surface of the first electrode 601 and the second electrode 602 needs to expose the passivation layer 700 so as to be used as a lead-out terminal for subsequent packaging processes. Therefore, after the passivation layer 700 is formed, an etching process may be performed to remove a portion of the passivation layer 700 so as to expose at least a portion of the top surface of the first electrode 601 and the second electrode 602.

[0158] As an optional embodiment, the passivation layer 700 can also be formed before forming the first electrode 601 and the second electrode 602. In this way, before forming the first electrode 601 and the second electrode 602, the passivation layer 700 needs to be etched to form openings to accommodate the first electrode 601 and the second electrode 602.

[0159] See also Fig.14 The third electrode 603 is formed on the second surface of the first substrate 101, and the third electrode 603 is electrically connected to the first semiconductor layer 204 through the first substrate 101, the second current spreading layer 502 and the second ohmic contact layer 214. The step of forming the third electrode 603 includes: forming a conductive material on the second surface of the first substrate 101 by an electron beam evaporation process, thereby forming the third electrode 603.

[0160] Furthermore, the first substrate 101 is cut along the scribe line by using a grinding wheel or a laser (water-guided laser, laser surface cutting), so as to separate individual vertical light-emitting diodes.

[0161] Embodiment 2

[0162] Fig.25 The schematic diagram of the structure of the vertical light emitting diode provided in this embodiment. Fig.25 As shown, the difference from the first embodiment is that in this embodiment, the vertical light emitting diode is an ultraviolet vertical light emitting diode, and the material of the first ohmic contact layer 216 is a transparent conductive material.

[0163] Specifically, in this embodiment, the first semiconductor layer 204 is an n-GaN layer, the second semiconductor layer 206 is a p-GaN layer, and the light-emitting layer 205 is a multi-quantum well layer (MQW), which can be formed by stacking an InGaN structure with a gradient In component, and the corresponding light-emitting wavelength range is 320nm to 400nm. The buffer layer 201 can be a GaN layer, the low defect density layer 202 can be a thicker non-intentionally doped GaN layer, and the stress adjustment layer 203 can be an AlGaN superlattice structure, specifically: AlGaN with a gradient Al component (gradually decreasing) is prepared from the low defect density layer 202 to the first semiconductor layer 204. x Ga 1-x N superlattice structure, wherein 0<x<0.2, thereby reducing the stress difference between the second substrate 100 and the first semiconductor layer 204 caused by the difference in lattice and thermal expansion coefficient.

[0164] It should be understood that other film layers may be formed in the epitaxial layer 200, for example, an EBL electron blocking layer may be formed between the light emitting layer 205 and the second semiconductor layer 206, which will not be explained here one by one. The thickness of the epitaxial layer 200 may be 5 μm to 10 μm, but it should not be limited thereto.

[0165] Furthermore, since the first semiconductor layer 204 is an n-GaN layer with a high electron concentration inside the film layer, the second ohmic contact layer is omitted in this embodiment, that is, the second current spreading layer 502 directly contacts the first semiconductor layer 204, which can also achieve good electrical connection.

[0166] Of course, as an optional embodiment, the second ohmic contact layer may also be prepared on the first semiconductor layer 204, and the second current spreading layer 502 is still electrically connected to the first semiconductor layer 204 through the second ohmic contact layer, which does not affect the implementation of the present invention.

[0167] Furthermore, in this embodiment, the material of the first ohmic contact layer 216 may be ITO, IFO, IZO, AZO, GZO or GTO, and the thickness may be 10 nm to 200 nm.

[0168] Furthermore, the first ohmic contact layer 216 is also covered with an etching protection layer ( Fig.25 The etching protection layer can protect the first ohmic contact layer 216 from being damaged when etching the dielectric layer (usually F-based gas is used for etching), thereby ensuring the electrical connection between the first current spreading layer 501 and the first ohmic contact layer 216. The material of the etching protection layer can be at least one of Cr, Al, Pt and Ti.

[0169] Figure 15 to Figure 25 The schematic diagram of the structure corresponding to the corresponding steps of the method for preparing the vertical light emitting diode provided in this embodiment is shown below. Figure 15 to Figure 25 The method for preparing the vertical light emitting diode provided in this embodiment is described in detail.

[0170] See also Fig.15 On the basis of forming the groove 200a in the first embodiment, a first ohmic contact layer 216 is formed only on the second semiconductor layer 206. The first ohmic contact layer 216 may be formed by an electron beam evaporation process, a sputtering process, an atomic layer deposition process, a plasma assisted process, an ion beam assisted deposition process or a chemical vapor deposition process to form an ohmic contact material in a corresponding area.

[0171] Optionally, after forming the first ohmic contact layer 216, the first ohmic contact layer 216 may be annealed to enhance the ohmic contact effect between the first ohmic contact layer 216 and the second semiconductor layer 206. The annealing of the first ohmic contact layer 216 may be performed in an atmosphere of an inert gas such as N2, the annealing temperature may be 700° C. to 1100° C., and the annealing time may be 30 s to 2 min.

[0172] See also Fig.16 , an insulating reflective layer 301 is formed on the second semiconductor layer 206, and the insulating reflective layer 301 covers the second semiconductor layer 206, the first ohmic contact layer 216 and the inner wall of the groove 200a. The insulating reflective layer 301 can be formed by: using an electron beam evaporation process, a sputtering process, an atomic layer deposition process, a plasma assisted process, an ion beam assisted deposition process or a chemical vapor deposition process to fully deposit an insulating reflective material ( Fig.16 (not shown in the figure), the insulating reflective material constitutes the insulating reflective layer 301.

[0173] Please continue reading Fig.16, a metal reflective layer 302 is formed on the insulating reflective layer 301, and the metal reflective layer has a plurality of third through-holes 302a and a plurality of fourth through-holes 302b. The third through-holes 302a penetrate the metal reflective layer 302 and expose the insulating reflective layer 301, and each of the third through-holes 302a is aligned with the first ohmic contact layer 216; each of the fourth through-holes 302b is connected to one of the grooves 200a, thereby exposing the insulating reflective layer 301 in the groove 200a. The formation process of the metal reflective layer 302 can be: forming a metal reflective material ( Fig.16 (not shown), then a portion of the metal reflective material on the insulating reflective layer 301 and the metal reflective material in the groove 200a are removed by photolithography and etching processes, and the remaining metal reflective material constitutes the metal reflective layer 302.

[0174] The insulating reflective layer 301 and the metal reflective layer 302 constitute the ODR reflective layer 300 .

[0175] See also Fig.17 , forming a first dielectric layer 401 on the metal reflective layer 302, the first dielectric layer 401 also fills the third through-hole 302a, the fourth through-hole 302b and the groove 200a, the first dielectric layer 401 has a plurality of fifth through-holes 401a and a sixth through-hole 401b, the fifth through-hole 401a is aligned with the third through-hole 302a and exposes the first ohmic contact layer 216, the sixth through-hole 401b is aligned with the fourth through-hole 302b and directly exposes the first semiconductor layer 204. The formation process of the first dielectric layer 401 can be: using an electron beam evaporation process, a sputtering process, an atomic layer deposition process, a plasma assisted process, an ion beam assisted deposition process or a chemical vapor deposition process to fully deposit the first dielectric material ( Fig.17 ), and then use photolithography and etching processes to remove the third through-hole 302a, the fourth through-hole 302b and part of the first dielectric material in the groove 200a, and also etch the insulating reflective layer 301 downward along the groove 200a until the first semiconductor layer 204 is exposed. After etching, the remaining first dielectric material constitutes the first dielectric layer 401.

[0176] See also Fig.18, forming a first current spreading layer 501 on the first dielectric layer 401, wherein the first current spreading layer 501 covers a portion of the first dielectric layer 401 and fills the fifth through-hole 401a. The first current spreading layer 501 may be formed by: using an electron beam evaporation process, a sputtering process, an atomic layer deposition process, a plasma assisted process, an ion beam assisted deposition process or a chemical vapor deposition process to deposit a first current spreading material ( Fig.18 (not shown), then a portion of the first current spreading material on the first dielectric layer 401 and the first current spreading material in the sixth through-hole 401b are removed by photolithography and etching processes, and the remaining first current spreading material constitutes the first current spreading layer 501.

[0177] See also Fig.19 , forming a second dielectric layer 402 on the first current spreading layer 501 and the first dielectric layer 401, the second dielectric layer 402 also fills the sixth through-hole 401b, and the second dielectric layer 402 has a plurality of seventh through-holes 402a, the seventh through-holes 402a are aligned with the sixth through-holes 401b and expose the first semiconductor layer 204. The formation process of the second dielectric layer 402 can be: using an electron beam evaporation process, a sputtering process, an atomic layer deposition process, a plasma assisted process, an ion beam assisted deposition process or a chemical vapor deposition process to fully deposit a second dielectric material ( Fig.19 (not shown), then a portion of the second dielectric material in the sixth through hole 401 b is removed by photolithography and etching processes, and the remaining second dielectric material constitutes the second dielectric layer 402.

[0178] See also Fig. 20 , forming a second current spreading layer 502 on the second dielectric layer 402, the second current spreading layer 502 covers the second dielectric layer 402 and fills the seventh through hole 402a. The second current spreading layer 502 can be formed by: using an electron beam evaporation process, a sputtering process, an atomic layer deposition process, a plasma assisted process, an ion beam assisted deposition process or a chemical vapor deposition process to fully deposit a second current spreading material ( Fig. 20 ), thereby forming the second current spreading layer 502.

[0179] See also Fig.21, providing a first substrate 101, and bonding the first surface of the first substrate 101 to the second current spreading layer 502. Specifically, the method for bonding the first substrate 101 may be: forming a second bonding material layer on the first surface of the first substrate 101, and then bonding the second current spreading layer 502 and the second bonding material layer together, and then at a certain temperature, using a liquid phase transient bonding process, the second bonding material layer is fused into the second current spreading layer 502 ( Fig.21 As can be seen in the figure, the thickness of the second current spreading layer 502 is increased), thereby achieving permanent bonding between the first substrate 101 and the second current spreading layer 502.

[0180] As an optional embodiment, the method for bonding the first substrate 101 may also be: forming a first bonding material layer and a second bonding material layer on the second current spreading layer 502 and the first surface of the first substrate 101, respectively, and then laminating the first bonding material layer and the second bonding material layer together, and then at a certain temperature, using a liquid phase transient bonding process, the first bonding material layer and the second bonding material layer are fused together to achieve permanent bonding of the first substrate 101 and the second current spreading layer 502. After the first bonding material layer and the second bonding material layer are fused, a bonding layer is formed between the second current spreading layer 502 and the first substrate 101.

[0181] The materials of the first bonding material layer (or the second current spreading layer 502) and the second bonding material layer can be the same, for example, both are binary bonding layers composed of an alloy of a high melting point metal and a low melting point metal; of course, the materials of the first bonding material layer (or the second current spreading layer 502) and the second bonding material layer can also be different, for example, one is a high melting point metal layer and the other is a low melting point metal layer.

[0182] Optionally, before forming the first bonding material layer and the second bonding material layer on the second current spreading layer 502 and the first surface of the first substrate 101, respectively, a fourth adhesion layer may be formed on the second current spreading layer 502 and the first surface of the first substrate 101 to enhance the adhesion between the first bonding material layer and the second current spreading layer 502 and between the second bonding material layer and the first surface of the first substrate 101 to avoid delamination. The material of the fourth adhesion layer may be titanium.

[0183] See also Fig. 22, separating the second substrate 100. In this embodiment, an ultraviolet laser with a certain wavelength (for example, 193 nm) is used to irradiate the buffer layer 201 on the second substrate 100 with a small spot of a certain size (for example, 200 μm). Under the irradiation of the ultraviolet laser, the buffer layer 201 is decomposed into Al and N2, and then the second substrate 100 and the epitaxial layer 200 are separated by heating.

[0184] It should be understood that since the buffer layer 201 in this embodiment is made of AlN material, ultraviolet laser irradiation is used to separate the second substrate 100. When the material of the second substrate 100 changes, other methods such as etching can also be used to separate the second substrate 100. For example, the second substrate 100 is replaced with a silicon substrate, and the second substrate 100 is removed by a grinding process.

[0185] See also Fig.23 , etching the epitaxial layer 200 and the insulating reflective layer 301 to form a first step 210a exposing the metal reflective layer 302; etching the epitaxial layer 200, the insulating reflective layer 301 and the metal reflective layer 302 to form a second step 210b exposing the first current spreading layer 501.

[0186] Furthermore, after forming the first step 210a and the second step 210b, etching can be continued along the first step 210a and the second step 210b until the first substrate 101 is exposed. After etching is completed, horizontal and vertical scribe grooves are formed. The scribe grooves can be used to define the area of ​​a single vertical light-emitting diode, which is convenient for subsequent scribe.

[0187] Please continue reading Fig.23 The low defect density layer 202 is etched with a hot KOH solution (eg, 50° C. to 70° C.) of a certain concentration (eg, 2 mol / L to 6 mol / L) to roughen the surface of the low defect density layer 202 , thereby improving the luminous efficiency.

[0188] Please continue reading Fig.24, a first electrode 601 and a second electrode 602 are formed on the lower step surfaces of the first step 210a and the second step 210b respectively. The first electrode 601 contacts the metal reflective layer 302 to achieve electrical connection; the second electrode 602 contacts the first current spreading layer 501, thereby being electrically connected to the second semiconductor layer 206 through the first current spreading layer 501 and the first ohmic contact layer 216. The steps of forming the first electrode 601 and the second electrode 602 include: forming a photoresist mask to cover the area where the electrode does not need to be formed, then forming a conductive material by an electron beam evaporation process, and then removing the photoresist mask and the conductive material on the photoresist mask by a stripping process, and the conductive material in the area not covered by the photoresist mask is retained, thereby forming the first electrode 601 and the second electrode 602.

[0189] Next, a passivation material may be deposited on the entire surface to form a passivation layer 700. The passivation layer 700 may cover the entire surface of the low defect density layer 202 and cover the sidewalls and lower step surfaces of the first step 210a and the second step 210b, as well as the inner wall of the scribe groove, thereby isolating the epitaxial layer 200 from the outside to protect the epitaxial layer 200. It should be understood that at least a portion of the top surface of the first electrode 601 and the second electrode 602 needs to expose the passivation layer 700 so as to be used as a lead-out terminal for subsequent packaging processes. Therefore, after the passivation layer 700 is formed, an etching process may be performed to remove a portion of the passivation layer 700 so as to expose at least a portion of the top surface of the first electrode 601 and the second electrode 602.

[0190] As an optional embodiment, the passivation layer 700 can also be formed before forming the first electrode 601 and the second electrode 602. In this way, before forming the first electrode 601 and the second electrode 602, the passivation layer 700 needs to be etched to form openings to accommodate the first electrode 601 and the second electrode 602.

[0191] See also Fig.25 The third electrode 603 is formed on the second surface of the first substrate 101, and the third electrode 603 is electrically connected to the first semiconductor layer 204 through the first substrate 101 and the second current spreading layer 502. The step of forming the third electrode 603 includes: forming a conductive material on the second surface of the first substrate 101 by an electron beam evaporation process, thereby forming the third electrode 603.

[0192] Furthermore, the first substrate 101 is cut along the scribe line by using a grinding wheel or a laser (water-guided laser, laser surface cutting), so as to separate individual vertical light-emitting diodes.

[0193] In summary, in the vertical light-emitting diode and the preparation method thereof provided in the embodiment of the present invention, the metal reflective layer and the insulating reflective layer of the ODR reflective layer are used to form a MIS (Metal-Insulator-Semiconductor) capacitor structure with the epitaxial layer. When the vertical light-emitting diode is in use, the second electrode can be connected to a relatively high potential and the third electrode can be connected to a relatively low potential, so that the light-emitting layer in the epitaxial layer emits light. At the same time, the first electrode is connected to a relatively high potential and the third electrode is connected to a relatively low potential, so that electrons gather from the first semiconductor layer of the epitaxial layer to the light-emitting layer, and holes gather from the second semiconductor layer of the epitaxial layer to the light-emitting layer, thereby improving the hole injection efficiency, increasing the radiation recombination efficiency in the light-emitting layer, and improving the photoelectric conversion efficiency without reducing the transmission efficiency of the radiation recombination luminescence, and the cost is low. In addition, since the ODR reflective layer can improve the light extraction efficiency, the ODR reflective layer is widely used in the current vertical light-emitting diodes. The present invention only slightly improves the existing vertical light-emitting diodes and will not significantly increase the complexity of the structure and the preparation process.

[0194] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0195] It should also be noted that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

[0196] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are merely used to distinguish between the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0197] It should also be recognized that the terms described herein are only used to describe specific embodiments and are not intended to limit the scope of the invention. It should be noted that the singular forms "a" and "an" used herein and in the appended claims include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps and secondary devices. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or", rather than a logical "exclusive or", unless the context clearly indicates otherwise. In addition, the implementation of the method and / or device in the embodiments of the present invention may include performing the selected task manually, automatically, or in combination.

Claims

1. A vertical light emitting diode, characterized in that: include: a first substrate; An epitaxial layer, located on the first surface of the first substrate, comprising a first semiconductor layer, a light-emitting layer and a second semiconductor layer arranged in sequence from top to bottom; An ODR reflective layer, located between the epitaxial layer and the first surface of the first substrate, includes an insulating reflective layer and a metal reflective layer arranged in sequence from top to bottom, wherein the metal reflective layer, the insulating reflective layer and the epitaxial layer constitute a MIS capacitor structure; and The first electrode, the second electrode and the third electrode which are insulated from each other are electrically connected to the metal reflective layer, the second semiconductor layer and the first semiconductor layer respectively.

2. The vertical light emitting diode according to claim 1, characterized in that: Also includes: A plurality of grooves, penetrating the second semiconductor layer and the light emitting layer and exposing the first semiconductor layer; a plurality of first through holes, penetrating the ODR reflective layer and exposing the second semiconductor layer; a plurality of second through holes, penetrating the ODR reflective layer and communicating with the corresponding grooves; and, The dielectric layer is located between the ODR reflective layer and the first surface of the first substrate and covers at least the sidewalls of the first through-hole and the second through-hole corresponding to the metal reflective layer, and is at least used to electrically isolate the first electrode and the second electrode.

3. The vertical light emitting diode according to claim 2, characterized in that: Also includes: A first step, penetrating the epitaxial layer and exposing the metal reflective layer, wherein the first electrode is located on a lower step surface of the first step and is electrically connected to the metal reflective layer; a first current spreading layer, located in the dielectric layer and passing through a portion of the dielectric layer to fill the first through hole so as to be electrically connected to the second semiconductor layer; a second step, penetrating the epitaxial layer, the ODR reflective layer and a portion of the dielectric layer and exposing the first current spreading layer, wherein the second electrode is located on a lower step surface of the second step and is electrically connected to the first current spreading layer; as well as, The second current spreading layer is located between the dielectric layer and the first surface of the first substrate, and is electrically connected to the first semiconductor layer after passing through the dielectric layer and filling the second through-hole and the groove. The third electrode is located on the second surface of the first substrate, and is electrically connected to the second current spreading layer through the first substrate.

4. The vertical light emitting diode according to claim 3, characterized in that: The dielectric layer includes a first dielectric layer and a second dielectric layer stacked sequentially on the metal reflective layer, the first current spreading layer is located between the first dielectric layer and the second dielectric layer, penetrates the first dielectric layer and fills the first through-hole and is electrically connected to the second semiconductor layer, and the second current spreading layer is located between the second dielectric layer and the first surface of the first substrate, penetrates the second dielectric layer and the first dielectric layer and fills the second through-hole and the groove and is electrically connected to the first semiconductor layer.

5. The vertical light emitting diode according to claim 3, characterized in that: Also includes: The first ohmic contact layer is located on a surface of the second semiconductor layer close to the first substrate and in each of the first through-holes. After the first current spreading layer fills the first through-holes, it is electrically connected to the second semiconductor layer through the first ohmic contact layer.

6. The vertical light emitting diode according to claim 5, characterized in that: The material of the first ohmic contact layer is a metal material; and / or the thickness of the first ohmic contact layer is 10 nm to 200 nm.

7. The vertical light emitting diode according to claim 5, characterized in that: The material of the first ohmic contact layer is a transparent conductive material, and a surface of the first ohmic contact layer close to the first substrate is also covered with an etching protection layer; and / or the thickness of the first ohmic contact layer is 10nm to 200nm.

8. The vertical light emitting diode according to claim 5, characterized in that: Also includes: The second ohmic contact layer is located on a surface of the first semiconductor layer close to the first substrate and in each of the grooves. After the second current spreading layer fills the second through-hole and the grooves, it is electrically connected to the first semiconductor layer through the second ohmic contact layer.

9. The vertical light emitting diode according to claim 3, characterized in that: A bonding layer is further provided between the second current spreading layer and the first surface of the first substrate.

10. The vertical light emitting diode according to claim 3, characterized in that: A first adhesion layer is provided between the first current spreading layer and the dielectric layer at a surface close to the first substrate; and / or a second adhesion layer is provided between the first current spreading layer and / or the second current spreading layer and the dielectric layer at a surface away from the first substrate.

11. The vertical light emitting diode according to claim 10, characterized in that: The material of the first adhesion layer and / or the second adhesion layer is at least one of Ti, Cr and Ni; the thickness of the first adhesion layer and / or the second adhesion layer is 5nm-50nm.

12. The vertical light emitting diode according to claim 3, characterized in that: Also includes: A passivation layer conformally covers the surface of the epitaxial layer, the sidewall and lower step surface of the first step, and the sidewall and lower step surface of the second step, and at least part of the surface of the first electrode and the second electrode is exposed from the passivation layer.

13. The vertical light emitting diode according to claim 12, characterized in that: The passivation layer is a single layer or at least two layers of SiO2 and / or Al2O3.

14. The vertical light emitting diode according to claim 4, characterized in that: The materials of the first dielectric layer and the second dielectric layer are SiO2 and SiN x , at least one of AlN, BN and diamond; and / or, the thickness of the first dielectric layer and the second dielectric layer are respectively 200nm~2μm.

15. The vertical light emitting diode according to claim 1, characterized in that: The insulating reflective layer is a single-layer reflective film or is formed by two layers of reflective films with different refractive indices being alternately distributed.

16. The vertical light emitting diode according to claim 15, characterized in that: The material of the reflective film is SiO2, Al2O3, HfO2, SiN x , AlN, BN or MgF2; and / or, the thickness of the reflective film is λ / 4n, wherein λ is the light emitting wavelength of the light emitting layer and n is the refractive index of the reflective film.

17. The vertical light emitting diode according to any one of claims 1 to 16, characterized in that: When the vertical light emitting diode is in use, the first electrode is connected to a first potential, the second electrode is connected to a second potential, the third electrode is connected to a third potential, and the first potential and the second potential are both greater than the third potential.

18. The vertical light emitting diode according to claim 17, characterized in that: The difference between the first potential and the third potential is 3V to 10V.

19. A method for preparing a vertical light emitting diode, characterized in that: include: providing a first substrate; Transferring an epitaxial layer to the first surface of the first substrate, the epitaxial layer comprising a first semiconductor layer, a light-emitting layer and a second semiconductor layer arranged in sequence from top to bottom; forming an ODR reflective layer, the ODR reflective layer being located between the epitaxial layer and the first surface of the first substrate, and comprising an insulating reflective layer and a metal reflective layer arranged in sequence from top to bottom, the metal reflective layer, the insulating reflective layer and the epitaxial layer constituting a MIS capacitor structure; and, A first electrode, a second electrode and a third electrode are formed which are insulated from each other. The first electrode, the second electrode and the third electrode are electrically connected to the metal reflective layer, the second semiconductor layer and the first semiconductor layer respectively.

20. The method for preparing a vertical light emitting diode according to claim 19, wherein: The steps of forming the epitaxial layer and the ODR reflective layer include: Providing a second substrate, and sequentially forming the first semiconductor layer, the light-emitting layer, and the second semiconductor layer on the second substrate; Etching the second semiconductor layer and the light emitting layer to form a plurality of grooves exposing the first semiconductor layer; forming the insulating reflective layer on the second semiconductor layer; and, The metal reflection layer is formed on a portion of the insulating reflection layer. The metal reflection layer has a plurality of third through holes and a plurality of fourth through holes. The third through holes expose the insulating reflection layer, and the fourth through holes are connected to the groove.

21. The method for preparing a vertical light emitting diode according to claim 20, characterized in that: After forming the groove and before forming the insulating reflective layer, the method further includes: A first ohmic contact layer is formed on a portion of the second semiconductor layer, and each of the third through holes is aligned with the first ohmic contact layer.

22. The method for preparing a vertical light emitting diode according to claim 21, characterized in that: The material of the first ohmic contact layer is a metal material; and / or the thickness of the first ohmic contact layer is 10 nm to 200 nm.

23. The method for preparing a vertical light emitting diode according to claim 21, characterized in that: After the first ohmic contact layer is formed, an etching protection layer is further formed on the first ohmic contact layer.

24. The method for preparing a vertical light emitting diode according to claim 23, characterized in that: The material of the first ohmic contact layer is a transparent conductive material; and / or the thickness of the first ohmic contact layer is 10 nm to 200 nm.

25. The method for preparing a vertical light emitting diode according to claim 21, characterized in that: When forming the first ohmic contact layer, a second ohmic contact layer is also formed on the first semiconductor layer in each of the grooves, and each of the fourth through holes exposes the second ohmic contact layer.

26. The method for preparing a vertical light emitting diode according to any one of claims 20 to 25, characterized in that: The step of forming the first electrode, the second electrode and the third electrode which are insulated from each other comprises: Forming a first dielectric layer on the metal reflective layer, the first dielectric layer also filling the third through-hole, the fourth through-hole and the groove, the first dielectric layer having a plurality of fifth through-holes and a plurality of sixth through-holes, the fifth through-holes aligning with the third through-holes and exposing the second semiconductor layer, the sixth through-holes aligning with the fourth through-holes and exposing the first semiconductor layer; forming a first current spreading layer on a portion of the first dielectric layer, wherein the first current spreading layer fills the fifth through-hole and is electrically connected to the second semiconductor layer; forming a second dielectric layer on the first current spreading layer and the first dielectric layer, wherein the second dielectric layer further fills the sixth through-hole, and the second dielectric layer has a plurality of seventh through-holes, wherein the seventh through-holes are aligned with the sixth through-holes and expose the first semiconductor layer; forming a second current spreading layer on at least a portion of the second dielectric layer, wherein the second current spreading layer fills the seventh through hole and is electrically connected to the first semiconductor layer; bonding the first substrate on the second current spreading layer, and separating the second substrate; Sequentially etching the epitaxial layer and the insulating reflective layer to form a first step exposing the metal reflective layer, and sequentially etching the epitaxial layer and the ODR reflective layer to form a second step exposing the first current spreading layer; forming a first electrode and a second electrode on lower step surfaces of the first step and the second step, respectively, the first electrode and the second electrode being electrically connected to the metal reflection layer and the first current spreading layer, respectively; and, A third electrode is formed on the second surface of the first substrate, and the third electrode is electrically connected to the second current spreading layer through the first substrate.

27. The method for preparing a vertical light emitting diode according to claim 26, wherein: A first adhesion layer is provided between the first current spreading layer and the dielectric layer at a surface close to the first substrate; and / or a second adhesion layer is provided between the first current spreading layer and / or the second current spreading layer and the dielectric layer at a surface away from the first substrate.

28. The method for preparing a vertical light emitting diode according to claim 27, characterized in that: The material of the first adhesion layer and / or the second adhesion layer is at least one of Ti, Cr and Ni; the thickness of the first adhesion layer and / or the second adhesion layer is 5nm-50nm.

29. The method for preparing a vertical light emitting diode according to claim 26, wherein: The materials of the first dielectric layer and the second dielectric layer are SiO2 and SiN x , at least one of AlN, BN and diamond; and / or, the thickness of the first dielectric layer and the second dielectric layer are respectively 200nm~2μm.

30. The method for preparing a vertical light emitting diode according to claim 26, wherein: The step of bonding the first substrate on the second current spreading layer comprises: forming a first bonding material layer and a second bonding material layer on the second current spreading layer and the first substrate respectively; and, The first bonding material layer and the second bonding material layer are fused to bond the first substrate on the second current spreading layer. After the first bonding material layer and the second bonding material layer are fused, a bonding layer is formed between the first substrate and the second current spreading layer.

31. The method for preparing a vertical light emitting diode according to claim 26, wherein: The step of bonding the first substrate on the second current spreading layer comprises: forming a second bonding material layer on the first surface of the first substrate; and, The second bonding material layer is fused into the second current spreading layer to bond the first substrate on the second current spreading layer.

32. The method for preparing a vertical light emitting diode according to claim 26, wherein: After forming the first step and the second step, the method further includes: Continue etching along the first step and the second step until a scribe line is formed that exposes the first surface of the first substrate; and, After forming the first electrode, the second electrode and the third electrode, the first substrate is cut along the scribe line to form a single vertical light emitting diode.

33. The method for preparing a vertical light emitting diode according to claim 26, wherein: Before or after forming the first electrode and the second electrode, and before forming the third electrode, the method further includes: A passivation layer is formed, the passivation layer conformally covers the surface of the epitaxial layer, the sidewall and lower step surface of the first step, and the sidewall and lower step surface of the second step, and at least part of the surface of the first electrode and the second electrode is exposed from the passivation layer.

34. The method for preparing a vertical light emitting diode according to claim 33, characterized in that: The passivation layer is a single layer or at least two layers of SiO2 and / or Al2O3.

35. The method for preparing a vertical light emitting diode according to claim 19, wherein: The insulating reflective layer is a single-layer reflective film or is formed by two layers of reflective films with different refractive indices being alternately distributed.

36. The method for preparing a vertical light emitting diode according to claim 35, characterized in that: The material of the reflective film is SiO2, Al2O3, HfO2, SiN x , AlN, BN or MgF2; and / or, the thickness of the reflective film is λ / 4n, wherein λ is the light emitting wavelength of the light emitting layer and n is the refractive index of the reflective film.

37. The method for preparing a vertical light emitting diode according to claim 19, wherein: When the vertical light emitting diode is in use, the first electrode is connected to a first potential, the second electrode is connected to a second potential, the third electrode is connected to a third potential, and the first potential and the second potential are both greater than the third potential.

38. The method for preparing a vertical light emitting diode according to claim 37, characterized in that: The difference between the first potential and the third potential is 3V to 10V.

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