Average Current Controller and BUCK Constant Current Circuit

Abstract

The present invention provides an average current controller and a BUCK constant current circuit. The controller includes: a capacitor charge / discharge control module, a capacitor charge / discharge module, a MOS transistor turn-off signal control module, and a logic control module. The capacitor charge / discharge control module controls the equal current charge / discharge of the capacitor in the capacitor charge / discharge module based on the charge / discharge control signal generated from the sampled voltage and the reference voltage, so as to achieve the precise replication of the Δt time. In addition, the MOS transistor turn-off signal control module generates a turn-off control signal based on the voltage of the capacitor in the capacitor charge / discharge module, so that the logic control module generates a turn-off signal of the MOS transistor based on the turn-off control signal, thereby achieving the turn-off of the MOS transistor. Finally, the logic control module generates a turn-on signal of the MOS transistor after a preset time and enters the next Ton time, repeating in cycles. This controller can well solve the problem of the constant current accuracy of the load output, and does not require a high-voltage differential sampling circuit, which can solve the problems of high process requirements and high cost.

Description

Technical Field

[0001] The present invention relates to the technical field of constant current drive power supplies, and particularly to an average current controller and a BUCK constant current circuit. Background Art

[0002] LED lighting sources have the advantages of environmental protection, energy conservation, long lifespan, etc., and are regarded as the most promising lighting sources in the 21st century. In recent years, with the development of LED lighting technology, LED lighting sources have begun to replace traditional light sources and are widely used in various lighting fixtures. To obtain an ideal lighting effect, LEDs require a constant current drive power supply.

[0003] The core of DC LED drive technology is to solve the problem of constant current control, that is, the LED driver should be able to ensure the stability of the output current under various external changes. Currently, there are generally two classification methods for constant current control. The first is to distinguish according to different circuit topologies. Different topologies have different constant current control methods due to different conversion ratios, such as linear, buck (step-down conversion), buck-boost, etc. The second is to distinguish according to different control principles, which are divided into open-loop control and closed-loop feedback control. Since the buck topology is simple and has strong adaptability, and the open-loop control has a lower cost, the BUCK architecture with open-loop constant current control (as Figure 1 shown) is one of the mainstream topologies of DC LED drivers.

[0004] As Figure 2 shown, it is the topology of the existing BUCK architecture with open-loop constant current control, where the current sampling resistor Rcs is at the high voltage end. Figure 3 For its common control method (also known as Bang-bang control), the inductor L current is sampled through a differential operational amplifier. The internal set current peak given value Ipk and the current valley given value Iva are set. When the inductor current reaches Ipk, the Mos transistor N is turned off; when the inductor current reaches Iva, the Mos transistor N is turned on, and so on, controlling the average value of the inductor current at 1 / (Ipk + Iva), and the output LED current is equal to the inductor current, thereby controlling the constancy of the output current.

[0005] As Figure 4 shown, it is the topology of the existing BUCK architecture with open-loop constant current control, where the current sampling resistor Rcs is at the low voltage end. Figure 5Its common control method (also known as Constant Toff control) samples the current when Mos tube N is turned on through the single-ended current sampling resistor Rcs. The internal set current peak given value Ipk and the fixed Toff time are set. When the inductor current reaches Ipk, Mos tube N is turned off; when the fixed Toff time arrives, Mos tube N is turned on, and so on. The average value of the inductor L current is controlled at Ipk - 0.5 * Vout * Toff / L, and the output LED lamp voltage Vout and the inductance L are basically unchanged, thereby controlling the constancy of the output current.

[0006] For the Bang-bang control method, a high-voltage differential sampling circuit is required, and the process requirements are relatively high. Currently, the highest can reach about 60V, and the cost will be very high if it is made higher; while using the Constant Toff control method, the system consistency requirements are relatively high. Because there are differences in the output lamp voltage and inductance among individuals, it will affect the system constant current accuracy, and it is very difficult to achieve below ±5% in practice. Therefore, for the medium-voltage BUCK LED driver market with a breakdown voltage above 60V, if the constant current consistency requirements are relatively high, neither of the above two control methods can meet the requirements well. Summary of the Invention

[0007] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide an average current controller and a BUCK constant current circuit, which are used to solve the problems that in the prior art, for the medium-voltage BUCK drive market, if the constant current consistency requirements are relatively high, neither the Bang-bang control method nor the Constant Toff control method can meet the market demand.

[0008] To achieve the above purpose and other related purposes, the present invention provides an average current controller, which is applied to a BUCK circuit. The BUCK circuit operates in the CCM mode and the current sampling resistor is set at the low-voltage end. The average current controller includes:

[0009] A capacitor charge / discharge control module, a capacitor charge / discharge module, a MOS tube turn-off signal control module, and a logic control module;

[0010] The capacitor charge / discharge control module is connected to the current sampling resistor and receives a reference voltage, and generates a charge / discharge control signal based on the sampling voltage of the current sampling resistor and the reference voltage;

[0011] The capacitor charge / discharge module is connected to the output end of the capacitor charge / discharge control module, and controls the equal-current charge / discharge of the capacitor in the capacitor charge / discharge module based on the charge / discharge control signal;

[0012] The MOS transistor turn-off signal control module is connected to the output terminal of the capacitor charge / discharge module, and generates a turn-off control signal based on the voltage of the capacitor in the capacitor charge / discharge module;

[0013] The logic control module is connected to the output terminal of the MOS transistor turn-off signal control module, generates the turn-off signal of the MOS transistor in the BUCK circuit based on the turn-off control signal, and generates the turn-on signal of the MOS transistor after a preset time.

[0014] Optionally, the BUCK circuit includes: the current sampling resistor, the MOS transistor, the freewheeling diode, the capacitor and the inductor; the first end of the current sampling resistor is connected to the first end of the MOS transistor, and the second end is connected to the low-voltage end of the DC power supply; the second end of the MOS transistor is connected to the anode of the freewheeling diode and the first end of the inductor; the second end of the inductor is connected to the first end of the capacitor; the high-voltage end of the DC power supply is connected to the cathode of the freewheeling diode and the second end of the capacitor.

[0015] Optionally, the capacitor charge / discharge control module includes:

[0016] A comparator and a switch;

[0017] The negative input terminal of the comparator is connected to the sampling voltage, the positive input terminal of the comparator is connected to the reference voltage, and the output terminal of the comparator is connected to the switch.

[0018] Optionally, the capacitor charge / discharge control module includes:

[0019] A first capacitor, a second capacitor, a first comparator, a first switch, a second switch, a third switch, a fourth switch, a fifth switch and a sixth switch;

[0020] The first end of the first switch is connected to the sampling voltage, and the second end is connected to the first end of the third switch and the first end of the first capacitor;

[0021] The second end of the third switch is connected to the reference voltage;

[0022] The second end of the first capacitor is connected to the first end of the second capacitor and the negative input terminal of the first comparator;

[0023] The second end of the second capacitor is connected to the first end of the second switch and the first end of the fourth switch;

[0024] The second end of the second switch is connected to the sampling voltage, and the second end of the fourth switch is connected to the reference ground terminal;

[0025] The positive input terminal of the first comparator is connected to a first bias voltage, and the output terminal of the first comparator is connected to the first terminal of the sixth switch;

[0026] The fifth switch is connected between the negative input terminal and the output terminal of the first comparator;

[0027] The second terminal of the sixth switch is connected to the capacitor charge / discharge module.

[0028] Optionally, the capacitor charge / discharge module includes:

[0029] An inverter, a P-type MOS transistor, an N-type MOS transistor, a first constant current source, a second constant current source, and a third capacitor;

[0030] The input terminal of the inverter is connected to the capacitor charge / discharge control module, and the output terminal is connected to the gate of the P-type MOS transistor and the gate of the N-type MOS transistor;

[0031] The source of the P-type MOS transistor is connected to the operating voltage, and the drain is connected to the first terminal of the third capacitor through the first constant current source;

[0032] The source of the N-type MOS transistor Q2 is connected to the reference ground terminal, and the drain is connected to the first terminal of the third capacitor through the second constant current source;

[0033] The second terminal of the third capacitor is connected to the reference ground terminal.

[0034] Optionally, the MOS transistor turn-off signal control module includes:

[0035] A seventh switch and a second comparator;

[0036] The seventh switch is connected between the positive input terminal and the negative input terminal of the second comparator;

[0037] The positive input terminal of the second comparator is connected to a second bias voltage, the negative input terminal is connected to the first terminal of the third capacitor, and the output terminal outputs the turn-off control signal.

[0038] Optionally, the MOS transistor is an N-channel enhancement-mode MOS transistor.

[0039] The present invention further provides a BUCK constant current circuit, which is connected to a DC power supply and outputs a constant current to a load. The BUCK constant current circuit includes the average current controller described in any one of the above.

[0040] Optionally, the load is an LED.

[0041] As described above, the average current controller and the BUCK constant current circuit of the present invention are directed to the BUCK architecture that uses open-loop constant current control in the prior art. For the sampling topology of the current sampling resistor Rcs at the low-voltage end, a control method of 2-fold Δt control + constant turn-off time Toff can be used to achieve the constant current output of the BUCK architecture. As long as it is ensured that the system operates in CCM, the switch current at only the Ton moment can be sampled to control the magnitude of the load output current, and the load output current does not change with the output voltage Vout and the inductance L, which can well solve the problem of output constant current accuracy, and a high-voltage differential sampling circuit is not required, which can solve the problems of high process requirements and high cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It shows a schematic diagram of a BUCK architecture that uses open-loop constant current control in the prior art.

[0043] Figure 2 It shows a schematic diagram of the topology of the BUCK architecture that uses open-loop constant current control in the prior art, where the current sampling resistor is at the high-voltage end.

[0044] Figure 3 It shows Figure 2 the method for implementing open-loop constant current control of the BUCK architecture.

[0045] Figure 4 It shows a schematic diagram of the topology of the BUCK architecture that uses open-loop constant current control in the prior art, where the current sampling resistor is at the low-voltage end.

[0046] Figure 5 It shows Figure 4 the method for implementing open-loop constant current control of the BUCK architecture.

[0047] Figure 6 It shows the method for implementing open-loop constant current control of the BUCK architecture by the average current controller of the present invention.

[0048] Figure 7 It shows a schematic diagram of an embodiment of the capacitor charge / discharge control module in the average current controller of the present invention.

[0049] Figure 8 It shows a schematic diagram of the average current controller of the present invention.

[0050] DESCRIPTION OF REFERENCE NUMERALS

[0051] 100 Capacitor charge / discharge control module

[0052] 200 Capacitor charge / discharge module

[0053] 300 MOS transistor turn-off signal control module

[0054] 400 Logic Control Module Detailed Implementation Manner

[0055] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0056] Please refer to Figures 6 to 8 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and ratios of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0057] As Figure 6 and Figure 8 shown, the average current controller provided in this embodiment, for the BUCK architecture that uses open-loop constant current control in the prior art and the sampling topology of the current sampling resistor Rcs at the low-voltage end, can implement a control method of 2 times Δt control (i.e., conduction time Ton) + constant turn-off time Toff (or constant frequency f) to achieve constant current output of the BUCK architecture. As long as it is ensured that the system operates in CCM (Continuous Conduction Mode), the MOS tube switch current at the Ton moment can be sampled only to control the magnitude of the load output current, and the load output current does not change with the output voltage Vout and the inductance L, which can well solve the problem of output constant current accuracy, and does not require a high-voltage differential sampling circuit, which can solve the problems of high process requirements and high cost.

[0058] The average current controller includes:

[0059] a capacitor charge / discharge control module 100, a capacitor charge / discharge module 200, a MOS tube turn-off signal control module 300, and a logic control module 400;

[0060] The capacitor charge / discharge control module 100 is connected to the current sampling resistor Rcs and receives a reference voltage Vref, and generates a charge / discharge control signal based on the sampling voltage Vcs of the current sampling resistor Rcs and the reference voltage Vref;

[0061] The capacitor charge / discharge module 200 is connected to the output end of the capacitor charge / discharge control module 100, and controls the capacitor (such asFigure 8 equal current charging / discharging of the third capacitor C3 therein;

[0062] The MOS transistor turn-off signal control module 300 is connected to the output end of the capacitor charging / discharging module 200, and generates a turn-off control signal based on the voltage of the capacitor in the capacitor charging / discharging module 200;

[0063] The logic control module 400 is connected to the output end of the MOS transistor turn-off signal control module 300, generates a turn-off signal of the MOS transistor N in the BUCK circuit based on the turn-off control signal, and generates a turn-on signal of the MOS transistor N after a preset time Toff (Toff is the constant turn-off time of the MOS transistor N).

[0064] As Figure 6 shown, within the Ton time, the equal current charging / discharging of the capacitor in the capacitor charging / discharging module 200 is controlled by the charging / discharging control signal generated by the capacitor charging / discharging control module 100 based on the sampled voltage Vcs of the current sampling resistor Rcs and the reference voltage Vref. The equal current charging of the capacitor is achieved through the Δt time, and then the equal current discharging of the capacitor is achieved through the Δt time, so as to achieve the accurate replication of the Δt time. In addition, the MOS transistor turn-off signal control module 300 generates a turn-off control signal based on the voltage of the capacitor in the capacitor charging / discharging module 200, so that the logic control module 400 generates a turn-off signal of the MOS transistor N based on this turn-off control signal, thereby achieving the turn-off of the MOS transistor N after 2 times of the Δt time. Finally, the logic control module 400 generates a turn-on signal of the MOS transistor N after a preset time Toff, and enters the next Ton time, repeating in cycles, thereby realizing the control method of 2 times of the Δt control + the constant turn-off time Toff. This control method can control the magnitude of the output current by only sampling the MOS transistor current within the Ton time, and the output current is always constant at Vref / Rcs. This output current does not change with the output voltage Vout and the inductance L, thus effectively solving the problem of the output constant current accuracy, and does not require a high-voltage differential sampling circuit, which can solve the problems of high process requirements and high cost.

[0065] As Figure 4As shown, by way of example, the BUCK circuit includes: the current sampling resistor Rcs, the MOS transistor N, the freewheeling diode D, the capacitor C, and the inductor L; the first end of the current sampling resistor Rcs is connected to the first end of the MOS transistor N, and the second end is connected to the low-voltage end of the DC power supply DC; the second end of the MOS transistor N is connected to the anode of the freewheeling diode D and the first end of the inductor L; the second end of the inductor L is connected to the first end of the capacitor C; the high-voltage end of the DC power supply DC is connected to the cathode of the freewheeling diode D and the second end of the capacitor C. It should be noted here that Figure 4 This is only a schematic diagram of the BUCK circuit. Those skilled in the art know that the BUCK circuit can also have other forms of deformation, and all of them can use the average current controller of this embodiment to achieve open-loop constant current control.

[0066] As Figure 7 shown, by way of example, the capacitor charge / discharge control module 100 includes: a comparator Cp and a switch SW;

[0067] The negative input terminal of the comparator Cp is connected to the sampling voltage Vcs, the positive input terminal of the comparator Cp is connected to the reference voltage Vref, and the output terminal of the comparator Cp is connected to the switch SW.

[0068] The working process of the capacitor charge / discharge control module 100 is as follows: during the time when the MOS transistor N in the BUCK circuit is in the off state, that is, during the Toff time, the switch SW is disconnected; during the time when the MOS transistor N in the BUCK circuit is in the on state, that is, during the Ton time, the switch SW is closed, and when the sampling voltage Vcs is less than the reference voltage Vref, the output terminal of the comparator Cp sends a charge control signal to the capacitor charge / discharge module 200 to form a Δt time. When the sampling voltage Vcs is greater than the reference voltage Vref, the output terminal of the comparator Cp sends a discharge control signal to the capacitor charge / discharge module 200 to accurately replicate the Δt time, so as to achieve a Ton time of 2 times Δt. And during this process, since the reference voltage Vref is always at the midpoint of the sampling voltage Vcs during the Ton period, the output current is ensured to be constant at Vref / Rcs all the time.

[0069] Due to efficiency issues, the current sampling resistor Rcs is generally very small, and the obtained sampling voltage Vcs is also very small. If the sampling voltage Vcs is directly input to the comparator to control the charge and discharge of the capacitor, the delay is relatively large, and the delay of the comparator will affect the constant current accuracy of the system. Based on this, as Figure 8As shown, as a further example, a capacitance charge / discharge control module 100 is provided to solve this problem. The capacitance charge / discharge control module 100 includes:

[0070] a first capacitor C1, a second capacitor C2, a first comparator Cp1, a first switch SW1, a second switch SW2, a third switch SW3, a fourth switch SW4, a fifth switch SW5, and a sixth switch SW6;

[0071] A first end of the first switch SW1 is connected to the sampling voltage Vcs, and a second end thereof is connected to a first end of the third switch SW3 and a first end of the first capacitor C1;

[0072] A second end of the third switch SW3 is connected to the reference voltage Vref;

[0073] A second end of the first capacitor C1 is connected to a first end of the second capacitor C2 and a negative input terminal of the first comparator Cp1;

[0074] A second end of the second capacitor C2 is connected to a first end of the second switch SW2 and a first end of the fourth switch SW4;

[0075] A second end of the second switch SW2 is connected to the sampling voltage Vcs, and a second end of the fourth switch SW4 is connected to the reference ground terminal;

[0076] A positive input terminal of the first comparator Cp1 is connected to a first bias voltage Vbias1, and an output terminal of the first comparator Cp1 is connected to a first end of the sixth switch SW6;

[0077] The fifth switch SW5 is connected between the negative input terminal and the output terminal of the first comparator Cp1;

[0078] A second end of the sixth switch SW6 is connected to the capacitance charge / discharge module 200.

[0079] The working process of the capacitor charge / discharge control module 100 is as follows: During the time when the MOS transistor N in the BUCK circuit is in the off state, that is, during the Toff time, the third switch SW3, the fourth switch SW4, and the fifth switch SW5 are closed. At this time, capacitors C1 and C2 are connected in series, and the comparator Cp1 is configured in a follower structure. The voltage Vc at the negative input terminal of the first comparator Cp1 is Vbias1. Then, the charge stored on capacitor C1 is C1*(Vbias1 - Vref), and the charge stored on capacitor C2 is C2*Vbias1. During the time when the MOS transistor N in the BUCK circuit is in the on state, the first switch SW1, the second switch SW2, and the sixth switch SW6 are closed. Capacitors C1 and C2 are connected in parallel, one end is connected to the voltage Vc at the negative input terminal of the first comparator Cp1, and the other end is connected to the sampling voltage Vcs. The charge stored on capacitors C1 and C2 is (C1 + C2)*Vc. Since the charge transfer of the switching point capacitance of the MOS transistor N follows the principle of total charge conservation, the following equation can be obtained:

[0080] C1*(Vbias1 - Vref)+C2*Vbias1 = (C1 + C2)*Vc

[0081] After conversion, it can be obtained that: Vc = Vbias1 - Vref*C1 / (C1 + C2). When one end of capacitors C1 and C2 changes from the reference ground to the sampling voltage Vcs, it is equivalent to raising the level of capacitors C1 and C2 by a sampling voltage Vcs. That is, during the Ton time when the MOS transistor N is conducting, the absolute voltage of Vc is: Vc = Vbias1 - Vref*C1 / (C1 + C2)+Vcs. And this Vc value will be compared with Vbias1. Vcs gradually increases with the Ton time, and Vc also gradually increases. In the first half of Ton, that is, during the △t time, Vcs < Vref*C1 / (C1 + C2), so Vc < Vbias1, and the comparator Cp1 outputs 1, sending a charge control signal to the capacitor charge / discharge module 200. In the second half of Ton, that is, during the copied △t time, Vcs > Vref*C1 / (C1 + C2), so Vc > Vbias1, and the comparator Cp1 outputs 0, sending a discharge control signal to the capacitor charge / discharge module 200. The logic of the entire control ensures that the average value of Vcs during the Ton time period is Vref*C1 / (C1 + C2). By properly matching the ratio of C1 and C2 in the circuit, the constant current control of Vref for Vcs during the Ton time period is completed. Since the system operates in the CCM mode, the average value of the switching current during the Ton time period is equal to the average value of the inductor current, which is also equal to the average value of the load output current. Therefore, this circuit controls the average value of the switching current during the Ton time period through Vref, and indirectly achieves the purpose of controlling the load output current.

[0082] As Figure 8 shown, as an example, the capacitor charge / discharge module 200 includes:

[0083] an inverter, a P-type MOS transistor Q1, an N-type MOS transistor Q2, a first constant current source, a second constant current source, and a third capacitor C3;

[0084] The input terminal of the inverter is connected to the capacitor charge / discharge control module 100, and the output terminal is connected to the gate of the P-type MOS transistor Q1 and the gate of the N-type MOS transistor Q2;

[0085] The source of the P-type MOS transistor Q1 is connected to the working voltage, and the drain is connected to the first end of the third capacitor C3 through the first constant current source;

[0086] The source of the N-type MOS transistor Q2 is connected to the reference ground terminal, and the drain is connected to the first end of the third capacitor C3 through the second constant current source;

[0087] The second end of the third capacitor C3 is connected to the reference ground terminal.

[0088] When the capacitor charge / discharge module 200 receives the charge control signal sent by the capacitor charge / discharge control module 100, as a specific example of as Figure 8 such, when the comparator Cp1 in the capacitor charge / discharge control module 100 outputs 1, the P-type MOS transistor Q1 is turned on, and the third capacitor C3 is charged, that is, the Δt time is achieved; when the capacitor charge / discharge module 200 receives the discharge control signal sent by the capacitor charge / discharge control module 100, as a specific example of as Figure 8 such, when the comparator Cp1 in the capacitor charge / discharge control module 100 outputs 0, the N-type MOS transistor Q2 is turned on, and the third capacitor C3 is discharged, and through the first constant current source and the second constant current source, it can be ensured that the charge / discharge currents of the third capacitor C3 are equal, that is, the accurate replication of the Δt time is achieved.

[0089] As Figure 8 shown, as an example, the MOS transistor turn-off signal control module 300 includes:

[0090] a seventh switch SW7 and a second comparator Cp2;

[0091] The seventh switch SW7 is connected between the positive input terminal and the negative input terminal of the second comparator Cp2;

[0092] The positive input terminal of the second comparator Cp2 is connected to a second bias voltage Vbias2, the negative input terminal is connected to the first end of the third capacitor C3, and the output terminal outputs the turn-off control signal.

[0093] During the time when the MOS transistor N in the BUCK circuit is in the off state, that is, during the Toff time, the seventh switch SW7 is closed; during the time when the MOS transistor N in the BUCK circuit is in the on state, that is, during the Ton time, the seventh switch SW7 is open. In this way, it can be ensured that when the third capacitor C3 is exactly discharged to the second bias voltage Vbias2, a Reset signal is issued, that is, the turn-off control signal is issued, so as to turn off the MOS transistor N and enter the next Toff.

[0094] As an example, the MOS transistor N is an N-channel enhancement-mode MOS transistor. However, this is not a limitation, and the MOS transistor N can also be other types of MOS transistors.

[0095] As an example, there is no limitation here on the implementation manner of the logic control module 400 for the preset time, that is, the turn-off time Toff of the MOS transistor N. For example, it can be implemented by a constant time method (such as a clock circuit) or a constant frequency method.

[0096] Based on the average current controller of the above example, the present embodiment further provides a BUCK constant current circuit, which is connected to a DC power supply and outputs a constant current to a load. The BUCK constant current circuit includes the above-mentioned average current controller.

[0097] As an example, the BUCK constant current circuit can achieve a constant current output for an LED.

[0098] In summary, for the average current controller and the BUCK constant current circuit of the present invention, aiming at the BUCK architecture that adopts open-loop constant current control in the prior art and the sampling topology of the current sampling resistor Rcs at the low-voltage end, a control method of 2-fold Δt control + constant turn-off time Toff can be used to achieve a constant current output of the BUCK architecture. As long as it is ensured that the system operates in CCM, the MOS transistor switching current at the Ton moment can be sampled only to control the magnitude of the load output current, and the output current does not change with the load output voltage Vout and the inductance L, which can well solve the problem of the output constant current accuracy, and there is no need for a high-voltage differential sampling circuit, which can solve the problems of high process requirements and high cost. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0099] The above embodiments are only illustrative of the principles and effects of the present invention, and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. An average current controller is applied to a BUCK circuit, where The BUCK circuit operates in the CCM mode and the current sampling resistor is set at the low-voltage end. It is characterized in that the average current controller includes: a capacitor charge / discharge control module, a capacitor charge / discharge module, a MOS transistor turn-off signal control module, and a logic control module; The capacitor charge / discharge control module is connected to the current sampling resistor and receives a reference voltage, and generates a charge / discharge control signal based on the sampled voltage of the current sampling resistor and the reference voltage; The capacitor charge / discharge module is connected to the output end of the capacitor charge / discharge control module, and controls the equal-current charge / discharge of the capacitor in the capacitor charge / discharge module based on the charge / discharge control signal; The MOS transistor turn-off signal control module is connected to the output end of the capacitor charge / discharge module, and generates a turn-off control signal based on the voltage of the capacitor in the capacitor charge / discharge module; The logic control module is connected to the output end of the MOS transistor turn-off signal control module, generates a turn-off signal of the MOS transistor in the BUCK circuit based on the turn-off control signal, and generates a turn-on signal of the MOS transistor after a preset time; wherein, The capacitor charge / discharge control module includes: a first capacitor, a second capacitor, a first comparator, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, and a sixth switch; The first end of the first switch is connected to the sampled voltage, and the second end is connected to the first end of the third switch and the first end of the first capacitor; The second end of the third switch is connected to the reference voltage; The second end of the first capacitor is connected to the first end of the second capacitor and the negative input terminal of the first comparator; The second end of the second capacitor is connected to the first end of the second switch and the first end of the fourth switch; The second end of the second switch is connected to the sampled voltage, and the second end of the fourth switch is connected to the reference ground terminal; The positive input terminal of the first comparator is connected to a first bias voltage, and the output terminal of the first comparator is connected to the first end of the sixth switch; The fifth switch is connected between the negative input terminal and the output terminal of the first comparator; The second end of the sixth switch is connected to the capacitor charge / discharge module; The capacitor charge / discharge module includes: a NOT gate, a P-type MOS transistor, an N-type MOS transistor, a first constant current source, a second constant current source, and a third capacitor; The input terminal of the NOT gate is connected to the capacitor charge / discharge control module, and the output terminal is connected to the gate of the P-type MOS transistor and the gate of the N-type MOS transistor; The source of the P-type MOS transistor is connected to the operating voltage, and the drain is connected to the first end of the third capacitor through the first constant current source; The source of the N-type MOS transistor Q2 is connected to the reference ground terminal, and the drain is connected to the first end of the third capacitor through the second constant current source; The second end of the third capacitor is connected to the reference ground terminal; The MOS transistor turn-off signal control module includes: a seventh switch and a second comparator; The seventh switch is connected between the positive input terminal and the negative input terminal of the second comparator; The positive input terminal of the second comparator is connected to a second bias voltage, the negative input terminal is connected to the first terminal of the third capacitor, and the output terminal outputs the turn-off control signal.

2. The average current controller according to claim 1, characterized in that The BUCK circuit includes: the current sampling resistor, the MOS transistor, the freewheeling diode, the capacitor, and the inductor; the first terminal of the current sampling resistor is connected to the first terminal of the MOS transistor, and the second terminal is connected to the low-voltage terminal of the DC power supply; the second terminal of the MOS transistor is connected to the anode of the freewheeling diode and the first terminal of the inductor; the second terminal of the inductor is connected to the first terminal of the capacitor; The high-voltage terminal of the DC power supply is connected to the cathode of the freewheeling diode and the second terminal of the capacitor.

3. The average current controller according to claim 1, wherein: The MOS transistor is an N-channel enhancement-mode MOS transistor.

4. A BUCK constant current circuit is connected to a DC power supply and outputs a constant current to a load, characterized in that, The BUCK constant-current circuit includes the average current controller according to any one of claims 1 to 3.

5. The BUCK constant current circuit according to claim 4, wherein: The load is an LED.

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