Complementary cell circuits using isolation structures for defect reduction and related manufacturing methods

Abstract

In order to prevent short circuit defects between the source / drain of the transistor of the complementary unit circuit, an isolation wall (414A) is formed in the isolation region between the source / drain of the transistor before growing the P-type epitaxial layer and the N-type epitaxial layer on the corresponding sides of the isolation region. The isolation wall provides a physical barrier to prevent the formation of short circuit defects that may otherwise be formed between the P-type epitaxial layer (412P) and the N-type epitaxial layer (412N). Therefore, the isolation wall prevents circuit failures caused by electrical short circuits between the source / drain regions of the transistor in the complementary unit circuit. The width of the isolation region between the P-type transistor and the N-type transistor in the circuit unit layout can be reduced, so that the total layout area of ​​the complementary unit circuit can be reduced without reducing product yield. The process of forming the isolation wall can be used to form a gate cut in the dummy gate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to non-provisional application No. 16 / 798,947, filed on February 24, 2020, entitled “COMPLEMENTARY CELL CIRCUITSEMPLOYING ISOLATION STRUCTURES FOR DEFECT REDUCTION AND RELATED METHODS OF FABRICATION,” which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The field of the present disclosure relates to complementary circuits including N-type and P-type transistors to form integrated circuits (ICs), and more particularly, to avoiding short circuit defects when fabricating circuits having N-type and P-type transistors. Background Art

[0004] Integrated circuits (ICs) employ a large number of transistors, which are essential for providing many of the functions performed by electronic devices. For example, IC components such as central processing units (CPUs), digital signal processors (DSPs), and memory systems each employ a large number of transistors in logic circuits and memory circuits. As the functions of electronic devices become more complex, the number of transistors required to perform such functions increases. Electronic devices such as mobile devices are required to perform functions faster while becoming smaller in size. In order to respond to these demands, the ICs within such devices and the transistors within those ICs must be made smaller. The area occupied by transistor circuits in an IC is minimized by efficiently arranging the circuits. In this regard, IC developers employ standard cells, which are transistors and interconnect structures that provide functions (e.g., Boolean or memory) and have a layout that is determined to optimize area. Standard cell layouts reduce unused space. However, making standard cell circuit layouts smaller requires positioning circuit elements closer together, which poses certain technical challenges. Reference Figure 1 The circuit layout example in Figure 2 illustrates one aspect of these challenges.

[0005] Figure 1 1 is an illustration of a standard cell circuit layout 100 of an inverter circuit 102. The inverter circuit 102 is an example of a complementary metal oxide semiconductor (MOS) (CMOS) cell circuit, or a complementary cell circuit that employs one or more P-type transistors and one or more N-type transistors (e.g., in a complementary manner). Figure 1In the embodiment of the present invention, a P-type transistor 104 for an inverter circuit 102 is formed in a P-type diffusion region ("P-type region") 106, which is a surface region of a semiconductor substrate 108 such as silicon, which is lightly doped with trivalent impurities to generate a large number of holes in the semiconductor substrate 108. An N-type transistor 110 is formed in an N-type diffusion region ("N-type region") 112, which is a region of the semiconductor substrate 108 lightly doped with pentavalent impurities to generate a large number of free electrons. Between the P-type region 106 and the N-type region 112 is a region having a width W. ISO The isolation region 114 is an undoped region of the semiconductor substrate 108 that isolates the P-type region 106 on one side of the isolation region 114 from the N-type region 112 on the other side. The P-type transistor 104 includes a source 116P, a drain 118P, and a channel 120P. The N-type transistor 110 includes a source 116N, a drain 118N, and a channel 120N. Figure 1 In the example of the inverter circuit 102 shown, the P-type transistor 104 and the N-type transistor 110 are both coupled to a common gate 122. The gate 122 spans both the channel 120P and the channel 120N to control the operation of the P-type transistor 104 and the N-type transistor 110 via a voltage applied to the gate 122. The details of the operation of the inverter circuit 102 are understood by those of ordinary skill and are therefore not discussed further herein.

[0006] The source 116P, 116N and drain 118P, 118N of the P-type transistor 104 and the N-type transistor 110 are formed of a crystalline material having properties that are beneficial to CMOS circuits. For example, silicon crystalline material is formed by silicon epitaxial deposition or epitaxy, which is a process for growing a crystalline epitaxial layer on a substrate. The source 116P and drain 118P of the P-type transistor 104 are formed in the P-type region 106 in a first epitaxial process, and the source 116N and drain 118N of the N-type transistor 110 are formed in the N-type region 112 in a second epitaxial process. As the crystal structure grows vertically, it also extends horizontally. Therefore, in the inverter circuit 102, the epitaxial layer in the source 112P of the P-type transistor 104 extends above the isolation region 114 (e.g., horizontally) toward the N-type transistor 110. Similarly, the epitaxial layer in the source 116N of the N-type transistor 110 extends over the isolation region 114 toward the P-type transistor 104 .

[0007] One method for minimizing the area occupied by the standard cell circuit layout 100 is to reduce the width W of the isolation region 114. ISO, which reduces the distance between the portions of the epitaxial layers of the source 116P, 116N and drain 118P, 118N extending above the isolation region 114. However, in this regard, the physical limitations of the lithography methods and epitaxial growth processes pose a challenge to further reducing the geometry of the transistors. Small variations in these processes can lead to defects, such as short circuits that cause circuit failures. Therefore, the problems associated with process variations that arise in the manufacture of planar and three-dimensional transistors are an obstacle to further reducing the circuit area. Summary of the invention

[0008] Aspects disclosed herein include complementary unit circuits using isolation structures for defect reduction. The present invention also discloses related methods for manufacturing complementary unit circuits using such isolation structures. Since the distance between the P-type region and the N-type region of the complementary unit circuit is reduced in order to reduce the circuit area, the number of short-circuit defects caused by process variations increases. In the exemplary aspects disclosed herein, in order to reduce or avoid short-circuit defects between the source and drain (source / drain) of adjacent P-type and N-type transistors of the complementary unit circuit, isolation walls are formed in the isolation region between the source / drain of the P-type and N-type transistors. These isolation walls can be formed before the P-type epitaxial layer and the N-type epitaxial layer grow on the respective sides of the isolation region. The isolation walls are used to limit the growth of the corresponding epitaxial layer extending above the isolation region in a certain direction. The isolation walls provide a physical barrier to prevent the formation of short-circuit defects, which may otherwise be formed between the P-type epitaxial layer and the N-type epitaxial layer. Therefore, the isolation walls can prevent circuit failures caused by electrical short circuits between the source / drain regions of the transistors in the complementary unit circuit. In this way, the width of the isolation region between the P-type transistor and the N-type transistor in the circuit unit layout can be reduced, so that the total layout area of ​​the complementary unit circuit can be reduced without reducing the product yield. In another exemplary aspect, a gate cutout can be formed by the isolation wall, and the gate cutout is an isolation structure that electrically isolates the gate of the complementary unit circuit from the gate of the adjacent unit circuit.

[0009] In a first aspect, a complementary unit circuit is disclosed. The complementary unit circuit includes a semiconductor substrate, the semiconductor substrate including: a P-type region; an N-type region; and an isolation region between the P-type region and the N-type region, the isolation region having a width extending in the direction of a first axis. The complementary unit circuit also includes a gate, the gate extending longitudinally in the direction of the first axis. The gate extends across a portion of each of the P-type region, the isolation region, and the N-type region. The complementary unit circuit includes: a first P-type epitaxial (epi) source / drain (S / D) (epi-S / D), the first P-type epi-S / D is formed on the P-type region on the first side of the gate, the first P-type epi-S / D extends above the isolation region in the first direction of the first axis; and a first N-type epi-S / D, the first N-type epi-S / D is formed on the N-type region on the first side of the gate, the first N-type epi-S / D extends above the isolation region in the second direction of the first axis. The complementary unit circuit includes a first isolation wall extending from the isolation region in a third direction orthogonal to the first axis on the first side of the gate, the first isolation wall isolating the first P-type epi-S / D from the first N-type epi-S / D. The complementary unit circuit includes: a second P-type epi-S / D formed on the P-type region on the second layer of the gate, the second P-type epi-S / D extending over the isolation region in the first direction of the first axis; and a second N-type epi-S / D formed on the N-type region on the second side of the gate, the second N-type epi-S / D extending over the isolation region in the second direction of the first axis. The complementary unit circuit includes a second isolation wall extending from the isolation region in a third direction orthogonal to the first axis on the second side of the gate, the second isolation wall isolating the second P-type epi-S / D from the second N-type epi-S / D.

[0010] In another aspect, a method of forming a complementary unit circuit including an isolation structure is disclosed. The method includes: forming a P-type region on a first side of an isolation region on a semiconductor substrate, the isolation region extending longitudinally in a first direction; and forming an N-type region on a second side of the isolation region on the semiconductor substrate. The method includes forming a dummy gate, the dummy gate extending longitudinally in a second direction orthogonal to the first direction and extending across portions of the P-type region, the isolation region, and the N-type region. The method includes: depositing a dielectric layer on the P-type region, the isolation region, and the N-type region on a first side and a second side of the dummy gate; and etching a first trench through the dielectric layer on the first side of the dummy gate, and etching a second trench through the dielectric layer on the second side of the dummy gate. The method includes forming an isolation structure, including: filling the first trench with an isolation material to form a first isolation wall; and filling the second trench with an isolation material to form a second isolation wall. The method includes: forming a first N-type epi-S / D on an N-type region on a first side of a dummy gate, the first N-type epi-S / D extending over an isolation region on a first side of a first isolation wall; and forming a second N-type epi-S / D on an N-type region on the second side of the dummy gate, the second N-type epi-S / D extending over an isolation region on a first side of a second isolation wall. The method also includes: forming a first P-type epi-S / D on a P-type region on a first side of the dummy gate, the first P-type epi-S / D extending over an isolation region on a second side of the first isolation wall and isolated from the first N-type epi-S / D by the first isolation wall; and forming a second P-type epi-S / D on a P-type region on a second side of the dummy gate, the second P-type epi-S / D extending over an isolation region on a second side of the second isolation wall and isolated from the second N-type epi-S / D by the second isolation wall. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a top view of a standard cell layout of one example of a conventional complementary cell circuit including a P-type diffusion region ("P-type region") and an N-type diffusion region ("N-type region") formed on a substrate;

[0012] Figure 2A is a top view in a manufacturing stage of a complementary unit circuit including a fin of a P-type fin field effect transistor (FET) (FinFET) (PFET) and an N-type FinFET (NFET) across which a dummy gate has been formed;

[0013] Figure 2B yes Figure 2A A cross-sectional side view of the complementary unit circuit in the manufacturing stage after the epitaxial regions are formed on the P-type fin and the N-type fin, without short circuit defects caused by process variations;

[0014] Figure 2C yes Figure 2A A cross-sectional side view of the complementary unit circuit in the manufacturing stage after forming the epitaxial regions on the P-type and N-type fins, including the short circuit defect caused by process variation;

[0015] Figure 3A is a top view of a complementary unit circuit in a manufacturing stage, the complementary unit circuit including a P-type gate all around (GAA) region across which a dummy gate has been formed and an N-type GAA region;

[0016] Figure 3B yes Figure 3A A cross-sectional side view of a complementary unit circuit in a manufacturing stage after forming an epitaxial region on the P-type and N-type GAA regions without short circuit defects caused by process variations;

[0017] Figure 3C yes Figure 3A A cross-sectional side view of a complementary unit circuit in a manufacturing stage after forming an epitaxial region on the P-type and N-type GAA regions, including a short circuit defect caused by process variation;

[0018] Figure 4A is a top view of an exemplary complementary unit circuit including fins of a PFET and an NFET on a substrate across which dummy gates have been formed, and including a spacer formed between a P-type region and an N-type region (i.e., a region in which source / drain (S / D) of the PFET and the NFET are grown) to prevent short circuit defects caused by process variations in the formation of an epitaxial layer;

[0019] Figure 4B yes Figure 4A A cross-sectional side view of an exemplary complementary unit circuit in FIG. 1 , showing an isolation wall providing a barrier to the growth of epitaxial S / D material over the isolation region in a certain direction;

[0020] Figure 4C yes Figure 4A A cross-sectional side view of an exemplary complementary unit circuit in FIG. 1 , showing that no isolation wall is formed in the dummy gate;

[0021] Figure 5A is a top view of an exemplary complementary unit circuit in a manufacturing stage, the complementary unit circuit including fins of a PFET and an NFET on a substrate and including a dummy gate, the complementary unit circuit including a spacer formed between the S / D regions of the PFET and the NFET and a gate cutout formed at one end of the dummy gate to separate the PFET and the NFET from each other. Figure 5A The gate of the complementary unit circuit in is isolated from the gate of the adjacent circuit;

[0022] Figure 5B yes Figure 5AA cross-sectional side view of an exemplary complementary unit cell circuit in FIG. 1 , illustrating an isolation wall providing a barrier to growth of epitaxial S / D material in a direction extending over the isolation region;

[0023] Figure 5C yes Figure 5A A cross-sectional side view of an exemplary complementary unit circuit in , illustrating a gate cutout formed at an end of a dummy gate;

[0024] Fig. 6A and Figure 6B The picture is made in Figure 5A A flowchart of an exemplary process in a method of forming a complementary unit circuit in a method of forming a complementary unit circuit, the complementary unit circuit including an isolation wall formed between a P-type region and an N-type region to prevent a short circuit defect caused by a process variation;

[0025] Fig. 7A yes Figures 4A-4C A top view of a first manufacturing stage of a complementary unit circuit or FinFET circuit in a device including fins formed in P-type and N-type regions of a substrate and a dummy gate formed across the fins;

[0026] Figure 7B yes Fig. 7A A cross-sectional side view of an S / D region of a FinFET circuit in FIG. 1 , illustrating fins extending from a substrate in a P-type region and an N-type region;

[0027] Figure 7C is through Fig. 7A A cross-sectional side view of a channel of a fin in a FinFET circuit in FIG. 1 , illustrating a dummy gate overlapping the fin extending from a substrate in a P-type region and an N-type region;

[0028] Fig. 8A is a top view of the fabrication stage, where the dielectric layer is Fig. 7A The fin of the FinFET circuit is deposited to the height of the dummy gate;

[0029] Figure 8B yes Fig. 8A A cross-sectional side view of the S / D region of the FinFET circuit in FIG. 1 , showing a dielectric layer deposited on the fin on the substrate on one side of the dummy gate;

[0030] Figure 8C is through Fig. 8A A cross-sectional side view of a channel of a fin in a FinFET circuit in FIG. 1 , illustrating a dummy gate overlapping the fin extending from a substrate in a P-type region and an N-type region;

[0031] Fig. 9A is a top view of the manufacturing stage, where Fig. 8Aforming a first patterned mask on the FinFET circuit, and etching a void in the dielectric layer according to the first patterned mask;

[0032] Fig. 9B yes Fig. 9A A cross-sectional side view of an S / D region of a FinFET circuit in FIG. 1 , showing a first patterned mask on a dielectric layer and a void etched in the dielectric layer in an isolation region according to the first patterned mask;

[0033] Fig. 9C is through Fig. 9A A cross-sectional side view of a channel of a fin in a FinFET circuit in FIG. 1 , illustrating a first patterned mask on a dummy gate;

[0034] Fig. 10A is a top view of the manufacturing stage, where Fig. 9A Depositing a second patterned mask on the FinFET circuit in the embodiment of the present invention, and etching a gap in the dummy gate according to the second patterned mask;

[0035] Fig. 10B yes Fig. 10A a cross-sectional side view of an S / D region of a FinFET circuit in FIG. 1 , illustrating a second patterned mask deposited on the dielectric layer and in a void etched in the dielectric layer;

[0036] Fig. 10C is through Fig. 10A a cross-sectional side view of a channel of a FinFET circuit in FIG. 1 , illustrating a second patterned mask deposited on a dummy gate and a void etched in the dummy gate according to the second patterned mask;

[0037] Fig.11A is a top view of the manufacturing stage, where Fig. 10A removing the second patterning mask from the FinFET circuit;

[0038] Fig. 11B yes Fig.11A a cross-sectional side view of an S / D region of a FinFET circuit in FIG. 1 , illustrating a second patterned mask removed from a dielectric layer and voids etched in the dielectric layer in an isolation region;

[0039] Fig. 11C is through Fig.11A a cross-sectional side view of a channel of a fin in a FinFET circuit in FIG. 1 , showing a second patterning mask removed from a dummy gate;

[0040] Fig. 12A This is a top view of the manufacturing stage, which has been filled Fig.11A A dielectric layer of a FinFET circuit and a void in a dummy gate to form an isolation structure including an isolation wall and a gate cutout;

[0041] Fig. 12B yes Fig. 12A A cross-sectional side view of an S / D region of a FinFET circuit in FIG. 1 , illustrating isolation walls formed in voids etched in a dielectric layer in an isolation region;

[0042] Fig. 12C is through Fig. 12A A cross-sectional side view of a channel of a fin in a FinFET circuit in FIG. 1 , illustrating a gate cutout formed in a void etched in a dummy gate;

[0043] Fig.13A This is a top view of the manufacturing stage, where the Fig. 12A a dielectric layer of a FinFET circuit in the semiconductor device and forming an epitaxial material on the fins in the P-type region and the N-type region;

[0044] Fig. 13B yes Fig.13A A cross-sectional side view of an S / D region of a FinFET circuit in FIG. 1 , illustrating an isolation wall for preventing short circuit defects between an epitaxial material formed on a P-type region and an epitaxial material formed on an N-type region;

[0045] Fig. 13C is through Fig.13A A cross-sectional side view of a channel of a fin in a FinFET circuit in FIG. 1 , illustrating a gate cutout formed in a void etched in a dummy gate;

[0046] Fig.14A is a top view of another exemplary complementary unit circuit, which is a GAA circuit, in which a spacer is formed on each side of a dummy gate to prevent a short defect from being formed between an epitaxial material in a P-type region and an epitaxial material in an N-type region;

[0047] Fig. 14B yes Fig.14A A cross-sectional side view of an epitaxial (epi) S / D (epi-S / D) region of a GAA circuit in FIG. 1 , illustrating a spacer wall that provides a barrier to prevent the formation of a short defect between an epitaxial material formed on a P-type region and an epitaxial material formed on an N-type region;

[0048] Fig.15 is a block diagram of an exemplary processor-based system that may include an IC including a complementary cell circuit employing isolation walls for preventing shorting defects between epitaxial regions, such as Figures 4A-4C , Figures 5A-5C and Figures 12A-14B Any of ; and

[0049] Fig.16is a block diagram of an exemplary wireless communication device including a radio frequency (RF) component formed of an IC including a complementary unit circuit using an isolation wall for preventing short circuit defects between epitaxial regions, such as Figures 4A-4C , Figures 5A-5C and Figures 12A-14B as shown in any one of the following. DETAILED DESCRIPTION

[0050] With reference now to the accompanying drawings, several exemplary aspects of the present invention are described. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0051] Aspects disclosed herein include complementary unit circuits using isolation structures for defect reduction. The present invention also discloses related methods for manufacturing complementary unit circuits using such isolation structures. Since the distance between the P-type region and the N-type region of the complementary unit circuit is reduced in order to reduce the circuit area, there is an increase in the number of short-circuit defects caused by process variations. In the exemplary aspects disclosed herein, in order to reduce or avoid short-circuit defects between the source and drain (source / drain) of adjacent P-type and N-type transistors of the complementary unit circuit, isolation walls are formed in the isolation region between the source / drain of the P-type and N-type transistors. These isolation walls can be formed before the P-type epitaxial layer and the N-type epitaxial layer grow on the respective sides of the isolation region. The isolation walls are used to limit the growth of the corresponding epitaxial layer extending above the isolation region in a certain direction. The isolation walls provide a physical barrier to prevent the formation of short-circuit defects that may otherwise be formed between the P-type and N-type epitaxial layers. Therefore, the isolation walls can prevent circuit failures caused by electrical short circuits between the source / drain regions of the transistors in the complementary unit circuit. In this way, the width of the isolation region between the P-type transistor and the N-type transistor in the circuit unit layout can be reduced, so that the total layout area of ​​the complementary unit circuit can be reduced without reducing product yield. In another exemplary aspect, the isolation wall can be used to form a gate cutout, which is an isolation structure that electrically isolates the gate of the complementary unit circuit from the gate of the adjacent unit circuit.

[0052] In the discussion, the source / drain (S / D) of the PFET and NFET may be grown to prevent or reduce Figure 4A Before starting the example of a complementary unit circuit of a short circuit defect caused by process variation in the formation of the epitaxial layer, first in Figure 2A-2C Examples of complementary unit circuits of different three-dimensional (3D) transistors that do not include such isolation walls are illustrated and discussed in FIGS. 3A-3C .

[0053] Figure 2A-2CAn example of a complementary cell circuit 201 including a fin field effect transistor (FET) (FinFET) circuit 202 is shown. Figure 2A 2 is a top view of a FinFET circuit 200 including a P-type region 202P and an N-type region 202N of a semiconductor substrate 204. The P-type region 202P and the N-type region 202N are on opposite sides of an isolation region 206. The semiconductor substrate 204 extends in a plane including an X-axis and a Y-axis that are orthogonal to each other. The fins 208P and 208N extend longitudinally in a direction substantially parallel to the Y-axis ("Y-axis direction"), and the dummy gate 210 extends longitudinally in a direction substantially parallel to the X-axis ("X-axis direction"). The channels 212P and 212N across the fins 208P and 208N form a dummy gate 210. In this context, "substantially parallel" means parallel or differing from parallel by a few degrees (e.g., 3 degrees).

[0054] Figure 2B After forming epitaxial (epi) source / drain (S / D) (epi-S / D) 214P and 214N on fins 208P and 208N, respectively Figure 2A Side view of the cross section AA'. Figure 2B Fin 208P is shown extending from P-type region 202P in the Z-axis direction, orthogonal to the plane of semiconductor substrate 204, and fin 208N extends from N-type region 202N in the Z-axis direction. A shallow trench isolation (STI) layer 216 is deposited between fins 208P and 208N. As the crystal structure 218 of epi-S / D 214P and 214N grows on fins 208P and 208N, epi-S / D 214P and 214N extend horizontally and couple to the crystal structure 218 on adjacent fins 208P and 208N. The extent of this growth is determined by various factors, including time and load effects. In order to keep epi-S / D 214P separated from epi-S / D 214N, an isolation region 206 is provided between P-type region 202P and N-type region 202N. In normal processing, the growth time of crystal structure 218 is set to allow epi-S / D 214P and 214N to extend horizontally far enough to couple with each other, but not far enough to extend across isolation region 206 .

[0055] Figure 2C It is formed after the short circuit defect is formed due to process variation. Figure 2A Another cross-sectional side view of the line BB' in FIG. 1. To explain how this is produced Figure 2C A high-level description of the process used to form epi-S / D 214P and 214N is provided. Figure 2AA first mask (not shown) is formed on the fin 208P in the recessed fin 208N. In the first epitaxial growth process, the epi-S / D 214N is formed on the fin 208N. Next, the first mask is removed from the recessed fin 208P, and a second mask 220 is formed on the epi-S / D 214N. Assuming that no process variations have affected the size of the epi-S / D 214N, the second mask 220 extends horizontally to a point in the isolation region 206 that is farther than the epi-S / D 214N may extend horizontally. The extent of the second mask 220 is based on the expected size of the crystal structure 218. Then, in the second epitaxial growth process, the epi-S / D 214P is formed on the fin 208P.

[0056] Certain process factors (e.g., loading effects) may vary during the first epitaxial growth process. Figure 2C The epi-S / D 214N in the isolation region 206 is larger than expected. Therefore, the distance that the second mask 220 extends horizontally above the isolation region 206 is not enough to completely cover the epi-S / D 214N. Therefore, there is an exposed portion of the epi-S / D 214N that is not covered by the second mask 220, and in the second epitaxial growth process, an unexpected crystal structure 222 is also formed on the exposed portion of the epi-S / D 214N. The crystal structure 222 extends horizontally across the isolation region 206 and contacts the epi-S / D 214P, thereby generating an electrical connection or short circuit defect. Therefore, the FinFET circuit 200 cannot operate as expected.

[0057] In the second example of a complementary unit circuit, Figures 3A-3C A gate-all-around (GAA) circuit 300 is shown in FIG. Figure 3A 30 is a top view of a GAA circuit 300 including a P-type region 302P and an N-type region 302N on a semiconductor substrate 304. The P-type region 302P and the N-type region 302N are on opposite sides of an isolation region 306. The P-type region 302P and the N-type region 302N include nanosheets (or nanoplates) 308P and 308N, respectively. The semiconductor substrate 304 extends in a plane including an X-axis and a Y-axis that are orthogonal to each other. The P-type region 302P and the N-type region 302N each extend longitudinally in the Y-axis direction, and the dummy gate 310 extends longitudinally in the X-axis direction. The dummy gate 310 is formed on channels 312P and 312N of the P-type region 302P and the N-type region 302N, respectively.

[0058] Figure 3B After forming epi-S / D 314P and 314N on nanosheets 308P and 308N, respectively Figure 3A A side view of the cross section A-A'. Figure 3BAs shown, epi-S / D 314P and 314N are also formed on P-type and N-type portions 316P and 316N, respectively, extending from semiconductor substrate 304 in the Z-axis direction. STI layer 318 is deposited between P-type and N-type portions 316P and 316N. Located above P-type and N-type portions 316P and 316N in the Z-axis direction are nanosheets 308P and 308N separated from each other by gaps 320. N-type epi-S / D 314N is formed on N-type portion 316N and nanosheet 308N in a first epitaxial growth process. P-type epi-S / D 314P is formed on P-type portion 316P and nanosheet 308P in a second epitaxial growth process. In the first epitaxial growth process, similar to the process with respect to Figure 2C In the first epitaxial growth process described, the N-type epi-S / D 314N grows to a desired size extending horizontally in the Y-axis direction toward the P-type region 302P above the isolation region 306. In the second epitaxial growth process, the P-type epi-S / D 314P grows to a desired size extending horizontally in the Y-axis direction toward the N-type region 302N above the isolation region 306. Figure 3B There is no short circuit defect in the GAA circuit 300.

[0059] Figure 3C After the short circuit defect is formed due to process variation Figure 3A Another side view of the cross section A-A' of FIG. The process flow for forming epi-S / D 314N and 314P is similar to that of the above reference Figure 2C The process described. Figure 3C In the embodiment of the present invention, due to process variations, epi-S / D 314N is larger than expected, thereby extending horizontally farther than expected across isolation region 306. As a result, normally grown epi-S / D 314P (which also extends horizontally across isolation region 306) contacts the oversized epi-S / D 314N, thereby generating an electrical connection or short circuit defect. Therefore, GAA circuit 300 cannot operate as expected.

[0060] Figures 4A-4C is a view of an exemplary FinFET circuit 400, which is an example of a complementary unit circuit that includes an isolation wall formed in an isolation region between P-type and N-type transistors to limit the growth of corresponding epitaxial layers extending over the isolation region in a certain direction, as disclosed herein. Figure 4A4 is a top view of a FinFET circuit 400, which includes a top view of a P-type region 402P and an N-type region 402N of a semiconductor substrate 404 extending in a plane including an X-axis and a Y-axis. The semiconductor substrate 404 includes an isolation region 406 between the P-type region 402P and the N-type region 402N. The isolation region 406 has a width W extending in the direction of the X-axis ("X-axis direction"). The FinFET circuit 400 includes a dummy gate 408, which extends longitudinally across the P-type region 402P, the isolation region 406, and a portion of the N-type region 402N in the X-axis direction. In the completed FinFET circuit 400, the dummy gate 408 is used to control the conductive gate replacement of the transistor formed by the P-type region 402P and the N-type region 402N. The P-type region 402P includes a fin 410P extending in the Y-axis direction. The N-type region 402N includes a fin 410N extending in the Y-axis direction.

[0061] refer to Figure 4A In the FinFET circuit 400 in FIG. 4 , an epi-S / D 412P is formed on a fin 410P in a P-type region 402P on a side Z4A of a dummy gate 408. The epi-S / D 412P extends over the isolation region 406 in a first X-axis direction (i.e., toward the N-type region 402N). The epi-S / D 412N is formed on a fin 410N in an N-type region 402N on a side Z4A of the dummy gate 408, and the epi-S / D 412N extends over the isolation region 406 in a second X-axis direction (i.e., toward the P-type region 402P). The isolation region 406 includes an isolation wall 414A on the side Z4A of the dummy gate 408. The isolation wall 414A extends from the isolation region 406 in the Z-axis direction to a height H WALL , which is high enough to prevent epi-S / D 412N and 416N from contacting epi-S / D 412P and 416P above isolation region 406.

[0062] Before the epi-S / D 412P and the epi-S / D 412N are grown, the isolation wall 414A is formed in the isolation region 406. If either the epi-S / D 412P or the epi-S / D 412N is not grown correctly due to process variations, the isolation wall 414A is inserted between the spaces that will be occupied by the short-circuit defect. Rather than relying solely on the accuracy of the manufacturing (e.g., photolithography) process to avoid short-circuit defects, the isolation wall 414A acts as a physical barrier that prevents or at least reduces the generation of short-circuit defects even when process variations do occur.

[0063] Further references Figure 4AIn the FinFET circuit 400 in FIG. 4 , an epi-S / D 416P is formed on a fin 410P in a P-type region 402P on a side Z4B of a dummy gate 408. The epi-S / D 416P extends over the isolation region 406 in a first X-axis direction (i.e., toward the N-type region 402N). The epi-S / D 416N is formed on the fin 410N in the N-type region 402N on the side Z4B of the dummy gate 408, and the epi-S / D 416N extends over the isolation region 406 in a second X-axis direction (i.e., toward the P-type region 402P). The isolation region 406 also includes an isolation wall 414B on the side Z4B of the dummy gate 408, which extends from the isolation region 406 to a height H in a Z-axis direction (e.g., orthogonal to the dummy gate 408). WALL The isolation wall 414B isolates the epi-S / D 416P from the epi-S / D 416N. For example, the isolation wall 414A and the isolation wall 414B may be formed of at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SIC), and aluminum oxide (AlO) or other isolation materials for providing electrical isolation.

[0064] Figure 4B yes Figure 4A FIG. 4 is a cross-sectional side view of the FinFET circuit 400 at line AA' in FIG. Figure 4B , STI 418 is formed between the respective fins 410P and 410N, including in the isolation region 406. Here, it can be seen that the horizontal growth of the epi-S / D 412P and 412N in the X-axis direction above the isolation region 406 is limited by the isolation wall 414A. In this regard, even in the presence of process variations in which the epi-S / D 412N generated by the epitaxial growth process becomes larger than expected, the epi-S / D 412P and 412N are prevented from forming a short defect. In addition, because the isolation of the epi-S / D 412N during the second epitaxial growth process in which the epi-S / D 412P is formed is not provided solely by a mask based on the expected size of the epi-S / D 412N, a short defect cannot be generated during the formation of the epi-S / D 412P. As Figure 4B As shown, bottom end 420A of isolation wall 414A is below the top surface of isolation region 406 , which is the top surface of STI 418 .

[0065] In one non-limiting example, FinFET circuit 400 may be formed with the following dimensions: Isolation walls 414A and 414B have a width W in the range of 10 nanometers (nm) to 30 nm. WALL The isolation walls 414A and 414B extend to a height H in the range of 50 nm to 150 nm above the substrate 406. WALLThe height H corresponding to the fins 410N and 410P above the substrate 406 WALL (See Figure 4C ). Fins 410N and 410P each have a fin width W in the range of 3 nm to 12 nm. FIN , and with a pitch P of 15nm to 40nm FIN The epi-S / Ds 416P, 416N, 412P, and 412N are formed on the fins 410N and 410P and extend orthogonally from the dummy gate 408 by a length L of 30 nm to 80 nm. EPI (See Figure 4A ) portion. The dummy gate 408 has a width W of 6 nm to 200 nm. DMY .

[0066] Figure 4C yes Figure 4A 4 is a cross-sectional side view of the FinFET circuit 400 (ie, the complementary unit circuit) at line BB′ in FIG. Figure 4C Dummy gate 408 is shown formed across channels 422P and 422N of fins 410P and 410N, respectively. Figure 4C The FinFET circuit 400 is also shown to have no isolation wall in the dummy gate 408 between the P-type region 402P and the N-type region 402N.

[0067] exist Figures 4A-4C In the FinFET circuit 400 in FIG. 4 , the N-type region 402N includes an N-type fin 410N extending from the semiconductor substrate 404 in the Z-axis direction. The N-type epi-S / D 412N and the N-type epi-S / D 416N are formed on the N-type fin 410N. The P-type region 402P includes a P-type fin 410P extending from the semiconductor substrate 404 in the Z-axis direction. The P-type epi-S / D 412P and the P-type epi-S / D 416P are formed on the P-type fin 410P. Therefore, forming the N-type region 402N includes forming the N-type fin 410N extending orthogonally to the semiconductor substrate 404 (i.e., in the Z-axis direction), and forming the P-type region 402P includes forming the P-type fin 410P extending orthogonally to the semiconductor substrate 404 (i.e., in the Z-axis direction).

[0068] Figures 5A-5C Shows Figures 4A-4C Another example of a FinFET circuit 400 having a gate cutout 500 disposed at an end of a dummy gate 408 is shown. Figure 5A is similar to Figure 4A The top view of the FinFET circuit 400 is shown in FIG. Figure 5AA gate cut 500 is shown extending across the dummy gate 408. Thus, when the dummy gate 408 is replaced by a conductive gate at a subsequent manufacturing stage, the conductive gate on the FinFET circuit 400 will be separated (i.e., electrically isolated) from the conductive gate formed on the opposite side of the gate cut 500, where a dummy gate segment 502 is shown. Thus, the gate cut 500 will be disposed at the end of the conductive gate. The dummy gate segment 502 may extend across adjacent circuits and be replaced by a conductive gate. As discussed in more detail below, the material forming the gate cut 500 may be the same as the material forming the isolation walls 414A and 414B as part of a common process.

[0069] Figure 5B yes Figure 5A FIG. 4 is a cross-sectional side view of the FinFET circuit 400 at line AA′ in FIG. 4 , which shows the epi-S / Ds 412P and 412N separated by the isolation wall 414A and does not show the gate cut 500 in the FinFET circuit 400 .

[0070] Figure 5C yes Figure 5A A cross-sectional side view of the FinFET circuit 400 at line BB' in FIG. Figure 4C , but includes a gate cutout 500. The gate cutout 500 is disposed at the end of the dummy gate 408, thereby providing a barrier that electrically isolates the conductive gate in the FinFET circuit 400 from adjacent circuits (not shown).

[0071] Fig. 6A and 6B is a diagram showing the formation of a complementary unit circuit including an isolation structure (such as Figures 4A-4C 5A-5C). The isolation structure in the FinFET circuit 400 includes isolation walls 414A and 414B and may include a gate cutout 500. Figures 7A-7C to Figures 13A-13C Method 600 is described.

[0072] Figures 7A-7C The first manufacturing stage 700 is shown. Figures 4A-4C The first manufacturing stage 700 includes forming a P-type region 402P ( Fig. 6A The first manufacturing stage 700 also includes forming an N-type region 402N ( Fig. 6A The first manufacturing stage 700 also includes forming a dummy gate 408 ( Fig. 6A In block 606 of FIG. Fig. 7A In the FinFET circuit 400 in FIG. 1 , fins 410P and 410N extending in the Y-axis direction are formed in the P-type region 402P and the N-type region 402N, respectively, and a dummy gate 408 is formed to extend longitudinally in the X-axis direction.

[0073] Figure 7B yes Fig. 7A 4 , illustrating the STI 418 between the fins 410P and 410N and in the isolation region 406. The fins 410P and 410N extend above the top surface of the STI 418. Figure 7C yes Fig. 7A The cross-sectional side view of the FinFET circuit 400 at line BB′ in FIG. 4 shows a dummy gate 408 formed across channels 422P and 422N and a portion of the STI 418 .

[0074] Figures 8A-8C The FinFET circuit 400 is shown in a manufacturing stage 800. Fig. 8A As shown, manufacturing stage 800 includes depositing a dielectric layer 802 ( 402N) on the first side and the second side of the dummy gate 408 on the P-type region 402P, the isolation region 406, and the N-type region 402N. Fig. 6A In the photolithography process, dielectric layer 802 is deposited on fins 410N and 410P, dummy gate 408, and STI 418 to protect these structures of FinFET circuit 400. In subsequent manufacturing stages, dielectric layer 802 provides a medium in which isolation walls 414A and 414B are formed.

[0075] Figure 8B and 8C They are Fig. 8A FIG. 4 is a cross-sectional side view of the FinFET circuit 400 at lines AA′ and BB′ in FIG. 4 . The dielectric layer 802 may be planarized to a height H of the dummy gate 408 above the semiconductor substrate 404. DMY , which is higher than fins 410P and 410N.

[0076] Figures 9A-9C The FinFET circuit 400 is shown in a fabrication stage 900 . The fabrication stage 900 includes forming a trench mask 902 on the dielectric layer 802 and the dummy gate 408 . Fig. 9A yes Fig. 8AFIG. 4 is a top view of the FinFET circuit 400 in FIG. 4 , showing a trench mask 902 deposited on the dielectric layer 802 and the dummy gate 408. The trench mask 902 is a patterned layer formed of a material that is not susceptible to the etching process. The trench mask 902 is used to protect areas that are not etched and expose areas to be etched. Forming the trench mask 902 includes depositing a trench mask layer 902L and patterning the trench mask layer 902L to produce openings 904A and 904B for forming trenches 906A and 906B in the dielectric layer 802. The openings 904A and 904B expose the areas of the FinFET circuit 400 in which the trenches 906A and 906B are formed. Fig. 9A A trench mask 902 is shown that is patterned over the isolation regions 406 to create openings 904A and 904B, below which trenches 906A and 906B are etched into the dielectric layer 802 .

[0077] Fabrication stage 900 also includes etching a trench 906A through dielectric layer 802 on a first side of dummy gate 408 and etching a trench 906B through dielectric layer 802 on a second side of dummy gate 408 ( Fig. 6A 610 in FIG. Fig. 9B yes Fig. 9A , illustrates trench 906A etched in dielectric layer 802. Trench 906A and 906B extend into the surface of isolation region 406. Thus, etching trench 906A includes etching into the surface of isolation region 406 on a first side of dummy gate 408, and etching trench 906B includes etching into the surface of isolation region 406 on a second side of dummy gate 408. Fig. 9B Trench 906A is shown etched through dielectric layer 802 below opening 904A in trench mask 902 and into STI 418 in isolation region 406. Thus, trench 906A extends in the Z-axis direction into isolation region 406 including STI 418. Etching trenches 906A and 906B into dielectric layer 802 and STI 418 provides a mold or hollow that defines the shape / size of isolation walls 414A and 414B to be formed. In addition, after isolation walls 414A and 414B are formed and dielectric layer 802 is removed, the portions of trenches 906A and 906B in STI 418 provide support for isolation walls 414A and 414B through subsequent processing. Fig. 9C yes Fig. 9A 4. A cross-sectional side view of the FinFET circuit 400 at line BB′ in FIG. Fig. 9C 9. The trench mask 902 is shown formed over the dummy gate 408 to protect the dummy gate during the etching process for forming the trenches 906A and 906B. Figures 10A-10C The mask used to form the gate cut 500 is different.

[0078] Figures 10A-10C The FinFET circuit 400 is shown in an optional manufacturing stage 1000. The manufacturing stage 1000 is an optional manufacturing stage for manufacturing the FinFET circuit 400 to include the gate cut mask 500. The manufacturing stage 1000 includes Fig. 9A The FinFET circuit 400 in FIG. 1 is shown in FIG. 1 . The manufacturing stage 1000 includes forming a Figure 5A and 5C The manufacturing stage 1000 includes forming a gate cut mask 1002 having an opening 1004 over the dummy gate 408 . Fig. 10A yes Fig. 9A FIG. 4 is a top view of the FinFET circuit 400 in FIG. 4 , showing the gate cut mask 1002 formed over the dielectric layer 802 and the dummy gate 408 . Fig. 10A Openings 1004 are shown on each side of dummy gate 408 over dummy gate 408 and extending onto dielectric layer 802. In this aspect, forming gate cut mask 1002 includes depositing gate cut mask layer 1002L over dielectric layer 802 and dummy gate 408 and into trenches 906A and 906B.

[0079] Fig. 10B yes Fig. 10A 906A, showing a gate cut mask 1002 on the dielectric layer 802 and in the trench 906A. Forming the gate cut mask 1002 includes patterning the gate cut mask 1002 to create an opening 1004 above the dummy gate 408 for forming a gate cut trench 1006 in the dummy gate 408. The dummy gate 408 below the gate cut mask 1002 is exposed to an etching process that is controlled, for example, by time and concentration, to remove material of the dummy gate 408 below the opening 1004 and some material of the STI 418. The manufacturing stage 1000 includes etching the gate cut mask 1002 having the opening 1004 above the dummy gate 408, and etching the gate cut trench 1006 through the dummy gate 408 ( Fig. 6A 612 in FIG. Fig. 10C yes Fig. 10A The cross-sectional side view of the FinFET circuit 400 at line BB′ in FIG. 4 illustrates the gate cut trench 1006 etched through the dummy gate 408 below the opening 1004 . Fig. 10CThe gate cut trench 1006 is illustrated as extending into the STI 418 , but may not extend completely through the STI 418 to the semiconductor substrate 404 .

[0080] Figures 11A-11C The FinFET circuit 400 is shown in an optional manufacturing stage 1100 for manufacturing the gate cut 500. The manufacturing stage 1100 includes removing the gate cut mask 1002 ( Fig. 6A 614 in FIG. Fig.11A yes Fig. 10A FIG. 4 is a top view of the FinFET circuit 400 in FIG. 4 , with the gate cut mask 1002 removed. Fig. 11B yes Fig.11A The cross-sectional side view of the FinFET circuit 400 at line AA′ in FIG. 4 shows that the gate cut mask 1002 has been removed from the dielectric layer 802 and from the trench 906A. Fig. 11C yes Fig.11A 4 , showing the gate cut mask 1002 removed from the dummy gate 408 and the gate cut trench 1006 formed in the manufacturing stage 1000 .

[0081] Figures 12A-12C The FinFET circuit 400 is shown in a manufacturing stage 1200. The manufacturing stage 1200 includes forming an isolation structure ( Figure 6B Forming the isolation structure includes filling the trench 906A with the isolation material 1202 to form the isolation wall 414A, and filling the trench 906B with the isolation material 1202 to form the isolation wall 414B ( Figure 6B 618 in FIG. Fig. 12A yes Fig.11A FIG. 4 is a top view of the FinFET circuit 400 in FIG. 4 , wherein the trenches 906A and 906B and the gate cut trench 1006 are filled with the isolation material 1202. The trenches 906A and 906B are filled to the top of the dielectric layer 802.

[0082] Since the dielectric layer 802 is planarized to the height H of the dummy gate 408 DMY (See Fig. 12C ), so filling trenches 906A and 906B includes filling trenches 906A and 906B to a height H of the dummy gate using isolation material 1202. DMY . Fig. 12B yes Fig. 12AThe cross-sectional side view of the FinFET circuit 400 at line AA′ in FIG. 1 shows the isolation material 1202 in the trench 906A to form an isolation wall 414A between the P-type region 402P and the N-type region 402N to limit the horizontal growth of the epitaxial material above the isolation region 406.

[0083] Furthermore, if the optional step for producing the gate cut 500 is performed, depositing the isolation material 1202 further includes filling the gate cut trench 1006 with the isolation material 1202 to a height H of the dummy gate 408. DMY To form a gate cutout 500 ( Figure 6B 6. The isolation material 1202 may include at least one of SiN, SiON, SIC, and AlO or other insulating materials. Fig. 12C yes Fig. 12A A cross-sectional side view at line BB' of the FinFET circuit 400 in FIG. 1 shows a gate cut trench 1006 filled with an isolation material 1202 to form a gate cut 500 to electrically isolate a conductive gate (not shown) of a dummy gate segment 502 that replaces a dummy gate 408 in an adjacent circuit.

[0084] Figures 13A-13C The FinFET circuit 400 is shown in a manufacturing stage 1300. The manufacturing stage 1300 includes forming an N-type epi-S / D 412N on the N-type region 402N on the first side of the dummy gate 408, such that the first N-type epi-S / D 412N extends over the isolation region 406 on the first side of the first isolation wall 414A ( Figure 6B The manufacturing stage 1300 includes forming a second N-type epi-S / D 416N on the N-type region 402N on the second side of the dummy gate 408, the second N-type epi-S / D 416N extending over the isolation region 406 on the first side of the second isolation wall 414B ( Figure 6B The manufacturing stage 1300 includes forming a first P-type epi-S / D 412P on the P-type region 402P on the first side of the dummy gate 408, the first P-type epi-S / D 412P extending over the isolation region 406 on the second side of the first isolation wall 414A and isolated from the first N-type epi-S / D 412N by the first isolation wall 414A ( Figure 6B The manufacturing stage 1300 includes forming a second P-type epi-S / D 416P on the P-type region 402P on the second side of the dummy gate 408, the second P-type epi-S / D 416P extending over the isolation region 406 on the second side of the second isolation wall 414B and isolated from the second N-type epi-S / D 416N by the second isolation wall 414B ( Figure 6B628 in the figure).

[0085] Figures 13A-13C Corresponds to Figures 5A-5C , which illustrates a FinFET circuit 400 including a gate cut 500 . Fig.13A yes Fig. 12A 4 is a top view of a FinFET circuit 400 in which epi-S / Ds 412N and 416N are formed on fin 410N in N-type region 402N and epi-S / Ds 412P and 416P are formed on fin 410P in P-type region 402P. Fig. 13B yes Fig.13A The cross-sectional side view of FinFET circuit 400 at line AA' in FIG. 4 shows that the growth of epi-S / D 412P and 412N in the horizontal direction over isolation region 406 is limited by isolation wall 414A. In this way, short circuit defects due to process variations are prevented. Fig. 13C yes Fig.13A The cross-sectional side view of the FinFET circuit 400 at line BB′ in FIG. 4 shows the gate cut 500 disposed at the end of the dummy gate 408 .

[0086] Fig.14A 1 is a top view of an exemplary GAA circuit 1400, which is another example of a complementary unit circuit as disclosed herein. Fig.14A , the GAA circuit 1400 includes a P-type region 1402P and an N-type region 1402N of a semiconductor substrate 1404. The P-type region 1402P and the N-type region 1402N each extend in the Y-axis direction on opposite sides of an isolation region 1406. The GAA circuit 1400 also includes a dummy gate 1408 extending longitudinally in the X-axis direction.

[0087] Fig. 14B yes Fig.14A FIG. 14 is a cross-sectional side view of a GAA circuit 1400 at line AA' in FIG. N-type region 1402N includes nanosheet 1410N, wherein epi-S / D 1412N is formed on and around nanosheet 1410N. P-type region 1402P includes nanosheet 1410P, wherein epi-S / D 1412P is formed on and around nanosheet 1410P. In another example of a GAA circuit according to the present disclosure, nanosheets 1410P and 1410N may alternatively be nanoplates, nanowires, or other GAA structures, as known in the art. Fig. 14BIt is shown that an isolation wall 1414A is formed between the P-type region 1402P and the N-type region 1402N to limit the growth of the epi-S / D 1412N in the horizontal direction over the isolation region 1406, and to limit the growth of the epi-S / D 1412P in the horizontal direction over the isolation region 1406. In this way, short circuit defects in the GAA circuit 1400 can be prevented.

[0088] In the GAA circuit 1400, an N-type epi-S / D 1412N is formed on at least one N-type GAA structure, the at least one N-type GAA structure extending longitudinally in the Y-axis direction, and a P-type epi-S / D 1412P is formed on at least one P-type GAA structure, the at least one P-type GAA structure extending longitudinally in the Y-axis direction. The N-type GAA structure and the P-type GAA structure are nanosheets 1410N and 1410P, respectively, as shown in FIG. Fig. 14B As shown, other GAA structures (e.g., nanoplates, nanowires, etc.) may also be used. Fig.14A and 14B The P-type region 1402P includes at least one P-type GAA structure extending longitudinally in a direction substantially parallel to the semiconductor substrate 1404, and the N-type region 1402N includes at least one N-type GAA structure extending longitudinally in a direction substantially parallel to the semiconductor substrate 1404.

[0089] In another example, by including an isolation wall in the isolation region, a complementary unit circuit (not shown) using a planar transistor can be manufactured without a short circuit defect between the P-type region and the N-type region. In this complementary unit circuit, the planar N-type transistor includes a first N-type epi-S / D and a second N-type epi-S / D, and the planar P-type transistor includes a first P-type epi-S / D and a second P-type epi-S / D. In the manufacture of this complementary unit circuit, forming the P-type region also includes forming a P-type planar region on a semiconductor substrate, and forming the N-type region also includes forming an N-type planar region on a substrate.

[0090] According to any aspect disclosed herein Figures 4A-4CAs shown in any one of , 5A-5C, 13A-13C and 14A-14B, the complementary unit circuit can be set in any processor-based device or integrated into any processor-based device, and the complementary unit circuit includes an isolation wall formed between the N-type region and the P-type region to limit the growth of the P-type epi-S / D and the N-type epi-S / D in the horizontal direction above the isolation region between the N-type region and the P-type region so as to prevent short circuit defects caused by process variations in the process for forming the epitaxial layer. Examples include, but are not limited to, a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a Session Initiation Protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, glasses, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, an avionics system, a drone, and a multirotor helicopter.

[0091] In this regard, Fig.15 An example of a processor-based system 1500 including a complementary unit circuit including an isolation wall formed between an N-type region and a P-type region to limit the growth of a P-type epi-S / D and an N-type epi-S / D in a horizontal direction over an isolation region between the N-type region and the P-type region so as to prevent short circuit defects caused by process variations in a process for forming an epitaxial layer, such as Figures 4A-4C , 5A-5C, 13A-13C, and 14A-14B, and according to any aspect disclosed herein. In this example, the processor-based system 1500 includes one or more central processor units (CPUs) 1502, which may also be referred to as CPUs or processor cores, each CPU or processor core including one or more processors 1504. The CPU 1502 may have a cache memory 1506 coupled to the processor 1504 for fast access to temporarily stored data. As an example, the processor 1504 may include a complementary cell circuit, which includes an isolation wall formed between an N-type region and a P-type region to limit the growth of the P-type epi-S / D and the N-type epi-S / D in a horizontal direction above the isolation region between the N-type region and the P-type region to prevent short circuit defects caused by process variations in the process for forming the epitaxial layer, such as Figures 4A-4C, 5A-5C, 13A-13C, and 14A-14B, and in accordance with any aspect disclosed herein. (Multiple) CPU 1502 is coupled to system bus 1508 and can interconnect master devices and slave devices included in processor-based system 1500. As is well known, (multiple) CPU 1502 communicates with these other devices by exchanging address, control, and data information using system bus 1508. For example, CPU 1502 can transmit bus transaction requests to memory controller 1510, which is an example of a slave device. Although in Fig.15 Although not shown, multiple system buses 1508 may be provided, each of which may be configured in a different structure.

[0092] Other master devices and slave devices may be connected to the system bus 1508. Fig.15 As illustrated, the devices may include a memory system 1512 including a memory controller 1510 and one or more memory arrays 1514, one or more input devices 1516, one or more output devices 1518, one or more network interface devices 1520, and one or more display controllers 1522, as examples. Each of the memory system 1512, the one or more input devices 1516, the one or more output devices 1518, the one or more network interface devices 1520, and the one or more display controllers 1522 may include a complementary unit circuit including an isolation wall formed between an N-type region and a P-type region to limit the growth of the P-type epi-S / D and the N-type epi-S / D in a horizontal direction above the isolation region between the N-type region and the P-type region so as to prevent short circuit defects caused by process variations in a process for forming an epitaxial layer, such as Figures 4A-4C , 5A-5C, 13A-13C and 14A-14B, and according to any aspect disclosed herein. (Multiple) input device 1516 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. (Multiple) output device 1518 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. (Multiple) network interface device 1520 can be any device configured to allow data to be exchanged to and from network 1524. Network 1524 can be any type of network, including but not limited to wired or wireless network, private or public network, local area network (LAN), wireless local area network (WLAN), wide area network (WAN), BLUETOOTH TM Network and Internet. Network interface device(s) 1520 may be configured to support any type of communication protocol desired.

[0093] The CPU(s) 1502 may also be configured to access the display controller 1522 via the system bus 1508 to control information sent to one or more displays 1526. The display controller(s) 1522 sends information to the display(s) 1526 to be displayed via one or more video processors 1528, which processes the information to be displayed into a format suitable for the display(s) 1526. The display 1526 may include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, etc. The display controller(s) 1522, the display(s) 1526, and / or the video processor(s) 1528 may include a complementary unit circuit including an isolation wall formed between an N-type region and a P-type region to limit the growth of the P-type epi-S / D and the N-type epi-S / D in a horizontal direction above the isolation region between the N-type region and the P-type region, so as to prevent short circuit defects caused by process variations in the process for forming the epitaxial layer, such as Figures 4A-4C , any of 5A-5C, 13A-13C and 14A-14B, and according to any aspect disclosed herein.

[0094] Fig.16 An exemplary wireless communication device 1600 is shown including radio frequency (RF) components formed by IC 1602, any of which may include, for example, Figures 4A-4C , 5A-5C, 13A-13C and 14A-14B and a complementary unit circuit according to any aspect disclosed herein, the complementary unit circuit includes an isolation wall formed between an N-type region and a P-type region to limit the growth of a P-type epi-S / D and an N-type epi-S / D in a horizontal direction above an isolation region between the N-type region and the P-type region, so as to prevent a short circuit defect caused by a process variation in a process for forming an epitaxial layer. As an example, the wireless communication device 1600 may include any of the above-referenced devices or be disposed therein. Fig.16 As shown, the wireless communication device 1600 includes a transceiver 1604 and a data processor 1606. The data processor 1606 may include a memory for storing data and program codes. The transceiver 1604 includes a transmitter 1608 and a receiver 1610 that support two-way communication. In general, the wireless communication device 1600 may include any number of transmitters 1608 and / or receivers 1610 for any number of communication systems and frequency bands. All or part of the transceiver 1604 may be implemented on one or more analog ICs, RF ICs (RFICs), mixed signal ICs, etc.

[0095] The transmitter 1608 or the receiver 1610 can be implemented using a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal is frequency converted between RF and baseband in multiple stages, for example, from RF to an intermediate frequency (IF) in one stage, and then from IF to baseband in another stage for the receiver 1610. In a direct conversion architecture, the signal is frequency converted between RF and baseband in one stage. Superheterodyne architectures and direct conversion architectures may use different circuit blocks and / or have different requirements. Fig.16 In the wireless communication device 1600, the transmitter 1608 and the receiver 1610 are implemented using a direct conversion architecture.

[0096] In the transmit path, the data processor 1606 processes data to be transmitted and provides I and Q analog output signals to the transmitter 1608. In the exemplary wireless communication device 1600, the data processor 1606 includes digital-to-analog converters (DACs) 1612(1), 1612(2) for converting digital signals generated by the data processor 1606 into I and Q analog output signals (e.g., I and Q output currents) for further processing.

[0097] Within the transmitter 1608, low pass filters 1614(1), 1614(2) filter the I and Q analog output signals, respectively, to remove undesired signals caused by the previous digital-to-analog conversion. Amplifiers (AMPs) 1616(1), 1616(2) amplify the signals from the low pass filters 1614(1), 1614(2), respectively, and provide I and Q baseband signals. An up converter 1618 up-converts the I and Q baseband signals with I and Q transmit (TX) local oscillator (LO) signals from a TX LO signal generator 1622 through mixers 1620(1), 1620(2) to provide up-converted signals 1624. A filter 1626 filters the up-converted signals 1624 to remove undesired signals caused by the frequency up-conversion and noise in the receive frequency band. A power amplifier (PA) 1628 amplifies the up-converted signals 1624 from the filter 1626 to obtain a desired output power level and provide a transmitted RF signal. The transmitted RF signal is routed through a duplexer or switch 1630 and transmitted via an antenna 1632 .

[0098] In the receive path, antenna 1632 receives the signal transmitted by the base station and provides a received RF signal, which is routed through a duplexer or switch 1630 and provided to a low noise amplifier (LNA) 1634. The duplexer or switch 1630 is designed to operate with a specific receive (RX) to TX duplexer frequency separation so that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 1634 and filtered by filter 1636 to obtain the desired RF input signal. Down-conversion mixers 1638 (1), 1638 (2) mix the output of filter 1636 with the I and Q RXLO signals (i.e., LO_I and LO_Q) from RX LO signal generator 1640 to generate I and Q baseband signals. The I and Q baseband signals are amplified by amplifiers (AMPs) 1642(1), 1642(2) and further filtered by low pass filters 1644(1), 1644(2) to obtain I and Q analog input signals, which are provided to the data processor 1606. In this example, the data processor 1606 includes analog-to-digital converters (ADCs) 1646(1), 1646(2) for converting the analog input signals into digital signals for further processing by the data processor 1606.

[0099] exist Fig.16 In the wireless communication device 1600 of the embodiment, the TX LO signal generator 1622 generates I and Q TX LO signals for frequency up-conversion, and the RX LO signal generator 1640 generates I and Q RX LO signals for frequency down-conversion. Each LO signal is a periodic signal with a specific base frequency. The TX phase-locked loop (PLL) circuit 1648 receives timing information from the data processor 1606 and generates a control signal for adjusting the frequency and / or phase of the TX LO signal from the TX LO signal generator 1622. Similarly, the RX PLL circuit 1650 receives timing information from the data processor 1606 and generates a control signal for adjusting the frequency and / or phase of the RX LO signal from the RX LO signal generator 1640.

[0100] It will be further understood by those skilled in the art that the various illustrative logic blocks, modules, circuits and algorithms described in conjunction with the aspects disclosed herein may be implemented as electronic hardware, stored in a memory or in another computer-readable medium and executed by a processor or other processing device, or a combination of the two. As an example, the master device and slave device described herein may be used for any circuit, hardware component, IC or IC chip. The memory disclosed herein may be a memory of any type and size, and may be configured to store any type of information desired. In order to clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits and steps have been generally described above with respect to their functions. How to implement such functions depends on specific applications, design choices and / or design constraints imposed on the entire system. Those skilled in the art may implement the described functions in different ways for each specific application, but such implementation decisions should not be interpreted as causing deviations from the scope of the present disclosure.

[0101] The various illustrative logical blocks, modules, and circuits described in conjunction with the various aspects disclosed herein may be implemented or executed by a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices designed to perform the functions described herein, discrete gate or transistor logic, discrete hardware components, or any combination thereof. The processor may be a microprocessor, but in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0102] The aspects disclosed herein may be embodied in hardware and instructions stored in hardware, and may reside, for example, in random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable media known in the art. An exemplary storage medium is coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. In an alternative, the storage medium may be integrated with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. In an alternative, the processor and storage medium may reside in a remote station, a base station, or a server as discrete components.

[0103] It should also be noted that the operation steps described in any exemplary aspect herein are described to provide examples and discussions. The described operation can be performed in many different sequences different from the sequence shown. In addition, the operation described in a single operation step can actually be performed in a plurality of different steps. In addition, one or more operation steps discussed in the exemplary aspects can be combined. It should be understood that the operation steps shown in the flow chart can be subjected to many different modifications, which will be obvious to those skilled in the art. Those skilled in the art will also understand that any one of the various technologies and techniques can be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be cited throughout the above description can be replaced by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0104] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications of the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations. Therefore, the disclosure is not intended to be limited to the examples and designs described herein, but should be consistent with the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A complementary unit circuit, include: Semiconductor substrate, comprising: P-type region; N-type region; and an isolation region, between the P-type region and the N-type region, the isolation region having a width extending in the direction of the first axis; a gate extending longitudinally in the direction of the first axis, the gate extending across a portion of each of the P-type region, the isolation region, and the N-type region; a first P-type epitaxial (epi) source / drain (S / D) (epi-S / D) formed on the P-type region on a first side of the gate, the first P-type epi-S / D extending over the isolation region in a first direction along the first axis; a first N-type epi-S / D formed on the N-type region on the first side of the gate, the first N-type epi-S / D extending over the isolation region in a second direction of the first axis; a first isolation wall extending from the isolation region in a third direction orthogonal to the first axis on the first side of the gate, the first isolation wall isolating the first P-type epi-S / D from the first N-type epi-S / D; a second P-type epi-S / D formed on the P-type region on a second side of the gate, the second P-type epi-S / D extending over the isolation region in the first direction of the first axis; a second N-type epi-S / D formed on the N-type region on the second side of the gate, the second N-type epi-S / D extending over the isolation region in the second direction of the first axis; and a second isolation wall extending from the isolation region in the third direction orthogonal to the first axis on the second side of the gate, the second isolation wall isolating the second P-type epi-S / D from the second N-type epi-S / D; The bottom end of the first isolation wall and the bottom end of the second isolation wall are below the top surface of the isolation region, so that the isolation region provides structural support for the first isolation wall and the second isolation wall.

2. The complementary unit circuit according to claim 1, further comprising: include: A gate cutout is disposed at an end of the gate, and the gate cutout includes a material forming the first spacer and the second spacer.

3. The complementary unit circuit according to claim 2, in: The material of the gate cut, the first spacer, and the second spacer includes at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SIC), and aluminum oxide (AlO).

4. The complementary unit circuit according to claim 1, in: The first partition wall and the second partition wall each extend longitudinally in a fourth direction orthogonal to the gate.

5. The complementary unit circuit according to claim 1, in: The N-type region includes an N-type fin extending from the semiconductor substrate in the third direction; The first N-type epi-S / D and the second N-type epi-S / D are formed on the N-type fin; The P-type region includes a P-type fin extending from the semiconductor substrate in the third direction; and The first P-type epi-S / D and the second P-type epi-S / D are formed on the P-type fin.

6. The complementary unit circuit according to claim 1, in: The first N-type epi-S / D and the second N-type epi-S / D are formed on at least one N-type gate-all-around (GAA) structure, and the at least one N-type gate-all-around structure extends longitudinally in a fourth direction orthogonal to the first direction and the third direction; The first P-type epi-S / D and the second P-type epi-S / D are formed on at least one P-type GAA structure, and the at least one P-type GAA structure extends longitudinally in the fourth direction; and The N-type GAA structure and the P-type GAA structure each include a nanosheet, a nanoplate, or a nanowire.

7. The complementary unit circuit according to claim 1, in: The planar N-type transistor includes the first N-type epi-S / D and the second N-type epi-S / D; and The planar P-type transistor includes the first P-type epi-S / D and the second P-type epi-S / D.

8. The complementary unit circuit according to claim 1, integrated into an integrated circuit (IC).

9. The complementary unit circuit of claim 1 , integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet computer; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; an unmanned aerial vehicle; and a multirotor helicopter.

10. A method of forming a complementary unit circuit including an isolation structure, the method include: forming a P-type region on a first side of an isolation region on a semiconductor substrate, the isolation region extending longitudinally in a first direction; forming an N-type region on the semiconductor substrate on a second side of the isolation region; forming a dummy gate extending longitudinally in a second direction orthogonal to the first direction and extending across the P-type region, the isolation region, and a portion of the N-type region; depositing a dielectric layer on the P-type region, the isolation region, and the N-type region on the first and second sides of the dummy gate; etching a first trench through the dielectric layer on the first side of the dummy gate and into a surface of the isolation region on the first side of the dummy gate, A second trench is etched through the dielectric layer on the second side of the dummy gate and to in a surface of the isolation region on the second side of the dummy gate; An isolation structure is formed, including: filling the first trench with an isolation material to form a first isolation wall, wherein a portion of the first trench in the isolation region provides structural support for the first isolation wall; and filling the second trench with the isolation material to form a second isolation wall, wherein a portion of the second trench in the isolation region provides structural support for the second isolation wall; forming a first N-type epitaxial (epi) source / drain (S / D) (epi-S / D) on the N-type region on the first side of the dummy gate, the first N-type epi-S / D extending over the isolation region on the first side of the first isolation wall; forming a second N-type epi-S / D on the N-type region on the second side of the dummy gate, the second N-type epi-S / D extending over the isolation region on the first side of the second isolation wall; forming a first P-type epi-S / D on the P-type region on the first side of the dummy gate, the first P-type epi-S / D extending over the isolation region on a second side of the first isolation wall and isolated from the first N-type epi-S / D by the first isolation wall; and A second P-type epi-S / D is formed on the P-type region on the second side of the dummy gate, the second P-type epi-S / D extending over the isolation region on the second side of the second isolation wall and isolated from the second N-type epi-S / D by the second isolation wall.

11. The method according to claim 10, further comprising: include: Forming a trench mask on the dielectric layer, comprising: depositing a trench mask layer; and The trench mask layer is patterned to create openings for forming trenches in the dielectric layer.

12. The method according to claim 10, in: Filling the first trench and the second trench with the isolation material further includes: filling the first trench and the second trench with the isolation material to a height of the dummy gate.

13. The method according to claim 10, further comprising: include: A gate cut mask is formed, comprising: depositing a gate cut mask layer; and The gate cut mask layer is patterned to create an opening over the dummy gate for forming a trench in the dummy gate.

14. The method according to claim 13, further comprising: include: etching a gate cut trench through the dummy gate; The forming of the isolation structure further comprises: filling the gate cut trench with the isolation material to form a gate cut.

15. The method according to claim 14, in: Filling the gate cut trench with the isolation material further includes: filling the gate cut trench with the isolation material to a height of the dummy gate.

16. The method according to claim 10, in: Forming the P-type region further comprises: forming a P-type plane region on the semiconductor substrate; and Forming the N-type region further includes: forming an N-type plane region on the semiconductor substrate.

17. The method according to claim 10, in: Forming the P-type region further includes: forming at least one P-type fin extending orthogonally to the semiconductor substrate; and Forming the N-type region further includes forming at least one N-type fin extending orthogonally to the semiconductor substrate.

18. The method according to claim 10, in: Forming the P-type region further comprises: forming at least one P-type gate-all-around (GAA) structure, the at least one P-type gate-all-around structure extending longitudinally in a direction substantially parallel to the semiconductor substrate; and Forming the N-type region further comprises: forming at least one N-type GAA structure, the at least one N-type GAA structure extending longitudinally in a direction substantially parallel to the semiconductor substrate; The GAA structure includes nanosheets, nanoplates or nanowires.

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