Control logic circuit, memory, storage system and operating method

Abstract

The embodiment of the present application provides a control logic circuit, a memory, a storage system and an operating method. The control logic circuit comprises a microprocessor and a control bus CBUS, the microprocessor is connected with a setting circuit in a peripheral circuit of the memory through the CBUS; the setting circuit comprises a register; wherein; the CBUS comprises a mask control line used for transmitting a mask control signal sent by the microprocessor and a group of data transmission lines used for transmitting data; wherein, in the case that the mask control signal transmitted by the mask control line is valid, the data transmission line is used for transmitting mask data; the mask data and the control data are used to change data bits that need to be changed in original data stored by the register.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memory, and in particular to a control logic circuit of memory, memory, storage system and operating method. BACKGROUND

[0002] With the development of computer and storage technology, the dependence of various industries on computer and memory is gradually increasing, and the performance of computer and its contained memory has also been increasingly high requirements. At present, the use of bus cannot meet the increasing demand for data access in the field of communication. SUMMARY

[0003] Therefore, the main purpose of the present application is to provide a control logic circuit of memory, memory, storage system and operating method to realize the bit-level control of data in the register.

[0004] To achieve the above purpose, the technical scheme of the present application is as follows:

[0005] In the first aspect, the present application provides a control logic circuit of memory, comprising: a microprocessor and a control bus CBUS, the microprocessor is connected with a setting circuit in the peripheral circuit of the memory through the CBUS; the setting circuit contains a register; wherein;

[0006] The CBUS includes a mask control line for transmitting a mask control signal issued by the microprocessor and a group of data transmission lines for transmitting data; wherein, in the case that the mask control signal transmitted by the mask control line is effective, the data transmission line is used to transmit mask data; the mask data and the control data are used to change the data bits of the original data stored in the register that need to be changed. In the above scheme, the CBUS further includes a clock control line, wherein;

[0007] The clock control line is used to transmit a clock signal;

[0008] The data transmission line is used to transmit the mask data based on the clock signal in the case that the mask control signal is effective.

[0009] In the above scheme, the data transmission line is also used to transmit the control data based on the transmission of the clock signal before or after the transmission of the mask data.

[0010] In the above scheme, the CBUS further includes a group of address transmission lines, wherein;

[0011] The set of address transmission lines are configured to transmit address signals of the register; the address signals are configured to cause the mask data and the control data to be transmitted to the register.

[0012] In the above aspect, the mask data, the control data, and the original data contain the same bit.

[0013] In the above aspect, the microprocessor includes at least one.

[0014] In a second aspect, an embodiment of the present application further provides a memory, comprising: a memory array and a peripheral circuit coupled to the memory array and configured to control the memory array, wherein the peripheral circuit comprises the control logic circuit of any one of the above aspects.

[0015] In the above aspect, the memory array is a three-dimensional NAND memory array.

[0016] In a third aspect, an embodiment of the present application further provides a memory system, comprising: one or more memories of the above aspects and a memory controller coupled to the memory; the memory controller is configured to send various operation commands to the memory.

[0017] In the above aspect, the memory system is a solid state drive (SSD) or a memory card.

[0018] In a fourth aspect, an embodiment of the present application further provides an operation method of a memory, wherein the memory comprises a control logic circuit; the control logic circuit comprises a microprocessor and a control bus (CBUS); the microprocessor is connected to a setting circuit in a peripheral circuit of the memory through the CBUS; the setting circuit comprises a register; the operation method comprises:

[0019] The microprocessor transmits a mask control signal through a mask control line of the CBUS;

[0020] When the mask control signal is valid, the microprocessor controls a data transmission line of the CBUS to transmit mask data; the mask data and the control data are used to change data bits in original data stored in the register.

[0021] In the above aspect, the operation method further comprises:

[0022] performing a first logical operation on the mask data and the original data to obtain an intermediate operation result;

[0023] performing a second logical operation on the intermediate operation result and the control data to obtain a target operation result;

[0024] The target operation result is stored in the register in the original order to change the data bit in the original data stored in the register.

[0025] The application provides a control logic circuit of a memory, a memory, a storage system and an operation method. The control logic circuit comprises a microprocessor and a control bus CBUS, the microprocessor is connected with a setting circuit in a peripheral circuit of the memory through the CBUS, the setting circuit comprises a register, the CBUS comprises a mask control line for transmitting a mask control signal sent by the microprocessor and a group of data transmission lines for transmitting data, and the data transmission lines are used for transmitting mask data when the mask control signal transmitted by the mask control line is valid, the mask data and the control data are used to change the data bit in the original data stored in the register. The control logic circuit provided by the application enables or disables the function of transmitting mask data on the data transmission lines according to whether the mask control signal transmitted on the mask control line is valid, and when the mask control signal is valid, the mask data is transmitted, and through the joint action of the transmitted mask data and the control data, only one or more data bits in the register in the memory can be changed, thereby realizing the bit-level control of the register. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 The application provides a structural schematic diagram of a data system;

[0027] Figure 2 The application provides a schematic diagram of an exemplary memory comprising a peripheral circuit;

[0028] Figure 3 The application provides a block diagram of an exemplary memory comprising a storage array and a peripheral circuit;

[0029] Figure 4 The application provides a schematic diagram of the connection relationship between the control logic circuit and other circuits in the peripheral circuit;

[0030] Figure 5 The application provides a structural schematic diagram of the control logic circuit;

[0031] Figure 6 The application provides a timing diagram of transmitting mask data based on the CBUS;

[0032] Figure 7 The application provides a timing diagram of not transmitting mask data based on the CBUS;

[0033] Figure 8A binary sequence schematic diagram of the pseudo-instruction of the mask data provided by the embodiment of the present application is shown in the following table.

[0034] Figure 9 A binary sequence schematic diagram of one example of the pseudo-instruction of the mask data provided by the embodiment of the present application is shown in the following table.

[0035] Figure 10 A binary sequence schematic diagram of the pseudo-instruction of the control data provided by the embodiment of the present application is shown in the following table.

[0036] Figure 11 A binary sequence schematic diagram of one example of the pseudo-instruction of the control data provided by the embodiment of the present application is shown in the following table.

[0037] Figure 12 A flowchart schematic diagram of the operation method of the memory provided by the embodiment of the present application is shown in the following table.

[0038] Figure 13 A schematic diagram of the bit-level data control of the register based on CBUS provided by the embodiment of the present application is shown in the following table. DETAILED DESCRIPTION

[0039] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application. In addition, the technical features involved in each embodiment of the present application described below can be combined with each other as long as there is no conflict.

[0040] In the embodiment of the present application, unless the context clearly indicates otherwise, the words "one", "a", "an" and / or "the" do not specifically refer to the singular, but also include the plural. Generally, the terms "comprise" and "include" only indicate the inclusion of the steps and elements explicitly identified, and these steps and elements do not constitute an exclusive list, and the method or device can also include other steps or elements.

[0041] In addition, it should be noted that the use of the words "first", "second", etc. to limit parts only facilitates the distinction of the corresponding parts, and unless otherwise stated, the above words have no special meaning, and therefore cannot be understood as limiting the scope of protection of the present application.

[0042] The technical solutions provided by the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0043] Figure 1A block diagram of an exemplary system including a memory is provided for embodiments of the present application. The system 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage. As shown in Figure 1 The system 100 can include a host 108 and a memory system 102, where the memory system 102 has one or more memories 104 and a memory controller 106; the host 108 can be a processor of an electronic device, such as a central processing unit (CPU) or a system of chip (SoC), which can be, for example, an application processor (AP). The host 108 can be configured to send data to or receive data from the memory 104.

[0044] In particular, the memory 104 can be any type of memory, such as any memory device disclosed in the present application, as disclosed in detail below, the memory 104, such as an electrically erasable programmable read-only memory (EEPROM), a NOR type flash memory, a phase change random (PRAM), a magnetic random memory (MRAM), a resistive random memory (RRAM), a ferroelectric random memory (FRAM), etc.

[0045] According to some embodiments, a memory controller 106 is coupled to the memory 104 and the host 108. And is configured to control the memory 104. The memory controller 106 can manage data stored in the memory 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed for operation in low duty cycle environments, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices in low duty cycle environments such as personal computers, digital cameras, mobile telephones, etc. In some embodiments, the memory controller 106 is designed for operation in high duty cycle environments, such as a Solid State Drive (SSD) or an embedded Multi Media Card (eMMC), where the SSD or eMMC is used as a data storage for mobile devices in high duty cycle environments such as smartphones, tablet computers, laptop computers, etc. as well as enterprise storage arrays. The memory controller 106 can be configured to control operations of the memory 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions with respect to data stored in or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to handle Error Correction Codes (ECC) with respect to data read from or written to the memory 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 can communicate with external devices (e.g., the host 108) according to a particular communication protocol.For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnection (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachmnet (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, etc.

[0046] The memory controller 106 and the one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. In one example, the memory controller 106 and a single memory 104 can be integrated into a memory card. The memory card can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card can also include a memory card connector that couples the memory card with a host (e.g., the host 108 in Figure 1 In another example, the memory controller 106 and a plurality of memories 104 can be integrated into an SSD. The SSD can also include an SSD connector that couples the SSD with a host (e.g., the host 108 in Figure 1 In some embodiments, the storage capacity and / or operating speed of the SSD is greater than that of the memory card. In addition, the memory controller 106 can also be configured to control erase, read, write operations of the memories 104.

[0047] Figure 2 A schematic circuit diagram of an exemplary memory 104 including a peripheral circuit is shown in accordance with some aspects of the present application. As Figure 2As shown, the memory 104 can include a storage array 201 and a peripheral circuit 202 coupled to the storage array 201. The storage array 201 can be a NAND flash storage array in which storage transistors 206 are provided in an array of NAND storage cell strings 208, each of which extends vertically over a substrate (not shown). In some embodiments, each NAND storage cell string 208 includes a plurality of storage transistors 206 (also referred to simply as storage cells) coupled in series and stacked vertically. Each storage transistor 206 can hold a continuous analog value, e.g., a voltage or a charge, that depends on the number of electrons trapped within a region of the storage transistor 206. Each storage transistor 206 can be a floating gate type of storage transistor that includes a floating gate transistor, or a charge trap type of storage transistor that includes a charge-trapping transistor.

[0048] Each storage transistor 206 discussed above can be a single-level storage cell or a multi-level storage cell, where a single-level storage cell can be a single-level cell (SLC) capable of storing 1 bit, a multi-level storage cell can be a multi-level cell (MLC) capable of storing 2 bits, a triple-level cell (TLC) capable of storing 3 bits, a quad-level cell (QLC) capable of storing 4 bits, a penta-level cell (PLC) capable of storing 5 bits, and so on. In actual applications, different kinds of storage cells have different data states.

[0049] Returning again to FIG. 1, the memory controller 102 can be coupled to the memory 104 via a bus 110. The bus 110 can be a serial bus, such as a serial advanced technology attachment (SATA) bus, a peripheral component interconnect express (PCIe) bus, a universal serial bus (USB) bus, or a serial bus of another type. In some embodiments, the bus 110 can be a parallel bus, such as a parallel advanced technology attachment (PATA) bus, a small computer system interface (SCSI) bus, or a parallel bus of another type. Figure 2As shown in FIG. 2, each NAND memory cell string 208 can include a source select gate (SSG) 210 at its source end and a drain select gate (DSG) 212 at its drain end. The SSG 210 and the DSG 212 can be configured to activate a selected NAND memory cell string 208 (column of the array) during read and program operations. In some embodiments, the sources of the NAND memory cell strings 208 in the same block 204 are coupled through the same source line (SL) 214 (e.g., a common SL). In other words, according to some embodiments, all of the NAND memory cell strings 208 in the same block 204 have an array common source (ACS). According to some embodiments, the DSG 212 of each NAND memory cell string 208 is coupled to a respective bit line 216 from which data can be read or written via an output bus (not shown). In some embodiments, each NAND memory cell string 208 is configured to be selected or deselected by applying a select voltage (e.g., above the threshold voltage of the transistor having the DSG 212) or a deselect voltage (e.g., 0V) to the respective DSG 212 via one or more DSG lines 213 and / or by applying a select voltage (e.g., above the threshold voltage of the transistor having the SSG 210) or a deselect voltage (e.g., 0V) to the respective SSG 210 via one or more SSG lines 215.

[0050] As another example Figure 2As shown in FIG. 1, the NAND memory cell strings 208 can be organized into a plurality of blocks 204, each of which can have a common source line 214 (e.g., coupled to ground). In some embodiments, each block 204 is the basic unit of data for erase operations, i.e., all memory transistors 206 on the same block 204 are erased at the same time. To erase the memory transistors 206 in a selected block 204, the source lines 214 coupled to the selected block 204 and to unselected blocks 204 in the same face as the selected block 204 can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It will be appreciated that in some examples, erase operations can be performed at a half-block level, at a quarter-block level, or at a level having any suitable fraction of blocks or blocks. The memory transistors 206 of the NAND memory cell strings 208 of the same layer can be coupled by word lines 218, all of the memory cells coupled by one word line 218 making up one memory cell layer. The word lines 218 select which row of memory transistors 206 is affected by read and program operations. In some embodiments, each word line 218 is coupled to a page 220 of memory transistors 206, which is the basic unit of data for program operations. The size of a page 220 in bits can be related to the number of NAND memory cell strings 208 in a block 204 coupled by a word line 218. Each word line 218 can include a plurality of control gates (gate electrodes) at each memory transistor 206 in the corresponding page 220 as well as a gate line coupling the control gates.

[0051] Referring back to FIG. 1, Figure 2 The peripheral circuitry 202 can be coupled to the memory array 201 by the bit lines 216, the word lines 218, the source lines 214, the SSG lines 215, and the DSG lines 213. The peripheral circuitry 202 can include any suitable analog, digital, and mixed-signal circuitry for facilitating the operation of the memory array 201 by applying voltage signals and / or current signals to and sensing voltage signals and / or current signals from each target memory transistor 206 via the bit lines 216, the word lines 218, the source lines 214, the SSG lines 215, and the DSG lines 213. The peripheral circuitry 202 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 3 Some example peripheral circuitry is shown, the peripheral circuitry 202 including a page buffer / sense amplifier 304, a column decoder / bit line driver 306, a row decoder / word line driver 308, a voltage generator 310, control logic circuitry 312, registers 314, an interface 316, and data transfer lines 318. It will be appreciated that additional peripheral circuitry not shown in FIG. 1 can also be included in some examples. Figure 3

[0052] ​The page buffer / sense amplifier 304 can be configured to read data from and program (write) data to the memory array 201 according to control signals from the control logic circuit 312. In one example, the page buffer / sense amplifier 304 can store a page of program data (write data) to be programmed into one page 220 of the memory array 201. In another example, the page buffer / sense amplifier 304 can perform a program verify operation to ensure that data has been correctly programmed into the memory transistors 206 coupled to the selected word line 218. In yet another example, the page buffer / sense amplifier 304 can also sense low power signals from the bit lines 216 representing data bits stored in the memory transistors 206 and amplify small voltage excursions to identifiable logic levels in read operations. The column decoder / bit line driver 306 can be configured to be controlled by the control logic circuit 312 and select one or more NAND memory cell strings 208 by applying bit line voltages generated from the voltage generator 310.

[0053] The row decoder / word line driver 308 can be configured to be controlled by the control logic circuit 312 and select / deselect blocks 204 of the memory array 201 and select / deselect word lines 218 of the blocks 204. The row decoder / word line driver 308 can also be configured to drive the word lines 218 using word line voltages generated from the voltage generator 310. In some implementations, the row decoder / word line driver 308 can also select / deselect and drive the SSG line 215 and the DSG line 213. As described in detail below, the row decoder / word line driver 308 is configured to perform erase operations on the memory transistors 206 coupled to the selected word line(s) 218. The voltage generator 310 can be configured to be controlled by the control logic circuit 312 and generate word line voltages (e.g., read voltages, program voltages, pass voltages, local voltages, verify voltages, etc.), bit line voltages, and source line voltages to be supplied to the memory array 201.

[0054] The control logic circuit 312 can be coupled to each of the peripheral circuits described above and configured to control the operation of each of the peripheral circuits. The registers 314 can be coupled to the control logic circuit 312 and include status registers, command registers, and address registers for storing status information, command operation codes (OP codes), and command addresses used to control the operation of each of the peripheral circuits. The interface 316 can be coupled to the control logic circuit 312 and act as a control buffer to buffer control commands received from a host (not shown) and relay the same to the control logic circuit 312, and to buffer status information received from the control logic circuit 312 and relay the same to the host. The interface 316 can also be coupled to the column decoder / bit line driver 306 via the data transfer lines 318 and act as a data I / O interface and data buffer to buffer data and relay the same to or from the memory array 201.

[0055] In some embodiments, the control logic circuit 312 can be implemented by a microprocessor, a microcontroller (also referred to as a microcontroller unit (MCU)), a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a programmable logic device (PLD), a state machine, gated logic, discrete hardware circuits, and other suitable hardware, firmware, and / or software configured to perform the various functions described.

[0056] It is noted that the control logic circuit 312, regardless of the type of hardware, firmware, and / or software used to implement it, can include a plurality of types of MCUs to control different functional circuits in the peripheral circuits. For example, as shown in FIG. 3, the control logic circuit 312 can include a first MCU 320 to control the column decoder / bit line driver 306, a second MCU 322 to control the row decoder 308, a third MCU 324 to control the sense amplifiers 310, and a fourth MCU 326 to control the data I / O interface 316. Figure 4As shown, the control logic circuit includes three types of MCUs, mainly including: a main program microcontroller MP_MCU, core microcontrollers CORE MCUx4, and a page buffer microcontroller PB MCU, wherein the MP_MCU communicates with the CORE MCU and the PB MCU through a bus MBUS, runs a main program, and controls the CORE MCU and the PB MCU to configure the functions of the corresponding circuits; the CORE MCUx4 communicates with the registers of the X_PATH circuit, the Y_PATH circuit, other analog circuits, and the like in the peripheral circuit of the memory through a CBUS to configure the parameters required for the operation of the above-mentioned circuits; and the PB MCU communicates with the registers of the page buffer through a PBUS to configure the parameters required for the operation of the page buffer. It should be noted that the control logic circuit 312 is only exemplarily shown as including three microprocessors, and it can actually include more, and the specific number is not limited. Here, the X_PATH circuit can refer to a circuit that provides voltage to the components in the X direction (the direction pointing to the word line) of the memory array 201 during different operations (such as reading or writing), such as a row decoder / WL driver 308; the Y_PATH circuit can refer to a circuit that provides voltage to the components in the Y direction (the direction pointing to the bit line or the source line) of the memory array 201 during different operations (such as reading or writing), such as a column decoder / BL driver 306; and the other analog circuits are, for example, voltage generators and the like.

[0057] Based on the above-described memory structure and related technology, the CORE MCU x4 (taking a microprocessor in the core control of the control logic circuit as an example) is connected to the setting circuit (X_PATH circuit, Y_PATH circuit, analog circuit) in the peripheral circuit of the memory through the CBUS to configure the registers included in the setting circuit, and can only operate the entire register, so that when one bit, two bits, or several bits of data in the register need to be changed, a statement for judging the state of other bits of data in the register also needs to be added, which not only increases the processing time, but also increases the size of the read-only memory (ROM) in the control logic circuit for storing programs.

[0058] Therefore, in order to solve the above technical problems, with reference to Figure 5 It shows that the control logic circuit of the memory provided by the embodiment of the present application. As Figure 5 As shown, the control logic circuit 312 includes: a microprocessor 501 and a control bus CBUS 502, the microprocessor is connected to the setting circuit in the peripheral circuit of the memory through the CBUS 502; the setting circuit includes a register; wherein;

[0059] The CBUS 502 includes a mask control line for transmitting mask control signals issued by the microprocessor and a set of data transmission lines for transmitting data; wherein, when the mask control signals transmitted by the mask control line are valid, the data transmission lines are used to transmit mask data; the mask data and the control data work together to change the data bits that need to be changed in the original data stored in the register.

[0060] It should be noted that one specific form of the microcontroller mentioned here can be the one described above. Figure 4 The COREMCU x4 mentioned above. One specific form of the CBUS 502 mentioned above could be the aforementioned... Figure 4 Any of CBUSx4 in the dataset.

[0061] The mask control signal can be active when high and inactive when low. It should be noted that the effective level of the mask control signal can also be active when low and inactive when high, depending on the specific memory; this is not limited here.

[0062] The technical solution described here can be understood as follows: A mask control line is added to the CBUS control bus (a mask control line that did not exist previously). Then, when the mask control signal transmitted on this mask control line is valid, mask data is transmitted using a data transmission line. This mask data is used in conjunction with the control data transmitted on the data transmission line to change the data bits that need to be modified in the original data stored in the register.

[0063] The data transmission line can refer to a group of data lines with a certain data width, where the data width is also known as the data bits, which can be 8 bits, 16 bits, 32 bits, etc. In other words, the data transmission line can refer to a group of data lines capable of transmitting a certain data width at a time.

[0064] In some embodiments, the CBUS is a unidirectional bus used only for writing data to the register.

[0065] In some embodiments, the microprocessor 501 includes at least one. For example, such as... Figure 4 As shown, the microprocessor 501 contains four.

[0066] It should be noted that the setting circuit here can refer to, for example... Figure 4 The X_PATH circuit, Y_PATH circuit, analog circuits, etc. shown, in other words, not all circuits in the peripheral circuits control the microprocessor in the logic circuit to communicate via CBUS, but rather... Figure 4 The different types of circuits shown can communicate using different types of control buses.

[0067] In some embodiments, the CBUS can further comprise a clock control line, wherein the clock control line is configured to transmit a clock signal.

[0068] The clock control line is configured to transmit a clock signal.

[0069] The data transmission line is configured to transmit the mask data based on the clock signal when the mask control signal is valid.

[0070] It should be noted that the clock signal is a term used in computer science and related fields, which is the basis of sequential logic and is used to determine when the state in the logic unit is updated. It is a fixed period and is independent of the running signal, and in general, the clock signal plays an important role in data transmission. Therefore, in general, there is a clock signal during data transmission. Therefore, the clock control line is also included in the control bus to receive the clock signal. Then, the data transmission line transmits the mask data based on the clock signal when the mask control signal is valid. It should be noted that during actual transmission, the mask data is transmitted using the data transmission line according to the rising edge and / or falling edge of the clock signal. That is, the condition for transmitting the mask data is that when the mask control signal transmitted on the mask control line is valid, the mask data is transmitted according to the rising edge and / or falling edge of the clock signal.

[0071] In some embodiments, the data transmission line is further configured to transmit the control data based on the clock signal before or after the mask data is transmitted.

[0072] It should be noted that the transmission of the control data before or after the transmission of the mask data is transmitted according to the rising edge and / or falling edge of the clock signal.

[0073] In some embodiments, the CBUS further comprises a group of address transmission lines, wherein the group of address transmission lines is configured to transmit an address signal of the register.

[0074] The group of address transmission lines is configured to transmit an address signal of the register, and the address signal is used to cause the mask data and the control data to be transmitted to the register.

[0075] It should be noted that in order to indicate which register is configured, the address signal needs to be transmitted through the address transmission line during data transmission.

[0076] In order to understand the above description, as shown in Figure 6 The timing diagram for transmitting the mask data based on the CBUS provided by the embodiments of the present application is shown. In Figure 6CBUS_clk represents a clock signal, wherein the data transmission line transmits mask data or control data at the falling edge of the clock signal; CBUS_data_is_mask represents a mask control signal input to the mask control line, wherein the high level of the mask control signal is the effective level. CBUS_data represents the mask data or control data transmitted by the data transmission line; CBUS_addr represents the address transmitted by the address bus. At this time, based on the foregoing description, the mask data is transmitted by the data transmission line when CBUS_data_is_mask is high and the falling edge of CBUS_clk arrives. The control data is transmitted by the data transmission line when CBUS_data_is_mask is low and the falling edge of CBUS_clk arrives. After the mask data is transmitted, the control data is transmitted. Then, the two work together to change the data bit that needs to be changed in the register.

[0077] In the embodiment of the present application, when the mask data is not needed to be transmitted, the timing diagram is as shown in Figure 7 Figure 7 In the embodiment, the transmission of data is directly based on the falling edge of the clock signal, which is the same as the previous data transmission, and will not be described here.

[0078] It should be noted that the number of bits of the mask data and the control data here is only an example. The number of bits of the address is also an example. It does not limit the present application. The mask data and the control data, and the address can contain known achievable number of bits.

[0079] It should be noted that the mask control signal transmitted by the mask control line, the mask data or the control data transmitted by the data transmission line, and the address signal transmitted by the address transmission line included in the CBUS are all a series of binary sequences, which are obtained by the assembly instruction sent by the CORE MCU x4 analysis main program microcontroller MP_MCU to the CORE MCU x4 through the bus MBUS. Among them, the assembly instruction can be a pseudo instruction.

[0080] The pseudo instruction of the mask data can be: MASK mask cRtgt, which is parsed into a binary sequence by the CORE MCU x4, as shown in Figure 8 0-3 bits represent the address signal; 4-11 bits represent the mask data; and 12-15 bits represent the mask control signal. From Figure 8 It can be seen that when the mask control signal is effective, 12-15 bits are all 1.

[0081] For example, when the assembly pseudo instruction of the mask data is: MASK 7Fh 1, the binary sequence is as shown in Figure 9 ​The address signal is 0001, which means the register is encoded as 1. The mask data is 7Fh, and the binary sequence is 01111111.

[0082] Similarly, the pseudo instruction for controlling data can be SETR data cRtgt, which is parsed by CORE MCUx4 into a binary sequence as shown in Figure 10 For example, the assembly pseudo instruction for controlling data is SETR 80h 1, and the binary sequence is as shown in Figure 11 The address signal is 0001, which means the register is encoded as 1. The control data is 80h, and the binary sequence is 10000000.

[0083] It should be noted that the aforementioned mask data is used to act together with the control data transmitted by the data transmission line to change the data bits in the original data stored in the register that need to be changed. Specifically, the mask data, the control data, and the original data are logically operated to change only the data bits in the original data in the register that need to be changed.

[0084] It should be noted that the logical operation can be OR operation, AND operation, or XOR operation, etc.

[0085] Here, the operation steps for changing only the data of the data bits in the register that need to be changed are described. In one implementation, the operation steps can include: performing a first logical operation on the mask data and the original data in the register to obtain an intermediate operation result; performing a second logical operation on the intermediate operation result and the control data to obtain a target operation result; and storing the target operation result in the register according to the original order.

[0086] At this time, the target operation result stored in the register is compared with the original data, only the data bits that need to be changed are changed to the expected value, and other data is not changed, but remains the original data.

[0087] For example, assuming that the register is an 8-bit register, the original data stored in the register is (00001000)2, if only the highest bit of the data needs to be changed, the mask control line in the control bus can be triggered to be effective to transmit the mask data (01111111)2, and the control data (10000000)2 is transmitted by using the data transmission line, then the mask data is first logically ANDed with the original data (first logical operation) to obtain an intermediate operation result (00001000)2, and then the intermediate operation result is logically ORed with the control data (second logical operation) to obtain a target operation result (10001000)2, and the (10001000)2 is stored in the register according to the original order, at this time, only one bit of the data stored in the register is changed, that is, the bit-level control of the register is realized.

[0088] Such a control mode not only does not affect the original data transmission mode in the register, but also can be conveniently realized when only some bits of the data in the register need to be changed, thereby saving processing time and not needing a large number of judgment statements for other bits that do not need to be changed, and the size of the ROM is saved.

[0089] Based on the same inventive concept, the embodiments of the present application also provide an operation method of a memory, the operation method being applied to the memory comprising a control logic circuit; the control logic circuit comprising a microprocessor and a control bus CBUS; the microprocessor being connected with a setting circuit in a peripheral circuit of the memory through the CBUS; the setting circuit comprising a register; as shown in the figure, the operation method comprises: Figure 12

[0090] S1201: the microprocessor transmits a mask control signal through a mask control line of the CBUS;

[0091] S1202: in the case that the mask control signal is effective, the microprocessor controls a data transmission line of the CBUS to transmit mask data; the mask data and the control data are used to change the data bits that need to be changed in the original data stored in the register.

[0092] In some embodiments, as shown in the figure, the operation method further comprises: Figure 13

[0093] S1301: first logical operation is performed on the mask data and the original data to obtain an intermediate operation result;

[0094] S1302: second logical operation is performed on the intermediate operation result and the control data to obtain a target operation result;

[0095] ​​S1303: store the target operation result in the register according to the original order, to change the data bit of the original data stored in the register.

[0096] It should be noted that the operation method of the memory provided by the embodiments of the present application is based on the control logic circuit provided in the foregoing, and therefore, both have the same technical features. The terms appearing in the technical solutions herein have been described in detail in the foregoing, and will not be described again here.

[0097] The embodiments of the present application also provide a memory, a memory array and a peripheral circuit coupled to the memory array and used for controlling the memory array, wherein the peripheral circuit includes the control logic circuit described above.

[0098] In some embodiments, the memory array is a three-dimensional NAND memory array.

[0099] The embodiments of the present application also provide a storage system, including one or more of the foregoing memories and a memory controller coupled to the memory; the memory controller is used to send various operation commands to the memory. The various operations include read, write, erase and the like.

[0100] The storage system is a solid state disk (SSD) or a memory card.

[0101] The above description is only a preferred embodiment of the present application, and is not intended to limit the protection scope of the present application.

Claims

1. A control logic circuit for a memory, characterized by The application relates to a memory and a control method thereof. The memory comprises a microprocessor and a control bus CBUS, the microprocessor is connected with a setting circuit in the peripheral circuit of the memory through the CBUS; the setting circuit comprises a register; The CBUS comprises a mask control line for transmitting a mask control signal sent by the microprocessor and a group of data transmission lines for transmitting data; wherein, when the mask control signal transmitted by the mask control line is valid, the data transmission lines are used for transmitting mask data; before or after the mask data is transmitted, the data transmission lines are used for transmitting control data; the mask data and the control data are used in common to change data bits that need to be changed in original data stored in the register. The CBUS further comprises a clock control line, wherein; 2. The control logic circuit of claim 1, wherein, The clock control line is used for transmitting a clock signal; The data transmission lines are used for transmitting the mask data based on the clock signal when the mask control signal is valid. The data transmission lines are used for transmitting the control data based on the clock signal.

3. The control logic circuit of claim 2, wherein, The CBUS further comprises a group of address transmission lines, wherein; 4. The control logic circuit of claim 1, wherein, The group of address transmission lines are used for transmitting an address signal of the register; the address signal is used for making the mask data and the control data be transmitted to the register. The mask data, the control data and the original data comprise bit positions with the same data width.

5. The control logic circuit of claim 1, wherein, The CBUS is a unidirectional bus used only for writing data into the register.

6. The control logic circuit of claim 1, wherein, The microprocessor comprises at least one.

7. The control logic circuit of claim 1, wherein, The application relates to a memory and a control method thereof.

8. A memory, comprising: The memory comprises a memory array and a peripheral circuit coupled with the memory array and used for controlling the memory array, wherein; the peripheral circuit comprises the control logic circuit in any one of claims 1 to 7. The application relates to a memory and a control method thereof.

9. A storage system, characterized by, The memory comprises one or more memories as claimed in claim 8 and a memory controller coupled with the memories; The memory controller is used for sending various operation commands to the memories.

10. The memory system according to claim 9, wherein the memory system is a solid state drive (SSD) or a memory card. The application is applied to the memory comprising a control logic circuit; the control logic circuit comprises a microprocessor and a control bus CBUS; the microprocessor is connected with a setting circuit in the peripheral circuit of the memory through the CBUS; 11. A method of operating a memory, comprising: The setting circuit comprises a register; the operation method comprises: The microprocessor transmits a mask control signal through a mask control line of the CBUS; When the mask control signal is valid, the microprocessor controls data transmission lines of the CBUS to transmit mask data; before or after the mask data is transmitted, the microprocessor controls the data transmission lines of the CBUS to transmit control data; the mask data and the control data are used in common to change data bits that need to be changed in original data stored in the register. The operation method further comprises:

12. The method of claim 11, wherein, Firstly, a first logical operation is performed on the mask data and the original data to obtain an intermediate operation result; Secondly, a second logical operation is performed on the intermediate operation result and the control data to obtain a target operation result; ​ The target operation result is stored in the register in the original order to change the data bit of the original data stored in the register.

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