Semiconductor structure and preparation method thereof

Abstract

The present application relates to a semiconductor structure and a method for preparing the same. The method for preparing the semiconductor structure comprises: providing a substrate; forming an epitaxial layer on the surface of the substrate; forming an initial trench; the initial trench is located in the epitaxial layer; forming a protective dielectric layer; the protective dielectric layer is located at the bottom of the initial trench and the surface of the epitaxial layer away from the substrate, and the top corner and sidewall of the initial trench are exposed; the top corner and sidewall of the initial trench are repaired to obtain a target trench. The method for preparing the semiconductor structure provided by the present application can accurately define the process window for the repair treatment, and can also prevent the bottom of the initial trench and the surface of the epitaxial layer away from the substrate from forming pits during the repair treatment of the initial trench; and the top corner can also be repaired to form a relatively smooth morphology.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a preparation method thereof. Background Art

[0002] A trench metal oxide semiconductor field effect transistor (MOSFET) is a device with a vertical conductive channel. When the trench MOSFET is in the on state, current flows vertically from the drain to the source. Trench MOSFETs have advantages such as low on-resistance, low gate leakage current, and high switching speed. Furthermore, because the conductive channel of a trench MOSFET is vertical, its conductive channel density can be further increased, reducing chip size.

[0003] However, in the fabrication of trench MOSFETs, the morphology and roughness of the channel sidewalls after trench etching remain difficult to control. These morphologies and roughness significantly impact device performance. Furthermore, electric field concentration can easily occur at trench corners, leading to breakdown of the gate oxide layer and consequently device damage. Therefore, improving trench morphology is an urgent issue. Summary of the Invention

[0004] Based on this, the present application provides a semiconductor structure and a method for preparing the same.

[0005] In one aspect, the present application provides a method for preparing a semiconductor structure according to some embodiments, comprising:

[0006] Providing a substrate; an epitaxial layer is formed on the surface of the substrate;

[0007] forming an initial trench; wherein the initial trench is located in the epitaxial layer;

[0008] forming a protective dielectric layer; the protective dielectric layer is located at the bottom of the initial trench and the surface of the epitaxial layer away from the substrate, and exposes the top corner and sidewall of the initial trench;

[0009] The top corner and the sidewall of the initial trench are repaired to obtain a target trench.

[0010] In one embodiment, forming the protective dielectric layer includes:

[0011] forming a protective dielectric material layer; the protective dielectric material layer covers the bottom of the initial trench, the sidewalls of the initial trench, and the surface of the epitaxial layer away from the substrate;

[0012] The protective dielectric material layer is subjected to a wet pretreatment to remove the protective dielectric material layer covering the sidewalls and the top surface of the top corner, and the remaining protective dielectric material layer serves as the protective dielectric layer.

[0013] In one embodiment, before the wet pretreatment of the protective dielectric material layer, the thickness of the protective dielectric material layer located at the bottom of the initial trench and the epitaxial layer away from the substrate surface is greater than the thickness of the protective dielectric material layer located at the sidewall of the initial trench.

[0014] In one embodiment, the wet pretreatment of the protective dielectric material layer is performed using a buffered hydrofluoric acid solution or an aqueous solution of hydrogen fluoride gas.

[0015] In one embodiment, the repairing of the top corner and the sidewall of the initial trench to obtain a target trench includes:

[0016] The top corner and the side wall of the initial groove are periodically repaired multiple times to make the top corner smooth and the surface roughness of the side wall less than a preset roughness value, thereby obtaining the target groove.

[0017] In one embodiment, a single repair process includes:

[0018] growing an oxide layer on the sidewalls of the initial trench;

[0019] The oxide layer is removed by a dry etching process.

[0020] In one embodiment, forming the initial trench includes:

[0021] forming a channel mask layer; the channel mask layer is located on a surface of the epitaxial layer away from the substrate, and the channel mask layer has an opening, and the opening defines a position of the initial trench;

[0022] The epitaxial layer is etched based on the opening to form the initial trench in the epitaxial layer.

[0023] In one embodiment, the forming of the channel mask layer includes:

[0024] forming a channel mask material layer; the channel mask material layer covers the surface of the epitaxial layer away from the substrate;

[0025] forming a patterned mask layer; the patterned mask layer is located on a surface of the channel mask material layer away from the epitaxial layer, and the mask pattern on the patterned mask layer defines the position of the opening;

[0026] The trench mask material layer is etched based on the patterned mask layer to form the opening in the trench mask material layer, and the trench mask material layer is used as the trench mask layer.

[0027] In one embodiment, the epitaxial layer is etched based on the opening using a reactive ion etching process to form the initial trench in the epitaxial layer.

[0028] On the other hand, the present application also provides a semiconductor structure according to some embodiments, wherein the semiconductor structure is prepared using the preparation method provided in any of the aforementioned embodiments.

[0029] The semiconductor structure and the method for manufacturing the same provided in this application have at least the following beneficial effects:

[0030] The method for preparing a semiconductor structure provided by the present application forms a protective dielectric layer before repairing the top corner and sidewalls of the initial trench, thereby accurately defining the process window for the repair process; by forming the protective dielectric layer, it is also possible to prevent pits from appearing on the bottom of the initial trench and the surface of the epitaxial layer away from the substrate during the repair process of the initial trench. After the protective dielectric layer is formed, the top corner of the initial trench is also exposed, so that the top corner can also be repaired, thereby forming a relatively smooth morphology. By repairing the top corner and sidewalls of the initial trench, the top corner of the initial trench can be made smooth, and the roughness of the sidewalls of the initial trench is also improved, obtaining a target trench with good morphology on both the sidewalls and the top corner.

[0031] The semiconductor structure provided in the present application is prepared using the preparation method provided in any of the aforementioned embodiments. Therefore, the technical effects that can be achieved by the aforementioned preparation method can also be achieved by the semiconductor structure, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0033] Figure 1 A flowchart of a method for preparing a semiconductor structure provided in one embodiment of the present application;

[0034] Figure 2 A flowchart of step S300 in the method for preparing a semiconductor structure provided in one embodiment of the present application;

[0035] Figure 3 A flowchart of a repair process in a method for preparing a semiconductor structure provided in one embodiment of the present application;

[0036] Figure 4 A flowchart of step S200 in the method for preparing a semiconductor structure provided in one embodiment of the present application;

[0037] Figure 5 A flowchart of step S210 in the method for preparing a semiconductor structure provided in one embodiment of the present application;

[0038] Figures 6 to 20 Schematic diagram of the cross-sectional structure of the structure obtained in each step of the method for preparing the semiconductor structure provided in some embodiments of the present application; Figure 20 It is also a schematic cross-sectional structural diagram of a semiconductor structure provided in another embodiment of the present application.

[0039] Description of reference numerals:

[0040] 100, substrate; 200, epitaxial layer; 201, initial trench; 202, target trench; 300, channel mask material layer; 301, channel mask layer; 302, opening; 400, photoresist layer; 401, patterned mask layer; 500, protective dielectric material layer; 501, protective dielectric layer; 502, oxide layer. DETAILED DESCRIPTION

[0041] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0043] It should be understood that when an element or layer is referred to as being "on the surface of" another element or layer, it can be directly on the surface of the other element or layer, or intervening elements or layers may be present. It should be understood that the spatially relative terms encompass different orientations of the device in use and operation in addition to the orientations depicted in the figures. Furthermore, the device may be included in alternative orientations (e.g., rotated 90 degrees or at other orientations), and the spatial descriptors used herein should be interpreted accordingly.

[0044] When used herein, the singular forms "a", "an", and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

[0045] While embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes due to, for example, manufacturing techniques. The regions shown in the figures are schematic in nature and their shapes are not intended to represent the actual shapes of regions of a device and are not intended to limit the scope of the invention.

[0046] Semiconductor devices made using silicon carbide substrates not only have ideal gate insulation characteristics, high-speed switching performance, low on-resistance and high stability, but also have very simple drive circuits and good compatibility with existing power electronic device drive circuits (such as silicon power MOSFETs and insulated gate bipolar transistors).

[0047] Two major challenges facing MOSFET devices over the long term are the long-term reliability of the gate oxide layer and channel resistance. High channel resistance leads to high conduction losses, necessitating ongoing research and development to reduce on-resistance. One approach to reducing on-resistance is to increase the carrier mobility in the inversion channel. Another approach is to employ a trench gate structure with trenches dug directly beneath the gate. This trenching approach not only reduces the specific on-resistance but also effectively reduces the size of the unit cell, making trench MOSFETs a promising future trend. However, during the fabrication of trench MOSFETs, the morphology and roughness of the channel sidewalls after trench etching cannot be well controlled. These morphology and roughness significantly impact the device's reverse breakdown, leakage performance, and reliability. During reverse operation, electric field concentration is easily generated at the trench corners. An uneven trench bottom or micro-trenching at the trench corners can easily cause gate oxide dielectric breakdown, leading to device damage. At the same time, the roughness of the trench sidewall also affects the quality of the gate oxide dielectric layer and the channel electron mobility. Therefore, the problem of sidewall channel surface flattening has long been a technical barrier.

[0048] According to some embodiments, the present application provides a method for preparing a semiconductor structure.

[0049] See also Figure 1 In one embodiment, the method for preparing the semiconductor structure may include the following steps:

[0050] S100: providing a substrate; an epitaxial layer is formed on the surface of the substrate;

[0051] S200: forming an initial trench; the initial trench is located in the epitaxial layer;

[0052] S300: forming a protective dielectric layer; the protective dielectric layer is located at the bottom of the initial trench and the surface of the epitaxial layer away from the substrate, and exposes the top corner and sidewall of the initial trench;

[0053] S400: Repairing the top corner and sidewall of the initial trench to obtain a target trench.

[0054] The method for preparing the semiconductor structure provided by the above embodiment forms a protective dielectric layer before repairing the top corner and sidewall of the initial trench, thereby accurately defining the process window for the repair process; by forming the protective dielectric layer, it is also possible to prevent pits from appearing on the bottom of the initial trench and the surface of the epitaxial layer away from the substrate during the repair process of the initial trench. After the protective dielectric layer is formed, the top corner of the initial trench is also exposed, so that the top corner can also be repaired, thereby forming a relatively smooth morphology. By repairing the top corner and sidewall of the initial trench, the top corner of the initial trench can be made smooth, thereby alleviating the problem of electric field concentration caused by the tip of the top corner; at the same time, the roughness of the sidewall of the initial trench is also improved, which is beneficial to the filling process in the subsequent process, and the sidewalls and top corners of the target trench obtained have good morphology.

[0055] In one embodiment, see Figure 2 The step S300 of forming a protective dielectric layer may include the following steps:

[0056] S310: forming a protective dielectric material layer; the protective dielectric material layer covers the bottom of the initial trench, the sidewalls of the initial trench, and the surface of the epitaxial layer away from the substrate;

[0057] S320: performing wet pretreatment on the protective dielectric material layer to remove the protective dielectric material layer covering the sidewalls and the top surface of the top corner, and the remaining protective dielectric material layer serves as the protective dielectric layer.

[0058] Optionally, before wet pretreatment of the protective dielectric material layer in step S320 , the thickness of the protective dielectric material layer at the bottom of the initial trench and the epitaxial layer away from the substrate surface is greater than the thickness of the protective dielectric material layer at the sidewalls of the initial trench.

[0059] Optionally, in step S320 , a buffered hydrofluoric acid solution or an aqueous solution of hydrogen fluoride gas may be used to perform a wet pretreatment on the protective dielectric material layer.

[0060] In one embodiment, in step S400, the top corner and sidewall of the initial trench are repaired to obtain a target trench, which may include the following steps:

[0061] The top corner and sidewall of the initial groove are periodically repaired multiple times to make the top corner smooth and the surface roughness of the sidewall less than a preset roughness value, thereby obtaining a target groove.

[0062] In one embodiment, see Figure 3 In the process of periodically performing multiple repair processes on the top corners and sidewalls of the initial trench, a single repair process may include the following steps:

[0063] S411: growing an oxide layer on the sidewalls of the initial trench;

[0064] S412: removing the oxide layer using a dry etching process.

[0065] In one embodiment, see Figure 4 The initial trench is formed in step S200, which may include the following steps:

[0066] S210: forming a channel mask layer; the channel mask layer is located on a surface of the epitaxial layer away from the substrate, and the channel mask layer has an opening, and the opening defines a position of an initial trench;

[0067] S220: etching the epitaxial layer based on the opening to form an initial trench in the epitaxial layer.

[0068] In one embodiment, see Figure 5 In step S210, forming a channel mask layer may include the following steps:

[0069] S211: forming a channel mask material layer; the channel mask material layer covers the surface of the epitaxial layer away from the substrate;

[0070] S212: forming a patterned mask layer; the patterned mask layer is located on a surface of the channel mask material layer away from the epitaxial layer, and the mask pattern on the patterned mask layer defines the position of the opening;

[0071] S213 : etching the channel mask material layer based on the patterned mask layer to form an opening in the channel mask material layer, and using the channel mask material layer as a channel mask layer.

[0072] Optionally, in step S220 , a reactive ion etching process may be used to etch the epitaxial layer to form an initial trench in the epitaxial layer.

[0073] In order to more clearly illustrate the preparation methods in some of the above embodiments, Figures 6 to 20 Understand some embodiments of the present application.

[0074] In step S100, refer to Figure 6 , providing a substrate 100; an epitaxial layer 200 is formed on the surface of the substrate 100.

[0075] The present application does not specifically limit the material of the substrate 100. As an example, the substrate 100 may include, but is not limited to, any one or more of a silicon (Si) substrate, a sapphire substrate, a glass substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a gallium arsenide (GaAs) substrate.

[0076] In one embodiment, the substrate 100 includes a silicon carbide substrate.

[0077] In step S200, refer to Figures 6 to 12 , forming an initial trench 201; the initial trench 201 is located in the epitaxial layer 200. As an example, step S200 can be specifically expressed as the following steps S210-S220.

[0078] In step S210, refer to Figures 6 to 10 , forming a channel mask layer 301 ; the channel mask layer 301 is located on the surface of the epitaxial layer 200 away from the substrate 100 , and the channel mask layer 301 has an opening 302 , and the opening 302 defines the position of the initial trench 201 .

[0079] In step S220, refer to Figures 10 to 12 , the epitaxial layer 200 is etched based on the opening 302 to form an initial trench 201 in the epitaxial layer 200 .

[0080] As an example, step S210 may be specifically expressed as the following steps S211 to S213.

[0081] In step S211, Figure 6 As shown, a channel mask material layer 300 is formed; the channel mask material layer 300 covers the surface of the epitaxial layer 200 away from the substrate 100 .

[0082] In step S212, Figures 7 and 8 As shown, a patterned mask layer 401 is formed; the patterned mask layer 401 is located on the surface of the channel mask material layer 300 away from the epitaxial layer 200 , and the mask pattern on the patterned mask layer 401 defines the position of the opening 302 .

[0083] In step S213, Figure 9 As shown, the trench mask material layer 300 is etched based on the patterned mask layer 401 to form an opening 302 in the trench mask material layer 300 , and the trench mask material layer 300 serves as the trench mask layer 301 .

[0084] As an example, see Figures 7 and 8 , step S212 can be specifically performed as follows:

[0085] like Figure 7 As shown, a photoresist layer 400 is formed, and the photoresist layer 400 covers the surface of the channel mask material layer 300 away from the epitaxial layer 200; Figure 8 As shown, the photoresist layer 400 is exposed and developed to form a mask pattern, and the photoresist layer 400 with the mask pattern is used as a patterned mask layer 401.

[0086] The present application does not specifically limit the method of etching the epitaxial layer 200 based on the opening 302 in step S220 . As an example, the epitaxial layer 200 may be etched using, but not limited to, reactive ion etching (RIE) to form the initial trench 201 in the epitaxial layer 200 .

[0087] In step S300, refer to Figures 13 and 14 , forming a protective dielectric layer 501; the protective dielectric layer 501 is located at the bottom of the initial trench 201 and the surface of the epitaxial layer 200 away from the substrate 100, and exposes the top corner and sidewall of the initial trench 201.

[0088] As an example, step S300 may be specifically expressed as the following steps S310 to S320.

[0089] In step S310, Figure 13 As shown, a protective dielectric material layer 500 is formed; the protective dielectric material layer 500 covers the bottom of the initial trench 201 , the sidewalls of the initial trench 201 and the surface of the epitaxial layer 200 away from the substrate 100 .

[0090] In step S320, Figure 14 As shown, the protective dielectric material layer 500 is wet pre-treated to remove the protective dielectric material layer 500 covering the sidewalls and the top corner surface, and the remaining protective dielectric material layer 500 is used as the protective dielectric layer 501.

[0091] The method for fabricating a semiconductor structure provided in the above-described embodiment employs a wet pretreatment method to form a protective dielectric layer 501 at the bottom of the initial trench 201 and on the surface of the epitaxial layer 200 away from the substrate 100. By removing the protective dielectric material layer 500 covering the top surface of the top corner, the top corner can also be repaired and made smooth, thereby alleviating the electric field concentration problem caused by the sharp tip of the top corner. Forming the protective dielectric layer 501 can also prevent pits from forming at the bottom of the initial trench 201 and on the surface of the epitaxial layer 200 away from the substrate 100 during the repair process of the initial trench 201.

[0092] As an example, before the protective dielectric material layer 500 is wet pretreated in step S320 , the thickness of the protective dielectric material layer 500 at the bottom of the initial trench 201 and the epitaxial layer 200 away from the surface of the substrate 100 is greater than the thickness of the protective dielectric material layer 500 at the sidewall of the initial trench 201 .

[0093] As an example, in step S320 , the protective dielectric material layer 500 may be wet pretreated using, but not limited to, a buffered hydrofluoric acid solution (BHF) or a hydrogen fluoride gas aqueous solution (DHF).

[0094] In step S400, refer to Figures 15 to 20 , the top corner and sidewall of the initial trench 201 are repaired to obtain the target trench 202.

[0095] As an example, step S400 may be specifically performed as follows:

[0096] The top corner and sidewall of the initial groove 201 are periodically repaired multiple times to make the top corner smooth and the surface roughness of the sidewall less than a preset roughness value, thereby obtaining the target groove 202 .

[0097] As an example, in the process of periodically performing multiple repair processes on the top corner and sidewall of the initial trench 201 , a single repair process may be performed as follows: steps S411 to S412 .

[0098] In step S411 , an oxide layer 502 is grown on the sidewalls of the initial trench 201 .

[0099] In step S412 , the oxide layer 502 is removed by a dry etching process.

[0100] like Figures 15 to 20 As shown, Figures 15 and 16 、 Figures 17 and 18 、 Figures 19 to 20 Three different repair processes are shown.

[0101] In the semiconductor structure fabrication method provided in the above embodiment, each repair step grows a thin oxide layer 502 on the sidewalls of the initial trench 201. The oxide layer 502 is then removed, repairing the rough initial trench 201. Through repeated repair processes, the damage to the sidewalls of the initial trench 201 is gradually completely repaired, ultimately resulting in a target trench 202 with smooth sidewalls and rounded top corners.

[0102] As an example, in steps S411 to S412 , a thermal oxidation process may be used to grow an oxide layer 502 on the sidewalls of the initial trench 201 , and an oxide etching process may be used to remove the oxide layer 502 .

[0103] As an example, in step S412 , a chemical dry etching (CDE) process may be used to remove the oxide layer 502 .

[0104] Please continue reading Figure 20 According to some embodiments, the present application also provides a semiconductor structure, which is prepared using the preparation method provided in any of the aforementioned embodiments.

[0105] The semiconductor structure provided in the above embodiment is prepared by the preparation method provided in any of the above embodiments. Therefore, the technical effects that can be achieved by the above preparation method can also be achieved by the semiconductor structure, which will not be repeated here.

[0106] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of these terms do not necessarily refer to the same embodiment or example.

[0107] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0108] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate; an epitaxial layer is formed on the surface of the substrate; forming an initial groove; The initial trench is located in the epitaxial layer; forming a protective dielectric layer; The protective dielectric layer is located at the bottom of the initial trench and the surface of the epitaxial layer away from the substrate, and exposes the top corner and sidewall of the initial trench; Performing a repair process on the top corner and the sidewall of the initial groove to obtain a target groove; Wherein, forming the protective dielectric layer includes: forming a protective dielectric material layer; the protective dielectric material layer covers the bottom of the initial trench, the sidewalls of the initial trench, and the surface of the epitaxial layer away from the substrate; the thickness of the protective dielectric material layer at the bottom of the initial trench and the surface of the epitaxial layer away from the substrate is greater than the thickness of the protective dielectric material layer at the sidewalls of the initial trench; The protective dielectric material layer is subjected to a wet pretreatment to remove the protective dielectric material layer covering the sidewalls and the top surface of the top corner, and the remaining protective dielectric material layer serves as the protective dielectric layer.

2. The method for preparing a semiconductor structure according to claim 1, wherein: The protective dielectric material layer is subjected to the wet pretreatment using a buffered hydrofluoric acid solution or an aqueous solution of hydrogen fluoride gas.

3. The method for preparing a semiconductor structure according to claim 1, wherein: The repairing process of the top corner and the sidewall of the initial trench to obtain a target trench includes: The top corner and the side wall of the initial groove are periodically repaired multiple times to make the top corner smooth and the surface roughness of the side wall less than a preset roughness value, thereby obtaining the target groove.

4. The method for preparing a semiconductor structure according to claim 3, wherein: The single repair process includes: growing an oxide layer on the sidewalls of the initial trench; The oxide layer is removed by a dry etching process.

5. The method for preparing a semiconductor structure according to claim 1, wherein: The forming of the initial groove comprises: forming a channel mask layer; the channel mask layer is located on a surface of the epitaxial layer away from the substrate, and the channel mask layer has an opening, and the opening defines a position of the initial trench; The epitaxial layer is etched based on the opening to form the initial trench in the epitaxial layer.

6. The method for preparing a semiconductor structure according to claim 5, wherein: The forming of the channel mask layer comprises: forming a channel mask material layer; the channel mask material layer covers the surface of the epitaxial layer away from the substrate; forming a patterned mask layer; the patterned mask layer is located on a surface of the channel mask material layer away from the epitaxial layer, and the mask pattern on the patterned mask layer defines the position of the opening; The trench mask material layer is etched based on the patterned mask layer to form the opening in the trench mask material layer, and the trench mask material layer is used as the trench mask layer.

7. The method for preparing a semiconductor structure according to claim 5, wherein: The epitaxial layer is etched based on the opening by using a reactive ion etching process to form the initial trench in the epitaxial layer.

8. A semiconductor structure, characterized in that The semiconductor structure is prepared by the preparation method according to any one of claims 1 to 7.

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