Method of forming a semiconductor device

Abstract

A method of forming a semiconductor device includes placing a first package component. The first package component includes a first alignment mark and a first pseudo-alignment mark. A second package component is aligned with the first package component. The second package component includes a second alignment mark and a second pseudo-alignment mark. The alignment is using the first alignment mark to position the first package component and using the second alignment mark to position the second package component. The second package component is bonded to the first package component to form a package, wherein the first alignment mark is bonded to the second pseudo-alignment mark.

Description

Technical Field

[0001] Embodiments of this application relate to methods for forming semiconductor devices. Background Technology

[0002] In the fabrication of three-dimensional (3D) integrated circuits, wafers or device dies are stacked together to achieve more functionality. Stacking is typically achieved through bonding. In the bonding process, alignment marks are formed to align the bonding devices with the stacked wafers / dies. Summary of the Invention

[0003] Some embodiments of this application provide a method for forming a semiconductor device, including: placing a first package assembly, wherein the first package assembly includes: a first alignment mark; and a first pseudo-alignment mark; aligning a second package assembly with the first package assembly, wherein the second package assembly includes: a second alignment mark; and a second pseudo-alignment mark, wherein the alignment is performed by using the first alignment mark to position the first package assembly and using the second alignment mark to position the second package assembly; and bonding the second package assembly to the first package assembly to form a package, wherein after bonding, the first alignment mark is bonded to the second pseudo-alignment mark.

[0004] Other embodiments of this application provide a method for forming a semiconductor device, comprising: aligning the first wafer and the second wafer using a first alignment mark in the first wafer and a second alignment mark in the second wafer, wherein the second alignment mark and a pseudo alignment mark in the second wafer are located in the same chip region; and bonding the first wafer to the second wafer by hybrid bonding, wherein, after the bonding, the first alignment mark in the first wafer is bonded to the pseudo alignment mark in the second wafer.

[0005] Further embodiments of this application provide a method for forming a semiconductor device, comprising: retrieving a first alignment mark in a first package assembly, wherein the first package assembly further includes a first pseudo-alignment mark occupying the same chip region as the first alignment mark; retrieving a second alignment mark in a second package assembly, wherein the second package assembly further includes a second pseudo-alignment mark occupying the same chip region as the second alignment mark; aligning the second package assembly with the first package assembly using the first alignment mark and the second alignment mark; and bonding the second package assembly with the first package assembly. Attached Figure Description

[0006] When with attachment Figure 1When reading this invention, the various aspects of it will be best understood from the following detailed description. It should be noted that, in accordance with standard industry practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0007] Figures 1 to 13 and Figure 14A A cross-sectional view is shown of an intermediate stage of aligning and joining the die according to some embodiments.

[0008] Figure 14B A cross-sectional view of a die stack including alignment marks and pseudo-alignment marks according to some embodiments is shown.

[0009] Figure 15 , Figure 16 and Figure 17 A top view showing alignment marks and pseudo-alignment marks of a first-layer encapsulation assembly, a second-layer encapsulation assembly, and a coupled encapsulation assembly according to some embodiments is shown.

[0010] Figure 18 , Figure 19 and Figure 20 A top view showing alignment marks and pseudo-alignment marks of a first-layer encapsulation assembly, a second-layer encapsulation assembly, and a coupled encapsulation assembly according to some embodiments is shown.

[0011] Figure 21 , Figure 22 and Figure 23 A top view showing alignment marks and pseudo-alignment marks of a first-layer encapsulation assembly, a second-layer encapsulation assembly, and a coupled encapsulation assembly according to some embodiments is shown.

[0012] Figure 24 , Figure 25 and Figure 26 A top view showing alignment marks and pseudo-alignment marks of a first-layer encapsulation assembly, a second-layer encapsulation assembly, and a coupled encapsulation assembly according to some embodiments is shown.

[0013] Figure 27 Examples are shown in which the alignment mark and the corresponding pseudo-align mark have different sizes, according to some embodiments.

[0014] Figure 28 An embodiment is shown in which the alignment mark and the corresponding pseudo-alignment mark have the same size, according to some embodiments.

[0015] Figure 29 The process flow for forming die stacks according to some embodiments is shown. Detailed Implementation

[0016] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0017] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0018] A package assembly stack having alignment marks bonded to pseudo-alignment marks is provided, and a method of forming the same. According to some embodiments of the invention, a first alignment mark is formed in a first package assembly and bonded to a first pseudo-alignment mark in a second package assembly. The first pseudo-alignment mark is not used for alignment purposes. Furthermore, a second alignment mark may be formed in the second package assembly and bonded to a second pseudo-alignment mark in the first package assembly. Bond strength is improved by bonding the alignment mark to the pseudo-alignment mark instead of to the dielectric layer. The embodiments discussed herein are intended to provide examples enabling the making or use of the subject matter of the invention, and those skilled in the art will readily understand that modifications can be made while remaining within the intended scope of the different embodiments. Similar reference numerals are used to indicate similar elements throughout the various views and illustrative embodiments. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0019] Figures 1 to 13 and Figure 14A A cross-sectional view is shown illustrating an intermediate stage in the formation of a stack of packaged components including alignment marks and pseudo-alignment marks according to some embodiments of the present invention. The corresponding process is also schematically reflected in... Figure 29 The process flow shown is as follows.

[0020] refer to Figure 1A packaging assembly 20 is provided, which includes dies 20'. The packaging assembly 20 may also include a substrate 22. According to some embodiments, the substrate 22 is a semiconductor substrate, which may be formed of or include a crystalline silicon substrate. The substrate 22 may also be formed of or include other semiconductor materials, such as silicon germanium, carbon-doped silicon, etc. According to some embodiments, the packaging assembly 20 is a device wafer, which includes active devices and / or passive devices. According to an alternative embodiment, the packaging assembly 20 is an interposer wafer, which does not include active and passive devices. According to an alternative embodiment, the packaging assembly 20 is a reconfiguration wafer, which includes discrete dies sealed in a sealant (such as molding compound), and redistribution lines formed to connect to the discrete dies. The packaging assembly 20 is hereinafter referred to as wafer 20, which includes a plurality of dies 20'.

[0021] According to some embodiments, device die 20' includes active circuitry (not shown) comprising active devices, such as transistors (not shown), formed on the top surface of semiconductor substrate 22. According to an alternative embodiment where wafer 20 is an interposer wafer, no active circuitry is present on the top surface of wafer 20. Through-hole vias (sometimes referred to as through-silicon vias (TSVs)) 26 may be formed to extend into substrate 22. When formed in a silicon substrate, TSV 26 is sometimes also referred to as a through-silicon via. Each TSV 26 may be surrounded by an isolation pad (not shown) formed of a dielectric material such as silicon oxide or silicon nitride. The isolation pad isolates the respective TSV 26 from semiconductor substrate 22. The TSV 26 and the isolation pad extend from the top surface of semiconductor substrate 22 to an intermediate layer between the top and bottom surfaces of semiconductor substrate 22.

[0022] An interlayer dielectric (ILD, not shown separately) may be included above the substrate 22, filling the space between the gate stacks of transistors in the integrated circuit device 22. According to some embodiments, the ILD may be formed of phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), silicon oxide, etc. Contact plugs (not shown) are formed in the ILD and serve to electrically connect the integrated circuit device 22 to conductive components thereon. According to some embodiments of the invention, the contact plugs are formed of a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multiple layers thereof. Forming the contact plugs may include forming contact openings in the ILD, filling the contact openings with one or more conductive materials, and performing a planarization process (such as a chemical mechanical polishing (CMP) process or a mechanical polishing process) to make the top surface of the contact plug flush with the top surface of the ILD.

[0023] Interconnect structure 27 is formed over semiconductor substrate 22. Interconnect structure 27 may include ILD, contact plugs, multiple dielectric layers 28, and metal lines / pads 30 and vias 32 formed in dielectric layers 28. Metal lines / pads 30 and vias 32 are electrically connected to TSV 26 and integrated circuit. Dielectric layer 28 may include one or more inter-metal dielectric (IMD) layers. IMD layers may be formed of a low-k dielectric material having a low-k value, such as below about 3.0, or in the range of about 2.5 to about 3.0. The low-k dielectric material may be a carbon-containing low-k dielectric material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc. According to alternative embodiments, dielectric layer 28 is formed of or includes silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, combinations thereof, and / or multiple layers thereof.

[0024] Metal lines / pads 30 are formed in dielectric layer 28. Vias 32 are formed in dielectric layer 28 to interconnect metal lines / pads 30. The metal lines / pads 30 in the topmost IMD 28 are also referred to as top metal lines / pads 30T. According to some embodiments, the top metal lines / pads 30T are metal lines / pads formed in the topmost inorganic low-k dielectric layer of the interconnect structure 27, and the dielectric layer / layer 33 above the top metal lines / pads is a non-low-k dielectric layer, a polymer layer, etc. For example, the non-low-k dielectric layer 33 may include a dielectric layer 33 with a k value greater than 3.9, and may be formed or include undoped silicate glass (USG), silicon oxide, silicon nitride, etc., composite layers of them, and / or combinations thereof. The dielectric layer 33 may also include a polymer layer, which may be formed of or include polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), etc.

[0025] Metal pads 34 may be formed in dielectric layer 33. A first (non-low k) passivation layer may be present directly above the top metal line / pad 30T, and metal pads 34 may extend into the first passivation layer, which contacts the topmost dielectric layer 28 and the top metal line / pad 30T. A second passivation layer may extend along the edge and top surface of metal pads 34. The passivation layer may be formed of silicon oxide, silicon nitride, USG, etc. Metal pads 34 may be formed of aluminum, aluminum-copper, copper, nickel, etc., or may include aluminum, aluminum-copper, copper, nickel, etc. Post-passivated interconnects (PPIs) may or may not be present, formed above and connected to metal pads 34. Dielectric layer 36 is deposited above metal pads 24 as the surface dielectric layer of wafer 20. Dielectric layer 36 may be formed of PBO, polyimide, silicon oxide, silicon nitride, etc., or may include PBO, polyimide, silicon oxide, silicon nitride, etc.

[0026] refer to Figure 2 The wafer 20 is placed on the release film 12, which is further coated on the carrier 10. Figure 29 In the illustrated process flow 200, the corresponding process is shown as process 202. According to some embodiments, the front side of wafer 20, i.e., the side of substrate 22 with active devices and interconnect structures 27, faces carrier 10. According to alternative embodiments, the back side of wafer 20 may alternatively face carrier 10. Carrier 10 is formed of a transparent material, such as a glass carrier, ceramic carrier, etc. Release film 12 may be formed of a photothermal conversion (LTHC) coating material. According to some embodiments of the invention, the LTHC coating material is capable of decomposing under the heat of light / radiation (such as a laser beam), thus releasing carrier 10 from the structure formed thereon. A buffer layer (not shown) may be formed on release film 12, wherein wafer 20 is placed above the buffer layer. According to some embodiments, the buffer layer may be formed of or include a polymer such as polyimide, PBO, BCB, etc. According to alternative embodiments, no buffer layer is formed.

[0027] refer to Figure 3 A back-side grinding process is performed to remove a portion of the substrate 22 until the through-hole 26 is exposed. In such cases... Figure 29 In the process flow 200 shown, the corresponding process is indicated as process 204. Next, similarly... Figure 3 As shown, substrate 22 may be slightly recessed (e.g., by etching) such that the top portion of the through-hole 26 protrudes beyond the back surface of substrate 22. In the case of... Figure 29 In the process flow 200 shown, the corresponding process is indicated as process 206. Next, a dielectric layer 40 is deposited, followed by a planarization process, such as chemical mechanical polishing (CMP) or mechanical polishing, to re-expose the through-hole 26, thereby forming... Figure 4 The structure shown. In, as... Figure 29 In the process flow 200 shown, the corresponding process is shown as process 208. In the resulting structure, through-hole 26 penetrates both the substrate 22 and the dielectric layer 40. According to some embodiments, the dielectric layer 40 is formed of or includes silicon oxide, silicon nitride, silicon carbide, silicon carbide, etc.

[0028] refer to Figure 4 A dielectric layer 42 is deposited. In such a case... Figure 29 In the illustrated process flow 200, the corresponding process is shown as process 210. According to some embodiments, such as... Figure 5As shown, dielectric layer 42 contacts dielectric layer 40 and through-hole 26, with no other dielectric layer or redistribution line (RDL) between them. According to an optional embodiment of the invention, one or more dielectric layers may be present between dielectric layers 40 and 42. One or more RDL layers may also be present in the dielectric layers, these RDLs being electrically connected to the through-hole 26. Dielectric layer 42 may comprise or be formed of a silicon-containing dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon oxycarbonide, silicon oxycarbonitride, etc. In the illustrated example, the subsequently formed bonding pads and alignment marks are formed using a single damascene process. According to an optional embodiment, a dual damascene process is used, and a through-hole is also formed under the subsequently formed bonding pads and connects the subsequently formed bonding pads to the through-hole 26.

[0029] Further reference Figure 4 An opening 44 is formed in the dielectric layer 42. To form the opening 44, photoresist (not shown) and possibly a hard mask (not shown) may be formed over the dielectric layer 42 and patterned to define the pattern of the opening 44. According to some embodiments of the invention, an anisotropic etching process is performed to etch the dielectric layer 42 and form the opening 44. According to some embodiments in which an RDL is not formed over the through-hole 26, the through-hole 26 is exposed to the opening 44. According to an alternative embodiment in which an RDL is formed, the RDL is exposed to the opening 44.

[0030] Figure 5 The formation of bonding pad 48, alignment mark 50-AM, and pseudo-alignment mark 50-DAM is shown. (In...) Figure 29 In the process flow 200 shown, the corresponding process is shown as process 212. The formation process may include depositing a diffusion barrier layer, depositing a conductive material (metallic material) over the diffusion barrier layer, and performing a planarization process to remove excess diffusion barrier layer and conductive material. According to some embodiments of the invention, the diffusion barrier layer is formed of titanium, titanium nitride, tantalum, tantalum nitride, etc. For example, the diffusion barrier layer can be formed using atomic layer deposition (ALD), physical vapor deposition (PVD), etc. For example, the metallic material can be deposited by an electrochemical plating (ECP) process. The metallic material may include copper or copper alloys, tungsten, aluminum, silver, alloys thereof, or other metallic materials that can diffuse in a subsequent annealing process, thereby forming a metal-to-metal direct bond. Thus, bonding pads 48, alignment marks 50-AM, and pseudo-alignment marks 50-DAM are formed in the surface dielectric layer 42. The diffusion barrier layer in each of the bonding pads 48, alignment marks 50-AM, and pseudo-alignment marks 50-DAM may have a basin shape, and the metallic material is located in the basin. For example, as Figure 27 and Figure 28As shown, each of the alignment mark 50-AM and the pseudo-alignment mark 50-DAM includes a diffusion barrier layer 49A and a metal material 49B. In the top view, the diffusion barrier layer may surround the metal material in the corresponding bonding pad 48, alignment mark 50-AM, and pseudo-alignment mark 50-DAM. It should be understood that some bonding pads 48 are not shown to have electrical connections to the corresponding through-holes 26, but these electrical connections are also formed.

[0031] According to some embodiments, alignment mark 50-AM and pseudo alignment mark 50-DAM are electrically floating, and all materials (such as dielectric layers 40 and 42) located below and in contact with alignment mark 50-AM and pseudo alignment mark 50-DAM can be dielectric materials. Furthermore, all materials surrounding and in contact with each alignment mark 50-AM and pseudo alignment mark 50-DAM can be dielectric materials. According to alternative embodiments, some or all of alignment mark 50-AM and pseudo alignment mark 50-DAM can be connected to through-holes for connection to electrical ground, power supply voltage VDD, or signal lines.

[0032] Wafer 20 can be used to perform the bonding processes discussed later at the wafer level, such as wafer-to-wafer bonding. According to an alternative embodiment, a dicing process is performed to cut wafer 20, such that die 20' is divided into discrete dies. The discrete dies 20' are then used to form die-level die stacks. In the subsequent discussion, wafer-to-wafer bonding is used, and die-to-die bonding is also within the scope of this invention. The corresponding wafer 20 or die 20' is also referred to as a package assembly to indicate that the wafer / die is an example, and the invention is also applicable to the bonding of other types of package assemblies such as packages.

[0033] refer to Figure 6 A package assembly 120 is provided. The package assembly 120 may also be a wafer, which may include a die 120'. The package assembly 120 may be a device wafer, an interposer wafer, a reconfiguration wafer, etc. In the following discussion, for example, a device wafer will be used, but this discussion can also be applied to other types of package assemblies. As mentioned above, bonding can also be at the die level, so the package assembly 120' may also be a discrete die.

[0034] According to some embodiments, wafer 120 includes components similar to those already discussed with respect to wafer 20. Similar components in wafer 120 can be identified by adding "100" to the component designation of their corresponding components in wafer 20. For example, wafer 120 may include a substrate 122, through-hole 126, metal line / pad 130, top metal line / pad 130T, via 132, dielectric layers 128 and 133, metal pad 134, surface dielectric layer 142, bonding pad 148, alignment mark 150-AM, and pseudo-alignment mark 150-DAM. Unless otherwise stated, the fabrication processes and materials of components in wafer 120 may be similar to those of their corresponding components in wafer 20, and will not be repeated here. However, it should be understood that the circuitry and structure in wafer 120 may be the same as (except for the alignment mark and pseudo-alignment mark) or different from the circuitry and structure in wafer 20.

[0035] Figure 15 Wafer 120 according to some embodiments is shown (e.g.) Figure 6 An exemplary top view of alignment mark 150-AM and pseudo alignment mark 150-DAM is shown. It should be understood that the patterns of alignment marks and pseudo alignment marks shown throughout the specification are examples, and the alignment marks and pseudo alignment marks may have any suitable arrangement and shape. Alignment mark 150-AM may include one or more components (also referred to as patterns) that interact with forming bonding pad 148 ( Figure 6 Formed in the same forming process as bonding pad 48. The forming process and materials may be similar to those used for bonding pad 48, as described above. Multiple components in alignment mark 150-AM collectively form a pattern recognizable by an aligner, which may be part of a bonding apparatus for bonding wafer 120 to wafer 20. Pseudo alignment mark 150-DAM also includes multiple components that, in conjunction with the forming of bonding pad 148 (… Figure 6 Alignment mark 150-AM and pseudo alignment mark 150-DAM are formed in the same forming process. Throughout the description, when using the terms "alignment mark" or "pseudo alignment mark," depending on the context, it can be collectively referred to as a component, or individual components within a set pattern. It should be understood that although alignment mark 150-AM and pseudo alignment mark 150-DAM are located in the same chip area, the aligner retrieves and identifies the pattern of alignment mark 150-AM, while the pattern of pseudo alignment mark 150-DAM is not retrieved by the aligner. Instead, components in pseudo alignment mark 150-DAM are treated by the aligner as ambient components or background patterns. Therefore, pseudo alignment mark 150-DAM is called a "pseudo" alignment mark because it does not have the function of being used for alignment purposes, even though it can be mixed with alignment mark 150-AM.

[0036] Figure 16 Wafer 20 is shown according to some embodiments. Figure 6 An exemplary top view of alignment mark 50-AM and pseudo alignment mark 50-DAM in the ). Alignment mark 50-AM may also include one or more components that interact with the forming bonding pad 48. Figure 4 and Figure 5 The alignment mark 50-AM is formed in the same fabrication process as the bonding pad 48 and the alignment mark 50-AM. Multiple components in the alignment mark 50-AM collectively form a pattern recognizable by an aligner, which may be part of a bonding assembly. The pseudo-align mark 50-DAM may also include multiple components formed in the same fabrication process as the bonding pad 48 and the alignment mark 50-AM. It should be understood that although the alignment mark 50-AM and the pseudo-align mark 50-DAM are located in the same chip area, the aligner retrieves and recognizes the pattern of the alignment mark 50-AM, while the pattern of the pseudo-align mark 50-DAM is not retrieved by the aligner. Instead, the components of the pseudo-align mark 50-DAM are treated by the aligner as an ambient or background pattern. Therefore, the pseudo-align mark 50-DAM is a "pseudo" alignment mark because it does not have the function of alignment for alignment purposes.

[0037] Refer again Figure 6 The alignment instrument's aligner retrieves and identifies the pattern of alignment marks 50-AM on wafer 20. The alignment instrument's aligner also retrieves and identifies the pattern of alignment marks 150-AM on wafer 120. Given the relative positions of wafers 20 and 120, an alignment process can be performed to align wafer 120 with wafer 20. In such cases... Figure 29 In the process flow 200 shown, the corresponding process is shown as process 214.

[0038] refer to Figure 7 With wafer 120 aligned with wafer 20, a bonding process is performed to bond wafer 120 to wafer 20. In such cases... Figure 29 In the illustrated process flow 200, the corresponding process is shown as process 216. The bonding process can be performed via hybrid bonding. Thus, the surface dielectric layer 142 in wafer 120 is bonded to the surface dielectric layer 42 in wafer 20 via fusion bonding, for example, forming a Si-O-Si bond between surface dielectric layers 142 and 42. Alignment mark 150-AM is bonded to the corresponding pseudo-alignment mark 50-AM via metal-to-metal bonding (wherein the metals diffuse into each other), and pseudo-alignment mark 150-DAM is bonded to alignment mark 50-AM via metal-to-metal bonding (wherein the metals diffuse into each other).

[0039] Figure 17A top view is shown of the alignment mark 50-AM, pseudo-alignment mark 50-DAM, alignment mark 150-AM, and pseudo-alignment mark 150-DAM joined according to some embodiments. Components / patterns in alignment mark 150-AM overlap and join to corresponding components / patterns in pseudo-alignment mark 50-DAM. Components / patterns in pseudo-alignment mark 150-DAM overlap and join to components / patterns in alignment mark 50-AM. According to some embodiments, it is possible that no alignment mark 50-AM overlaps with and joins to alignment mark 150-AM, and it is possible that no alignment mark 150-AM is located below and joins to alignment mark 50-AM. According to an optional embodiment, some (but not all) components / patterns in alignment mark 150-AM overlap with some (but not all) components / patterns in alignment mark 50-AM, while some other components / patterns in alignment mark 150-AM overlap with some components / patterns in pseudo alignment mark 50-AM, and some components / patterns in alignment mark 50-AM are located below some components / patterns in pseudo alignment mark 150-DAM.

[0040] According to some embodiments, alignment mark 150-AM, pseudo alignment mark 150-DAM, alignment mark 50-AM, and pseudo alignment mark 50-DAM are electrically floating (when the corresponding final package is used and powered on). According to alternative embodiments, some or all of alignment mark 150-AM, pseudo alignment mark 50-DAM, alignment mark 150-AM, and pseudo alignment mark 150-DAM may be connected in any combination to electrical ground, power supply voltage VDD, and / or signal lines, while the remainder (if any) are electrically floating.

[0041] refer to Figure 8 A back-side polishing process is performed on the back side of substrate 122 to expose through-hole 126. In such a way... Figure 29 In the process flow 200 shown, the corresponding process is shown as process 218. Next, the substrate 122 is slightly recessed (e.g., by etching) so that the top portion of the through-hole 126 protrudes beyond the back side of the substrate 122. Next, a dielectric layer 140' is deposited, followed by a planarization process, such as a CMP process or a mechanical polishing process, to re-expose the through-hole 26.

[0042] refer to Figure 9One or more dielectric layers 142' are deposited. Additional dielectric layers and RDLs (not shown) may or may not be formed between dielectric layers 142' and substrate 122. A patterning process is then performed to form openings 144 in the dielectric layers 142'. In subsequent processes, such as... Figure 10 As shown, pseudo-alignment mark 150-DAM' and alignment mark 150-AM' are formed. In... Figure 29 In the process flow 200 shown, the corresponding process is shown as process 220. The structure, materials, and forming process are substantially the same as those of the pseudo-alignment mark 50-DAM' and alignment mark 150-AM'.

[0043] Figure 11 This illustrates, according to some embodiments, stacking additional wafers (if any) on top of wafer 120 until the top wafer is joined. In such... Figure 29 In the illustrated process flow 200, the corresponding process is shown as process 222. According to an optional embodiment, no additional wafers (or dies) are bonded above wafer 120 (or die 120'). The bonding process can be performed using alignment marks, which are bonded to pseudo-alignment marks, similar to the bonding of the wafers / dies below. The top wafers are identified as 20-n, where n is 2 or greater, indicating two wafers (wafers 20 and 120, where n equals 2) or up to n wafers stacked together.

[0044] In the previously shown bonding of wafer 120 and wafer 20, a face-to-back bonding is illustrated, but any bonding of a wafer to the underlying wafer can also be a face-to-face bonding or a back-to-back bonding. For example, Figure 11 The back side of wafer 20-n is shown as the wafer stack (chip stack) with the back side facing down. Therefore, the corresponding bonding will be either back-to-back bonding or back-to-back bonding, depending on the orientation of the wafer / die directly below.

[0045] Figure 11 The formation of an under-bump metal layer (UBM) 52-n is also illustrated. Each UMB 52-n may include a barrier layer (such as a titanium layer) and a metal layer (including copper, aluminum, nickel, palladium, etc.) above the titanium layer. The formation process may include etching the surface dielectric layer of the top wafer 20-n to form an opening, and, for example, depositing the barrier layer and the metal layer using PVD. The deposited titanium and copper layers are patterned to form the UBM 52-n as shown.

[0046] Figure 12 The diagram illustrates the formation of electrical connectors 54-n, each of which may be formed or comprise metal pillars (such as copper pillars), solder areas, or solder layers on metal pillars and copper pillars. Figure 29In the illustrated process flow 200, the corresponding process is shown as process 224. The formation process may include placing solder balls on UBM 52-n and then performing a reflow process to reflow the solder balls. Optionally, the formation of UBM 52-n and electrical connector 54-n may include depositing a metal seed layer, forming a patterned plating mask over the metal seed layer, plating the electrical connector 54-n in openings in the plating mask, removing the plating mask, and etching the metal seed layer. Throughout the description, the stacked wafers are collectively referred to as wafer stack 60.

[0047] In subsequent processes, the wafer stack 60 is debonded from the carrier 10. (As in...) Figure 29 In the process flow 200 shown, the corresponding process is indicated as process 226. For example, a laser beam can be projected onto the release membrane 12, causing the release membrane 12 to decompose, thereby releasing the wafer stack 60. In subsequent processes, the wafer stack 60 can be flipped over and placed on another carrier (not shown) or tape 62, which is fixed to the frame 64, as shown. Figure 13 As shown. Electrical connections 66 can then be formed on the front side of wafer 20. In such a way... Figure 29 In the illustrated process flow 200, the corresponding process is shown as process 228. Electrical connector 66 may include a solder area. According to an optional embodiment, electrical connector 66 is used when bonding wafer 20 (e.g., ...) Figure 2 (As shown) is formed before being placed on carrier 10. According to some embodiments where wafer-level bonding is performed, a dicing process can be performed to cut the wafer stack 60 along scribing line 67. The die stack 60 is diced into discrete packages 60'. Figure 29 In the process flow 200 shown, the corresponding process is shown as process 230.

[0048] Figure 14A An example is shown in which package 60' is bonded to package assembly 68, which may be another package, interposer, package substrate, printed circuit board, etc. Underfill 70 may be dispensed into the gap between package 60' and package assembly 68. This forms package 72. Package 60' may also be bonded to the package assembly above it (not shown) via electrical connector 66.

[0049] Figure 14B , Figure 18 , Figure 19 and Figure 20 The package 72 is shown in combination according to an optional embodiment. Figure 14BA cross-sectional view of package 72 is shown. Alignment marks 50-AM are formed on the surface of wafer 20 and in surface dielectric layer 42. The formation process is substantially the same as that described in the previous embodiments. Pseudo-alignment marks 150-DAM are formed on the surface of wafer 120 and in surface dielectric layer 142. Components in pseudo-alignment marks 150-DAM overlap and are bonded to components in pseudo-alignment marks 50-DAM in a one-to-one correspondence. During the alignment of wafers 120 and 20, alignment marks 50-DAM are retrieved by an aligner and used for the alignment and positioning of wafer 20. Pseudo-alignment marks 50-DAM and alignment marks 150-AM may be formed in or not formed in wafers 20 and 120, respectively.

[0050] On the other hand, alignment and positioning of wafer 120 are not performed using pseudo-alignment mark 150-DAM. Instead, alignment is performed using embedded alignment marks embedded inside wafer 120, rather than on the surface of wafer 120. An exemplary embedded alignment mark is 130T-AM. Alignment mark 130T-AM is also... Figure 14A The embedded alignment mark (130T-AM in the illustrated embodiment) is shown using dashed lines to indicate whether it may or may not be formed. According to some embodiments, the embedded alignment mark 130T-AM may be in the top metal layer (the same metal layer as the top metal line / pad 130T). The embedded alignment mark 130T-AM is formed in the same process as the metal line / pad 130 in the top metal layer used to form wafer 120. To make the embedded alignment mark 130T-AM visible in the alignment process, the upper dielectric layer in wafer 120 covering the embedded alignment mark 130T-AM is transparent. The upper dielectric layer may include a surface layer 142 and a dielectric layer between the surface layer 142 and the embedded alignment mark. According to alternative embodiments, the embedded alignment mark may be in another layer between the top metal layer 130 and the surface layer 142. For example, the embedded alignment mark may be in the layer of the metal pad 34. Optionally, embedded alignment marks may be formed in a dielectric layer in which PPIs (if present) are formed, the dielectric layer being located between the metal pad 34 and the surface layer 142.

[0051] Figure 18A top view of a pseudo-alignment mark 150-DAM and an embedded alignment mark 130T-AM in a wafer 120 according to some embodiments is shown. In the illustrated example, the pseudo-alignment mark 150-DAM includes circular components, and these components can be arranged to align with characters (such as "Z" in the illustrated example). The embedded alignment mark 130T-AM can form a ring. In the top or bottom view of the wafer 120, this ring surrounds the pseudo-alignment mark 150-DAM. It should also be understood that the patterns and shapes of the alignment marks and pseudo-alignment marks shown throughout the description are examples, and these marks can have any suitable arrangement and shape that can be recognized by an aligner. For example, in the top view, the embedded alignment mark 130T-AM may be next to the pseudo-alignment mark 150-DAM, or may have other patterns / shapes, such as different characters, stripes, rectangular shapes, hexagonal shapes, etc.

[0052] Figure 19 A top view is shown of alignment mark 50-AM in wafer 20 according to some embodiments. Components in alignment mark 50-AM may have the same arrangement as pseudo alignment mark 150-DAM (e.g., aligned with characters). Figure 20 This is a top view showing the (pseudo) alignment marks after wafer 120 is bonded to wafer 20. Components in pseudo alignment marks 150-DAM can be bonded one-to-one with corresponding components in alignment marks 50-AM. On the other hand, since alignment marks 130T-AM are embedded and spaced from wafer 20 by surface dielectric layer 142, alignment marks 130T-AM are not bonded to any pseudo alignment marks on wafer 20.

[0053] According to some embodiments, as described above, embedded alignment marks (such as 130T-AM) are formed in wafer 120, and there are no alignment marks (such as 150-AM) on the surface of wafer 120. Therefore, the positioning of wafer 120 and the alignment of wafer 120 with wafer 20 are based on the embedded alignment marks (such as 130T-AM) in wafer 120, rather than on the alignment marks on the surface of wafer 120. According to an alternative embodiment, both alignment mark 150-AM and embedded alignment mark 130T-AM are formed in wafer 120, and both alignment mark 50-AM and pseudo-alignment mark 50-DAM are formed in wafer 20. Therefore, the positioning of wafer 120 and the alignment of wafer 120 with wafer 20 are based on both alignment mark 150-AM and embedded alignment mark 130T-AM in wafer 120. Therefore, in Figure 14B In the diagram, pseudo-alignment mark 150-DAM and alignment mark 50-DAM are shown as dashed lines to indicate whether these components can be formed or not.

[0054] Figure 21 , Figure 22 and Figure 23 Alignment marks and pseudo-alignment marks are shown according to an optional embodiment. A cross-sectional view corresponding to the (pseudo)alignment marks can also be provided. Figure 14B express, Figure 14B The embedded alignment mark 130T-AM, pseudo alignment mark 150-DAM, and alignment mark 50-AM are shown. (Reference) Figure 21 The embedded alignment mark 130T-AM includes multiple elongated strips, and the pseudo alignment mark 150-DAM includes multiple circular parts aligned with multiple straight lines. Figure 22 Alignment mark 50-AM is shown, which includes multiple circular patterns aligned with multiple straight lines. Figure 23 This is a top view showing the (pseudo) alignment marks after wafer 120 has been bonded to wafer 20. The upper alignment mark 50-AM is... Figure 23 The 150-DAM is drawn as transparent to show the pseudo-alignment mark 150 below, but is not limited to transparent material. Components in the pseudo-alignment mark 150-DAM are bonded one-to-one with corresponding components in the alignment mark 50-AM. On the other hand, the alignment mark 130T-AM is not bonded to any pseudo-alignment mark on wafer 20.

[0055] Figure 24 , Figure 25 and Figure 26 Alignment marks and pseudo-alignment marks are shown according to an optional embodiment. A cross-sectional view corresponding to the (pseudo)alignment marks can also be provided. Figure 14B express, Figure 14B The embedded alignment mark 130T-AM, pseudo alignment mark 150-DAM, and alignment mark 50-AM are shown. (Reference) Figure 24 The embedded alignment mark 130T-AM comprises multiple elongated strips, while the pseudo alignment mark 150-DAM comprises multiple circular patterns arranged in an array. The array arrangement of patterns in the pseudo alignment mark 150-DAM allows for a more uniform pattern density, thereby enabling the formation of larger alignment marks without compromising the pattern loading effect.

[0056] According to some embodiments, the embedded alignment mark 130T-AM may overlap (or partially overlap depending on the viewing direction) some patterns in the pseudo alignment mark 150-DAM. According to an alternative embodiment, the embedded alignment mark 130T-AM may overlap all patterns in the pseudo alignment mark 150-DAM. Figure 25 Alignment mark 50-AM is shown, which includes a plurality of circular patterns also forming an array. According to some embodiments, such as... Figure 24 and Figure 25As shown, the array of pseudo-alignment marks 150-DAM (and the array of alignment marks 50-AM) has a non-uniform spacing and includes subarrays with uniform spacing. According to an optional embodiment, all alignment marks 50-AM and pseudo-alignment marks 50-DAM may have uniform spacing. Figure 26 This is a top view showing the (pseudo) alignment marks after wafer 120 has been bonded to wafer 20. The upper alignment mark 50-AM is... Figure 26 The 150-DAM is drawn as transparent to show the pseudo-alignment mark 150 below, but is not limited to transparent material. Components in the pseudo-alignment mark 150-DAM are bonded one-to-one with corresponding components in the alignment mark 50-AM. On the other hand, the alignment mark 130T-AM is not bonded to any pseudo-alignment mark on wafer 20.

[0057] Refer again Figures 15 to 26 It was observed that pseudo-alignment marks and alignment marks can have rectangular outlines. The outline of an alignment mark is a rectangle drawn aligned with the edges of the alignment mark. For example, as... Figure 21 As shown, alignment mark 130T-AM has profile 174-AM, and pseudo alignment mark 150-DAM has profile 174-DAM. Figure 22 As shown, alignment mark 50-AM has contour 74-AM. (As...) Figure 23 As shown, contours 174-AM, 174-DAM, and 74-AM have overlapping areas and occupy the same chip area of ​​package 72. Figure 14B The overlap of the contour regions can be partial, wherein the portion of the first contour region occupied by the pseudo-alignment mark partially overlaps the portion of the second contour region occupied by the alignment mark. However, at least a portion of the first or second contour regions will not overlap each other in a partially overlapping manner. Alternatively, the overlap can be complete, wherein the first and second contour regions occupy exactly the same chip area of ​​the package 72. Figure 14B ).

[0058] In addition, such as Figures 15 to 26 As shown, in the top view of wafers 20 and / or 120, the patterns of the pseudo-alignment marks and the corresponding alignment marks can be mixed together. For example, at least one component of the pseudo-alignment mark 50-DAM (or 150-DAM) can be inserted between the components of the corresponding alignment mark 50-AM (or 150-DAM). Furthermore, at least one component of the alignment mark 50-AM (or 150-AM) can be inserted between the components of the corresponding pseudo-alignment mark 50-DAM (or 150-DAM).

[0059] Figure 27An embodiment is shown in which the dimensions of alignment marks and / or pseudo-alignment marks in wafer 120 differ from those in wafer 20. For example, in the illustrated embodiment, alignment mark 150-AM and pseudo-alignment mark 150-DAM in wafer 120 are smaller (in lateral dimensions) than their corresponding pseudo-alignment marks 50-DAM and alignment mark 50-AM in wafer 20. This also... Figure 17 The example embodiments shown are illustrated. According to... Figure 28 In the alternative embodiment shown, the size of the alignment marks and / or pseudo-alignment marks in wafer 120 is the same as or larger than the size of the alignment marks and / or pseudo-alignment marks in wafer 20.

[0060] In the embodiments shown above, some processes and components are discussed according to some embodiments of the present invention to form a three-dimensional (3D) package. Other components and processes may also be included. For example, test structures may be included to assist in the verification testing of the 3D package or 3DIC device. Test structures may include, for example, test pads formed in a redistribution layer or on a substrate, which allow testing of the 3D package or 3DIC, using probes and / or probe cards, etc. Verification testing can be performed on intermediate structures as well as the final structure. Furthermore, the structures and methods disclosed herein can be used in conjunction with test methods that combine intermediate verification with known good dies to increase yield and reduce costs.

[0061] The embodiments of the present invention have several advantageous features. By forming pseudo-alignment marks together with alignment marks, the pseudo-alignment marks of one wafer, although not used for alignment, can form a metal-to-metal bond with the alignment marks of another wafer. Therefore, the non-bonding problem that occurs when using conventional alignment marks for bonding is avoided, and the bonding quality of hybrid bonding is improved.

[0062] In some embodiments of the present invention, the method includes: placing a first encapsulation assembly, wherein the first encapsulation assembly includes: a first alignment mark; and a first pseudo-alignment mark; aligning a second encapsulation assembly with the first encapsulation assembly, wherein the second encapsulation assembly includes: a second alignment mark; and a second pseudo-alignment mark, wherein the alignment is performed by using the first alignment mark to position the first encapsulation assembly and using the second alignment mark to position the second encapsulation assembly; and engaging the second encapsulation assembly to the first encapsulation assembly to form an encapsulation, wherein, after engagement, the first alignment mark is engaged to the second pseudo-alignment mark. In an embodiment, the first alignment mark includes a first plurality of discrete components, the second pseudo-alignment mark includes a second plurality of discrete components, and wherein the first plurality of discrete components are engaged one-to-one with the second plurality of discrete components. In an embodiment, after engagement, the second alignment mark is engaged to the first pseudo-alignment mark. In an embodiment, the first alignment mark includes a first plurality of discrete components, the first pseudo-alignment mark includes a second plurality of discrete components, and wherein the first plurality of discrete components and the second plurality of discrete components are mixed together. In one embodiment, a first surface dielectric layer in the first package assembly is bonded to a second surface dielectric layer in the second package assembly by fusion bonding, and the first alignment mark is bonded to the second pseudo-alignment mark by metal-to-metal direct bonding. In another embodiment, the second alignment mark is an embedded alignment mark, and after bonding, the second alignment mark is physically spaced apart from the first package assembly. In another embodiment, bonding the second package assembly to the first package assembly includes bonding a second wafer to the first wafer. In another embodiment, the first alignment mark has a first outer contour, and the first pseudo-alignment mark has a second outer contour, wherein the first outer contour at least partially overlaps with the second outer contour. In another embodiment, the first alignment mark includes a first plurality of discrete components, the second pseudo-alignment mark includes a second plurality of discrete components, and each of the first plurality of discrete components is smaller than a corresponding one of the second plurality of discrete components. In yet another embodiment, the first alignment mark includes a first plurality of discrete components, the second pseudo-alignment mark includes a second plurality of discrete components, and each of the first plurality of discrete components has the same size as a corresponding one of the second plurality of discrete components and completely overlaps with a corresponding one of the second plurality of discrete components.

[0063] According to some embodiments of the present invention, the method includes: aligning a first wafer with a second wafer using a first alignment mark in a first wafer and a second alignment mark in a second wafer, wherein the second alignment mark and a pseudo-alignment mark in the second wafer are located in the same chip region; and bonding the first wafer to the second wafer by hybrid bonding, wherein, after bonding, the first alignment mark in the first wafer is bonded to the pseudo-alignment mark in the second wafer. In an embodiment, after bonding, the second alignment mark in the second wafer is bonded to an additional pseudo-alignment mark in the first wafer. In an embodiment, the second alignment mark in the second wafer is embedded in the second wafer, and after bonding, the second alignment mark is separated from the first wafer by a dielectric layer in the second wafer. In an embodiment, the second alignment mark includes a ring, and in a top view of the second wafer and the first wafer, the ring surrounds the second pseudo-alignment mark and the first alignment mark. In an embodiment, the first alignment mark and the pseudo-alignment mark include circular patterns.

[0064] According to some embodiments of the present invention, the method includes: retrieving a first alignment mark in a first package assembly, wherein the first package assembly further includes a first pseudo-alignment mark occupying the same chip region as the first alignment mark; retrieving a second alignment mark in a second package assembly, wherein the second package assembly further includes a second pseudo-alignment mark occupying the same chip region as the second alignment mark; aligning the second package assembly with the first package assembly using the first alignment mark and the second alignment mark; and bonding the second package assembly with the first package assembly. In an embodiment, the first pseudo-alignment mark is not retrieved during the retrieval of the first alignment mark. In an embodiment, after bonding, the first alignment mark is bonded to the second pseudo-alignment mark, and the second alignment mark is bonded to the first pseudo-alignment mark. In an embodiment, a plurality of first discrete patterns in the first alignment mark are bonded one-to-one to a plurality of second discrete patterns in the second pseudo-alignment mark. In an embodiment, a plurality of third discrete patterns in the second alignment mark are bonded one-to-one to a plurality of fourth discrete patterns in the first pseudo-alignment mark.

[0065] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. A method for forming a semiconductor device, comprising: Place a first encapsulation component, wherein the first encapsulation component includes: a first alignment mark; and a first pseudo alignment mark; Aligning the second encapsulation component with the first encapsulation component, wherein the second encapsulation component includes: a second alignment mark; and a second pseudo-alignment mark, wherein the alignment is performed by using the first alignment mark to position the first encapsulation component and using the second alignment mark to position the second encapsulation component; and The second packaging component is bonded to the first packaging component to form a package, wherein, during the bonding process, the first alignment mark is bonded to the second pseudo-alignment mark by metal-to-metal direct bonding. Wherein, the first alignment mark includes a first plurality of discrete components, the first pseudo alignment mark includes a second plurality of discrete components, and wherein the first plurality of discrete components and the second plurality of discrete components are mixed together.

2. The method according to claim 1, wherein, The first alignment mark includes a first plurality of discrete components, the second pseudo alignment mark includes a third plurality of discrete components, and wherein the first plurality of discrete components are coupled to the third plurality of discrete components in a one-to-one correspondence.

3. The method according to claim 1, wherein, During the engagement process of the second packaging component to the first packaging component, the second alignment mark is engaged to the first pseudo alignment mark.

4. The method according to claim 1, wherein, The second pseudo-alignment mark consists of multiple circular patterns arranged in an array.

5. The method according to claim 1, wherein, The first surface dielectric layer in the first packaging assembly is bonded to the second surface dielectric layer in the second packaging assembly by fusion bonding.

6. The method according to claim 1, wherein, The second alignment mark is an embedded alignment mark, and during the engagement of the second packaging component to the first packaging component, the second alignment mark is physically spaced apart from the first packaging component.

7. The method according to claim 1, wherein, The step of bonding the second packaging component to the first packaging component includes bonding the second wafer to the first wafer.

8. The method according to claim 1, wherein, The first alignment mark has a first outer contour, and the first pseudo alignment mark has a second outer contour, wherein the first outer contour at least partially overlaps with the second outer contour.

9. The method according to claim 1, wherein, The first alignment mark includes a first plurality of discrete components, the second pseudo-alignment mark includes a third plurality of discrete components, and wherein the size of each of the first plurality of discrete components is smaller than the size of a corresponding one of the third plurality of discrete components.

10. The method according to claim 1, wherein, The first alignment mark includes a first plurality of discrete components, the second pseudo-alignment mark includes a third plurality of discrete components, and wherein each of the first plurality of discrete components has the same size as a corresponding one of the third plurality of discrete components and completely overlaps with a corresponding one of the third plurality of discrete components.

11. A method of forming a semiconductor device, comprising: The first wafer and the second wafer are aligned using a first alignment mark in the first wafer and a second alignment mark in the second wafer, wherein the second alignment mark and a pseudo alignment mark in the second wafer are located in the same chip region; and The first wafer is bonded to the second wafer by hybrid bonding, wherein, during the bonding process, the first alignment mark in the first wafer is bonded to the pseudo alignment mark in the second wafer by metal-to-metal direct bonding, and the second alignment mark in the second wafer is bonded to an additional pseudo alignment mark in the first wafer.

12. The method according to claim 11, wherein, The pseudo-alignment markers consist of multiple circular patterns arranged in an array.

13. The method according to claim 11, wherein, The second alignment mark is embedded in the second wafer, and during the bonding process from the first wafer to the second wafer, the second alignment mark is separated from the first wafer through the dielectric layer in the second wafer.

14. The method according to claim 13, wherein, The second alignment mark includes a ring, and in a top view of the second wafer and the first wafer, the ring surrounds the pseudo alignment mark and the first alignment mark.

15. The method according to claim 11, wherein, The first alignment mark and the pseudo alignment mark both comprise circular patterns.

16. A method of forming a semiconductor device, comprising: A first alignment mark is retrieved in a first packaging component, wherein the first packaging component further includes a first pseudo alignment mark occupying the same chip area as the first alignment mark; A second alignment mark is retrieved in a second packaging assembly, wherein the second packaging assembly further includes a second pseudo alignment mark occupying the same chip area as the second alignment mark; Align the second package component with the first package component using the first alignment mark and the second alignment mark; and The second packaging component is joined to the first packaging component. During the joining process, the first alignment mark is joined to the second pseudo alignment mark by metal-to-metal direct joining, and the second alignment mark is joined to the first pseudo alignment mark.

17. The method according to claim 16, wherein, During the retrieval of the first alignment mark, the first pseudo alignment mark was not retrieved.

18. The method according to claim 16, wherein, The second pseudo-alignment mark comprises a plurality of circular patterns arranged in an array.

19. The method of claim 16, wherein, The plurality of first discrete patterns in the first alignment mark are joined one-to-one with the plurality of second discrete patterns in the second pseudo alignment mark.

20. The method according to claim 19, wherein, The plurality of third discrete patterns in the second alignment mark are joined one-to-one with the plurality of fourth discrete patterns in the first pseudo alignment mark.

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