A heterogeneous interconnected Internet of Things impedance measurement chip

Abstract

The present invention discloses a heterogeneous interconnected Internet of Things impedance measurement chip, which relates to the field of impedance measurement chips and includes: a functional module and a heterogeneous interconnection structure. The functional module includes: an Internet of Things chip module, a communication interface, a sensor module, a power management module, a microprocessor module, a memory module, a digital signal processing module, and a signal conditioning link module. The functional modules are integrated on the heterogeneous interconnection structure and are interconnected by circuits. The microprocessor module is electrically connected to the memory module, the digital signal processing module, the communication interface, the sensor module, the signal conditioning link module, and the Internet of Things chip. The digital signal processing module is electrically connected to the communication interface and the signal conditioning link module. The power management module provides power network support for each functional module. The present invention improves the integration of circuits on the chip, enriches the functions of the chips within a single package, reduces the design cost of the peripheral circuits, and improves the efficiency of interconnected communication through the Internet of Things.

Description

Technical Field

[0001] The present invention relates to the technical field of impedance measurement chips, and in particular to a heterogeneous interconnected Internet of Things impedance measurement chip. Background Art

[0002] In the development of integrated circuit technology in recent years, very large scale integrated circuits have achieved a doubling of chip performance and a reduction in power consumption through the improvement of manufacturing processes. At the same time, the scale of microfabrication technology is constantly approaching the limit of the physical line width. When it becomes increasingly difficult to increase according to Moore's law under traditional CMOS processes, a development route beyond Moore's law has emerged by introducing new device types, new packaging structures, and new composite materials to achieve higher density circuit integration. By integrating different functional modules on the same platform, not only can the integration density be increased, the cost of individual functions be reduced, but also the information processing ability of the entire system can be improved. However, how to integrate and be compatible with different processing techniques required for manufacturing modules with different functions on the same chip is a major challenge. In addition to different manufacturing processes, the substrate materials of different functional modules are also different. For example, the manufacturing processes and special materials used in the processing of MEMS sensors are difficult to be well compatible with traditional CMOS processes. In the design of the new generation of integrated circuits, in addition to the in-package interconnection integration in the two-dimensional direction, three-dimensional integration technology is also required to enable the chip modules to achieve multi-functional integration in the vertical direction, so as to improve the performance of the interconnection in the traditional two-dimensional planar integrated circuit, increase the signal transmission speed between modules, reduce the delay, and thus achieve a higher integration density. With the development of the new generation of information technology, the Internet of Things technology extends the Internet through various dedicated chips on the basis of Internet technology, combines various information sensing devices and networks, and realizes efficient interconnection between humans and machines, and between devices and devices. The development of the Internet of Things technology relies on the support of the development of chip technology, and the development of chip technology can also be promoted by its application in the Internet of Things technology. In the field of impedance measurement applications, traditional impedance measurement instruments require higher costs and are not conducive to playing a role in the integration of small systems in the Internet of Things era. General impedance measurement chips only include some structures and still require several peripheral chips to assist in completing functions, which requires more space. If heterogeneous interconnected chips can be used to improve the integration density of the internal circuits of the chips and concentrate circuits with different functions in the same chip, the space occupation can be effectively reduced and the application scenarios of the chips can be broadened.

[0003] The prior art discloses an impedance measurement system, including a connector unit, a forward and reverse unit, a current signal, a sequential logic unit, and an analog-to-digital converter. It is electrically connected to the point to be measured on the circuit board through the connector unit. According to the current control signal sent by the measurement host, it outputs a forward current signal or a negative current signal and transmits it to the connection point of the connector unit, so that the point to be measured on the circuit board generates a relative impedance according to the flowing current signal. According to the conversion signal sent by the measurement host, it converts the impedance read through the connector unit into a digital signal and transmits the converted digital signal to the measurement host, enabling the display unit electrically connected to the measurement host to display the impedance represented by the digital signal. This technical solution can improve the measurement accuracy and thus greatly increase the measurement efficiency. However, this technical solution does not solve the problems of circuit integration and interconnection between devices. Summary of the Invention

[0004] In order to solve the problems of low circuit integration and low interconnection efficiency between devices, the present invention provides a heterogeneous interconnected Internet of Things impedance measurement chip. By integrating different functional modules into a heterogeneous interconnected structure, the integration degree is improved, the cost of single functions is reduced, and information interconnection is realized through Internet of Things technology.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0006] A heterogeneous interconnected Internet of Things impedance measurement chip includes: functional modules and a heterogeneous interconnected structure. The functional modules are as follows: an Internet of Things chip module, a communication interface, a sensor module, a power management module, a microprocessor module, a memory module, a digital signal processing module, and a signal conditioning link module.

[0007] The Internet of Things chip module, the communication interface, the sensor module, the power management module, the microprocessor module, the memory module, the digital signal processing module, and the signal conditioning link module are integrated on the heterogeneous interconnected structure and are interconnected by circuits with each other.

[0008] The Internet of Things chip module is electrically connected to the first port of the microprocessor module.

[0009] The first port of the communication interface is electrically connected to the second port of the microprocessor module.

[0010] The sensor module is electrically connected to the third port of the microprocessor module.

[0011] The first port of the digital signal processing module is electrically connected to the fourth port of the microprocessor module.

[0012] The second port of the digital signal processing module is electrically connected to the second port of the communication interface.

[0013] The described memory module is electrically connected to the fifth port of the microprocessor module;

[0014] The described signal conditioning link module includes an input line and an output line. The input line and the output line are connected to the object under test. The third port of the digital signal processing module is electrically connected to the input line, and the sixth port of the microprocessor module is electrically connected to the output line;

[0015] The described power management module includes a power chip. The power management module provides power network support to each functional module through external power supply.

[0016] The working principle of the present invention is as follows:

[0017] The described signal link module sends the collected information to the digital signal processing module. The digital signal processing module processes the information and then sends it to the microprocessor, and the microprocessor processes the information; The heterogeneous interconnection structure integrates different functional modules, improving the circuit integration on the chip; The Internet of Things chip module realizes the communication between the impedance measurement chip system and the Internet of Things cloud.

[0018] Preferably, the output line is provided with a digital-to-analog converter, a filter link and an operational amplifier circuit; The input line is provided with an analog-to-digital converter, a filter link and an operational amplifier circuit;

[0019] The circuit connection mode of the input line is as follows: The input end of the operational amplifier circuit is electrically connected to the object under test, the input end of the filter link is electrically connected to the output end of the operational amplifier circuit, the input end of the analog-to-digital converter is electrically connected to the output end of the filter link, and the output end of the analog-to-digital converter is electrically connected to the third port of the digital signal processing module;

[0020] The circuit connection mode of the output line is as follows: The input end of the digital-to-analog converter is electrically connected to the sixth port of the microprocessor module, the output end of the digital-to-analog converter is electrically connected to the input end of the filter link, the input end of the operational amplifier circuit is electrically connected to the output end of the filter link, and the output end of the operational amplifier circuit is electrically connected to the object under test; The signal conditioning link module is used for exciting and generating signals for collection.

[0021] Preferably, the Internet of Things chip module includes an Internet of Things communication chip for communicating with the Internet of Things cloud.

[0022] Preferably, the microprocessor module includes an MCU processor and an FPGA chip for data processing.

[0023] Preferably, the communication interface is used for communicating with an external chip; the sensor module is used for measuring the state of the spatio-temporal environment, including time, location, acceleration, etc.; the memory module is used for storing initial state configuration parameters and working data; the digital signal processing module is used for processing digital signal data.

[0024] Preferably, the heterogeneous interconnection structure includes a first substrate layer, a second substrate layer, a bonding layer, a substrate multi-layer interconnection module, and embedded passive devices;

[0025] The embedded passive devices include resistors, capacitors, and inductors; the resistors, capacitors, and inductors are passive devices processed between the first substrate layer and the second substrate layer;

[0026] On the first substrate layer and the second substrate layer, various functional modules, embedded passive devices, and various interconnection lines are provided;

[0027] The bonding layer is between the first substrate layer and the second substrate layer, below the first substrate layer, and above the second substrate layer; it provides circuit interconnection between the first substrate layer and the second substrate layer;

[0028] The substrate multi-layer interconnection module includes two stacking methods: the first stacking method is a multi-layer stacking method with a bonding layer sandwiched between two substrate layers, and multiple stacks of the above three-layer sandwich structure; the second stacking method is when there is no bonding layer back-to-back between the sandwich structures, a wiring channel is etched in the substrate so that the substrates can be wired and connected in the vertical direction;

[0029] The substrate multi-layer interconnection module is provided with various functional modules; the substrate multi-layer interconnection module is arranged above the first substrate layer.

[0030] Furthermore, the materials of different substrate layers are different, and the material of the bonding layer used to connect the substrate layers is also different. The first substrate layer and the second substrate layer are connected through the bonding layer. The material used for the bonding layer is a polysilicon material, and the polysilicon material is a polysilicon material with a surface of a III-V compound thin film.

[0031] Furthermore, when the first substrate layer and the second substrate layer are connected through the bonding layer, first, the circuits on the surfaces of the two substrate layers are each completed, then the bonding layer is combined with any one of the substrate layers, and then the circuit surface of the other substrate layer is combined with the bonding layer, and then electrical connection is formed after processing;

[0032] The electrical connection between the bonding layer and the first and second substrate layers is achieved by processing connection channels on the bonding layer and filling them with metal materials to form bonding layer interconnections. The functional modules of the first substrate layer and the second substrate layer are electrically connected through the bonding layer interconnections.

[0033] Furthermore, the resistors in the embedded passive devices are set according to the heterogeneous resistor device design method, the capacitors are set according to the heterogeneous capacitor device design method, and the inductors are set according to the heterogeneous inductor device design method.

[0034] Even further, in the heterogeneous resistor device design method, the resistor element is composed of at least one metal material, connected between the first substrate layer and the second substrate layer through the bonding layer, and different metal materials and processing structures are used to obtain the required resistance characteristics, which are used as peripheral devices for the functional modules on any substrate layer;

[0035] In the heterogeneous capacitor device design method, the basic capacitor element is composed of at least one metal material and at least one dielectric material, connected between the first substrate layer and the second substrate layer through the bonding layer, and different metal materials, dielectric materials, and processing structures are used to obtain the required capacitance characteristics, which are used as peripheral devices for the functional modules on any substrate layer;

[0036] In the heterogeneous inductor device design method, the basic inductor element is composed of at least one metal material, and a planar inductor structure in the shape of a circle, octagon, or square is processed on either the first substrate layer or the second substrate layer, connected between the first substrate layer and the second substrate layer through the bonding layer, and different metal materials and processing structures are used to obtain the required inductance characteristics, which are used as peripheral devices for the functional modules on any substrate layer.

[0037] Compared with the prior art, the beneficial effects of the present invention are:

[0038] 1. This heterogeneous interconnected Internet of Things impedance measurement chip can more efficiently integrate the impedance measurement circuit, realizing relatively rich and complete functions of the impedance measurement system within a single chip, and greatly reducing the design cost of the peripheral circuit compared with the traditional impedance measurement system.

[0039] 2. This heterogeneous interconnected Internet of Things impedance measurement chip can improve efficiency through the high-efficiency computing ability of the cloud in the Internet of Things application and the high-speed interconnection communication method between devices, and expand the applications of impedance measurement in aspects such as human health and industrial detection.

[0040] 3. The described heterogeneous interconnection structure provides a solution for the vertical integration of modules using different substrate materials in integrated circuits, thereby enabling the improvement of the integration degree and performance of a single chip.

[0041] 4. The heterogeneous interconnection structure used in this chip improves the integration of circuit devices in the chip by processing embedded passive devices between substrate layers, enabling the reduction of discrete passive devices used in integrated circuit chips to achieve functions and saving the occupation of the overall structure area and volume in the case of multi-module integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is a schematic circuit connection diagram of the heterogeneous interconnection Internet of Things impedance measurement chip described in the present invention.

[0043] Figure 2 It is a schematic structural diagram of the heterogeneous interconnection structure described in the present invention.

[0044] Figure 3 It is a schematic structural diagram of the design method of the embedded passive device described in the present invention.

[0045] Wherein: 101, Internet of Things chip module; 102, communication interface; 103, sensor module; 104, power management module; 105, microprocessor module; 106, memory module; 107, digital signal processing module; 108, digital-to-analog converter; 109, filter link; 110, operational amplifier circuit; 111, analog-to-digital converter; 201, substrate multi-layer interconnection module; 202, chip of functional modules on the first substrate layer and the second substrate layer; 203, chip of functional modules on the substrate multi-layer interconnection module; 204, first substrate layer; 205, bonding layer; 206, second substrate layer; 301, dielectric; 302, first metal on the first substrate layer; 303, second metal structure; 304, third metal structure; 305, fourth metal on the second substrate layer. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0046] The present invention will be described in detail below with reference to the drawings and specific embodiments.

[0047] Embodiment 1

[0048] As Figure 1 shown, a heterogeneous interconnection Internet of Things impedance measurement chip includes: functional modules and a heterogeneous interconnection structure. The functional modules are as follows: Internet of Things chip module 101, communication interface 102, sensor module 103, power management module 104, microprocessor module 105, memory module 106, digital signal processing module 107, signal conditioning link module;

[0049] The described Internet of Things chip module 101, communication interface 102, sensor module 103, power management module 104, microprocessor module 105, memory module 106, digital signal processing module 107, and signal conditioning link module are integrated on the described heterogeneous interconnection structure and are interconnected by circuits with each other;

[0050] The described Internet of Things chip module 101 is electrically connected to the first port of the described microprocessor module 105;

[0051] The first port of the described communication interface 102 is electrically connected to the second port of the described microprocessor module 105;

[0052] The described sensor module 103 is electrically connected to the third port of the described microprocessor module 105;

[0053] The first port of the described digital signal processing module 107 is electrically connected to the fourth port of the microprocessor module 105;

[0054] The second port of the described digital signal processing module 107 is electrically connected to the second port of the communication interface 102;

[0055] The described memory module 106 is electrically connected to the fifth port of the microprocessor module 105;

[0056] The described signal conditioning link module includes an input line and an output line. The input line and the output line are connected to the object to be measured. The third port of the described digital signal processing module 107 is electrically connected to the input line, and the sixth port of the described microprocessor module 105 is electrically connected to the output line;

[0057] The described power management module 104 includes a power chip. The power management module 104 provides power network support for each functional module of the impedance measurement chip through external power supply.

[0058] The working principle of the present invention is as follows:

[0059] The described signal link module sends the collected information to the digital signal processing module 107. The digital signal processing module 107 processes the information and then sends it to the microprocessor module, and the microprocessor module processes the information; the heterogeneous interconnection structure integrates different functional modules together, improving the circuit integration degree on the chip; the Internet of Things chip module 101 realizes the communication between the impedance measurement chip system and the Internet of Things cloud, and is used for Internet of Things communication, identity recognition, and security encryption.

[0060] In this embodiment, the output line is provided with a digital-to-analog converter 108, a filter link 109, and an operational amplifier circuit 110; the input line is provided with an analog-to-digital converter 111, a filter link 109, and an operational amplifier circuit 110;

[0061] The circuit connection mode of the input line is as follows: the input end of the operational amplifier circuit 110 is electrically connected to the object to be measured, the input end of the filter link 109 is electrically connected to the output end of the operational amplifier circuit 110, the input end of the analog-to-digital converter 111 is electrically connected to the output end of the filter link 109, and the output end of the analog-to-digital converter 111 is electrically connected to the third port of the digital signal processing module 107;

[0062] The circuit connection mode of the output line is as follows: the input end of the digital-to-analog converter 108 is electrically connected to the sixth port of the microprocessor module 105, the output end of the digital-to-analog converter 108 is electrically connected to the input end of the filter link 109, the input end of the operational amplifier circuit 110 is electrically connected to the output end of the filter link 109, and the output end of the operational amplifier circuit 110 is electrically connected to the object to be measured; the signal conditioning link module is used for exciting and generating signals for signal collection.

[0063] The excitation generation of signals and the signal acquisition link can be combined in multiple channels. The circuit for realizing the complete impedance measurement function includes the internal circuit of the chip and the circuit composed of external passive devices. In this embodiment, only the internal circuit of the chip is described.

[0064] In this embodiment, the Internet of Things chip module 101 includes an Internet of Things communication chip for communicating with the Internet of Things cloud.

[0065] In this embodiment, the microprocessor module 105 includes an MCU processor and an FPGA chip for data processing. The communication interface 102 is used for communicating with external chips; the sensor module 103 is used for measuring the state of the time and space environment, including time, location, accelerometer, etc.; the memory module 106 is used for storing initial state configuration parameters and working data, which can be EEPROM or FLASH; the digital signal processing module 107 uses a DSP chip to process digital data.

[0066] Embodiment 2

[0067] In this embodiment, as Figure 2 shown, the heterogeneous interconnection structure includes a first substrate layer 204, a second substrate layer 206, a bonding layer 205, a substrate multi-layer interconnection module 201, and embedded passive devices;

[0068] In this embodiment, it further includes a chip 202 of a functional module disposed on the first substrate layer 204 and the second substrate layer 206, and a chip 203 of a functional module interconnected on the substrate multi-layer interconnection module 201; the chip 202 of the functional module on the first substrate layer 204 and the second substrate layer 206 can be a chip of various functional modules such as a microprocessor, an analog-to-digital converter 111, a power chip, etc., or can be an MCU, an EEPROM, a DAC, a DSP, a power management unit PMU, a MEMS sensor, an Internet of Things chip with functions such as communication encryption and identity recognition, a radio frequency antenna module; the chip 203 of the functional module interconnected on the substrate multi-layer interconnection module 201 can be a chip of various functional modules such as a microprocessor, a digital-to-analog converter, and a power chip.

[0069] The embedded passive devices include resistors, capacitors, and inductors; the resistors, capacitors, and inductors are passive devices processed between the first substrate layer 204 and the second substrate layer 206; the embedded passive devices processed between the substrate layers can be as close as possible to the chip modules on the substrate layers, thereby reducing the resource occupation of the lead-out traces connected to the external SMT discrete passive devices.

[0070] On the first substrate layer 204 and the second substrate layer 206, various functional modules, embedded passive devices, and various interconnection lines are provided.

[0071] The bonding layer 205 is between the first substrate layer 204 and the second substrate layer 206, located below the first substrate layer 204 and above the second substrate layer 206; it provides circuit interconnection between the first substrate layer 204 and the second substrate layer 206.

[0072] The substrate multi-layer interconnection module 201 includes two stacking methods: the first stacking method is a multi-layer stacking method with the bonding layer 205 sandwiched between two substrate layers, and the stacking of multiple such three-layer sandwich structures; the second stacking method is when there is no bonding layer 205 back-to-back between the sandwich structures, a wiring channel is etched in the substrate so that the substrates can be wired and connected in the vertical direction.

[0073] The substrate multi-layer interconnection module 201 is provided with various functional modules; the substrate multi-layer interconnection module 201 is disposed above the first substrate layer 204.

[0074] In this embodiment, the materials of different substrate layers are different, and the materials of the bonding layer 205 used to connect the substrate layers are also different. The first substrate layer 204 and the second substrate layer 206 are connected through the bonding layer 205. The material used for the bonding layer 205 is a polysilicon material, and the polysilicon material is a polysilicon material with a surface of a III-V compound thin film, which simplifies the electrical connection during the integration between different processes and improves the heat dissipation efficiency.

[0075] More specifically, when the first substrate layer 204 and the second substrate layer 206 are connected through the bonding layer 205, first, the circuit processing on the surface of each of the two substrate layers is completed, then the bonding layer 205 is combined with any one of the substrate layers, and then the circuit surface of the other substrate layer is combined with the bonding layer 205, and then an electrical connection is formed after processing.

[0076] The electrical connection between the bonding layer 205 and the first substrate layer 204 and the second substrate layer 206 is formed by processing connection channels on the bonding layer and filling metal materials therein to form bonding layer interconnection lines. The functional modules of the first substrate layer 204 and the functional modules of the second substrate layer 206 are electrically connected through the bonding layer interconnection lines.

[0077] Embodiment 3

[0078] As Figure 3 shown, the resistors in the embedded passive devices are set according to the heterogeneous resistor device design method, the capacitors are set according to the heterogeneous capacitor device design method, and the inductors are set according to the heterogeneous inductor device design method.

[0079] The heterogeneous resistor device design method, the heterogeneous capacitor device design method, and the heterogeneous inductor device design method are all used to plan appropriate interconnect materials and geometric dimensions between substrate layers with different structures in order to achieve more diverse parameter design and higher device density for passive device integration. The materials for processing the three embedded devices consist of the following parts: a dielectric 301, a first metal 302 on the first substrate layer 204, a second metal structure 303, a third metal structure 304, and a fourth metal 305 on the second substrate layer 206.

[0080] The heterogeneous resistor device design method, the resistor element is composed of at least one metal material, which is connected between the first substrate layer 204 and the second substrate layer 206 through the bonding layer 205, and the required resistance characteristics are obtained by using different metal materials and processing structures, and it is used as a peripheral device of the functional module on any substrate layer.

[0081] The described heterogeneous capacitor device design method, the capacitor element is composed of at least one metal material and at least one dielectric material, and is connected between the first substrate layer 204 and the second substrate layer 206 through the bonding layer 205. The required capacitance characteristics are obtained through different metal materials, dielectric materials and processing structures, and it is used as a peripheral device of the functional module on any substrate layer; As Figure 3 The shown capacitance design method processes a parallel plate capacitor structure by using different kinds of metal and dielectric materials between the first substrate layer 204 and the second substrate layer 206. This parallel plate capacitor structure utilizes the two substrate layers, and the pins can return to the same substrate layer or connect the two substrate layers through metal interconnection.

[0082] The described heterogeneous inductor device design method, the inductor element is composed of at least one metal material, and a planar inductor structure in the shape of a circle, octagon, or square is processed on any one of the first substrate layer 204 and the second substrate layer 206, and is connected between the first substrate layer 204 and the second substrate layer 206 through the bonding layer 205. The required inductance characteristics are obtained through different metal materials and processing structures, and it is used as a peripheral device of the functional module on any substrate layer; Since the substrate layers can be connected to each other, Figure 3 the planar inductor shapes shown in can be processed on both substrate layers simultaneously, and then connected, and several patterns can be connected, so as to process the required inductance value by using the material characteristics on different substrate layers.

[0083] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, rather than limiting the implementation manners of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the claims of the present invention.

Claims

1. An impedance measurement chip for an Internet of Things with heterogeneous interconnection, characterized in that Including: A functional module and a heterogeneous interconnection structure. The functional modules are as follows: an Internet of Things chip module (101), a communication interface (102), a sensor module (103), a power management module (104), a microprocessor module (105), a memory module (106), a digital signal processing module (107), and a signal conditioning link module; The Internet of Things chip module (101), the communication interface (102), the sensor module (103), the power management module (104), the microprocessor module (105), the memory module (106), the digital signal processing module (107), and the signal conditioning link module are integrated on the heterogeneous interconnection structure and are interconnected by circuits with each other; The Internet of Things chip module (101) is electrically connected to the first port of the microprocessor module (105); The first port of the communication interface (102) is electrically connected to the second port of the microprocessor module (105); The sensor module (103) is electrically connected to the third port of the microprocessor module (105); The first port of the digital signal processing module (107) is electrically connected to the fourth port of the microprocessor module (105); The second port of the digital signal processing module (107) is electrically connected to the second port of the communication interface (102); The memory module (106) is electrically connected to the fifth port of the microprocessor module (105); The signal conditioning link module includes an input line and an output line. The input line and the output line are connected to the object to be measured. The third port of the digital signal processing module (107) is electrically connected to the input line, and the sixth port of the microprocessor module (105) is electrically connected to the output line; The power management module (104) provides power network support to each functional module through external power supply.

2. The heterogeneous interconnected Internet of Things impedance measurement chip according to claim 1, wherein The output line is provided with a digital-to-analog converter (108), a filter link (109), and an operational amplifier circuit (110); the input line is provided with an analog-to-digital converter (111), a filter link (109), and an operational amplifier circuit (110); The circuit connection mode of the input line is as follows: the input end of the operational amplifier circuit (110) is electrically connected to the object to be measured, the input end of the filter link (109) is electrically connected to the output end of the operational amplifier circuit (110), the input end of the analog-to-digital converter (111) is electrically connected to the output end of the filter link (109), and the output end of the analog-to-digital converter (111) is electrically connected to the third port of the digital signal processing module (107); The circuit connection mode of the output line is as follows: The input end of the digital-to-analog converter (108) is electrically connected to the sixth port of the microprocessor module (105), the output end of the digital-to-analog converter (108) is electrically connected to the input end of the filter link (109), the input end of the operational amplifier circuit (110) is electrically connected to the output end of the filter link (109), and the output end of the operational amplifier circuit (110) is electrically connected to the object to be measured; The signal conditioning link module is used to generate excitation and collect signals.

3. The heterogeneous interconnected Internet of Things impedance measurement chip according to claim 1, characterized in that, The IoT chip module (101) includes an IoT communication chip for communicating with the IoT cloud.

4. The heterogeneous interconnected Internet of Things impedance measurement chip according to claim 1, characterized in that The microprocessor module (105) includes an MCU processor and an FPGA chip for data processing.

5. The impedance measurement chip for heterogeneous interconnected Internet of Things according to claim 1, characterized in that, The communication interface (102) is used for communicating with external chips; The sensor module (103) is used to measure the state of the spatio-temporal environment, including any one or more of time, location, or acceleration; The memory module (106) is used to store initial state configuration parameters and working data; The digital signal processing module (107) is used to process digital signal data.

6. The heterogeneous interconnected Internet of Things impedance measurement chip according to claim 1, wherein, The heterogeneous interconnect structure includes a first substrate layer (204), a second substrate layer (206), a bonding layer (205), a substrate multi-layer interconnect module (201), and embedded passive devices; The embedded passive devices include resistors, capacitors, and inductors; The resistors, capacitors, and inductors are passive devices processed between the first substrate layer (204) and the second substrate layer (206); Each functional module, embedded passive device, and various interconnect lines are provided on the first substrate layer (204) and the second substrate layer (206); The bonding layer (205) is between the first substrate layer (204) and the second substrate layer (206), below the first substrate layer (204), and above the second substrate layer (206); It provides circuit interconnection between the first substrate layer (204) and the second substrate layer (206); The substrate multi-layer interconnect module (201) includes two stacking methods: The first stacking method is a multi-layer stacking method with the bonding layer (205) sandwiched between two substrate layers, and a stack of multiple such three-layer sandwich structures; The second stacking method is a stacking method in which when there is no bonding layer (205) back-to-back between sandwich structures, a wiring channel is etched in the substrate so that the substrates can be wired and connected in the vertical direction; The substrate multi-layer interconnect module (201) is provided with each functional module; The substrate multi-layer interconnect module (201) is arranged above the first substrate layer (204).

7. The impedance measurement chip for heterogeneous interconnected Internet of Things according to claim 6, characterized in that, The materials of different substrate layers are different, and the materials of the bonding layer (205) used to connect the substrate layers are also different. The first substrate layer (204) and the second substrate layer (206) are connected through the bonding layer (205). The material used for the bonding layer (205) is a polysilicon material, and the polysilicon material is a polysilicon material with a surface of a III-V compound thin film.

8. The heterogeneous interconnected Internet of Things impedance measurement chip according to claim 7, wherein, When the first substrate layer (204) and the second substrate layer (206) are connected through the bonding layer (205), first, the circuits on the surfaces of the two substrate layers are processed respectively. Then, the bonding layer (205) is combined with any one of the substrate layers, and then the circuit surface of the other substrate layer is combined with the bonding layer (205). After further processing, an electrical connection is formed. The electrical connection between the bonding layer (205) and the first substrate layer (204) and the second substrate layer (206) is achieved by processing connection channels on the bonding layer and filling metal materials therein to form bonding layer interconnections. The functional modules of the first substrate layer (204) and the second substrate layer (206) are electrically connected through the bonding layer interconnections.

9. The heterogeneous interconnected Internet of Things impedance measurement chip according to claim 6, characterized in that, The resistors in the embedded passive devices are set according to the heterogeneous resistor device design method, the capacitors are set according to the heterogeneous capacitor device design method, and the inductors are set according to the heterogeneous inductor device design method.

10. The heterogeneous interconnected Internet of Things impedance measurement chip according to claim 9, wherein In the heterogeneous resistor device design method, the resistor element is composed of at least one metal material, which is connected between the first substrate layer (204) and the second substrate layer (206) through the bonding layer (205). Different metal materials and processing structures are used to obtain the required resistance characteristics and are used as peripheral devices for the functional modules on any one of the substrate layers. In the heterogeneous capacitor device design method, the capacitor element is composed of at least one metal material and at least one dielectric material, which is connected between the first substrate layer (204) and the second substrate layer (206) through the bonding layer (205). Different metal materials, dielectric materials, and processing structures are used to obtain the required capacitance characteristics and are used as peripheral devices for the functional modules on any one of the substrate layers. In the heterogeneous inductor device design method, the inductor element is composed of at least one metal material. A planar inductor structure such as a circle, an octagon, or a square is processed on any one of the first substrate layer (204) and the second substrate layer (206). It is connected between the first substrate layer (204) and the second substrate layer (206) through the bonding layer (205). Different metal materials and processing structures are used to obtain the required inductance characteristics and are used as peripheral devices for the functional modules on any one of the substrate layers.

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