Enhancement-mode power transistor with high threshold voltage and method for manufacturing the same

Abstract

The present invention discloses an enhancement-mode power transistor with a high threshold voltage and a method for fabricating the same. The enhancement-mode power transistor comprises: a substrate; a heterojunction located on the substrate, the heterojunction comprising a channel layer and a barrier layer; a passivation layer structure located above the heterojunction, wherein the heterojunction and passivation layer structure are formed along a first direction with a first source region, a first gate region, a drain region, a second source region, and a second gate region; a first source, a first gate, a drain, a second source, and a second gate, respectively formed in the first source region, the first gate region, the drain region, the second source region, and the second gate region, wherein the first gate is electrically connected to the second source; and the first source, drain, and second gate serve as the source, drain, and gate of the enhancement-mode power transistor, respectively. The present invention can increase the threshold voltage of the device while reducing the leakage current of the device gate.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor devices and process technology, and in particular relates to an enhancement-mode power transistor with a high threshold voltage and a preparation method thereof. Background Art

[0002] Gallium nitride (GaN), a third-generation semiconductor material, has become a research hotspot for high-temperature, high-frequency, and high-power density applications due to its wide bandgap (3.4 eV), high electron mobility, and high breakdown electric field. Currently, GaN-based high electron mobility transistors (HEMTs) hold broad application prospects in high-efficiency, high-voltage power electronics. The aluminum gallium nitride / gallium nitride (AlGaN / GaN) heterostructure exhibits strong spontaneous polarization and piezoelectric polarization effects, generating a high concentration of carriers—a two-dimensional electron gas (2DEG)—at the interface. This AlGaN / GaN heterostructure-based HEMT exhibits a depletion-mode (D-mode) channel modulation mechanism. However, enhancement-mode (E-mode) power transistors are more popular among circuit designers for their safe operation and low power consumption. Using E-mode power transistors eliminates the need for a negative power supply, simplifying the design of gate drive circuits.

[0003] Currently, the mainstream technologies for manufacturing GaN enhancement-mode devices include gate grooves, fluorine ion implantation, and p-type GaN gate technology. However, the GaN enhancement-mode devices produced often have a relatively low threshold voltage and are prone to false turn-on in power electronics applications, which poses a huge safety hazard.

[0004] Therefore, in order to solve the above technical problems, it is necessary to provide an enhancement-mode power transistor with a high threshold voltage and a method for manufacturing the same. Summary of the Invention

[0005] In view of this, an object of the present invention is to provide an enhancement mode power transistor with a high threshold voltage and a method for manufacturing the same.

[0006] In order to achieve the above-mentioned purpose, the technical solution provided by one embodiment of the present invention is as follows:

[0007] An enhancement-mode power transistor with a high threshold voltage, the enhancement-mode power transistor comprising:

[0008] substrate;

[0009] A heterojunction located on a substrate, the heterojunction comprising a channel layer and a barrier layer;

[0010] A passivation layer structure is located above the heterojunction, wherein a first source region, a first gate region, a drain region, a second source region, and a second gate region are formed in the heterojunction and the passivation layer structure along a first direction;

[0011] A first source, a first gate, a drain, a second source, and a second gate are formed in the first source region, the first gate region, the drain region, the second source region, and the second gate region, respectively, and the first gate is electrically connected to the second source;

[0012] The first source, drain and second gate serve as the source, drain and gate of an enhancement-mode power transistor, respectively.

[0013] In one embodiment, a first isolation region, a second isolation region and a third isolation region are formed in the heterojunction along a first direction, the first source, the first gate and the drain are located between the first isolation region and the second isolation region, and the second source and the second gate are located between the second isolation region and the third isolation region.

[0014] In one embodiment, the first source electrode, the drain electrode, and the second source electrode respectively include one or more layers of a first metal layer, a second metal layer, and a third metal layer;

[0015] The first gate and the second gate respectively include one or more layers of the second metal layer and the third metal layer;

[0016] The first gate and the second source are electrically connected through a fourth metal layer.

[0017] In one embodiment, the material of the first metal layer is metal and / or metal compound, the metal includes one or more combinations of gold, platinum, nickel, titanium, aluminum, palladium, tantalum, tungsten, and molybdenum, and the metal compound includes one or more combinations of titanium nitride and tantalum nitride;

[0018] The material of the second metal layer is metal and / or metal compound, the metal includes one or more combinations of gold, platinum, nickel, titanium, palladium, tantalum, and tungsten, and the metal compound includes one or more combinations of titanium nitride and tantalum nitride;

[0019] The material of the third metal layer is metal and / or metal compound, the metal includes one or more combinations of gold, platinum, nickel, titanium, palladium, tantalum, and tungsten, and the metal compound includes one or more combinations of titanium nitride and tantalum nitride;

[0020] The material of the fourth metal layer is metal and / or metal compound, the metal includes one or more combinations of gold, platinum, nickel, titanium, palladium, tantalum, and tungsten, and the metal compound includes one or more combinations of titanium nitride and tantalum nitride.

[0021] In one embodiment, the passivation layer structure further forms a plurality of field plates, and the field plates are one or more of source field plates, gate field plates, and drain field plates.

[0022] In one embodiment, the passivation layer structure includes:

[0023] a first passivation layer located on the heterojunction, wherein the first passivation layer is a combination of one or more of a silicon nitride passivation layer, a silicon oxide passivation layer, an aluminum oxide passivation layer, an aluminum nitride passivation layer, and a gallium oxide passivation layer, and has a thickness of 20 to 300 nm;

[0024] a second passivation layer, located on the first passivation layer, wherein the second passivation layer is a combination of one or more of a silicon nitride passivation layer and a silicon oxide passivation layer, and has a thickness of 50 to 300 nm;

[0025] a third passivation layer, located on the second passivation layer, wherein the third passivation layer is a combination of one or more of a silicon nitride passivation layer and a silicon oxide passivation layer, and has a thickness of 50 to 300 nm;

[0026] a fourth passivation layer, located on the third passivation layer, wherein the fourth passivation layer is a combination of one or more of a silicon nitride passivation layer and a silicon oxide passivation layer, and has a thickness of 50 to 300 nm;

[0027] The fifth passivation layer is located on the fourth passivation layer. The fifth passivation layer is a combination of one or more of a silicon nitride passivation layer, a silicon oxide passivation layer, a polyimide passivation layer, and a benzocyclobutene passivation layer, and has a thickness of 1 to 5 μm.

[0028] In one embodiment, the heterojunction surface has a first P-type semiconductor structure and a second P-type semiconductor structure formed on the first gate region and the second gate region, respectively, and the first gate and the second gate are formed on the first P-type semiconductor structure and the second P-type semiconductor structure, respectively;

[0029] The first P-type semiconductor structure and the second P-type semiconductor structure are one or more of a P-type gallium nitride layer, a P-type aluminum gallium nitride layer, and a P-type aluminum indium nitride layer, and have a thickness of 70 nm to 120 nm.

[0030] In one embodiment, the heterojunction is etched at the first gate region and the second gate region to form a first gate groove and a second gate groove, and the first gate and the second gate are formed inside the first gate groove and the second gate groove respectively;

[0031] The first gate groove and the second gate groove are etched to the barrier layer, and the thickness of the barrier layer below the first gate groove and the second gate groove is less than or equal to 10nm; or, the first gate groove and the second gate groove are etched to the channel layer, and the etching depth of the channel layer is 0 to 10nm.

[0032] In one embodiment, the substrate is any one of a silicon substrate, a sapphire substrate, and a silicon carbide substrate; and / or,

[0033] The channel layer is a gallium nitride channel layer with a thickness of 50 nm to 2 μm; and / or,

[0034] The barrier layer is aluminum gallium nitride (Al x GaN 1-x N, x = 0.1 to 0.3) barrier layer, thickness is 10 nm to 50 nm; and / or,

[0035] A buffer layer is provided between the substrate and the channel layer, and the buffer layer is a nitride buffer layer.

[0036] Another embodiment of the present invention provides a technical solution as follows:

[0037] A method for preparing an enhancement-mode power transistor with a high threshold voltage, the method comprising:

[0038] providing a substrate;

[0039] epitaxially growing a channel layer and a barrier layer on a substrate to form a heterojunction;

[0040] Epitaxially growing a passivation layer structure on the heterojunction, and forming a first source region, a first gate region, a drain region, a second source region, and a second gate region in the heterojunction and the passivation layer structure along a first direction;

[0041] A first source, a first gate, a drain, a second source and a second gate are formed in the first source region, the first gate region, the drain region, the second source region and the second gate region respectively, and the first gate is electrically connected to the second source.

[0042] The present invention has the following beneficial effects:

[0043] The enhancement-mode power transistor of the present invention is provided with a dual-gate-source structure, including a first source, a first gate, a drain, a second source and a second gate, and the first gate and the second source are electrically connected, thereby greatly increasing the threshold voltage of the device and reducing the leakage current of the device gate; and the preparation method is easily compatible with the preparation of conventional enhancement-mode power transistors, and the implementation method is simple. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in this application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0045] Figure 1 Schematic diagram of the process of preparing the enhancement mode power transistor of the present invention;

[0046] Figure 2 Schematic diagram of the structure of the enhancement mode power transistor in Example 1 of the present invention;

[0047] Figures 3 to 8 1 is a process flow chart of a method for preparing an enhancement-mode power transistor in Example 1 of the present invention;

[0048] Figure 9 Schematic diagram of the structure of the enhancement mode power transistor in Example 2 of the present invention;

[0049] Figure 10 These are the transfer characteristic curves of two enhancement-mode power transistors. DETAILED DESCRIPTION

[0050] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0051] The present invention discloses an enhancement-mode power transistor with a high threshold voltage, comprising:

[0052] substrate;

[0053] A heterojunction located on a substrate, the heterojunction comprising a channel layer and a barrier layer;

[0054] A passivation layer structure is located above the heterojunction, wherein a first source region, a first gate region, a drain region, a second source region, and a second gate region are formed in the heterojunction and the passivation layer structure along a first direction;

[0055] A first source, a first gate, a drain, a second source, and a second gate are formed in the first source region, the first gate region, the drain region, the second source region, and the second gate region, respectively, and the first gate is electrically connected to the second source;

[0056] The first source, the drain and the second gate serve as the source, the drain and the gate of the enhancement mode power transistor respectively.

[0057] Ginseng Figure 1 As shown, the present invention also discloses a method for preparing an enhancement-mode power transistor with a high threshold voltage, comprising:

[0058] providing a substrate;

[0059] epitaxially growing a channel layer and a barrier layer on a substrate to form a heterojunction;

[0060] Epitaxially growing a passivation layer structure on the heterojunction, and forming a first source region, a first gate region, a drain region, a second source region, and a second gate region in the heterojunction and the passivation layer structure along a first direction;

[0061] A first source, a first gate, a drain, a second source and a second gate are formed in the first source region, the first gate region, the drain region, the second source region and the second gate region respectively, and the first gate is electrically connected to the second source.

[0062] The present invention will be further described below with reference to specific embodiments.

[0063] Example 1:

[0064] The gate of the enhancement-mode power transistor in this embodiment is a gate structure based on a P-type semiconductor layer, which depletes the two-dimensional electron gas (2DEG) thereunder through the P-type semiconductor layer.

[0065] Specifically, the enhancement-mode power transistor in this embodiment includes:

[0066] substrate 10;

[0067] a buffer layer 20 located on the substrate;

[0068] A heterojunction located on the buffer layer, the heterojunction including a channel layer 30 and a barrier layer 40;

[0069] A passivation layer structure is located above the heterojunction, wherein a first source region, a first gate region, a drain region, a second source region, and a second gate region are formed in the heterojunction and the passivation layer structure along a first direction, and a first P-type semiconductor structure 61 and a second P-type semiconductor structure 62 are respectively formed on the surface of the heterojunction on the first gate region and the second gate region;

[0070] A first source 71, a first gate 72, a drain 73, a second source 74, and a second gate 75 are formed in the first source region, the first gate region, the drain region, the second source region, and the second gate region, respectively, and the first gate 72 is electrically connected to the second source 74 via a fourth metal layer 80;

[0071] The first source 71 , the drain 73 and the second gate 75 serve as the source S, the drain D and the gate G of the enhancement mode power transistor respectively.

[0072] In which, a first isolation region 101, a second isolation region 102 and a third isolation region 103 are formed in the heterojunction along the first direction, the first source 71, the first gate 72 and the drain 73 are located between the first isolation region 101 and the second isolation region 102, and the second source 74 and the second gate 75 are located between the second isolation region 102 and the third isolation region 103.

[0073] Preferably, the passivation layer structure in this embodiment includes:

[0074] A first passivation layer 51 is located on the heterojunction;

[0075] a second passivation layer 52, located on the first passivation layer;

[0076] a third passivation layer 53, located on the second passivation layer;

[0077] a fourth passivation layer 54, located on the third passivation layer;

[0078] The fifth passivation layer 55 is located on the fourth passivation layer.

[0079] Furthermore, in this embodiment, a first field plate 91 and a second field plate 92 are formed above the second passivation layer 52 and the third passivation layer 53 . The first field plate 91 and the second field plate 92 can be any one of a source field plate, a gate field plate, and a drain field plate.

[0080] The enhancement mode power transistor and the manufacturing method thereof in this embodiment are described in detail below with reference to the accompanying drawings.

[0081] Ginseng Figure 3 As shown, the epitaxial structure of this embodiment mainly includes a substrate 10, a buffer layer 20, a channel layer 30 and a barrier layer 40. The manufacturing method is also compatible with other epitaxial structures including an aluminum nitride spacer (AlN spacer), a gallium nitride cap layer (GaNcap) or a p-type nitride epitaxial layer.

[0082] The substrate may include materials such as silicon (Si), sapphire (Al2O3) and silicon carbide (SiC);

[0083] The buffer layer is mainly nitride, including gallium nitride, aluminum nitride, aluminum gallium nitride, etc.

[0084] The channel layer is a gallium nitride channel layer with a thickness of 50nm to 2μm;

[0085] The barrier layer is aluminum gallium nitride (Al x GaN 1-x N, x = 0.1 to 0.3) barrier layer, thickness 10 nm to 50 nm;

[0086] The p-type semiconductor layer 60 can be a p-type gallium nitride layer (p-GaN), a p-type aluminum gallium nitride layer (p-AlGaN), a p-type aluminum indium nitride layer (p-AlInN), or the like. In this embodiment, p-type gallium nitride is used as an example. The p-type gallium nitride layer has a thickness of 70 nm to 120 nm. Due to the presence of the p-type gallium nitride layer, a two-dimensional electron gas (2DEG) cannot form at the interface between the gallium nitride channel layer and the aluminum gallium nitride barrier layer below the p-type gallium nitride layer.

[0087] Ginseng Figure 4 As shown, the p-type GaN layer outside the gate region is removed, perhaps by plasma etching. The two-dimensional electron gas in the channel is restored after the p-type GaN layer is removed. Ultimately, two P-type semiconductor structures are formed: a first P-type semiconductor structure 61 and a second P-type semiconductor structure 62.

[0088] Then, a first passivation layer 51 is grown to protect the surface of the AlGaN barrier layer and the p-type GaN layer. The material of the first passivation layer can be silicon nitride (SiN), silicon oxide (SiO2), aluminum oxide (Al2O3), aluminum nitride (AlN), gallium oxide (Ga2O3), etc., or a composite passivation layer composed of different materials. The thickness of the passivation layer is 20 to 300 nm.

[0089] Ginseng Figure 5 As shown, a hole is first opened in the ohmic region. The opening method can be plasma gas etching or wet etching using an acidic or alkaline solution, depending on the material of the first passivation layer. The opening depth can be sufficient to completely remove the first passivation layer 51, or further to remove a portion of the AlGaN barrier layer. Plasma gas etching is preferably used to remove the AlGaN barrier layer.

[0090] The ohmic region consists of three parts, namely the first source region, the drain region and the second source region. The two parts on the left are the source and drain regions corresponding to the first gate region, and the part on the right can be regarded as the source region corresponding to the second gate region.

[0091] After the holes are opened, the first metal layer M1 is made, and the first metal layer forms the first source 71, the drain 73 and the second source 74. The material of the first metal layer may include gold (Au), platinum (Pt), nickel (Ni), titanium (Ti), aluminum (Al), palladium (Pd), tantalum (Ta), tungsten (W), molybdenum (Mo), etc., and may also include metal compounds such as titanium nitride (TiN) and tantalum nitride (TaN). The metal can be formed by evaporation or sputtering. After formation, the photoresist and excess metal can be removed by stripping, or the metal can be removed from the area other than the source and drain by etching the metal. After the first metal layer is made, rapid annealing is required to form a good ohmic metal between the metal and the semiconductor. The annealing temperature can be 450-800°C, and the annealing time can be 30-300s.

[0092] Next, the second passivation layer 52 is grown. The second passivation layer 52 can be made of insulating materials such as silicon nitride, silicon oxide, or a composite passivation layer composed of different insulating materials. The thickness of the passivation layer is 50 to 300 nm. After the second passivation layer is grown, it can be planarized using chemical mechanical polishing (CMP).

[0093] After the second passivation layer is grown, the passive region is isolated to form a first isolation region 101, a second isolation region 102, and a third isolation region 103. These three isolation regions separate the left-side source-gate-drain region from the right-side source-gate region. Isolation can be achieved by ion implantation of highly electronegative elements such as O or F, or by etching using gases such as BCl3 and Cl2.

[0094] Ginseng Figure 6 As shown, the gate hole is opened. The hole opening method can be plasma gas etching or wet etching with acidic or alkaline solution according to the passivation layer material. A combination of plasma gas etching and wet etching can also be used. At the same time as the gate hole is opened, holes can also be opened for the source and drain.

[0095] After the hole is opened, a second metal layer M2 is formed. The second metal layer mainly forms the first gate 72 and the second gate 75. It can also form the source and drain thickening layers, and the first field plate 91. The second metal layer material may include gold (Au), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), tantalum (Ta), tungsten (W), etc., and may also include metal compounds such as titanium nitride (TiN) and tantalum nitride (TaN). The metal formation method can be evaporation or sputtering. After formation, the photoresist and excess metal can be removed by stripping, or the excess metal can be removed by metal etching.

[0096] Next, a third passivation layer 53 is grown. The third passivation layer 53 can be made of insulating materials such as silicon nitride, silicon oxide, or a composite passivation layer composed of different insulating materials. The thickness of the passivation layer is 50 to 300 nm. After the third passivation layer is grown, it can be planarized using chemical mechanical polishing (CMP).

[0097] Ginseng Figure 7 As shown, holes are opened. The opening method can be plasma gas etching or wet etching using an acidic or alkaline solution according to the material of the passivation layer. A combination of plasma gas etching and wet etching can also be used.

[0098] After the holes are opened, a third metal layer M3 is formed to form the second field plate 92, and the source and drain electrodes are thickened. The third metal layer can be made of gold (Au), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), tantalum (Ta), tungsten (W), etc., and can also include metal compounds such as titanium nitride (TiN) and tantalum nitride (TaN). The metal can be formed by evaporation or sputtering. After formation, the photoresist and excess metal can be removed by stripping, or by metal etching.

[0099] Next, the fourth passivation layer 54 is grown. The fourth passivation layer can be made of insulating dielectrics such as silicon nitride and silicon oxide, or a composite passivation layer composed of different insulating dielectrics. The passivation layer has a thickness of 50 to 300 nm. After the fourth passivation layer is grown, it can be planarized using chemical mechanical polishing (CMP).

[0100] Ginseng Figure 8 As shown, holes are opened. The opening method can be plasma gas etching or wet etching using an acidic or alkaline solution according to the material of the passivation layer. A combination of plasma gas etching and wet etching can also be used.

[0101] After the hole is opened, a fourth metal layer M4 is produced. The fourth metal layer is used to connect the first gate 72 of the left source-gate-drain region and the second source 74 of the right source-gate region. At the same time, the first source 71, the drain 73 and the second gate 75 can also be thickened. The fourth metal layer material may include gold (Au), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), tantalum (Ta), tungsten (W), etc., and may also include metal compounds such as titanium nitride (TiN) and tantalum nitride (TaN). The metal formation method may be evaporation or sputtering. After formation, the photoresist and excess metal may be removed by stripping, or the excess metal may be removed by metal etching.

[0102] Next, a fifth passivation layer 55 is grown. The fifth passivation layer can be made of an inorganic material such as silicon nitride or silicon oxide, an organic material such as polyimide (PI) or benzocyclobutene (BCB), or a composite passivation layer composed of different insulating materials. The passivation layer has a thickness of 1 to 5 μm. After the fifth passivation layer is grown, it can be planarized using chemical mechanical polishing (CMP).

[0103] Finally, holes are opened in the first source 71, drain 73, and second gate 75 to serve as the final source S, drain D, and gate G of the device. The hole opening method can be plasma gas etching or wet etching using an acidic or alkaline solution according to the material of the passivation layer, or a combination of plasma gas etching and wet etching can also be used.

[0104] It can be seen that the source and drain of the final device are the first source 71 and drain 73 of the left source-gate-drain region, and the gate is the second gate 75 of the right source-gate region.

[0105] In this embodiment, two layers of field plates are used as an example. In actual operation, more than two layers of field plates can also be provided. The field plate can be a source field plate, a gate field plate, or even a drain field plate. The connection between the first gate electrode 72 in the source-gate-drain region on the left side of the device and the second source electrode 74 in the source-gate region on the right side can be through the fourth metal layer M4, or can be connected through any other metal layer, or can be connected using multiple different metal layers.

[0106] Example 2:

[0107] The enhancement mode power transistor in this embodiment is a structure based on a recessed gate technology, which depletes the two-dimensional electron gas (2DEG) by partially or completely removing the barrier layer in the gate region.

[0108] Ginseng Figure 9 As shown, the enhancement-mode power transistor in this embodiment includes:

[0109] substrate 10;

[0110] a buffer layer 20 located on the substrate;

[0111] A heterojunction located on the buffer layer, the heterojunction including a channel layer 30 and a barrier layer 40;

[0112] A passivation layer structure is located above the heterojunction, wherein a first source region, a first gate region, a drain region, a second source region, and a second gate region are formed in the heterojunction and the passivation layer structure along a first direction, and a first gate groove and a second gate groove are formed by etching the heterojunction at the first gate region and the second gate region;

[0113] The first source 71, the first gate 72, the drain 73, the second source 74, and the second gate 75 are respectively formed in the first source region, the first gate region, the drain region, the second source region, and the second gate region. The first gate 72 and the second gate 75 are respectively formed in the first gate groove and the second gate groove. The first gate 72 and the second source 74 are electrically connected via the fourth metal layer 80.

[0114] The first source 71 , the drain 73 and the second gate 75 serve as the source S, the drain D and the gate G of the enhancement mode power transistor respectively.

[0115] In which, a first isolation region 101, a second isolation region 102 and a third isolation region 103 are formed in the heterojunction along the first direction, the first source 71, the first gate 72 and the drain 73 are located between the first isolation region 101 and the second isolation region 102, and the second source 74 and the second gate 75 are located between the second isolation region 102 and the third isolation region 103.

[0116] Preferably, the passivation layer structure in this embodiment includes:

[0117] A first passivation layer 51 is located on the heterojunction, and no first passivation layer exists in the first gate region and the second gate region;

[0118] a second passivation layer 52 , located on the first passivation layer and inner walls of the first gate groove and the second gate groove;

[0119] a third passivation layer 53, located on the second passivation layer;

[0120] a fourth passivation layer 54, located on the third passivation layer;

[0121] The fifth passivation layer 55 is located on the fourth passivation layer.

[0122] Furthermore, in this embodiment, a first field plate 91 and a second field plate 92 are formed above the second passivation layer 52 and the third passivation layer 53 . The first field plate 91 and the second field plate 92 can be any one of a source field plate, a gate field plate, and a drain field plate.

[0123] In the manufacturing steps of the gate groove in this embodiment, ohmic manufacturing is performed first, and after the ohmic manufacturing, the first passivation layer 51 is grown, and then the isolation step is performed.

[0124] After the isolation step is completed, the first gate region and the second gate region are opened. The opening method can be plasma gas etching or wet etching using acidic or alkaline solution according to the material of the passivation layer. A combination of plasma gas etching and wet etching can also be used.

[0125] After the hole is opened, the AlGaN barrier layer below the first gate region and the second gate region is etched. The AlGaN barrier layer can be partially etched, and the thickness of the remaining AlGaN barrier layer after etching needs to be less than or equal to 10 nm. The AlGaN barrier layer can also be completely etched, and the etching depth can be 0 to 10 nm below the interface of the AlGaN barrier layer / GaN channel layer.

[0126] Next, a second passivation layer 52 is grown. The second passivation layer is an insulating dielectric layer. The material of the insulating dielectric layer can be silicon nitride (SiN), silicon oxide (SiO2), aluminum oxide (Al2O3), aluminum nitride (AlN), gallium oxide (Ga2O3), etc., or a composite dielectric layer composed of different insulating dielectrics. The thickness of the insulating dielectric layer is 5 to 20 nm.

[0127] After the insulating dielectric layer is grown and the holes are opened, a second metal layer is formed. The second metal layer mainly forms the first gate and the second gate.

[0128] The subsequent process steps may be the same as those in Example 1 and will not be described again here.

[0129] Ginseng Figure 10 The transfer characteristic curves of two enhancement-mode power transistors are shown. The horizontal axis represents the voltage applied to the device gate, and the vertical axis represents the common logarithm of the source-drain current. Device 1 is a conventional gallium nitride enhancement-mode power transistor, and Device 2 is the gallium nitride enhancement-mode power transistor according to Example 1 of the present invention. Assuming a device current of 1 mA at the threshold voltage, the threshold voltage of conventional Device 1 is approximately 0.9 V, while that of Device 2 according to the present invention is approximately 1.8 V. This approximately 2-fold increase in threshold voltage significantly reduces device gate leakage current.

[0130] The threshold voltage increase of the gallium nitride enhancement-mode power transistor in the second embodiment of the present invention is similar to that in the first embodiment, and will not be further described here.

[0131] It can be seen from the above technical solutions that the present invention has the following advantages:

[0132] The enhancement-mode power transistor of the present invention is provided with a dual-gate-source structure, including a first source, a first gate, a drain, a second source and a second gate, and the first gate and the second source are electrically connected, thereby greatly increasing the threshold voltage of the device and reducing the leakage current of the device gate; and the preparation method is easily compatible with the preparation of conventional enhancement-mode power transistors, and the implementation method is simple.

[0133] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

[0134] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. An enhancement-mode power transistor with a high threshold voltage, characterized in that: The enhancement mode power transistor comprises: substrate; A heterojunction located on a substrate, the heterojunction comprising a channel layer and a barrier layer; A passivation layer structure is located above the heterojunction, wherein a first source region, a first gate region, a drain region, a second source region, and a second gate region are formed in the heterojunction and the passivation layer structure along a first direction; A first source, a first gate, a drain, a second source, and a second gate are formed in the first source region, the first gate region, the drain region, the second source region, and the second gate region, respectively, and the first gate is electrically connected to the second source; The first source, drain and second gate serve as the source, drain and gate of the enhancement mode power transistor respectively; The first source electrode, the drain electrode, and the second source electrode respectively include one or more layers of the first metal layer, the second metal layer, and the third metal layer; the first gate electrode and the second gate electrode respectively include one or more layers of the second metal layer and the third metal layer; The material of the first metal layer is metal and / or metal compound, the metal includes one or more combinations of gold, platinum, nickel, titanium, aluminum, palladium, tantalum, tungsten, and molybdenum, and the metal compound includes one or more combinations of titanium nitride and tantalum nitride; The material of the second metal layer is metal and / or metal compound, the metal includes one or more combinations of gold, platinum, nickel, titanium, palladium, tantalum, and tungsten, and the metal compound includes one or more combinations of titanium nitride and tantalum nitride; The material of the third metal layer is metal and / or metal compound, the metal includes one or more combinations of gold, platinum, nickel, titanium, palladium, tantalum, and tungsten, and the metal compound includes one or more combinations of titanium nitride and tantalum nitride.

2. The enhancement mode power transistor with a high threshold voltage according to claim 1, characterized in that A first isolation region, a second isolation region and a third isolation region are formed in the heterojunction along a first direction, the first source, the first gate and the drain are located between the first isolation region and the second isolation region, and the second source and the second gate are located between the second isolation region and the third isolation region.

3. The enhancement-mode power transistor with a high threshold voltage according to claim 1, wherein: The first gate and the second source are electrically connected through a fourth metal layer.

4. The enhancement mode power transistor with a high threshold voltage according to claim 3, characterized in that The material of the fourth metal layer is metal and / or metal compound, the metal includes one or more combinations of gold, platinum, nickel, titanium, palladium, tantalum, and tungsten, and the metal compound includes one or more combinations of titanium nitride and tantalum nitride.

5. The enhancement mode power transistor with a high threshold voltage according to claim 3, characterized in that: The passivation layer structure is further formed with a plurality of field plates, which are one or more of source field plates, gate field plates, and drain field plates.

6. The enhancement-mode power transistor with a high threshold voltage according to claim 1, wherein: The passivation layer structure comprises: a first passivation layer located on the heterojunction, wherein the first passivation layer is a combination of one or more of a silicon nitride passivation layer, a silicon oxide passivation layer, an aluminum oxide passivation layer, an aluminum nitride passivation layer, and a gallium oxide passivation layer, and has a thickness of 20 to 300 nm; a second passivation layer, located on the first passivation layer, wherein the second passivation layer is a combination of one or more of a silicon nitride passivation layer and a silicon oxide passivation layer, and has a thickness of 50 to 300 nm; a third passivation layer, located on the second passivation layer, wherein the third passivation layer is a combination of one or more of a silicon nitride passivation layer and a silicon oxide passivation layer, and has a thickness of 50 to 300 nm; a fourth passivation layer, located on the third passivation layer, wherein the fourth passivation layer is a combination of one or more of a silicon nitride passivation layer and a silicon oxide passivation layer, and has a thickness of 50 to 300 nm; The fifth passivation layer is located on the fourth passivation layer. The fifth passivation layer is a combination of one or more of a silicon nitride passivation layer, a silicon oxide passivation layer, a polyimide passivation layer, and a benzocyclobutene passivation layer, and has a thickness of 1 to 5 μm.

7. The enhancement-mode power transistor with a high threshold voltage according to claim 1, wherein: The heterojunction surface has a first P-type semiconductor structure and a second P-type semiconductor structure formed on the first gate region and the second gate region, respectively. The first gate and the second gate are formed on the first P-type semiconductor structure and the second P-type semiconductor structure, respectively. The first P-type semiconductor structure and the second P-type semiconductor structure are one or more of a P-type gallium nitride layer, a P-type aluminum gallium nitride layer, and a P-type aluminum indium nitride layer, and have a thickness of 70 nm to 120 nm.

8. The enhancement-mode power transistor with a high threshold voltage according to claim 1, wherein: The heterojunction is etched at the first gate region and the second gate region to form a first gate groove and a second gate groove, and the first gate and the second gate are formed inside the first gate groove and the second gate groove respectively; The first gate groove and the second gate groove are etched to the barrier layer, and the thickness of the barrier layer below the first gate groove and the second gate groove is less than or equal to 10nm; or, the first gate groove and the second gate groove are etched to the channel layer, and the etching depth of the channel layer is 0~10nm.

9. The enhancement-mode power transistor with a high threshold voltage according to claim 1, wherein: The substrate is any one of a silicon substrate, a sapphire substrate, and a silicon carbide substrate; and / or, The channel layer is a gallium nitride channel layer with a thickness of 50 nm to 2 μm; and / or, The barrier layer is an aluminum gallium nitride barrier layer with a thickness of 10 nm to 50 nm; and / or, A buffer layer is provided between the substrate and the channel layer, and the buffer layer is a nitride buffer layer.

10. A method for preparing an enhancement mode power transistor with a high threshold voltage, characterized in that: The preparation method comprises: providing a substrate; epitaxially growing a channel layer and a barrier layer on a substrate to form a heterojunction; Epitaxially growing a passivation layer structure on the heterojunction, and forming a first source region, a first gate region, a drain region, a second source region, and a second gate region in the heterojunction and the passivation layer structure along a first direction; A first source, a first gate, a drain, a second source and a second gate are respectively formed in the first source region, the first gate region, the drain region, the second source region and the second gate region, and the first gate is electrically connected to the second source. The first source, the drain and the second gate serve as the source, the drain and the gate of the enhancement mode power transistor respectively.

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