High-Voltage PLDMOS Device with Buried Drift Region and Its Manufacturing Method

Abstract

A high-voltage PLDMOS device with a buried drift region, comprising: a P-type substrate; an N-type buried layer located on the P-type substrate; a P-type buried layer located on the N-type buried layer; a P-type epitaxial layer located on the P-type substrate, the N-type buried layer, and the P-type buried layer; a high-voltage N-type well region, an N-type body region, a P-type well region, and a P-type buffer layer, respectively located on the P-type epitaxial layer; a first cathode P-type heavily doped region located on the P-type well region and connected to the drain; a second cathode P-type heavily doped region located on the P-type buffer layer and connected to the P-type substrate; an anode P-type heavily doped region and an anode N-type heavily doped region located on the N-type body region are short-circuited and connected to the source; a field-effect oxide layer located between the first cathode P-type heavily doped region and the anode P-type heavily doped region; a polysilicon gate located above the region between the anode P-type heavily doped region and the field-effect oxide layer and connected to the gate.

Description

Technical Field

[0001] The present application relates to the technical field of power semiconductor devices, and provides a high-voltage PLDMOS device with a buried drift region and a manufacturing method thereof. Background Art

[0002] The 1200V PLDMOS is an essential component in the high-low voltage compatible process, used to achieve the level conversion between high and low voltages, and is a key device in the level shift circuit, often used in 1200V gate driver chips.

[0003] In a conventional level shift circuit, a 1200V NLDMOS is used to boost the low-voltage signal generated in the dead zone of the previous stage to a high-voltage signal for use by the subsequent high-voltage circuit, preventing the mutual crosstalk between the high and low voltage signals of the front and rear stages. However, the high side bears a high voltage and is extremely prone to reliability problems. The 1200V PLDMOS can transmit the protection signal on the high side to the logic control circuits of the high-side and low-side power transistors to improve the reliability of the system.

[0004] In a 1200V PLDMOS, when the amount of charge in the drift region and the amount of charge in the substrate reach charge balance, the off-state breakdown voltage of the device is optimal. However, when the device is turned on, a large number of holes flow into the drift region through the inversion channel, disrupting the charge balance, resulting in the on-state breakdown voltage of the device being much lower than the off-state breakdown voltage, which limits the safe operating area of the LDMOS device and even the entire chip.

[0005] The LDMOS device operates in a short-circuit state of high voltage and large current and is extremely prone to burnout. The 1200V LDMOS needs to be set in an isolation structure to achieve self-isolation. Most of the domestic and foreign research on the safe operating area of high-voltage LDMOS devices is carried out for individual LDMOS devices, lacking the consideration of the compatibility between the LDMOS process and the isolation structure process and the mask version. The related technologies are difficult to apply to actual 1200V LDMOS devices. By introducing the carrier path into the body, the problem of carrier accumulation on the surface during conduction can be completely solved, and its safe operating area can be expanded. Summary of the Invention

[0006] In order to solve the deficiencies of the prior art, the purpose of the present application is to provide a high-voltage PLDMOS device with a buried drift region and a manufacturing method thereof, forming a P-type buried layer as the drift region of the device by epitaxy to broaden the safe operating area of the device.

[0007] To achieve the above purpose, the high-voltage PLDMOS device with a buried drift region provided by the present application includes:

[0008] A P-type substrate;

[0009] An N-type buried layer, located on the P-type substrate;

[0010] A P-type buried layer, located on the N-type buried layer;

[0011] A P-type epitaxial layer, located on the P-type substrate, the N-type buried layer, and the P-type buried layer;

[0012] A high-voltage N-type well region, an N-type body region, a P-type well region, and a P-type buffer layer are respectively located on the P-type epitaxial layer;

[0013] A first cathode P-type heavily doped region, located on the P-type well region and connected to the drain;

[0014] A second cathode P-type heavily doped region, located on the P-type buffer layer and connected to the P-type substrate;

[0015] An anode P-type heavily doped region and an anode N-type heavily doped region located on the N-type body region are shorted and connected to the source;

[0016] A field effect oxide layer, located between the first cathode P-type heavily doped region and the anode P-type heavily doped region;

[0017] A polysilicon gate, located above the region between the anode P-type heavily doped region and the field effect oxide layer and connected to the gate.

[0018] Further, the high-voltage N-type well region includes: a first high-voltage N-type well region and a second high-voltage N-type well region;

[0019] The P-type well region includes: a first P-type well region and a second P-type well region;

[0020] The first high-voltage N-type well region is located between the P-type buffer layer and the first P-type well region; the second high-voltage N-type well region is located between the first P-type well region and the second P-type well region;

[0021] The first P-type well region is located between the first high-voltage N-type well region and the second high-voltage N-type well region;

[0022] The second P-type well region is located between the second high-voltage N-type well region and the N-type body region.

[0023] Further, the left boundary of the P-type buried layer is consistent with the left boundary of the first P-type well region, and its right boundary is consistent with the left boundary of the N-type body region.

[0024] Further, the left boundary of the N-type buried layer is consistent with the left boundary of the first high-voltage N-type well region, and its right boundary is consistent with the right boundary of the device.

[0025] Further, the implantation concentration of the N-type buried layer is 2 - 4e12 cm -2 .

[0026] Further, the P-type buried layer is formed by segmentally implanting N-type impurities on the N-type buried layer, and the concentration of the implanted N-type impurities is 3 - 5e12 cm -2 , the implantation width is 1 - 2 μm, and the implantation pitch is 1 - 2 μm.

[0027] Further, the thickness of the P-type buried layer is 1 - 2 μm.

[0028] Further, the second P-type well region is formed by segmentally implanting the high-voltage N-type well region, and the concentration of the implanted impurities is 1 - 2e12 cm -2 , the implantation width is 3 - 4 μm, and the implantation pitch is 1 - 2 μm.

[0029] Furthermore, the width of the second P-type well region is 6 - 8 μm.

[0030] To achieve the above object, the present application further provides a method for manufacturing a high-voltage PLDMOS device with a buried drift region, including the following steps:

[0031] Form a P-type substrate;

[0032] Form an N-type buried layer on the P-type substrate;

[0033] Perform ion implantation on the N-type buried layer to form a P-type buried layer;

[0034] Form an epitaxial layer on the N-type buried layer, the P-type buried layer, and the P-type substrate;

[0035] Form a field-effect oxide layer, a high-voltage N-type well region, and an N-type body region on the epitaxial layer in sequence;

[0036] Form a P-type buffer layer and a P-type well region on the epitaxial layer in sequence.

[0037] Further, the step of forming a field-effect oxide layer, a high-voltage N-type well region, and an N-type body region on the epitaxial layer in sequence further includes:

[0038] Deposit a dielectric layer on the surface of the epitaxial layer, use a mask to lithograph the dielectric layer to remove the excess dielectric layer to form a field-effect oxide layer; perform the first N-type ion implantation to form a high-voltage N-type well region; then use the mask to perform the second N-type ion implantation, and the N-type ions are superposed and implanted to form an N-type body region.

[0039] Furthermore, the step of forming a P-type buffer layer and a P-type well region on the epitaxial layer in sequence further includes: perform a full-surface general implantation of P-type ions on the surface of the epitaxial layer, and after high-temperature annealing and diffusion, form a P-type buffer layer and a P-type well region.

[0040] To achieve the above object, the present application further provides a power chip, including the high-voltage PLDMOS device with a buried drift region as described above.

[0041] To achieve the above object, the present application further provides an electronic device, including the power chip as described above.

[0042] Compared with the prior art, the high-voltage PLDMOS device with a buried drift region and its manufacturing method according to the present application have the following advantages:

[0043] 1. The present application forms a P-type buried layer by epitaxy as the drift region of the device. The drift region is located inside the device, effectively optimizing the safe operating area of the device. The P-type buried layer is formed by ion implantation on the substrate, with easier depth control and fewer defects, which is beneficial to increasing the breakdown voltage of the device and improving the safe operating area of the device. Only one epitaxy is involved in manufacturing, with simple process steps and not too high cost. In traditional PLDMOS devices, the drift region is located on the surface. When in the on-state, due to the existence of the surface drift region, the surface impact ionization rate is relatively high, and it is extremely easy to appear electric field spikes, which is not conducive to the safe operation of the device. Compared with traditional PLDMOS devices, the PLDMOS drift region of the present application is a buried drift region, which transfers the surface carrier conduction channel to the body, breaking the limitation of the surface carrier accumulation of PLDMOS on its safe operating area and greatly broadening the safe operating area of the device.

[0044] 2. The present application uses a buried drift region to transform the surface conduction channel into a body conduction channel, extending the length of the drift region but having no impact on the overall size of the device, improving the current capacity of the device, and reducing the overall area of the isolation structure and the chip.

[0045] 3. The structure of the present application has strong plasticity. The main part of the device is fabricated on the epitaxial layer, and the formed P-type buried layer serves as the drift region. Under this design, the various parameters of the device are easy to adjust, and the structure can be modified on this basis to design a new device structure.

[0046] Other features and advantages of the present application will be described in the subsequent specification, and, in part, will become obvious from the specification, or will be understood by implementing the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The drawings are used to provide a further understanding of the present application, and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the present application and do not constitute a limitation to the present application. In the drawings:

[0048] Figure 1 is a schematic structural diagram of a high-voltage PLDMOS device with a buried drift region according to an embodiment of the present application;

[0049] Figure 2a , Figure 2b is a schematic diagram of the manufacturing process of the P-type buried layer drift region according to the present application;

[0050] Figure 3a , Figure 3b , Figure 3c is a schematic diagram of the manufacturing process of the P-type well region according to the present application;

[0051] Figure 4 is a flowchart of the manufacturing method of the high-voltage PLDMOS device with a buried layer drift region according to the present application;

[0052] Figure 5a is a schematic diagram of the current path of the traditional PLDMOS;

[0053] Figure 5b is a schematic diagram of the current path of the PLDMOS of the present application;

[0054] Figure 6a is a schematic diagram of the on-state impact ionization rate when the traditional PLDMOS breaks down;

[0055] Figure 6b is a schematic diagram of the on-state impact ionization rate when the PLDMOS of the present application breaks down;

[0056] Figure 7 is a comparison diagram of the safe operating areas of the traditional PLDMOS and the PLDMOS of the present application.

[0057] In the figure, 1 is a P-type substrate, 2 is an N-type buried layer, 3 is an N-type body region, 4 is an anode N-type heavily doped region, 5 is an anode P-type heavily doped region, 6 is a polysilicon gate, 7 is a second P-type well region, 8 is a second high-voltage N-type well region, 9 is a field effect oxide layer, 10 is a P-type buried layer, 11 is a first cathode P-type heavily doped region, 12 is a first P-type well region, 13 is a first high-voltage N-type well region, 14 is a P-type buffer layer, and 15 is a second cathode P-type heavily doped region. Detailed implementation manners

[0058] Embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although some embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Instead, these embodiments are provided to more thoroughly and completely understand the present application. It should be understood that the drawings and embodiments of the present application are only for exemplary purposes and are not used to limit the protection scope of the present application.

[0059] It should be understood that the steps recited in the method embodiments of the present application can be executed in different orders and / or in parallel. In addition, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present application is not limited in this regard.

[0060] As used herein, the term "comprising" and its variations are open-ended, i.e., "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The relevant definitions of other terms will be given in the following description.

[0061] It should be noted that the modification of "one" and "plural" mentioned in this application is illustrative rather than restrictive. Those skilled in the art should understand that unless otherwise clearly stated in the context, it should be understood as "one or more". "Plural" should be understood as two or more.

[0062] Next, the embodiments of the present application will be described in detail with reference to the accompanying drawings.

[0063] Embodiment 1

[0064] Figure 1 It is a schematic structural diagram of a high-voltage PLDMOS device with a buried drift region according to an embodiment of the present application. As Figure 1 shown, the high-voltage PLDMOS device with a buried drift region in this embodiment includes:

[0065] A P-type substrate 1.

[0066] An N-type buried layer 2 is provided on the P-type substrate 1, and a P-type buried layer 10 is implanted on the N-type buried layer 2.

[0067] A layer of P-type epitaxial layer is provided on the N-type buried layer 2, the P-type buried layer 10 and the P-type substrate 1. A first high-voltage N-type well region 13, a second high-voltage N-type well region 8, an N-type body region 4, a first P-type well region 12, and a P-type buffer layer 14 are provided in the epitaxial layer.

[0068] A first cathode P-type heavily doped region 11 is provided on the first P-type well region 12, and the first cathode P-type heavily doped region 11 is connected to the drain (D).

[0069] A second cathode P-type heavily doped region 15 is provided on the P-type buffer layer 14, and the second P-type heavily doped region 15 is connected to the substrate (Sub).

[0070] An anode P-type heavily doped region 5 and an anode N-type heavily doped region 4 are provided on the N-type body region 3, and the anode P-type heavily doped region 5 and the anode N-type heavily doped region 4 are short-circuited and connected to the source (S).

[0071] A field effect oxide layer 9 is provided between the first cathode P-type heavily doped region 11 and the anode P-type heavily doped region 5.

[0072] A polysilicon gate 6 serving as a gate G is provided on the field effect oxide layer 9, and the polysilicon gate 6 is located above the region between the anode P-type heavily doped region 5 and the field effect oxide layer 9. The polysilicon gate 6 is connected to the gate (G).

[0073] In the embodiment of the present application, the left boundary of the P-type buried layer 10 extends to the left side of the device and stops at the left boundary of the first P-type well region 12, and the right boundary of the P-type buried layer 10 extends to the right side of the device and stops at the left boundary of the N-type body region 3.

[0074] In the embodiment of the present application, the N-type buried layer 2 extends to the left to the left boundary of the first high-voltage N-type well region 13 and extends to the right boundary of the device to the right.

[0075] The implantation concentration of the N-type buried layer 2 is 2 - 4e12 cm -2 .

[0076] Figure 2a 、 Figure 2b is a schematic diagram of the manufacturing process of the P-type buried layer drift region according to the present application. As shown in Figure 2a and 2b shown, the P-type buried layer 10 is formed by segmented implantation on the N-type buried layer 2. The implanted N-type impurity concentration is 3 - 5e12 cm -2 , the implantation width is 1 - 2 um, and the implantation pitch is 1 - 2 um.

[0077] In the embodiment of the present application, the thickness of the P-type buried layer 10 is 1 - 2 um.

[0078] In the embodiment of the present application, a second P-type well region 7 is also provided in the epitaxial layer. Figure 3a 、 Figure 3b 、 Figure 3c is a schematic diagram of the manufacturing process of the P-type well region according to the present application. As shown in Figures 3a - 3c shown, the second P-type well region 7 is formed by segmented implantation of the high-voltage N-type well region. On the basis of the formation of the high-voltage N-type well region, P-type impurity general implantation is performed. Since the N-type impurity concentration is high, P-type impurities cannot be implanted into the N-type impurity region. Therefore, P-type impurities are implanted into the gaps of the high-voltage N-type well region, and after high-temperature annealing, the impurities diffuse to form the second P-type well region 7.

[0079] In the embodiment of the present application, the second P-type well region 7 is formed by segmented implantation of the high-voltage N-type well region. The implanted impurity concentration is 1 - 2e12 cm -2 , the implantation width is 3 - 4 um, and the implantation pitch is 1 - 2 um.

[0080] In the embodiment of the present application, the width of the second P-type well region 7 is 6 - 8 um.

[0081] Embodiment 2

[0082] Figure 4Flow chart of the manufacturing method of a high-voltage PLDMOS device with a buried drift region according to the present application. The following will be based on Figure 4 to describe in detail the manufacturing method of the high-voltage PLDMOS device with a buried drift region of the present application.

[0083] In step 401, a P-type substrate is formed.

[0084] In step 402, an N-type buried layer is formed on the P-type substrate.

[0085] In the embodiment of the present application, the implantation concentration of the N-type buried layer is 2-4e12 cm -2 .

[0086] In step 403, ion implantation is performed on the N-type buried layer to form a P-type buried layer.

[0087] In the embodiment of the present application, the P-type buried layer is formed by segmented implantation on the N-type buried layer. The implanted N-type impurity concentration is 3-5e12 cm -2 , the implantation width is 1-2 um, and the implantation spacing is 1-2 um. The thickness of the P-type buried layer 10 is 1-2 um.

[0088] In step 404, an epitaxial layer is formed on the N-type buried layer, the P-type buried layer, and the P-type substrate.

[0089] In step 405, a field effect oxide layer, a high-voltage N-type well region, and an N-type body region are sequentially formed on the epitaxial layer.

[0090] In the embodiment of the present application, a dielectric layer is deposited on the surface of the epitaxial layer, and the mask is used to lithographically remove the excess dielectric layer to form a field effect oxide layer; the first N-type ion implantation is performed to form a high-voltage N-type well region; then the mask is used for the second N-type ion implantation, and the N-type ions are superposed and implanted to form an N-type body region.

[0091] In step 406, a P-type buffer layer and a P-type well region are sequentially formed on the epitaxial layer.

[0092] In the embodiment of the present application, a comprehensive general implantation of P-type ions is performed on the surface of the epitaxial layer, and after high-temperature annealing and diffusion, a P-type buffer layer and a P-type well region are formed.

[0093] The P-type well region is formed by segmented implantation of the high-voltage N-type well region. On the basis of the formation of the high-voltage N-type well region, P-type impurity general implantation is performed. Since the N-type impurity concentration is high, P-type impurities cannot be implanted into the N-type impurity region. Therefore, P-type impurities are implanted into the gaps of the high-voltage N-type well region, and after high-temperature annealing, the impurities diffuse to form the P-type well region.

[0094] When the traditional P-channel LDMOS device is in the forward conduction state, the source electrode of the device is connected to a high potential, the substrate is grounded, the drain electrode is grounded, and the gate electrode is connected to a low potential. AsFigure 5a As shown, an inversion channel is formed under the polysilicon gate at this time. Holes flow from the P-type heavily doped region through the inversion channel into the P-type well region, and finally the hole current flows through the P-type well region into the P-type heavily doped region and is led out from the drain D. In the traditional PLDMOS, the drift region is located on the surface, and carriers accumulate on the surface when flowing, resulting in a relatively high surface impact ionization rate. As Figure 6a shown, breakdown is likely to occur on the surface, severely limiting the safe operating area of the device. When in the reverse breakdown voltage state, the source of the device is connected to a high potential, the substrate is connected to a low potential, the drain is connected to a low potential, and the gate is connected to a high potential. At this time, the P-type drift region and the N-well are mutually depleted.

[0095] When the structure of the present application is in the forward conduction state, the source of the device is connected to a high potential, the substrate is grounded, the drain is grounded, and the gate is connected to a high potential. As Figure 5b shown, an inversion channel is formed under the polysilicon gate 6 at this time. Holes flow from the anode P-type heavily doped region 5 through the channel into the second P-type well region 7, flow through the P-type buried layer 10, and flow into the first P-type heavily doped region 11 through the first P-type well region 13 and are then led out from the drain D, thereby generating a forward conduction current between the source and the drain. Due to the existence of the P-type buried layer drift region, the current path of the structure of the present application is transferred to the body, and the surface impact ionization rate is reduced. As Figure 6b shown, due to the reduction of the surface impact ionization rate, its safe operating area is greatly improved. In addition, the in-body conduction path improves the current capacity of the device. As Figure 7 shown. When the structure of the present application is in the reverse breakdown voltage state, the source of the device is connected to a high potential, the substrate is grounded, the drain is grounded, and the gate is connected to a high potential. At this time, the second high-voltage N-type well region 8 plays an auxiliary depletion role and optimizes the electric field distribution of the device through charge compensation, improving the breakdown voltage capacity of the device.

[0096] Embodiment 3

[0097] In the embodiment of the present application, a power chip is further provided, including the high-voltage PLDMOS device with a buried layer drift region in the above embodiment.

[0098] Embodiment 4

[0099] In the embodiment of the present application, an electronic device is further provided, including the high-voltage PLDMOS device with a buried layer drift region in the above embodiment.

[0100] Those of ordinary skill in the art can understand that the foregoing are only preferred embodiments of the present application and are not intended to limit the present application. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or perform equivalent replacements on some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A high-voltage PLDMOS device with a buried drift region, characterized in that, Including: P-type substrate; N-type buried layer, located on the P-type substrate; P-type buried layer, located on the N-type buried layer; P-type epitaxial layer, located on the P-type substrate, the N-type buried layer, and the P-type buried layer; a high-voltage N-type well region, an N-type body region, a P-type well region, and a P-type buffer layer are respectively located on the P-type epitaxial layer; a first cathode P-type heavily doped region, located on the P-type well region and connected to the drain; a second cathode P-type heavily doped region, located on the P-type buffer layer and connected to the P-type substrate; an anode P-type heavily doped region and an anode N-type heavily doped region located on the N-type body region are short-circuited and connected to the source; a field-effect oxide layer, located between the first cathode P-type heavily doped region and the anode P-type heavily doped region; A polysilicon gate, located above the region between the anode P-type heavily doped region and the field-effect oxide layer and connected to the gate; The high-voltage N-type well region includes: a first high-voltage N-type well region and a second high-voltage N-type well region; the P-type well region includes: a first P-type well region and a second P-type well region; the first high-voltage N-type well region is located between the P-type buffer layer and the first P-type well region; the second high-voltage N-type well region is located between the first P-type well region and the second P-type well region; the first P-type well region is located between the first high-voltage N-type well region and the second high-voltage N-type well region; the second P-type well region is located between the second high-voltage N-type well region and the N-type body region.

2. The high-voltage PLDMOS device with a buried drift region according to claim 1, characterized in that, The left boundary of the P-type buried layer is consistent with the left boundary of the first P-type well region, and its right boundary is consistent with the left boundary of the N-type body region.

3. The high-voltage PLDMOS device with a buried drift region according to claim 1, characterized in that, The left boundary of the N-type buried layer is consistent with the left boundary of the first high-voltage N-type well region, and its right boundary is consistent with the right boundary of the device.

4. The high-voltage PLDMOS device with a buried drift region according to claim 1, characterized in that, The implantation concentration of the N-type buried layer is 2~4e12 cm-2.

5. The high-voltage PLDMOS device with a buried drift region according to claim 1, characterized in that, The P-type buried layer is formed by segmentally implanting N-type impurities on the N-type buried layer, the implantation concentration of the N-type impurities is 3~5e12 cm-2, the implantation width is 1~2 um, and the implantation spacing is 1~2 um.

6. The high-voltage PLDMOS device with a buried drift region according to claim 1, characterized in that, The thickness of the P-type buried layer is 1~2 um.

7. The high-voltage PLDMOS device with a buried drift region according to claim 1, wherein The second P-type well region is formed by segmentally implanting the high-voltage N-type well region, the implantation impurity concentration is 1~2e12 cm-2, the implantation width is 3~4 um, and the implantation spacing is 1~2 um.

8. The high-voltage PLDMOS device with a buried drift region according to claim 1, wherein, The width of the second P-type well region is 6~8 um.

9. A method for fabricating a high-voltage PLDMOS device with a buried drift region, which is used to fabricate the high-voltage PLDMOS device with a buried drift region according to any one of claims 1-8, comprising the following steps: Form a P-type substrate; form an N-type buried layer on the P-type substrate; Perform ion implantation on the N-type buried layer to form a P-type buried layer; form an epitaxial layer on the N-type buried layer, the P-type buried layer, and the P-type substrate; sequentially form a field-effect oxide layer, a high-voltage N-type well region, and an N-type body region on the epitaxial layer; sequentially form a P-type buffer layer and a P-type well region on the epitaxial layer.

10. The preparation method according to claim 9, wherein, The step of sequentially forming a field-effect oxide layer, a high-voltage N-type well region, and an N-type body region on the epitaxial layer further includes: depositing a dielectric layer on the surface of the epitaxial layer, using a mask to lithographically remove the redundant dielectric layer to form a field-effect oxide layer; performing a first N-type ion implantation to form a high-voltage N-type well region; and then using a mask to perform a second N-type ion implantation, and the N-type ions are superposed and implanted to form an N-type body region.

11. The preparation method according to claim 9, characterized in that, The step of sequentially forming a P-type buffer layer and a P-type well region on the epitaxial layer further includes: performing a full-dose implantation of P-type ions on the surface of the epitaxial layer, and forming a P-type buffer layer and a P-type well region through high-temperature annealing and diffusion.

12. A power chip, characterized in that, It includes the high-voltage PLDMOS device with a buried drift region according to any one of claims 1-8.

13. An electronic device, characterized in that, It includes the power chip according to claim 12.

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