Electrostatic protection circuit

Abstract

This application provides an electrostatic discharge (ESD) protection circuit, including: a monitoring unit for monitoring electrostatic pulses on a power supply terminal; a main discharge transistor and an auxiliary discharge transistor, which are turned on upon detection of an ESD pulse to discharge electrostatic charge on the power supply terminal, wherein the main discharge transistor turns on earlier than the auxiliary discharge transistor; wherein the first terminal of the main discharge transistor and the first terminal of the auxiliary discharge transistor are connected to a first segment of a power supply metal line, the first terminal of the internal circuit is connected to a third segment of the power supply metal line, and a second segment of the power supply metal line is disposed between the first and third segments, with an angle of less than 180 degrees at the contact point between the second and first segments. This application provides both timely discharge of electrostatic charge and sufficient ESD discharge capability.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to an electrostatic discharge protection circuit. Background Technology

[0002] Static electricity is everywhere. Without electrostatic discharge protection circuits, a chip can be quickly damaged by static electricity due to various reasons, and it can almost be fatal.

[0003] Therefore, chips are usually equipped with electrostatic discharge (ESD) protection circuits. These circuits are used to discharge static charge in a timely manner to prevent the protected circuit from failing or even burning out due to the high voltage caused by the static charge. Summary of the Invention

[0004] This application provides an electrostatic discharge protection circuit, which aims to provide a technical solution that can both timely discharge electrostatic charge and have sufficient electrostatic discharge capability.

[0005] This application provides an electrostatic discharge (ESD) protection circuit disposed between a power supply terminal and a ground terminal on a chip. An internal circuit connects the power supply terminal and the ground terminal. The metal trace connecting the power supply terminal is referred to as a power supply metal trace. The circuit includes:

[0006] The monitoring unit is used to monitor electrostatic pulses on the power supply terminal;

[0007] The main discharge transistor and the auxiliary discharge transistor are used to conduct after detecting an electrostatic pulse to discharge the electrostatic charge on the power supply terminal. The main discharge transistor conducts earlier than the auxiliary discharge transistor.

[0008] The first end of the main discharge transistor and the first end of the auxiliary discharge transistor are connected to the first segment of the power supply metal line. The first end of the internal circuit is connected to the third segment of the power supply metal line. The second segment of the power supply metal line is located between the first segment and the third segment of the power supply metal line. The contact point between the second segment and the first segment of the power supply metal line has an angle of less than 180 degrees.

[0009] Optionally, the angle between the second segment of the power supply wire and the first segment of the power supply wire at their contact point may be a right angle or an acute angle.

[0010] Optionally, the contact point between the second segment and the third segment of the power supply wire has an angle of less than 180 degrees.

[0011] Optionally, the power metal lines are located within the topmost metal layer of the chip.

[0012] Optionally, the monitoring unit includes:

[0013] The monitoring capacitor has its first end connected to the first segment of the power supply metal wire.

[0014] The first end of the monitoring resistor is connected to the second end of the monitoring capacitor, and the second end is connected to the ground terminal.

[0015] Optionally, it also includes:

[0016] The delay circuit has its input terminal connected to the control terminal of the main discharge transistor and its output terminal connected to the control terminal of the auxiliary discharge transistor.

[0017] Optionally, the delay circuit includes:

[0018] The first inverter has its input terminal used as the input terminal of the delay circuit, and its output terminal used as the output terminal of the delay circuit.

[0019] Optionally, the main discharge transistor is an N-type transistor;

[0020] The auxiliary discharge transistor is a P-type transistor.

[0021] Optionally, the delay circuit includes:

[0022] The first inverter has its input terminal used as the input terminal of the delay circuit;

[0023] The second inverter has its input connected to the output of the first inverter, and its output is used as the output of the delay circuit.

[0024] Optionally, the main discharge transistor is an N-type transistor;

[0025] The auxiliary discharge transistor is an N-type transistor.

[0026] Optionally, the auxiliary discharge transistor, the N-type transistor of the first inverter, and the N-type transistor of the second inverter are all located in the same P-type well on the substrate;

[0027] The main discharge transistor and the auxiliary discharge transistor are located in different P-type wells on the substrate.

[0028] Optionally, the main discharge transistor and the auxiliary discharge transistor are located in the same P-type well on the substrate.

[0029] Optionally, the size of the main discharge transistor is larger than the size of the auxiliary discharge transistor.

[0030] Optionally, the monitoring unit includes:

[0031] The monitoring resistor has its first end connected to the first segment of the power supply metal wire;

[0032] The monitoring capacitor has its first end connected to the second end of the monitoring resistor, and its second end is connected to the ground terminal.

[0033] Optionally, the main discharge transistor is a P-type transistor.

[0034] This application provides an electrostatic discharge (ESD) protection circuit, which is disposed between the power supply terminal and the ground terminal on a chip. The circuit includes a main discharge transistor, an auxiliary discharge transistor, and a monitoring unit. Upon detecting an ESD pulse, the main discharge transistor conducts before the auxiliary discharge transistor, discharging a portion of the ESD charge at the moment the ESD pulse arrives. Furthermore, the contact point between the second and first segments of the power supply metal line has an angle of less than 180 degrees, meaning the trace between the first terminal of the internal circuit and the first segment of the power supply metal line is not a straight line. This increases the impedance change on the second and third segments of the power supply metal line, thereby reflecting a portion of the high-frequency pulse signal when the ESD pulse arrives. Through the discharge of the main discharge transistor and the reflection of the ESD pulse by the impedance change, excessive accumulation of ESD charge is avoided, preventing the voltage at the power supply terminal caused by ESD charge from rising too quickly. This effectively prevents damage to the protected circuit caused by the ESD pulse. Furthermore, since the main discharge transistor turns on earlier than the auxiliary discharge transistor, the main discharge transistor turns off earlier than the auxiliary discharge transistor. This means that the auxiliary discharge transistor can continue to discharge static charge after the main discharge transistor turns off, thereby extending the static discharge time and increasing the static discharge capability. Attached Figure Description

[0035] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0036] Figure 1 This is a schematic diagram of an electrostatic discharge protection circuit.

[0037] Figure 2 A circuit diagram of an electrostatic discharge protection circuit provided in an embodiment of this application;

[0038] Figure 3 A front view of an electrostatic discharge protection circuit structure provided in another embodiment of this application;

[0039] Figures 4a to 4c This is a schematic diagram of the power supply metal wire routing.

[0040] Figure 5 A circuit diagram of an electrostatic discharge protection circuit provided for another embodiment of this application;

[0041] Figure 6 A specific circuit diagram of an electrostatic discharge protection circuit provided in another embodiment of this application;

[0042] Figure 7 A specific circuit diagram of an electrostatic discharge protection circuit provided in another embodiment of this application;

[0043] Figure 8A specific circuit diagram of an electrostatic discharge protection circuit provided in another embodiment of this application;

[0044] Figure 9 A specific circuit diagram of an electrostatic discharge protection circuit provided in another embodiment of this application.

[0045] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0046] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0047] Static electricity is ubiquitous. Without electrostatic discharge (ESD) protection circuits, a chip can be quickly damaged by static electricity introduced from various sources, and it can almost be fatal. For example, in a human mannequin, the moment a hand touches a chip pin, typically for only tens of nanoseconds, the voltage can reach hundreds or even thousands of volts, enough to damage any chip. In a machine mannequin, such as a piece of equipment, even a few nanoseconds can cause the voltage on the touched pin to reach hundreds of volts.

[0048] To ensure chip safety, each chip contains an electrostatic discharge (ESD) protection circuit. Depending on the function of the pins, these circuits are further divided into ESD protection circuits for power pins and I / O pins.

[0049] like Figure 1 The diagram illustrates an embodiment of an electrostatic discharge (ESD) protection circuit 100, which is positioned between the power supply terminal VCC and the ground terminal GND. The ESD protection circuit 100 includes a monitoring unit 103 and a discharge transistor T. The monitoring unit 103 includes a monitoring capacitor C1 and a monitoring resistor R1. The monitoring capacitor C1 and the monitoring capacitor R1 are connected in series, with one end connected to the power supply terminal and the other end grounded.

[0050] The peak current of electrostatic discharge can typically reach 1.5A, which requires a larger discharge transistor. A larger discharge transistor T requires a larger drive current to turn on quickly, at the instant the electrostatic pulse arrives. Figure 1In this embodiment, the discharge transistor T is too large, which may result in the inability to conduct in a timely manner or non-uniform conduction. As a result, the electrostatic charge cannot be discharged in a timely manner, and the internal circuitry on the chip is still at risk of being damaged.

[0051] Figure 2 This is a circuit diagram of an electrostatic discharge protection circuit 100 provided in one embodiment of this application. Figure 3 This is a front view of an electrostatic discharge (ESD) protection circuit structure provided for another embodiment of this application. Figure 2 and Figure 3 As shown, one embodiment of this application provides an electrostatic discharge (ESD) protection circuit 100, which is disposed between a power supply terminal 201 and a ground terminal 202 on a chip. An internal circuit 300 is also provided between the power supply terminal 201 and the ground terminal 202, and the ESD protection circuit 100 is used to protect the internal circuit 300.

[0052] Continue to refer to Figure 3 The structure consists of a top metal layer M3, a second-to-top metal layer M2, a third metal layer M1, and a fourth metal layer M0, arranged sequentially from top to bottom. The top metal layer M3 and the second-to-top metal layer M2 are connected by a through-hole V3, the second-to-top metal layer M2 and the third metal layer M1 are connected by a through-hole V2, and the third metal layer M1 and the fourth metal layer M0 are connected by a through-hole V1.

[0053] The metal trace connecting to the power supply terminal 201 is called the power metal trace. The power metal trace is arranged in any one or more of the top metal layer M3 to the fourth metal layer M0. The power metal trace includes a first segment 2031 and a second segment 2032 (in...). Figure 3 Not shown in the image, but refer to the image below. Figure 3 and Figure 4c It can Figure 3 Understand as Figure 4c (Across section of the first segment 2031) and the third segment 2033. The first segment 2031 of the power supply metal wire is connected to the power supply terminal 201. The second segment 2032 of the power supply metal wire is located between the first segment 2031 and the third segment 2033. The third segment 2033 of the power supply metal wire is connected to the first terminal of the internal circuit 300. The second terminal of the internal circuit 300 is connected to the ground terminal 202. Figure 3 In the diagram, 100 indicates a device in the electrostatic discharge protection circuit, and 200 indicates a device in the internal circuit. The device 100 in the electrostatic discharge protection circuit is usually located near the power supply terminal 201, while the device 200 in the internal circuit is usually located further away from the power supply terminal 201.

[0054] refer to Figure 4a , Figure 4b and Figure 4cThe contact point between the second segment 2032 and the first segment 2031 of the power supply metal line has an angle of less than 180 degrees, meaning the power supply metal line between the first end of the internal circuit and the power supply end is not a straight line. Similarly, the contact point between the second segment 2032 and the third segment 2033 of the power supply metal line also has an angle of less than 180 degrees, meaning the power supply metal line between the first end of the internal circuit and the power supply end is not a straight line. From the perspective of signal flow, there are impedance abrupt changes at these contact points, both from the first segment 2031 to the second segment 2032 and from the second segment 2032 to the third segment 2033. An electrostatic pulse (ESP) can be considered a high-frequency signal. For example, the rise time of an ESP is often only a few nanoseconds. When an ESP is considered a high-frequency signal, signal reflection occurs at the points of impedance abrupt change. For instance, when a high-frequency signal propagates from the power supply terminal 201 through the first segment 2031 of the power metal wire to the second segment 2032, due to the impedance abrupt change, some of the high-frequency signal's energy is lost at the signal reflection point (i.e., the contact point between the first segment 2031 and the second segment 2032, i.e., the impedance abrupt change). For example, only 90% of the energy propagates from the first segment 2031 to the second segment 2032, with 10% lost at the signal reflection point. The energy loss of an ESP propagating from the power supply terminal to the first terminal of the internal circuit depends on several factors, such as the frequency of the ESP and the magnitude of the impedance abrupt change along the propagation path. Figure 4a , Figure 4b and Figure 4c The technical solutions described herein should be understood as three embodiments and do not constitute a limitation on the inventive concept of special treatment of the power line between the power supply terminal and the internal circuit in this application.

[0055] Continue to refer to Figure 2 and Figure 3 The electrostatic discharge (ESD) protection circuit 100 includes a main discharge transistor 101, an auxiliary discharge transistor 102, and a monitoring unit 103. The main discharge transistor 101 has a control terminal 113, a first terminal 111, and a second terminal 112. The auxiliary discharge transistor 102 also has a control terminal, a first terminal, and a second terminal. The first terminal 111 of the main discharge transistor 101 is connected to the first segment 2031 of the power supply metal line, and the second terminal 112 of the main discharge transistor 101 is connected to the ground terminal 202. The first terminal of the auxiliary discharge transistor 102 is also connected to the first segment 2031 of the power supply metal line, and the second terminal of the auxiliary discharge transistor 102 is connected to the ground terminal 202.

[0056] The monitoring unit 103 is used to monitor electrostatic pulses caused by electrostatic charges on the power supply terminal 201. The main discharge transistor 101 is turned on after detecting an electrostatic pulse to discharge the electrostatic charge from the power supply terminal 201 through the first segment 2031 of the power supply metal line and the main discharge transistor 101 to the ground terminal 202. The auxiliary discharge transistor 102 is also turned on after detecting an electrostatic pulse on the power supply terminal 201 to discharge the electrostatic charge from the power supply terminal 201 through the first segment 2031 of the power supply metal line and the auxiliary discharge transistor 102 to the ground terminal 202.

[0057] The main discharge transistor 101 turns on earlier than the auxiliary discharge transistor 102. That is, after detecting the electrostatic pulse, the main discharge transistor 101 turns on first, discharging a portion of the electrostatic charge to the ground terminal 202. Then the auxiliary discharge transistor 102 turns on, and the main discharge transistor 101 and the auxiliary discharge transistor 102 turn on together, discharging the electrostatic charge from the power supply terminal 201 to the ground terminal 202. After a period of time, the main discharge transistor 101 gradually turns off and stops discharging electrostatic charge. At this time, the auxiliary discharge transistor 102 is still on, and continues to discharge the remaining electrostatic charge to the ground terminal 202.

[0058] At the instant the electrostatic pulse arrives, the main discharge transistor 101 is turned on first, discharging part of the electrostatic charge. In addition, the impedance change on the first segment 2031 and the second segment 2032 of the power supply metal line can also reflect part of the high-frequency pulse signal, weakening the intensity of the electrostatic pulse transmitted to the internal circuit through the power supply metal line. Through the discharge of the main discharge transistor and the reflection of the impedance change, excessive accumulation of electrostatic charge can be avoided, so that the voltage at the power supply terminal caused by the accumulation of electrostatic charge does not rise too fast, thereby effectively preventing damage to the protected circuit caused by the electrostatic pulse.

[0059] The auxiliary discharge transistor 102 is turned on later. After both the main discharge transistor 101 and the auxiliary discharge transistor 102 are turned on, the main discharge transistor 101 and the auxiliary discharge transistor 102 discharge the electrostatic charge. At this time, the impedance change will continue to reflect the electrostatic pulse signal. After a period of time, the main discharge transistor 101 gradually turns off, while the auxiliary discharge transistor 102 remains on, continuing to discharge the electrostatic charge, thus extending the electrostatic discharge time and improving the electrostatic discharge capability.

[0060] In one embodiment, the power metal line is located within the topmost metal layer M3 of the chip, which facilitates the routing of the power metal line. This allows for the increase of impedance abrupt change value by changing the routing method of the power metal line, thereby enhancing the reflection of high-frequency pulse signals by the impedance abrupt change.

[0061] In one embodiment, such as Figure 4a and Figure 4b As shown, the angle between the second segment 2032 and the first segment 2031 of the power metal line at their contact points includes a right angle or an acute angle. By setting it in this way, the impedance change on the second segment 2032 and the third segment 2033 of the power metal line can be increased, thereby improving the ability of the impedance change to reflect high-frequency pulse signals and reducing the damage of electrostatic pulses to the internal circuit.

[0062] In one embodiment, such as Figure 4c As shown, the angle between the second segment 2032 and the first segment 2031 of the power metal wire is less than 180 degrees, and the angle between the second segment 2032 and the third segment 2033 of the power metal wire is less than 180 degrees. By setting it in this way, the impedance change rate on the second segment 2032 and the third segment 2033 of the power metal wire can be further increased.

[0063] When laying out power metal lines on the top metal layer, they are usually routed in a straight line. However, in the above embodiment, by making the contact point between the second segment 2032 and the first segment 2031 of the power metal line have an angle of less than 180 degrees, the impedance change on the second segment 2032 and the third segment 2033 of the power metal line can be increased. This impedance change can reflect part of the high-frequency pulse signal, thereby effectively preventing damage to the protected circuit caused by electrostatic pulses. Furthermore, this layout of the power metal lines has a minimal impact on the routing space and parasitic resistance, and will not affect the normal power-on of the internal circuit.

[0064] In the above technical solution, the main discharge transistor turns on before the auxiliary discharge transistor. This allows the main discharge transistor to discharge electrostatic charge the instant the electrostatic pulse arrives. Furthermore, the impedance change between the first segment of the power supply metal line and the internal circuitry also reflects part of the high-frequency pulse signal, preventing the voltage at the power supply terminal from rising too quickly due to the accumulation of electrostatic charge, thus protecting the internal circuitry. In addition, while the main discharge transistor gradually turns off, the auxiliary discharge transistor remains on, continuing to discharge any remaining electrostatic charge, extending the discharge time and improving the electrostatic discharge capability.

[0065] like Figure 5 As shown, another embodiment of this application provides an electrostatic discharge (ESD) protection circuit 100, which is located between a power supply terminal 201 and a ground terminal 202. A power supply metal line disposed at the power supply terminal includes a first segment 2031, a second segment 2032, and a third segment 2033. The routing method of the power supply metal line has been described in detail in the above embodiments and will not be repeated here. Due to the special design of the power supply metal line routing, the effect of impedance abrupt change can be equivalent to... Figure 5 The resistor r in the middle, and Figures 6 to 9The resistor 'r' in the diagram also represents a change in impedance. In reality, because the resistor 'r' is a physical metal trace within the chip, it includes both a resistance value and an inductance value. The magnitude of these values ​​depends on the length, width, and conductivity of the physical trace. While this application uses resistor 'r' to represent an impedance change, the resistance and inductance values ​​of 'r' also have additional effects on electrostatic pulses. For example, an increased impedance change often leads to an increase in parasitic inductance. For high-frequency signals, a larger parasitic inductance stores more energy from the electrostatic pulse, which helps reduce damage to internal circuitry.

[0066] The electrostatic discharge protection circuit 100 includes a main discharge transistor 101, an auxiliary discharge transistor 102, a monitoring unit 103, and a delay circuit 104. The monitoring unit 103 has an output terminal, and the main discharge transistor 101 has a control terminal, a first terminal, and a second terminal. The output terminal of the monitoring unit 103 is connected to the control terminal of the main discharge transistor 101. The first terminal of the main discharge transistor 101 is connected to the first segment 2031 of the power supply metal line, and the second terminal of the main discharge transistor 101 is connected to the ground terminal 202.

[0067] The delay circuit 104 has an input terminal and an output terminal. The auxiliary discharge transistor 102 has a control terminal, a first terminal, and a second terminal. The control terminal of the main discharge transistor 101 is also connected to the input terminal of the delay circuit 104, and the output terminal of the delay circuit 104 is connected to the control terminal of the auxiliary discharge transistor 102. The first terminal of the auxiliary discharge transistor 102 is also connected to the first segment 2031 of the power supply metal line, and the second terminal of the auxiliary discharge transistor 102 is connected to the ground terminal 202.

[0068] The monitoring unit 103 monitors electrostatic pulses caused by static charge on the power supply terminal 201 and outputs a control signal when a static pulse is detected to control the main discharge transistor 101 to turn on first, discharging the static charge to the ground terminal 202 in a timely manner. The delay circuit delays the control signal output by the monitoring unit 103 and converts it into a control signal that can turn on the auxiliary discharge transistor 102. The auxiliary discharge transistor 102 then turns on under the control of the main discharge transistor 101, discharging the static charge together with the main discharge transistor 101. After the static charge has been discharged for a period of time, the control signal at the output of the monitoring unit 103 switches, causing the main discharge transistor 101 to gradually turn off and stop discharging static charge. At this time, the control signal output by the delay circuit 104 needs to be delayed for a period of time before switching, and the auxiliary discharge transistor 102 continues to turn on, discharging the remaining static charge on the power supply terminal 201. After the control signal output by the delay circuit 104 switches, the auxiliary discharge transistor 102 gradually turns off. The delay time of the delay circuit 104 can be set according to the actual process conditions, such as hundreds of picoseconds or several nanoseconds.

[0069] In one embodiment, the main discharge transistor 101 is larger than the auxiliary discharge transistor 102, meaning the main discharge transistor 101 has a higher discharge capability than the auxiliary discharge transistor 102. The main discharge transistor 101 discharges most of the electrostatic charge. At the moment an electrostatic pulse arrives, the monitoring unit 103 controls the main discharge transistor 101 to turn on promptly, discharging the electrostatic charge to the ground terminal 202 with a larger discharge current. Furthermore, the impedance change of the first segment 2031 and the second segment 2032 of the power supply metal line can reflect part of the high-frequency pulse signal, weakening the intensity of the electrostatic pulse transmitted to the internal circuit through the power supply metal line. Through the discharge of the main discharge transistor and the reflection of the impedance change, the voltage on the power terminal 201 does not rise too quickly due to the accumulation of electrostatic charge. The auxiliary discharge transistor 102 continues to discharge the remaining electrostatic charge after the main discharge transistor 101 is turned off, enhancing the electrostatic discharge capability of the electrostatic protection circuit 100, thereby protecting the internal circuit 300.

[0070] refer to Figure 6 In one embodiment, the main discharge transistor 101 is an N-type transistor, and the auxiliary discharge transistor 102 is a P-type transistor. The monitoring unit 103 includes a monitoring capacitor C1 and a monitoring resistor R1. The monitoring capacitor C1 has a first terminal and a second terminal, and the monitoring resistor R1 also has a first terminal and a second terminal. The first terminal of the monitoring capacitor C1 is connected to the first segment 2031 of the power supply metal line, and the second terminal of the monitoring resistor R1 is connected to the ground terminal 202. The first terminal of the monitoring resistor R1 is connected to the second terminal of the monitoring capacitor C1, serving as the output terminal of the monitoring unit 103.

[0071] The delay circuit 104 includes a first inverter 1041, the input terminal of which serves as the input terminal of the delay circuit 104, and the output terminal of which serves as the output terminal of the delay circuit 104. The first inverter 1041 includes a first driving transistor P1 and a second driving transistor N1. The first driving transistor P1 is a P-type transistor, and the second driving transistor N1 is an N-type transistor.

[0072] The source of the first driving transistor P1 is connected to the first segment 2031 of the power supply metal line, and the source of the second driving transistor N1 is connected to the ground terminal 202. The drain of the first driving transistor P1 is connected to the drain of the second driving transistor N1, serving as the output terminal of the first inverter 1041. The gates of the first driving transistor P1 and the second driving transistor N1 are connected, serving as the input terminal of the first inverter 1041.

[0073] The gate of the main discharge transistor N01 is connected to the second terminal of the monitoring capacitor C1. The gates of the first driving transistor P1 and the second driving transistor N1 are also connected to the second terminal of the monitoring capacitor C1. The drains of the first driving transistor P1 and the second driving transistor N1 are connected to the gate of the auxiliary discharge transistor P02.

[0074] The following is combined with Figure 6 Describe the working principle of the electrostatic discharge protection circuit 100:

[0075] In the first stage, when an electrostatic pulse arrives, for example, during the process of the power supply voltage VCC rising from 0V to 1V, the rise time is 1ns (after Fourier decomposition, the fundamental frequency can be considered to be approximately 1GHz). Since the equivalent impedance of the monitoring capacitor C1 for high-frequency signals is 1 / (2*π*f*C1), the smaller the rise time, the higher the frequency of the signal, and the smaller the equivalent impedance of the monitoring capacitor C1, the voltage at node D1 can be approximated as VCC. The main discharge transistor N01 gradually turns on, and the second driving transistor N1 also gradually turns on. The electrostatic charge is discharged to the ground terminal through the first segment 2031 of the power supply metal line and the main discharge transistor N01.

[0076] After the second driving transistor N1 is turned on, the voltage at node D2 is pulled down to GND. This means that the voltage at node D2 will only be pulled down to GND after the turn-on time of the second driving transistor N1. The first inverter 1041 outputs a low-level signal, and the auxiliary discharge transistor P0 gradually turns on under the control of this low-level signal. Static charge is discharged to the ground terminal through the first segment 2031 of the power supply metal line and the auxiliary discharge transistor P02.

[0077] When an electrostatic pulse arrives, the impedance change on the first segment 2031 and the second segment 2032 of the power supply metal line can also reflect part of the high-frequency pulse signal, reducing the intensity of the electrostatic pulse signal transmitted to the internal circuit through the power supply metal line.

[0078] The conduction of the main discharge transistor N01 and the auxiliary discharge transistor P02, as well as the reflection of the electrostatic pulse by the impedance change, will slow down the rate at which the power supply voltage VCC continues to rise to some extent. However, because the discharge rate of the main discharge transistor N01 and the auxiliary discharge transistor P02 at this stage, and the amount of reflection of the electrostatic pulse signal by the impedance change are less than the rate of charge accumulation, the power supply voltage VCC will continue to rise.

[0079] In the second stage, as the power supply voltage continues to rise, for example, as the power supply voltage VCC continues to rise from 1V to 2V, the conduction capability or discharge speed of the main discharge transistor N01 and the auxiliary discharge transistor P02 will become stronger and stronger, until the discharge speed of the main discharge transistor N01 and the auxiliary discharge transistor P02, as well as the reflection amount of the electrostatic pulse due to the impedance change, are equal to the speed of electrostatic charge accumulation, and the power supply voltage VCC will no longer continue to rise, for example, the power supply voltage VCC will stop rising after rising to 2V.

[0080] In the third stage, when the power supply voltage VCC rises slowly, or stops rising, or begins to fall, the monitoring resistor R1 is typically in the tens of kiloohms range. At this time, the equivalent impedance of the monitoring capacitor C1 increases, and the gate of the main discharge transistor N01 discharges through the monitoring resistor R1. The voltage at node D1 gradually decreases to GND, causing the main discharge transistor N01 to gradually turn off. However, the static charge on the power supply terminal 201 is not completely discharged. After the voltage at node D1 drops from the power supply voltage VCC to GND, the voltage at node D2 will not immediately rise from GND to the power supply voltage VCC. The auxiliary discharge transistor P02 continues to discharge the remaining static charge until node D2 is pulled up to the power supply voltage VCC, at which point the auxiliary discharge transistor P02 turns off. Furthermore, after the main discharge transistor turns off, the impedance abrupt change of the first segment 2031 and the second segment 2032 of the power supply metal line can still reflect some high-frequency pulse signals.

[0081] In the above technical solution, the main discharge transistor N01 turns on first when an electrostatic pulse arrives, promptly discharging the electrostatic charge. Its impedance change also reflects part of the high-frequency pulse signal, preventing the voltage at power supply terminal 201 from rising too quickly due to electrostatic charge accumulation, thus protecting the internal circuit 300. However, when the voltage on the power pad stops rising, the voltage at node D1 switches from high to low, and the main discharge transistor N01 gradually turns off. Meanwhile, the voltage at node D2 needs a delay of one P-type transistor's turn-on time to switch from low to high, allowing the auxiliary discharge transistor P02 to continue discharging the remaining electrostatic charge, extending the discharge time and improving the discharge capability.

[0082] refer to Figure 7 In one embodiment, both the main discharge transistor 101 and the auxiliary discharge transistor 102 are N-type transistors. The delay circuit 104 includes a first inverter 1041 and a second inverter 1042. The first inverter 1041 has an input terminal and an output terminal, and the second inverter 1042 also has an input terminal and an output terminal. The output terminal of the first inverter 1041 is connected to the input terminal of the second inverter 1042. The input terminal of the first inverter 1041 serves as the input terminal of the delay circuit 104, and the output terminal of the second inverter 1042 serves as the output terminal of the delay circuit 104. The monitoring unit 103 and the first inverter have the same structure. Figure 6 The structures shown in the embodiments are the same, and will not be described again here.

[0083] The second inverter 1042 includes a third driving transistor P2 and a fourth driving transistor N2. The third driving transistor P2 is a P-type transistor, and the fourth driving transistor N2 is an N-type transistor. The source of the third driving transistor P2 is connected to the first segment 2031 of the power supply metal line, and the source of the fourth driving transistor N2 is connected to the ground terminal 202. The drain of the third driving transistor P2 is connected to the drain of the fourth driving transistor N2, serving as the output terminal of the second inverter 1042. The gates of the third driving transistor P2 and the fourth driving transistor N2 are connected, serving as the input terminal of the second inverter 1042.

[0084] The gate of the main discharge transistor N01 is connected to the second terminal of the monitoring capacitor C1. The gates of the first driving transistor P1 and the second driving transistor N1 are also connected to the second terminal of the monitoring capacitor C1. The drains of the first driving transistor P1 and the second driving transistor N1 are connected to the gate of the third driving transistor P2. The drains of the third driving transistor P2 and the fourth driving transistor N2 are connected to the gate of the auxiliary discharge transistor N02.

[0085] In one embodiment, the auxiliary discharge transistor N02, the N-type transistor of the first inverter 1041, and the N-type transistor of the second inverter 1042 are all located in the same P-type well on the substrate. That is, the auxiliary discharge transistor N02, the second driving transistor N1, and the fourth driving transistor N2 are disposed in the same P-type well on the substrate. The auxiliary discharge transistor N02 is used to assist in discharging electrostatic charge. The size of the auxiliary discharge transistor N02 can be relatively small. Disposing the auxiliary discharge transistor N02, the second driving transistor N1, and the fourth driving transistor N2 in the same P-type well on the substrate allows for the layout of the integrated circuit, reducing the layout area.

[0086] In one embodiment, the main discharge transistor N01 and the auxiliary discharge transistor N02 are located in different P-type wells on the substrate. The main discharge transistor N01 discharges most of the electrostatic charge, while the auxiliary discharge transistor N02 discharges a small portion of the electrostatic charge. The discharge capability of the main discharge transistor N01 is higher than that of the auxiliary discharge transistor N02. By arranging the main discharge transistor N01 and the auxiliary discharge transistor N02 separately, mutual interference between them is avoided, thereby ensuring the discharge performance of both the main discharge transistor N01 and the auxiliary discharge transistor N02.

[0087] In another embodiment, the main discharge transistor N01 and the auxiliary discharge transistor N02 are located in the same P-type well on the substrate in order to arrange the layout of the integrated circuit and reduce the area of ​​the layout.

[0088] In one embodiment, the dimensions of the main discharge transistor N01 and the auxiliary discharge transistor N02 can be continuously optimized so that the main discharge transistor N01 can be turned on in a timely manner to discharge most of the electrostatic charge, while the auxiliary discharge transistor N02 continues to be turned on after the main discharge transistor N01 is turned off to discharge the remaining electrostatic charge. For example, the dimensions of the main discharge transistor N01 and the auxiliary discharge transistor N02 can be set to 10:1, 5:1, or 2:1.

[0089] The following is combined with Figure 7 Describe the principle of the electrostatic discharge protection circuit 100:

[0090] In the first stage, when an electrostatic pulse arrives, for example, during the rise of the power supply voltage VCC from 0V to 1V with a rise time of 1ns, the impedance of the monitoring capacitor C1 decreases when the high-frequency electrostatic pulse arrives, and the voltage at node D1 is approximately VCC. The main discharge transistor N01 gradually turns on. The electrostatic charge is discharged to the ground terminal through the first segment 2031 of the power supply metal line and the main discharge transistor N01.

[0091] The second driving transistor N1 gradually turns on. After N1 turns on, the voltage at node D0 is pulled down to GND. The third driving transistor P2 then turns on, and the voltage at node D2 is pulled up to the power supply voltage VCC. After the turn-on time delay of the second driving transistor N1 and the third driving transistor P2, the auxiliary discharge transistor N02 turns on. The electrostatic charge is discharged to the ground terminal through the first segment 2031 of the power supply metal line and the auxiliary discharge transistor N02.

[0092] When an electrostatic pulse arrives, the impedance change of the first segment 2031 and the second segment 2032 of the power supply metal line can also reflect part of the high-frequency pulse signal, reducing the peak value of the electrostatic pulse transmitted to the internal circuit through the power supply metal line.

[0093] In the second stage, as the power supply voltage continues to rise, for example, the power supply voltage VCC rises from 1V to 2V, the conduction capability or discharge speed of the main discharge transistor N01 and the auxiliary discharge transistor N02 will become stronger and stronger until the discharge speed of the main discharge transistor N01 and the auxiliary discharge transistor N02, as well as the reflection amount of the electrostatic pulse due to the impedance change, are equal to the speed of electrostatic charge accumulation. At this point, the power supply voltage VCC will no longer rise, for example, the power supply voltage VCC will stop rising after it reaches 2V.

[0094] In the third stage, when the power supply voltage VCC rises slowly, or stops rising, or begins to fall, and the monitoring resistor R1 is typically in the tens of kiloohms range, the equivalent impedance of the monitoring capacitor C1 increases. The gate of the main discharge transistor N01 discharges through the monitoring resistor R1, and the voltage at node D1 gradually decreases to GND, causing the main discharge transistor N01 to gradually turn off. However, the static charge on the power supply terminal 201 is not completely discharged. After the voltage at node D1 drops from VCC to GND, the voltage at node D2 does not immediately drop from VCC to GND. Instead, it is pulled down to GND only after the conduction time of the first driving transistor P1 and the fourth driving transistor N2. This allows the auxiliary discharge transistor N02 to continue discharging the remaining static charge until node D2 is pulled to GND and the auxiliary discharge transistor N02 turns off. Furthermore, after the main discharge transistor turns off, the impedance abrupt change of the first segment 2031 and the second segment 2032 of the power supply metal line can still reflect some high-frequency pulse signals.

[0095] In the above technical solution, when an electrostatic pulse arrives, the main discharge transistor N01 turns on first, followed by the auxiliary discharge transistor N02. The main discharge transistor N01 promptly discharges the electrostatic charge, and the impedance change reflects part of the high-frequency pulse signal, preventing the voltage at the power supply terminal 201 from rising too quickly due to the accumulation of electrostatic charge, thus protecting the internal circuit 300. After a period of time, the main discharge transistor N01 turns off, while the auxiliary discharge transistor N02 remains on due to the delay effect of the two-stage driving transistors, continuing to discharge the remaining electrostatic charge, thereby extending the discharge time.

[0096] refer to Figure 8 In one embodiment, the main discharge transistor 101 is a P-type transistor, and the auxiliary discharge transistor 102 is also an N-type transistor. The monitoring unit 103 includes a monitoring resistor R1 and a monitoring capacitor C1. The first end of the monitoring resistor R1 is connected to the first segment 2031 of the power supply metal line, and the second end of the monitoring capacitor C1 is connected to the ground terminal 202. The first end of the monitoring capacitor C1 is connected to the second end of the monitoring resistor R1, serving as the output terminal of the monitoring unit 103. The structure of the delay circuit has already been described. Figure 6 As described in the text, it will not be repeated here.

[0097] The following is combined with Figure 8 Describe the principle of the electrostatic discharge protection circuit 100:

[0098] In the first stage, when an electrostatic pulse arrives, for example, during the rise of the power supply voltage VCC from 0V to 1V with a rise time of 1ns, the impedance of the monitoring capacitor C1 decreases when the high-frequency electrostatic pulse arrives, and the voltage at node D1 is approximately GND. The main discharge transistor P01 gradually turns on. The electrostatic charge is discharged to the ground terminal through the first segment 2031 of the power supply metal line and the main discharge transistor P01.

[0099] The first driving transistor P1 gradually turns on. After the first driving transistor P1 turns on, the voltage at node D0 is pulled up to the power supply voltage VCC. After the delay of the first driving transistor P1's conduction time, the auxiliary discharge transistor N02 turns on. The electrostatic charge is discharged to the ground terminal through the first segment 2031 of the power supply metal line and the auxiliary discharge transistor N02.

[0100] When an electrostatic pulse arrives, the impedance change of the first segment 2031 and the second segment 2032 of the power supply metal line can also reflect part of the high-frequency pulse signal, reducing the intensity of the electrostatic pulse signal transmitted to the internal circuit through the power supply metal line.

[0101] In the second stage, as the electrostatic pulse continues to rise, for example, as the power supply voltage VCC rises from 1V to 2V, the conduction capability or discharge speed of the main discharge transistor P01 and the auxiliary discharge transistor N02 will become stronger and stronger until the discharge speed of the main discharge transistor P01 and the auxiliary discharge transistor N02, as well as the reflection amount of the electrostatic pulse due to the impedance change, are equal to the speed of electrostatic charge accumulation. At this point, the power supply voltage VCC will no longer rise, for example, it will stop rising after the power supply voltage VCC reaches 2V.

[0102] In the third stage, when the power supply voltage VCC rises slowly, or stops rising, or begins to fall, the monitoring resistor R1 is typically in the tens of kiloohms range. At this time, the equivalent impedance of the monitoring capacitor C1 increases, and the power supply voltage charges the gate of the main discharge transistor P01 through the monitoring resistor R1. The voltage at node D1 is pulled up to the power supply voltage VCC, causing the main discharge transistor P01 to gradually turn off. However, the electrostatic charge on power supply terminal 201 is not completely discharged at this point. After the voltage at node D1 is pulled up from GND to the power supply voltage VCC, the voltage at node D2 will not immediately drop from VCC to GND. Instead, it will be pulled down to GND only after the conduction time of the second driving transistor N1. The auxiliary discharge transistor N02 will continue to discharge the remaining electrostatic charge until node D2 is pulled down to GND, at which point the auxiliary discharge transistor N02 turns off.

[0103] refer to Figure 9 In one embodiment, the main discharge transistor 101 is a P-type transistor, and the auxiliary discharge transistor 102 is also a P-type transistor. The monitoring unit 103 includes a monitoring resistor R1 and a monitoring capacitor C1. The first end of the monitoring resistor R1 is connected to the first segment 2031 of the power supply metal line, and the second end of the monitoring capacitor C1 is connected to the ground terminal 202. The first end of the monitoring capacitor C1 is connected to the second end of the monitoring resistor R1, serving as the output terminal of the monitoring unit 103. The structure of the delay circuit has already been described. Figure 7 As described in the text, it will not be repeated here.

[0104] The following is combined with Figure 9 Describe the principle of the electrostatic discharge protection circuit 100:

[0105] In the first stage, when an electrostatic pulse arrives, for example, during the rise of the power supply voltage VCC from 0V to 1V with a rise time of 1ns, the impedance of the monitoring capacitor C1 decreases when the high-frequency electrostatic pulse arrives, and the voltage at node D1 is approximately GND. The main discharge transistor P01 gradually turns on. The electrostatic charge is discharged to the ground terminal through the first segment 2031 of the power supply metal line and the main discharge transistor P01.

[0106] The first driving transistor P1 gradually turns on. After P1 turns on, the voltage at node D0 is pulled up to the power supply voltage VCC. The fourth driving transistor N2 then turns on, and the voltage at node D2 is lowered to GND. After the delay caused by the turn-on times of the first driving transistor P1 and the fourth driving transistor N2, the auxiliary discharge transistor P02 turns on. The electrostatic charge is discharged to the ground terminal through the first segment 2031 of the power supply metal line and the auxiliary discharge transistor P02.

[0107] When an electrostatic pulse arrives, the impedance change of the first segment 2031 and the second segment 2032 of the power supply metal line can also reflect part of the high-frequency pulse signal, reducing the intensity of the electrostatic pulse signal transmitted to the internal circuit through the power supply metal line.

[0108] In the second stage, as the electrostatic pulse continues to rise, for example, as the power supply voltage VCC rises from 1V to 2V, the conduction capability or discharge speed of the main discharge transistor P01 and the auxiliary discharge transistor P02 will become stronger and stronger until the discharge speed of the main discharge transistor P01 and the auxiliary discharge transistor P02, as well as the reflection amount of the electrostatic pulse due to the impedance change, are equal to the speed of electrostatic charge accumulation. At this point, the power supply voltage VCC will no longer rise, for example, it will stop rising after the power supply voltage VCC reaches 2V.

[0109] In the third stage, when the power supply voltage VCC rises slowly, or stops rising, or begins to fall, the monitoring resistor R1 is typically in the tens of kiloohms. At this time, the equivalent impedance of the monitoring capacitor C1 increases, and the power supply voltage charges the gate of the main discharge transistor P01 through the monitoring resistor R1. The voltage at node D1 is pulled up to the power supply voltage VCC, causing the main discharge transistor P01 to gradually turn off. However, the static charge on the power supply terminal 201 is not completely discharged at this point. After the voltage at node D1 is pulled up from GND to the power supply voltage VCC, the voltage at node D2 will not immediately be pulled up from GND to VCC. Instead, it needs to be delayed by the conduction times of the second driving transistor N1 and the third driving transistor P2 before being pulled up to VCC. The auxiliary discharge transistor P02 continues to discharge the remaining static charge until node D2 is pulled up to the power supply voltage VCC, at which point the auxiliary discharge transistor P02 turns off. Furthermore, after the main discharge transistor is turned off, the impedance change of the first segment 2031 and the second segment 2032 of the power supply metal line can still reflect part of the high-frequency pulse signal.

[0110] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0111] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. An electrostatic discharge (ESD) protection circuit, disposed between a power supply terminal and a ground terminal on a chip, wherein an internal circuit connects the power supply terminal and the ground terminal, and a metal trace connected to the power supply terminal is referred to as a power supply metal trace, characterized in that, include: The monitoring unit is used to monitor electrostatic pulses on the power supply terminal; The main discharge transistor and the auxiliary discharge transistor are used to turn on after the electrostatic pulse is detected in order to discharge the electrostatic charge on the power supply terminal. The main discharge transistor turns on earlier than the auxiliary discharge transistor. Wherein, the first end of the main discharge transistor and the first end of the auxiliary discharge transistor are connected to the first segment of the power supply metal line, the first end of the internal circuit is connected to the third segment of the power supply metal line, the second segment of the power supply metal line is disposed between the first segment and the third segment of the power supply metal line, and the contact point between the second segment and the first segment of the power supply metal line has an angle of less than 180 degrees.

2. The electrostatic discharge protection circuit according to claim 1, characterized in that: The angle between the second segment of the power metal wire and the first segment of the power metal wire at their contact point includes a right angle or an acute angle.

3. The electrostatic discharge protection circuit according to claim 1, characterized in that: The second segment of the power supply metal wire and the third segment of the power supply metal wire have an angle of less than 180 degrees at their contact points.

4. The electrostatic discharge protection circuit according to claim 1, characterized in that: The power metal line is located within the topmost metal layer of the chip.

5. The electrostatic discharge protection circuit according to claim 1, characterized in that, The monitoring unit includes: A monitoring capacitor, the first end of which is connected to the first segment of the power supply metal wire; The monitoring resistor has its first end connected to the second end of the monitoring capacitor, and its second end connected to the grounding terminal.

6. The electrostatic discharge protection circuit according to claim 5, characterized in that, Also includes: The delay circuit has its input terminal connected to the control terminal of the main discharge transistor and its output terminal connected to the control terminal of the auxiliary discharge transistor.

7. The electrostatic discharge protection circuit according to claim 6, characterized in that, The delay circuit includes: The first inverter has its input terminal serving as the input terminal of the delay circuit, and its output terminal serving as the output terminal of the delay circuit.

8. The electrostatic discharge protection circuit according to claim 6, characterized in that: The main discharge transistor is an N-type transistor; The auxiliary discharge transistor is a P-type transistor.

9. The electrostatic discharge protection circuit according to claim 6, characterized in that, The delay circuit includes: The first inverter has its input terminal used as the input terminal of the delay circuit; The second inverter has its input connected to the output of the first inverter, and its output serves as the output of the delay circuit.

10. The electrostatic discharge protection circuit according to claim 9, characterized in that: The main discharge transistor is an N-type transistor; The auxiliary discharge transistor is an N-type transistor.

11. The electrostatic discharge protection circuit according to claim 9, characterized in that: The auxiliary discharge transistor, the N-type transistor of the first inverter, and the N-type transistor of the second inverter are all located in the same P-type well on the substrate; The main discharge transistor and the auxiliary discharge transistor are located in different P-type wells on the substrate.

12. The electrostatic discharge protection circuit according to claim 9, characterized in that: The main discharge transistor and the auxiliary discharge transistor are located in the same P-type well on the substrate.

13. The electrostatic discharge protection circuit according to claim 1, characterized in that: The size of the main discharge transistor is larger than the size of the auxiliary discharge transistor.

14. The electrostatic discharge protection circuit according to claim 1, characterized in that, The monitoring unit includes: A monitoring resistor, the first end of which is connected to the first segment of the power supply metal wire; A monitoring capacitor, the first end of which is connected to the second end of the monitoring resistor, and the second end of which is connected to the ground terminal.

15. The electrostatic discharge protection circuit according to claim 14, characterized in that: The main discharge transistor is a P-type transistor.

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