A real-time optimization method, system and device for inverter output voltage harmonics

Abstract

The present application provides a real-time optimization method, system and device for inverter output voltage harmonics, the method comprising: obtaining control parameters of an inverter; controlling the inverter to work according to the control parameters and obtaining N waveforms corresponding to N periods; decomposing the N waveforms to determine a to-be-processed waveform harmonic; when the amplitude of the to-be-processed waveform harmonic exceeds a harmonic threshold, a first optimization mode is used for optimization processing; when the amplitude of the to-be-processed waveform harmonic does not exceed the harmonic threshold, a second optimization mode is used for optimization processing. A method combining two harmonic reduction technologies is used, when the harmonic amplitude is small, the active filter function of the auxiliary inverter is used to reduce the harmonic, and the SHEPWM complex calculation is not used, when the harmonic amplitude is large, the SHEPWM technology is used to eliminate the harmonic, and the flexibility of inverter control is improved.

Description

Technical Field

[0001] This article belongs to the field of power electronic power conversion technology, specifically involving a real-time optimization method, system, and equipment for inverter output voltage harmonics. Background Technology

[0002] With economic and social development, energy use and conversion are playing an increasingly important role, and inverter technology is becoming increasingly important in various fields. In some high-voltage, high-current, and high-power applications, the inverter frequency cannot be increased indefinitely, but can only reach a level of several kHz. The total harmonic distortion (THD) of the inverter output waveform is a crucial indicator of its quality. Excessive harmonic distortion can cause significant damage to the load or the power grid. At lower switching frequencies, reducing THD requires superior modulation methods and control algorithms. Specific Harmonic Elimination Pulse Width Modulation (SHE-PWM) technology is an important one. It eliminates specific harmonics in the inverter output waveform by incorporating specific switching angles. This technology has significant application value in applications with high requirements for waveform quality and efficiency. SHE-PWM technology can optimize harmonics according to the design concept, but the calculation of the switching angle is a set of trans-nonlinear equations, which is difficult to solve and brings great obstacles to engineering applications. Some current optimization algorithms have certain problems in various aspects. Due to the large amount of computation required for real-time calculation, offline calculation and storage are usually used, and online table lookup is performed during real-time control. The problem with this is that the control method is fixed in the control chip code, making it difficult to optimize the actual control effect online. Moreover, sometimes the same control method is still used even when the harmonic amplitude is not large, which is not conducive to the flexibility of control. Summary of the Invention

[0003] To address the aforementioned problems in the prior art, the purpose of this paper is to provide a method, system, and device for real-time optimization of inverter output voltage harmonics, thereby improving the optimization efficiency of the inverter.

[0004] To solve the above-mentioned technical problems, the specific technical solution presented in this paper is as follows:

[0005] On the one hand, this paper provides a real-time optimization method for inverter output voltage harmonics, the method comprising:

[0006] Obtain the control parameters of the inverter;

[0007] Based on the control parameters, the inverter is controlled to operate, and N waveforms corresponding to N cycles are obtained;

[0008] The N waveforms are decomposed to determine the harmonics of the waveform to be processed;

[0009] If the amplitude of the harmonics of the waveform to be processed exceeds the harmonic threshold, the first optimization method is used for optimization processing.

[0010] If the amplitude of the harmonics of the waveform to be processed does not exceed the harmonic threshold, then the second optimization method is used for optimization processing.

[0011] Furthermore, obtaining the control parameters of the inverter includes:

[0012] Obtain the inverter output harmonic waveform;

[0013] The harmonic waveform is subjected to Fourier transform processing to obtain a specific harmonic elimination calculation model;

[0014] The specific harmonic elimination calculation model is solved using the simulated annealing algorithm to obtain the switching angle of the PWM control signal.

[0015] Furthermore, the specific harmonic elimination calculation model is as follows:

[0016]

[0017] Among them, f N (α) is the expression for the Nth equation in the system of harmonic equations to be eliminated, U sm(M) U represents the harmonic components, m represents the current modulation index of the inverter, and U represents the frequency response index. d Where is the DC voltage, N is the number of pulses in half a cycle, and M is the number of the highest harmonics to be eliminated.

[0018] Further, the step of decomposing the N waveforms to determine the harmonics of the waveform to be processed includes:

[0019] FFT decomposition is performed on the N waveforms to obtain the amplitude of specific harmonic elimination, thereby determining the harmonics of the waveform to be processed.

[0020] Furthermore, when the amplitude of the harmonics in the waveform to be processed exceeds the harmonic threshold, a first optimization method is used for optimization processing, including:

[0021] When the amplitude of the harmonics of the waveform to be processed exceeds the harmonic threshold, SHE-PWM modulation is used, and the relay of the second inverter is disconnected to complete the optimization of the inverter.

[0022] Furthermore, when the amplitude of the harmonics in the waveform to be processed does not exceed the harmonic threshold, a second optimization method is used for optimization processing, including:

[0023] When the amplitude of the harmonic of the waveform to be processed does not exceed the harmonic threshold, it is modulated by SPWM and the relay of the second inverter is controlled to close, so that the second inverter generates harmonic currents with equal amplitude and opposite phase and injects them into the bus. The line of the second inverter is connected to the bus, and the power of the second inverter is less than the power of the inverter.

[0024] On the other hand, this paper also provides a real-time optimization system for inverter output voltage harmonics, the system comprising: a controller, a main topology circuit and an auxiliary topology circuit;

[0025] The main topology circuit includes: a main DC source, a first switch, a second switch, a third switch, a fourth switch, a first capacitor, a second capacitor, and a first inductor; the first terminal of the first switch is connected to the positive terminal of the main DC source, and the second terminal of the first switch is connected to the first inductor; the first terminal of the second switch is connected to the negative terminal of the main DC source, the second terminal of the second switch is connected to the third terminal of the first switch, the first terminal of the third switch is connected to the positive terminal of the main DC source, the first terminal of the fourth switch is connected to the negative terminal of the main DC source, and the second terminals of the third and fourth switches are connected to form a first common terminal; the positive and negative terminals of the main DC source are also connected to the first capacitor, and the output terminal of the first inductor is connected to the first common terminal via a second capacitor;

[0026] The auxiliary topology circuit includes: an auxiliary DC power source, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a third capacitor, a fourth capacitor, a second inductor, and a relay; the first terminal of the fifth switch is connected to the positive terminal of the main DC power source, and the second terminal of the fifth switch is connected to the second inductor; the first terminal of the sixth switch is connected to the negative terminal of the main DC power source, and the second terminal of the sixth switch is connected to the third terminal of the fifth switch; the first terminal of the seventh switch is connected to the positive terminal of the main DC power source; the first terminal of the eighth switch is connected to the negative terminal of the main DC power source; the second terminals of the seventh switch and the eighth switch are connected to form a second common terminal; the positive and negative terminals of the main DC power source are also connected to the third capacitor; the output terminal of the second inductor is connected to the second common terminal, and the fourth capacitor is connected between them; the relay is located on the negative terminal circuit.

[0027] The controller controls the operation of the first, second, third, fourth, fifth, sixth, seventh, and eighth switching transistors, as well as the relay.

[0028] The voltage of the main DC source is greater than the voltage of the auxiliary DC source.

[0029] On the other hand, this paper also provides a real-time optimization device for inverter output voltage harmonics, the device comprising:

[0030] The acquisition module is used to acquire the control parameters of the inverter;

[0031] The control module is used to control the inverter to work according to the control parameters and obtain N waveforms corresponding to N cycles;

[0032] The determination module is used to decompose the N waveforms and determine the harmonics of the waveform to be processed;

[0033] The first optimization module is used to perform optimization processing using a first optimization method when the amplitude of the harmonics of the waveform to be processed exceeds the harmonic threshold.

[0034] The second optimization module is used to perform optimization processing using a second optimization method when the amplitude of the harmonics of the waveform to be processed does not exceed the harmonic threshold.

[0035] On the other hand, this document also provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that the processor, when executing the computer program, implements the method described above.

[0036] Finally, this document also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method described by the mulberry tree.

[0037] Using the above technical solution, this paper describes a real-time optimization method, system, and device for inverter output voltage harmonics. The method includes: acquiring inverter control parameters; controlling the inverter to operate according to the control parameters and obtaining N waveforms corresponding to N cycles; decomposing the N waveforms to determine the harmonics of the waveform to be processed; when the amplitude of the harmonics of the waveform to be processed exceeds the harmonic threshold, a first optimization method is used for optimization; when the amplitude of the harmonics of the waveform to be processed does not exceed the harmonic threshold, a second optimization method is used for optimization. This method combines two harmonic reduction techniques. When the harmonic amplitude is small, the active filtering function of the auxiliary inverter is used to reduce the harmonics without using the complex calculation of SHEPWM. When the harmonic amplitude is large, SHEPWM technology is used to eliminate the harmonics, thus improving the flexibility of inverter control.

[0038] To make the above and other objects, features and advantages of this document more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments or prior art described herein, the accompanying drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this article. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 The main topology diagram of the single-phase inverter in the embodiment of this paper is shown;

[0041] Figure 2 A topology diagram of the real-time optimization system for inverter output voltage harmonics provided in the embodiments of this article is shown.

[0042] Figure 3 A schematic diagram illustrating the steps of the real-time optimization method for inverter output voltage harmonics provided in the embodiments of this paper is shown.

[0043] Figure 4 The waveform of a single-phase inverter before filtering (continuous) is shown;

[0044] Figure 5 A schematic diagram of the output waveform of a single-phase inverter is shown.

[0045] Figure 6 A control logic flowchart of the method provided in the embodiments of this article is shown;

[0046] Figure 7 A schematic diagram of the device provided in the embodiments of this article is shown.

[0047] Explanation of symbols in the attached drawings:

[0048] 702. Computer equipment;

[0049] 704, Processor;

[0050] 706. Memory;

[0051] 708. Drive mechanism;

[0052] 710. Input / Output Module;

[0053] 712. Input devices;

[0054] 714. Output devices;

[0055] 716. Presentation equipment;

[0056] 718. Graphical User Interface;

[0057] 720. Network interface;

[0058] 722. Communication link;

[0059] 724. Communication bus. Detailed Implementation

[0060] The technical solutions in the embodiments described below will be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments described herein, and not all of the embodiments. Based on the embodiments described herein, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this document.

[0061] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings herein are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, apparatus, product, or device that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0062] In existing technologies, some optimization algorithms for harmonic optimization during inverter operation have certain problems in various aspects. Due to the large amount of computation required for real-time calculations, offline calculations are usually stored in memory, and online table lookups are performed during real-time control. This results in the control method being fixed in the control chip code, making it difficult to optimize the actual control effect online. Furthermore, sometimes the same control method is still used even when the harmonic amplitude is not large, which is detrimental to control flexibility.

[0063] To address the aforementioned problems, embodiments of this specification provide a real-time optimization system for inverter output voltage harmonics, such as... Figure 2 As shown, the system includes: a controller, a main topology circuit, and an auxiliary topology circuit;

[0064] The main topology circuit includes: a main DC source DC, a first switch Q1, a second switch Q2, a third switch Q3, a fourth switch Q4, a first capacitor C1, a second capacitor C1, and a first inductor L1; the first terminal of the first switch is connected to the positive terminal of the main DC source, and the second terminal of the first switch is connected to the first inductor; the first terminal of the second switch is connected to the negative terminal of the main DC source, the second terminal of the second switch is connected to the third terminal of the first switch, the first terminal of the third switch is connected to the positive terminal of the main DC source, the first terminal of the fourth switch is connected to the negative terminal of the main DC source, and the second terminals of the third and fourth switches are connected to form a first common terminal; the positive and negative terminals of the main DC source are also connected to the first capacitor, and a second capacitor is connected between the output terminal of the first inductor and the first common terminal;

[0065] In the main topology circuit, a load R is also connected. Optionally, the actual load may be a motor, etc., and is not necessarily purely resistive.

[0066] The auxiliary topology circuit includes: an auxiliary DC source DC1, a fifth switch Q5, a sixth switch Q6, a seventh switch Q7, an eighth switch Q8, a third capacitor C3, a fourth capacitor C4, a second inductor L2, and a relay S1; the first terminal of the fifth switch is connected to the positive terminal of the main DC source, and the second terminal of the fifth switch is connected to the second inductor; the first terminal of the sixth switch is connected to the negative terminal of the main DC source, and the second terminal of the sixth switch is connected to the third terminal of the fifth switch; the first terminal of the seventh switch is connected to the positive terminal of the main DC source; the first terminal of the eighth switch is connected to the negative terminal of the main DC source; the second terminals of the seventh switch and the eighth switch are connected to form a second common terminal; the positive and negative terminals of the main DC source are also connected to the third capacitor; a fourth capacitor is connected between the output terminal of the second inductor and the second common terminal; the relay is located on the negative terminal circuit;

[0067] The controller controls the operation of the first, second, third, fourth, fifth, sixth, seventh, and eighth switching transistors, as well as the relay.

[0068] This specification's embodiments, by adding an auxiliary inverter topology circuit to the main inverter topology circuit, can optimize the modulation of specific harmonics in the main inverter topology circuit through the auxiliary topology circuit. Specifically, these embodiments utilize the concept of active power filter technology, where the aforementioned auxiliary inverter topology circuit performs the function of an active power filter, injecting a current with specific harmonics to eliminate harmonics in the bus. Furthermore, the active power filter includes harmonic detection technology and specific harmonic current generation technology.

[0069] In the embodiments described in this specification, the voltage of the main DC source is greater than the voltage of the auxiliary DC source. This allows for higher efficiency while reducing costs. The auxiliary DC source can be used to provide DC power to various devices such as fuel cells, iron batteries, lead-acid batteries, and nickel-metal hydride batteries.

[0070] In the embodiments of this specification, the first switch Q1, the second switch Q2, the third switch Q3, the fourth switch Q4, the fifth switch Q5, the sixth switch Q6, the seventh switch Q7, and the eighth switch Q8 can all be MOSFET switches. The controller turns off each of these switches, for example, by controlling the switching frequency of the switches using PWM technology, thereby enabling the inverter to operate. Furthermore, the switches can be independent devices, or they can be a device combined with a diode, or a parasitic diode of the switch; this specification does not impose any limitations on these embodiments. The diodes can be fast recovery diodes, silicon diodes, Schottky diodes, etc.

[0071] In some other embodiments, a controller, i.e. a control system, can be set in both the main topology circuit and the auxiliary topology circuit. For example, both use TI's latest 200MHz 28377 chip. The two controllers can communicate with each other through the 28377D dual-core IPC communication module to improve the reliability and accuracy of control.

[0072] Based on the real-time optimization system for inverter output voltage harmonics provided above, this embodiment provides a real-time optimization method for inverter output voltage harmonics, which can achieve efficient optimization of harmonics in the inverter through the above system. Figure 3 This is a schematic diagram illustrating the steps of a real-time optimization method for inverter output voltage harmonics provided in the embodiments of this document. This specification provides the operational steps of the method described in the embodiments or flowcharts, but based on conventional or non-inventive labor, more or fewer operational steps may be included. The order of steps listed in the embodiments is merely one possible execution order among many and does not represent the only execution order. In actual system or device products, the methods shown in the embodiments or accompanying drawings can be executed sequentially or in parallel. Specifically, as shown in the embodiments or accompanying drawings... Figure 3 As shown, the method may include:

[0073] S201: Obtain the control parameters of the inverter;

[0074] S202: Control the inverter to work according to the control parameters and obtain N waveforms corresponding to N cycles;

[0075] S203: Decompose the N waveforms to determine the harmonics of the waveform to be processed;

[0076] S204: When the amplitude of the harmonics of the waveform to be processed exceeds the harmonic threshold, the first optimization method is used for optimization processing;

[0077] S205: If the amplitude of the harmonics of the waveform to be processed does not exceed the harmonic threshold, then the second optimization method is used for optimization processing.

[0078] This specification addresses the issue of harmonic distortion in the output waveform during inverter operation. The embodiments utilize different optimization methods for varying harmonic amplitudes, thereby achieving targeted harmonic processing and improving optimization efficiency. Specifically, it decomposes N waveforms during inverter operation to obtain the harmonics to be processed. Then, based on pre-set harmonic thresholds, the corresponding optimization method is determined. The embodiments employ a method combining two harmonic reduction techniques: when the harmonic amplitude is small, the active filtering function of the auxiliary inverter is used to reduce harmonics without employing complex SHEPWM calculations; when the harmonic amplitude is large, SHEPWM technology is used to eliminate harmonics. This method can be applied to grid-connected inverters and various types of inverters with loads.

[0079] In this illustrative embodiment, obtaining the control parameters of the inverter includes:

[0080] Obtain the inverter output harmonic waveform;

[0081] The harmonic waveform is subjected to Fourier transform processing to obtain a specific harmonic elimination calculation model;

[0082] The specific harmonic elimination calculation model is solved using the simulated annealing algorithm to obtain the switching angle of the PWM control signal.

[0083] This specification can be understood as determining the control parameters for the initial operation of the inverter, i.e., the switching angles of the switching transistors, based on SHE-PWM (Specific Harmonic Reduction Method). It should be noted that these switching angles can be the switching angles of the switching transistors in the main topology circuit. The process for obtaining these switching angles is as follows:

[0084] To filter out harmonics, we first need to analyze the causes of harmonics, such as... Figure 4 and Figure 5 This is a schematic diagram of the output harmonics of a single-phase inverter. The waveform is symmetrical in both the half-cycle and quarter-cycle phases, and satisfies the Dirichlet condition.

[0085] (1) Within a period, there are either continuous or only a finite number of first-type discontinuities;

[0086] (2) The number of maxima and minima within a period is finite;

[0087] (3) It is absolutely integrable within one period.

[0088] Fourier decomposition of the waveform yields:

[0089]

[0090] In the above formula, the following conditions are met:

[0091]

[0092]

[0093] in,

[0094] U d DC voltage

[0095] Due to symmetry, A n =0,

[0096] To analyze methods for eliminating harmonics, let's analyze the following formula separately:

[0097]

[0098] From this formula, we can see that the i-th harmonic is a function of the switching angle. By choosing an appropriate value, the i-th harmonic can be made zero, thus eliminating harmonics of a specific order. Essentially, this can be abstracted into a mathematical problem, namely, solving the following system of equations (i.e., a specific harmonic elimination calculation model):

[0099]

[0100] Among them, f N (α) is the expression for the Nth equation in the system of harmonic equations to be eliminated, U sm(M) U represents the harmonic components, m represents the current modulation index of the inverter, and U represents the frequency response index. d Where is the DC voltage, N is the number of pulses in half a cycle, and M is the number of the highest harmonics to be eliminated.

[0101] This problem can be abstracted into a mathematical problem: solving the aforementioned nonlinear transcendental equations. In research, traditional methods such as Newton's iteration can yield approximate solutions, but these solutions are not precise enough. In high-power applications, inaccurate solutions can have a significant impact. To obtain a more accurate solution, this embodiment employs a simulated annealing algorithm to solve this set of equations. The specific solution process is not detailed in this embodiment. The equations are solved offline beforehand, and the results are stored in memory and read by digital signal processing (DSP), thereby enabling the acquisition of inverter control parameters.

[0102] It should be noted that the above describes the process of obtaining control parameters for a single-phase inverter. When dealing with grid-connected inverters or other types of inverters with loads, a similar method can be used to obtain the parameters. The specific process will not be elaborated in the embodiments of this specification.

[0103] In the embodiments of this specification, the step of decomposing the N waveforms to determine the harmonics of the waveform to be processed includes:

[0104] FFT decomposition is performed on the N waveforms to obtain the amplitude of specific harmonic elimination, thereby determining the harmonics of the waveform to be processed.

[0105] The FFT algorithm is a fast algorithm for Discrete Fourier Transform (DFT). The specific calculation method is a conventional method in this field and is not limited in the embodiments of this specification. The FFT algorithm can process N waveforms to obtain the amplitude of the harmonics corresponding to different waveforms, and determine the harmonics of the waveform to be processed based on the amplitude. Furthermore, the total harmonic distortion (THD) value of the output waveform can be calculated based on the amplitude of the waveform harmonics corresponding to the N waveforms, and the harmonics of the waveform to be processed can be determined based on the THD.

[0106] In some other embodiments, an amplitude preset value can be set, and the waveform harmonics to be processed can be determined according to the relationship between the preset value and the amplitude of the waveform harmonics to be processed. For example, waveform harmonics exceeding the amplitude preset value can be determined as waveform harmonics to be processed. In some other embodiments, waveform harmonics with a specified period can be determined as waveform harmonics to be processed. The process of determining the waveform harmonics to be processed is not limited in the embodiments of this specification.

[0107] In the embodiments of this specification, when the amplitude of the harmonics of the waveform to be processed exceeds the harmonic threshold, a first optimization method is used for optimization processing, including:

[0108] When the amplitude of the harmonics of the waveform to be processed exceeds the harmonic threshold, SHE-PWM modulation is used, and the relay of the second inverter is disconnected to complete the optimization of the inverter.

[0109] Furthermore, when the amplitude of the harmonics in the waveform to be processed does not exceed the harmonic threshold, a second optimization method is used for optimization processing, including:

[0110] When the amplitude of the harmonic of the waveform to be processed does not exceed the harmonic threshold, it is modulated by SPWM and the relay of the second inverter is controlled to close, so that the second inverter generates harmonic currents with equal amplitude and opposite phase and injects them into the bus. The line of the second inverter is connected to the bus, and the power of the second inverter is less than the power of the inverter.

[0111] In one specific embodiment, the present invention uses a single-phase inverter as an example, but the actual control method can be extended to a three-phase inverter, or it can be derived from... Figure 1 The full-bridge inverter topology shown is extended to three-level and multi-level topologies. For example... Figure 1 This diagram shows a typical full-bridge inverter topology with a DC input. In the embodiments of this specification, both the main inverter and the auxiliary inverter adopt a full-bridge inverter topology, which has advantages such as simple structure and high DC voltage utilization. Figure 2 This document describes the inverter control system topology in the embodiments of this specification. Taking the application scenario of a large-scale photovoltaic energy storage power station grid-connected inverter as an example, DC is the main DC source, representing the photovoltaic panels of the large-scale photovoltaic power station. The intermediate DC / DC module is omitted. It is assumed that DC is a photovoltaic source that has undergone DC / DC conversion, and DC1 is assumed to be an energy storage battery or a small-scale photovoltaic cell. The main inverter is assumed to have a rated power of 1MW, and the auxiliary inverter has a rated power of 10kW. The main inverter is the main power output source of the grid-connected inverter, while the auxiliary inverter is the waveform adjustment module of the grid-connected inverter and has a smaller power. The control chip selected is the TI 28377D chip, a dual-CPU, dual-CLA coprocessor chip with 200MHz, 1024KB Flash, and 204KB RAM. The two cores control the main inverter and the auxiliary inverter respectively, communicating data through the chip's IPC communication module. The R on the right represents the simulated load. In actual use, this inverter can achieve grid connection and can also operate with various loads. The main principles of the inverter are not elaborated here.

[0112] like Figure 6 The control logic flowchart is shown below. The control steps in the embodiments of this specification are as follows: Define the harmonic threshold as ψ. D In this example, 5% of the total effective current value is set as the harmonic threshold. Before the inverter starts operating, the switching angle in the memory is read, and the inverter is driven. After several cycles, the waveforms of the inverter for N cycles are collected, FFT decomposition is performed, and the average THD value and the amplitude of the harmonics that need to be eliminated are calculated. When the harmonic amplitude is greater than ψ... D At this time, SHE-PWM (Specific Harmonic Elimination Method) is used for modulation, the relay of the auxiliary inverter is disconnected, and the harmonic amplitude is less than ψ. DAt this time, traditional SPWM is used for modulation, and the relay of the auxiliary inverter is closed to enable the active filtering function of the auxiliary inverter, thereby improving the effect of small harmonics.

[0113] This specification employs an embodiment that combines two harmonic reduction techniques. When the harmonic amplitude is small, the active filtering function of the auxiliary inverter is used to reduce harmonics without employing the complex calculations of SHEPWM. When the harmonic amplitude is large, SHEPWM technology is used to eliminate harmonics. This method can be applied to grid-connected inverters and various types of inverters with loads.

[0114] like Figure 7 As shown, a computer device provided in this embodiment is described. The apparatus described herein can be the computer device in this embodiment, performing the methods described above. The computer device 702 may include one or more processors 704, such as one or more central processing units (CPUs), each of which can implement one or more hardware threads. The computer device 702 may also include any memory 706 for storing information of any kind, such as code, settings, data, etc. Without limitation, for example, memory 706 may include any type of RAM, any type of ROM, flash memory device, hard disk, optical disk, etc. More generally, any memory can use any technology to store information. Further, any memory can provide volatile or non-volatile retention of information. Further, any memory may represent a fixed or removable component of the computer device 702. In one case, when processor 704 executes associated instructions stored in any memory or combination of memories, the computer device 702 can perform any operation of the associated instructions. The computer device 702 also includes one or more drive mechanisms 708 for interacting with any memory, such as hard disk drive mechanisms, optical disk drive mechanisms, etc.

[0115] Computer device 702 may also include an input / output module 710 (I / O) for receiving various inputs (via input device 712) and providing various outputs (via output device 714). A specific output mechanism may include a presentation device 716 and an associated graphical user interface (GUI) 718. In other embodiments, the input / output module 710 (I / O), input device 712, and output device 714 may be omitted, and the device may function solely as a computer device within a network. Computer device 702 may also include one or more network interfaces 720 for exchanging data with other devices via one or more communication links 722. One or more communication buses 724 couple the components described above together.

[0116] Communication link 722 can be implemented in any way, such as via a local area network, a wide area network (e.g., the Internet), a point-to-point connection, or any combination thereof. Communication link 722 may include any combination of hardwired links, wireless links, routers, gateway functions, name servers, etc., governed by any protocol or combination of protocols.

[0117] Corresponding to Figure 3 In addition to the methods described above, this embodiment also provides a computer-readable storage medium storing a computer program that, when executed by a processor, performs the steps of the above-described methods.

[0118] This embodiment also provides a computer-readable instruction, wherein when a processor executes the instruction, the program therein causes the processor to perform the following: Figure 3 The method shown.

[0119] It should be understood that in the various embodiments of this document, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this document.

[0120] It should also be understood that, in the embodiments herein, the term "and / or" is merely a description of the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following associated objects have an "or" relationship.

[0121] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this document.

[0122] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0123] In the embodiments provided herein, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the couplings or direct couplings or communication connections shown or discussed may be indirect couplings or communication connections through some interfaces, devices, or units, or they may be electrical, mechanical, or other forms of connection.

[0124] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of the embodiments described herein, depending on actual needs.

[0125] Furthermore, the functional units in the various embodiments of this document can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0126] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this paper, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this paper. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0127] This document uses specific embodiments to illustrate the principles and implementation methods of this document. The descriptions of the embodiments above are only for the purpose of helping to understand the methods and core ideas of this document. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this document. Therefore, the content of this specification should not be construed as a limitation of this document.

Claims

1. A real-time optimization method for inverter output voltage harmonics, characterized in that, The method includes: Obtain the control parameters of the inverter; Based on the control parameters, the inverter is controlled to operate, and N waveforms corresponding to N cycles are obtained; The N waveforms are decomposed to determine the harmonics of the waveform to be processed; If the amplitude of the harmonics of the waveform to be processed exceeds the harmonic threshold, the first optimization method is used for optimization processing. If the amplitude of the harmonics of the waveform to be processed does not exceed the harmonic threshold, then the second optimization method is used for optimization processing. When the amplitude of the harmonic of the waveform to be processed exceeds the harmonic threshold, the first optimization method is used for optimization processing, including: when the amplitude of the harmonic of the waveform to be processed exceeds the harmonic threshold, SHE-PWM is used for modulation, and the relay of the second inverter is disconnected to complete the optimization of the inverter. If the amplitude of the harmonics in the waveform to be processed does not exceed the harmonic threshold, then a second optimization method is used for optimization processing, including: when the amplitude of the harmonics in the waveform to be processed does not exceed the harmonic threshold, modulation is performed by SPWM, and the relay of the second inverter is controlled to close, so that the second inverter generates harmonic currents with equal amplitude and opposite phase and injects them into the bus, wherein the line of the second inverter is connected to the bus, and the power of the second inverter is less than the power of the inverter.

2. The method according to claim 1, characterized in that, The acquisition of inverter control parameters includes: Obtain the inverter output harmonic waveform; The harmonic waveform is subjected to Fourier transform processing to obtain a specific harmonic elimination calculation model; The specific harmonic elimination calculation model is solved using the simulated annealing algorithm to obtain the switching angle of the PWM control signal.

3. The method according to claim 2, characterized in that, The specific harmonic elimination calculation model is as follows: ； in, Let N be the expression for the Nth equation in the system of harmonic equations that needs to be eliminated. Let m be the harmonic components and m be the current modulation index of the inverter. Where is the DC voltage, N is the number of pulses in half a cycle, and M is the number of the highest harmonics to be eliminated.

4. The method according to claim 1, characterized in that, The step of decomposing the N waveforms to determine the harmonics of the waveform to be processed includes: performing FFT decomposition on the N waveforms to obtain the amplitude of the specific harmonics to be eliminated, thereby determining the harmonics of the waveform to be processed.

5. A real-time optimization system for inverter output voltage harmonics, characterized in that, The system includes: a controller, a main topology circuit, and an auxiliary topology circuit; The main topology circuit includes: a main DC source, a first switch, a second switch, a third switch, a fourth switch, a first capacitor, a second capacitor, and a first inductor; the first terminal of the first switch is connected to the positive terminal of the main DC source, and the second terminal of the first switch is connected to the first inductor; the first terminal of the second switch is connected to the negative terminal of the main DC source, and the second terminal of the second switch is connected to the second terminal of the first switch; the first terminal of the third switch is connected to the positive terminal of the main DC source; the first terminal of the fourth switch is connected to the negative terminal of the main DC source; the second terminals of the third switch and the fourth switch are connected to form a first common terminal; the positive and negative terminals of the main DC source are also connected to the first capacitor; and the output terminal of the first inductor is connected to the first common terminal via a second capacitor. The auxiliary topology circuit includes: an auxiliary DC source, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a third capacitor, a fourth capacitor, a second inductor, and a relay; the first terminal of the fifth switch is connected to the positive terminal of the auxiliary DC source, and the second terminal of the fifth switch is connected to the second inductor; the first terminal of the sixth switch is connected to the negative terminal of the auxiliary DC source, and the second terminal of the sixth switch is connected to the second terminal of the fifth switch; the first terminal of the seventh switch is connected to the positive terminal of the auxiliary DC source; the first terminal of the eighth switch is connected to the negative terminal of the auxiliary DC source; the second terminals of the seventh switch and the eighth switch are connected to form a second common terminal; the positive and negative terminals of the auxiliary DC source are also connected to the third capacitor; the output terminal of the second inductor is connected to the second common terminal, and the fourth capacitor is connected between them; the relay is disposed on the negative terminal circuit. The controller controls the operation of the first, second, third, fourth, fifth, sixth, seventh, and eighth switching transistors, as well as the relay, in accordance with the real-time optimization method for inverter output voltage harmonics as described in any one of claims 1-4.

6. The system according to claim 5, characterized in that, The voltage of the main DC source is greater than the voltage of the auxiliary DC source.

7. A real-time optimization device for inverter output voltage harmonics, characterized in that, The device includes: The acquisition module is used to acquire the control parameters of the inverter; The control module is used to control the inverter to work according to the control parameters and obtain N waveforms corresponding to N cycles; The determination module is used to decompose the N waveforms and determine the harmonics of the waveform to be processed; The first optimization module is used to perform optimization processing using a first optimization method when the amplitude of the harmonics of the waveform to be processed exceeds the harmonic threshold. The first optimization method includes: when the amplitude of the harmonics of the waveform to be processed exceeds the harmonic threshold, SHE-PWM is used for modulation, and the relay of the second inverter is disconnected to complete the optimization of the inverter. The second optimization module is used to perform optimization processing using a second optimization method when the amplitude of the harmonics of the waveform to be processed does not exceed the harmonic threshold. The second optimization method includes: when the amplitude of the harmonics of the waveform to be processed does not exceed the harmonic threshold, modulation is performed by SPWM, and the relay of the second inverter is controlled to close, so that the second inverter generates harmonic currents with equal amplitude and opposite phase and injects them into the bus, wherein the line of the second inverter is connected to the bus, and the power of the second inverter is less than the power of the inverter.

8. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the method as described in any one of claims 1 to 4.

Images