A synchronous rectification control method and circuit for clamped LLC converter

Abstract

The present invention discloses a synchronous rectification control method and circuit for a clamped LLC converter. The converter includes a synchronous rectification control circuit. The method includes: after the synchronous rectifier tube is turned on, entering a first operating state and starting timing at a preset first minimum on-time; during the first operating state, detecting a drive signal of the clamp tube of the converter; when a rising edge of the drive signal of the clamp tube is detected, entering a second operating state and starting timing at a preset second minimum on-time; after the second minimum on-time expires, outputting a shutdown permission signal to control the shutdown of the synchronous rectifier tube; if no rising edge of the drive signal of the clamp tube is detected, outputting a shutdown permission signal to control the shutdown of the synchronous rectifier tube after the first minimum on-time expires. The minimum on-time of the synchronous rectifier tube is controlled based on the drive signal of the clamp tube, and the minimum on-time of the synchronous rectifier tube is adaptively adjusted to avoid interference of hard switching of the power tube on the secondary-side synchronous rectification.

Description

Technical Field

[0001] The present invention relates to the field of switching converter control, and in particular to a synchronous rectification control method and circuit for a clamped LLC converter. Background Art

[0002] The clamped LLC converter not only achieves zero-voltage switching (ZVS) for the primary-side switching transistor and quasi-zero-current switching (ZCS) for the secondary-side rectifier, but also operates within a narrower frequency range than a traditional LLC converter within the same input voltage range. This overcomes the narrow voltage adjustment range of the LLC converter and makes it more suitable for products with a wide input / output voltage range. Compared to traditional diode rectification, synchronous rectification significantly improves efficiency by leveraging the low on-resistance of synchronous rectifiers. However, due to the added clamping branch and more complex operating modes, the clamped LLC converter can experience premature shutdown of the synchronous rectifiers due to interference from the primary side.

[0003] Figure 1 This is a schematic diagram of a clamped half-bridge LLC converter using synchronous rectification. The following takes the synchronous rectification control of the clamped half-bridge LLC converter as an example to illustrate the problem to be solved by the present invention. The clamped half-bridge LLC converter includes an inverter circuit 101, an LLC resonant cavity 102, a transformer 103, a secondary-side synchronous rectification circuit 104, an output filter circuit 105, a bridge arm tube S1 and a bridge arm tube S2, a clamping tube S3 and a clamping tube S4, wherein the bridge arm tube S1 is complementary to the clamping tube S3, the bridge arm tube S2 is complementary to the clamping tube S4, and the phase difference between the bridge arm tube S1 and the bridge arm tube S2 is 180°. The output voltage is adjusted by changing the duty cycle of the bridge arm tube S1 and the bridge arm tube S2. The typical working waveform is as follows: Figure 2As shown in Figure 1, during the period t1 to t2, the bridge arm transistor of the primary half-bridge clamped LLC converter is turned off and the clamp transistor is turned on. During this period, a large current still flows through the secondary synchronous rectifier transistor. The ringing phenomenon caused by the turning on and off of the power transistor can easily interfere with the detection of the synchronous rectification control, resulting in false triggering of the synchronous rectifier transistor. The duty cycle of the bridge arm transistor and the clamp transistor varies according to the steady-state output voltage. Therefore, hard switching of the power transistor may occur at any time during the entire switching cycle. Currently, commonly used synchronous rectification control ICs and control circuits only generate a fixed minimum on-time when the synchronous rectification is turned on to ensure that the synchronous rectifier tube will not be disturbed and mistakenly shut down when it is turned on. However, when the clamped LLC converter is in low-voltage output, the secondary-side synchronous rectification current is in discontinuous mode, so the fixed minimum on-time cannot be set too long, otherwise the on-time will be too long and cause energy backflow. However, since hard switching of the power tube may occur at any time in the entire switching cycle, if the fixed minimum on-time is too short, the fixed minimum on-time cannot ensure that the synchronous rectifier tube will not be disturbed and mistakenly shut down due to oscillation generated by the hard switching of the power tube. Therefore, setting a fixed minimum on-time through conventional control methods cannot solve the problem of mistaken shutdown caused by oscillation of the power tube hard switching during the switching tube cycle. Summary of the Invention

[0004] In view of this, the technical problem to be solved by the present invention is: for a clamped LLC converter, a minimum on-time adaptive synchronous rectification control method is proposed. By detecting the driving signal of the primary-side clamping tube, the minimum on-time of the synchronous rectifier tube is controlled, thereby adaptively adjusting the minimum on-time of the synchronous rectifier tube according to the clamping switch tube driving signal, avoiding the interference of the hard switching of the power tube on the secondary-side synchronous rectification, and ensuring the stable and efficient operation of the secondary-side synchronous rectification circuit.

[0005] In order to solve the above problems, the technical solution adopted by the present invention is:

[0006] In a first aspect, a synchronous rectification control method for a clamped LLC converter is provided, wherein the clamped LLC converter has a synchronous rectification control circuit, comprising:

[0007] After the synchronous rectifier tube of the clamped LLC converter is turned on, the synchronous rectification control circuit enters a first working state and starts timing with a preset first minimum on-time;

[0008] When the synchronous rectification control circuit is in the first working state, the driving signal of the clamping tube of the converter is detected;

[0009] When the synchronous rectification control circuit detects the rising edge of the driving signal of the clamp tube, it enters the second working state and starts timing with the preset second minimum on-time. After the preset second minimum on-time is finished, it outputs the shutdown permission signal to control the synchronous rectification tube to turn off;

[0010] When the synchronous rectification control circuit does not detect the rising edge of the driving signal of the clamp tube, it outputs a shutdown permission signal after the preset first minimum on-time ends to control the synchronous rectification tube to be turned off.

[0011] Furthermore, the method further includes: the synchronous rectification control circuit resets itself and enters a standby state while outputting a shutdown signal.

[0012] Furthermore, the shutdown signal is allowed to be a high level signal.

[0013] In a second aspect, a control circuit for synchronous rectification of a clamped LLC converter is provided, comprising a logic control circuit, a minimum on-time generating circuit, and a gate drive circuit;

[0014] The first input end of the logic control circuit is used to connect the driving signal of the clamping tube of the LLC converter, the second input end is connected to the second output end of the gate driving circuit, and the output end is connected to the input end of the minimum on-time generating circuit;

[0015] The output end of the minimum on-time generating circuit is connected to the first input end of the gate driving circuit;

[0016] The second input end of the gate drive circuit is used to connect to the state signal of the synchronous rectifier tube, and the first output end is used to connect to the drive signal generator of the synchronous rectifier tube;

[0017] When the state signal of the synchronous rectifier is a conduction signal, the gate drive circuit controls the logic control circuit to enter a first working state;

[0018] After the logic control circuit enters the first working state, it detects the driving signal of the clamping tube of the converter and controls the minimum on-time generating circuit to start timing with a preset first minimum on-time;

[0019] When the logic control circuit detects a rising edge of the driving signal of the clamp tube, it enters a second working state and controls the minimum on-time generating circuit to start timing with a preset second minimum on-time. After the second minimum on-time is finished, the minimum on-time generating circuit outputs a shutdown permission signal to control the gate driving circuit to output a first shutdown signal to control the synchronous rectifier tube to turn off;

[0020] When the logic control circuit does not detect the rising edge of the driving signal of the clamp tube, the minimum on-time generating circuit outputs a shutdown signal to control the gate drive circuit to output a first shutdown signal to control the synchronous rectifier tube to turn off after the preset first minimum on-time timing ends.

[0021] Furthermore, the state signal of the synchronous rectifier includes a turn-on signal and a turn-off signal; the gate drive circuit includes an AND gate circuit and a gate controller;

[0022] The first input end of the AND gate circuit serves as the first input end of the gate drive circuit, the second input end serves as the second input end of the gate drive circuit and is used to connect to the second shutdown signal of the synchronous rectifier tube, and the output end is connected to the first input end of the gate controller;

[0023] The second input end of the gate controller serves as the second input end of the gate drive circuit for connecting the conduction signal of the synchronous rectifier tube, the first output end serves as the first output end of the gate drive circuit, and the second output end serves as the second output end of the gate drive circuit.

[0024] Furthermore, when the state signal of the synchronous rectifier is a conduction signal, the gate drive circuit controls the logic control circuit to enter the first working state, which specifically includes:

[0025] When the state signal of the synchronous rectifier is a conduction signal, the gate drive circuit outputs a set signal to the logic control circuit;

[0026] After receiving the set signal, the logic control circuit enters a first working state and outputs a first timing signal to the minimum on-time generating circuit, so that the minimum on-time generating circuit starts timing with a preset first minimum on-time.

[0027] Furthermore, while the gate drive circuit outputs the first shutdown signal, it also outputs a reset signal to the logic control circuit; after receiving the reset signal, the logic control circuit is reset and enters a standby state.

[0028] Furthermore, the shutdown permission signal is a high level signal.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] (1) The present invention controls the minimum on-time of the synchronous rectifier tube by detecting the driving signal of the primary-side clamping tube, thereby adaptively adjusting the minimum on-time of the synchronous rectifier tube according to the driving signal of the clamping switch tube, thereby avoiding the problem of oscillation of the secondary-side synchronous rectifier circuit caused by oscillation generated by parasitic parameters when the primary-side bridge arm tube of the clamped LLC topology is turned off and the clamping tube is turned on, thereby causing the synchronous rectifier tube to be incorrectly turned off.

[0031] (2) The overall efficiency and stability of the clamped LLC converter are improved.

[0032] (3) The control method is accurate, reliable, simple to implement and low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a schematic diagram of a clamped half-bridge LLC converter in the prior art;

[0034] Figure 2 The typical operating waveform of the existing clamped half-bridge LLC converter is shown in FIG.

[0035] Figure 3 Schematic diagram of the clamped half-bridge LLC converter of the present invention;

[0036] Figure 4 1 is a schematic diagram of a synchronous rectification control circuit 200 of the present invention;

[0037] Figure 5 This is a flow chart of a synchronous rectification control method of the present invention;

[0038] Figure 6 The synchronous rectification working state waveform diagram of the existing clamped half-bridge LLC converter;

[0039] Figure 7 This is a waveform diagram of the synchronous rectification working state of the present invention. DETAILED DESCRIPTION

[0040] The following describes in detail specific embodiments of the synchronous rectification control method and circuit for a clamped LLC converter according to the present invention. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the present invention. Based on the described embodiments of the present invention, all other embodiments derived by persons of ordinary skill in the art without inventive effort are intended to fall within the scope of protection of the present invention.

[0041] In this embodiment, a control method for synchronous rectification of a clamped LLC converter is provided. The clamped LLC converter has a synchronous rectification control circuit 200, comprising the following steps:

[0042] After the synchronous rectifier tube of the clamped LLC converter is turned on, the synchronous rectification control circuit 200 enters the first working state and starts timing with a preset first minimum on-time;

[0043] When the synchronous rectification control circuit 200 is in the first working state, the driving signal of the clamping tube of the converter is detected;

[0044] When the synchronous rectifier control circuit 200 detects the rising edge of the driving signal of the clamp tube, it enters the second working state and starts timing with the preset second minimum on-time. After the preset second minimum on-time is finished, it outputs the shutdown permission signal to control the synchronous rectifier tube to turn off.

[0045] When the synchronous rectification control circuit 200 does not detect the rising edge of the driving signal of the clamp tube, it outputs a shutdown permission signal after the preset first minimum on-time ends to control the synchronous rectification tube to be turned off.

[0046] Specifically, such as Figure 3 FIG2 is a circuit diagram of an LLC converter according to an embodiment of the present invention; the synchronous rectification control method and control circuit according to the present embodiment are applied to a clamped LLC resonant converter composed of an inverter circuit 101, an LLC resonant cavity 102, a transformer 103, a secondary synchronous rectification circuit 104, an output filter circuit 105, and a synchronous rectification control circuit 200; the inverter circuit 101 may be a full-bridge topology or a half-bridge topology, which is not limited here; Figure 3 , SR1 and SR2 are synchronous rectifier tubes, S3 and S4 are clamping tubes, and S1 and S2 are bridge arm tubes.

[0047] In this embodiment, the synchronous rectification control circuit resets itself and enters a standby state while outputting the shutdown signal.

[0048] As a specific implementation of the shutdown permission signal, the shutdown permission signal is a high level signal.

[0049] In this embodiment, a synchronous rectification control circuit for a clamped LLC converter is provided, comprising a logic control circuit 201, a minimum on-time generating circuit 202, and a gate driving circuit 203;

[0050] The first input terminal of the logic control circuit 201 is used to connect the drive signal of the clamping transistor of the converter, the second input terminal is connected to the second output terminal of the gate drive circuit 203, and the output terminal is connected to the input terminal of the minimum on-time generating circuit 202;

[0051] The output terminal of the minimum on-time generating circuit 202 is connected to the first input terminal of the gate driving circuit 203;

[0052] The second input terminal of the gate driving circuit 203 is used to connect to the state signal of the synchronous rectifier tube, and the first output terminal is used to connect to the driving signal generator of the synchronous rectifier tube;

[0053] When the state signal of the synchronous rectifier is a conduction signal, the gate drive circuit 203 controls the logic control circuit 201 to enter the first working state;

[0054] After the logic control circuit 201 enters the first working state, it detects the driving signal of the clamping tube of the converter and controls the minimum on-time generating circuit 202 to start timing with a preset first minimum on-time;

[0055] When the logic control circuit 201 detects the rising edge of the driving signal of the clamping tube, it enters the second working state and controls the minimum on-time generating circuit 202 to start timing with the preset second minimum on-time. After the second minimum on-time is finished, the minimum on-time generating circuit outputs a shutdown permission signal to control the gate driving circuit 203 to output a shutdown signal to control the synchronous rectifier tube to turn off.

[0056] When the logic control circuit 201 does not detect the rising edge of the driving signal of the clamp tube, the minimum on-time generating circuit 202 outputs a shutdown signal to control the gate driving circuit 203 to output a first shutdown signal to control the synchronous rectifier tube to be turned off after the preset first minimum on-time timing ends.

[0057] Specifically, the state signal of the synchronous rectifier includes a turn-on signal and a second turn-off signal.

[0058] As a specific embodiment of the gate driving circuit 203, the gate driving circuit 203 includes an AND gate circuit 2031 and a gate controller 2032;

[0059] The first input terminal of the AND gate circuit 2031 serves as the first input terminal of the gate driving circuit 2032, the second input terminal serves as the second input terminal of the gate driving circuit 2032 and is used to connect to the second shutdown signal of the synchronous rectifier tube, and the output terminal is connected to the first input terminal of the gate controller 2031;

[0060] The second input end of the gate controller 2032 serves as the second input end of the gate driving circuit 203 for connecting the conduction signal of the synchronous rectifier tube, the first output end serves as the first output end of the gate driving circuit 203, and the second output end serves as the second output end of the gate driving circuit 203.

[0061] like Figure 4 As shown, Figure 4 1 is a schematic diagram of the control circuit described in this embodiment, including a logic control circuit 201, a minimum on-time generating circuit 202, and a gate drive circuit 203, wherein the gate drive circuit 203 includes an AND gate circuit 2031 and a gate controller 2032, the logic control circuit 201 is connected to the minimum on-time generating circuit 202 and the gate driver 2032 respectively, the minimum on-time generating circuit 202 is connected to the first input end of the AND gate circuit 2031, the output end of the AND gate circuit 2031 is connected to the gate driver 2032, and the synchronous rectification control signal SR_VG is output through the gate driver 2032.

[0062] It should be noted that the first input terminal of the logic control circuit 201 is connected to the drive signal Clamp_VG of the clamp tube of the converter, and the second input terminal of the logic control circuit 201 is connected to the set / reset signal Status_reset output by the gate driver 2032; the second input terminal of the AND gate circuit 2031 is connected to the first shutdown signal SR_offA of the synchronous rectifier tube, and its output terminal is connected to the shutdown input terminal (also called the first input terminal) of the gate controller 2032. The opening input terminal (also called the second input terminal) of the gate controller 2032 is connected to the conduction signal SR_on of the synchronous rectifier tube.

[0063] Specifically, Clamp_VG is a driving signal for the clamping tube, and a rising edge can be used as a trigger signal for the logic control circuit 201. In the specific implementation process of this embodiment, a rising edge is used as the trigger signal for the logic control circuit 201. Status_reset is a set / reset signal for the logic control circuit 201. When Status_reset is at a high level, it is a set signal, and when it is at a low level, it is a reset signal. SR_offA is a second turn-off signal for the synchronous rectifier tube, which is a high-level active signal. SR_on is a turn-on signal for the synchronous rectifier tube. Status is the status signal output by the logic control circuit 201. The first working state outputs a low level, and the second working state outputs a high level. Premit_off is the shutdown permission signal output by the minimum on-time generating circuit 202, which is a high-level valid signal. SR_offB is the output signal of the AND gate circuit 2031. SR_VG is the control signal of the synchronous rectifier tube output by the gate controller 2032. When SR_VG is at a high level, the control signal is an on signal, controlling the synchronous rectifier tube to turn on. When it is at a low level, it is a shut-off signal, controlling the synchronous rectifier tube to turn off.

[0064] Specifically, the principle of the circuit described in this embodiment is as follows: Assuming that the synchronous rectifier SR is turned off at the beginning, when the status signal of the synchronous rectifier is an on signal, that is, the gate driver 2032 receives the on signal SR_on, and after the gate controller 2032 enhances the driving capability, the control signal SR_VG of the synchronous rectifier is output as an on signal (high level), so that the synchronous rectifier is turned on. At the same time, the set / reset signal Status_reset of the logic control circuit becomes high level, and the logic control circuit 201 enters the first working state. The status signal Status output by the logic control circuit 201 is low level, and the drive signal Clamp_VG of the clamp tube is detected. The minimum on time generating circuit 202 starts timing with the first minimum on time. If the drive signal Clamp_VG of the synchronous rectifier is not detected until the first minimum on time is expired, The logic control circuit 201 enters the second working state, and the status signal Status output by the logic control circuit 201 is high. The minimum on-time generating circuit 202 starts timing with the second minimum on-time. After the second minimum on-time is over, the shutdown signal Premit_off is allowed to become high. When the shutdown signal Premit_off and the second shutdown signal SR_offA of the synchronous rectifier are both high, the output signal SR_offB of the AND gate circuit 2031 becomes high, thereby outputting the control signal SR_VG of the synchronous rectifier through the gate drive circuit as the first shutdown signal to control the shutdown of the synchronous rectifier. By detecting the primary-side clamp switch drive signal, the minimum on-time of the synchronous rectifier is controlled, thereby adaptively adjusting the minimum on-time of the synchronous rectifier according to the clamp switch drive signal. This avoids the problem of oscillation of the secondary-side synchronous rectifier circuit caused by oscillation due to parasitic parameters when the primary-side bridge arm tube is turned off and the clamp tube is turned on when the clamp tube is working, resulting in erroneous shutdown of the synchronous rectifier, thereby improving the overall efficiency and stability of the power converter.

[0065] like Figure 5 The figure is a flow chart of the control method of synchronous rectification according to this embodiment. Figure 5 The control method of this embodiment is described in detail with reference to the control circuit; specifically, the synchronous rectification control method includes steps 301 to 312, and adopts the above-mentioned synchronous rectification control circuit. The method includes the following steps:

[0066] Step 301: The synchronous rectifier is turned off and the synchronous rectification is controlled to a standby state.

[0067] In step 302, the gate driver 2032 receives the turn-on signal SR_on of the synchronous rectifier tube. After the gate controller 204 enhances the driving capability, it outputs the control signal SR_VG of the synchronous rectifier tube as the turn-on signal to turn on the synchronous rectifier tube. At the same time, it outputs the set / reset signal Status_reset of the logic control circuit 201 at a low level to set the logic control circuit 201, and then enters step 303.

[0068] In step 303 , the logic control circuit 201 enters the first working state and outputs a low-level status signal Status to the minimum time generating circuit 202 , and then proceeds to step 304 .

[0069] In step 304 , the minimum on-time generating circuit 202 starts timing with the first minimum on-time, and then the process goes to step 305 .

[0070] In step 305 , the logic control circuit 201 starts detecting a rising edge of the clamping transistor driving signal Clamp_VG. If no rising edge of the clamping transistor driving signal Clamp_VG is detected, the process proceeds to step 306 . If a rising edge of the clamping transistor driving signal Clamp_VG is detected, the process proceeds to step 308 .

[0071] In step 306, the first minimum on-time continues to be counted. Before the first minimum on-time expires, the logic control circuit 201 continuously detects the rising edge of the clamp transistor drive signal Clamp_VG. If a rising edge of the clamp transistor drive signal Clamp_VG is detected before the first minimum on-time expires, the first minimum on-time is stopped. If no rising edge of the clamp transistor drive signal Clamp_VG is detected before the first minimum on-time expires, the process proceeds to step 307 after the first minimum on-time expires.

[0072] Step 307 : The first minimum on-time is timed out, and the process proceeds to step 311 .

[0073] In step 308 , the logic control circuit 201 enters the second working state and outputs a high-level status signal Status to the minimum time generating circuit 202 , and then proceeds to step 309 .

[0074] In step 309 , the minimum on-time generating circuit 202 stops timing the first minimum on-time and starts timing the second minimum on-time, and then proceeds to step 310 .

[0075] Step 310 , the second minimum on-time timing ends, and the process proceeds to step 311 .

[0076] Step 311 : The minimum on-time of the synchronous rectifier ends, and the process goes to step 312 .

[0077] In step 312, the output signal SR_offB of the AND gate circuit 2031 becomes high, the gate controller 2032 outputs a low-level synchronous rectifier control signal SR_VG to turn off the synchronous rectifier, and outputs a low-level set / reset signal Status_reset of the logic control circuit 201 to reset the logic control circuit 201 and return to step 301.

[0078] Specifically, the first turn-off signal SR_offA and the turn-on signal SR_on of the synchronous rectifier are both sent by the external control chip. Before the minimum on-time is over, the hard turn-off of the bridge arm tube and the hard turn-on of the clamp tube will generate a ringing phenomenon, which is easy to interfere with the detection of the synchronous rectification control, resulting in the first turn-off signal SR_offA of the synchronous rectifier tube being falsely triggered. The AND gate circuit 2031 has received the first turn-off signal SR_offA sent by the external control chip.

[0079] By using the rising edge of the driving signal of the clamp tube as the trigger signal of the logic control circuit 201, and then controlling the minimum on-time generating circuit through the logic control circuit 201, the minimum on-time of the synchronous rectifier tube is adaptively adjusted according to the working state, thereby avoiding the interference of the hard switching of the power tube on the secondary side synchronous rectification, and ensuring the stable and efficient operation of the secondary side synchronous rectification circuit. The control method is accurate, reliable, simple and easy to implement, and low in cost.

[0080] Specifically, a 750W prototype is used to test the existing synchronous rectification control method and the synchronous rectification control method described in this embodiment. In order to illustrate the beneficial effects of the synchronous rectification control method and control circuit of this embodiment, except for the different synchronous rectification control methods and control circuits, the clamped LLC converter of the prior art used for comparison and the clamped LLC converter used in this embodiment are exactly the same, and the same circuit parameters are used during the test process. Figure 6 This is a waveform diagram of the synchronous rectification working state of the synchronous rectification control method using the existing technology. The existing technology generates a fixed minimum time when the synchronous rectification is turned on to ensure that the synchronous rectifier tube will not be disturbed and mistakenly turned off when it is turned on. Among them, S1_VG is the primary side bridge arm tube drive signal waveform, SR1_VG is the secondary side synchronous rectifier tube drive signal waveform, SR1_Vds is the secondary side synchronous rectifier tube voltage drop waveform, and Clamp_VG is the rising edge trigger signal waveform of the primary side clamp tube drive signal. The existing technology does not detect the clamp tube drive signal, so Figure 6 The waveform of the driving signal Clamp_VG of the clamping tube is a straight line without any change. In this embodiment, the dead time between the complementary bridge arm tube driving and the clamping tube driving is 200ns. Figure 6As shown, at moment Y2, which is the moment when the clamp tube is turned on, the synchronous rectification detection circuit is interfered by the primary clamp tube, causing the synchronous rectification drive to be turned off early. According to the amplitude of the SR1_Vds waveform, it can be seen that the synchronous rectification drive pulse width is from moment Y1 to moment Y2. It can be seen from the figure that moment Y1 is -820ns and moment Y2 is 0ns, that is, the synchronous rectification drive pulse width is 820ns. After the synchronous rectifier tube is turned off, the large current on the secondary side continues to flow through the body diode, reducing the efficiency of the whole machine.

[0081] Figure 7 FIG1 is a waveform diagram of the synchronous rectification working state after using the synchronous rectification control method and control circuit of this embodiment. In this embodiment, the dead time between the complementary bridge arm tube drive and the clamp tube drive is 200ns. Figure 7 As shown, by detecting the driving signal Clamp_VG of the clamp tube, and the rising edge of the driving signal Clamp_VG of the clamp tube is a trigger signal, when the primary clamp tube is turned on, the driving signal of the synchronous rectifier tube is normal. From the amplitude of the SR1_Vds waveform, it can be seen that the synchronous rectifier tube is in a normal conduction state. The conduction time of the synchronous rectifier tube is first turned on according to the first minimum conduction time. When the rising edge of the driving signal Clamp_VG of the clamp tube is detected within the first minimum conduction time, it is turned on according to the second conduction time. Figure 7 It can be seen that the synchronous rectification drive pulse width is from moment Y1 to moment Y2, moment Y1 is -1.11us, moment Y2 is 0us, that is, the synchronous rectification drive pulse width is 1.11us, compared with Figure 6 The waveform diagram of the synchronous rectification working state of the prior art shows that in this embodiment, the synchronous rectification drive pulse width is increased from 820ns to 1.11us, and the synchronous rectification conduction rate is increased from 61.1% to 82.4%, solving the problem of premature shutdown of the synchronous rectifier tube. The efficiency of the 750W prototype is improved by 0.5%-1.8% under different loads.

[0082] The description of the above embodiments is only used to help understand the inventive concept of the present invention and is not intended to limit the present invention. For ordinary technicians in this technical field, any modifications, equivalent substitutions, improvements, etc. made without departing from the principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A synchronous rectification control method for a clamped LLC converter, wherein the clamped LLC converter has a synchronous rectification control circuit, characterized in that: include: After the synchronous rectifier tube of the clamped LLC converter is turned on, the synchronous rectification control circuit enters a first working state and starts timing with a preset first minimum on-time; When the synchronous rectification control circuit is in the first working state, the driving signal of the clamping tube of the converter is detected; When the synchronous rectification control circuit detects the rising edge of the driving signal of the clamp tube, it enters the second working state and starts timing with the preset second minimum on-time. After the preset second minimum on-time is finished, it outputs the shutdown permission signal to control the synchronous rectification tube to turn off; When the synchronous rectification control circuit does not detect the rising edge of the driving signal of the clamp tube, it outputs a shutdown permission signal after the preset first minimum on-time ends to control the synchronous rectification tube to be turned off.

2. The control method according to claim 1, characterized in that: Also includes: The synchronous rectification control circuit resets itself and enters a standby state while outputting a shutdown signal.

3. The control method according to claim 1, wherein: The shutdown signal is allowed to be a high level signal.

4. A synchronous rectification control circuit for a clamped LLC converter, characterized in that: Including logic control circuit, minimum on-time generating circuit, gate drive circuit; The first input end of the logic control circuit is used to connect the driving signal of the clamping tube of the LLC converter, the second input end is connected to the second output end of the gate driving circuit, and the output end is connected to the input end of the minimum on-time generating circuit; The output end of the minimum on-time generating circuit is connected to the first input end of the gate driving circuit; The second input end of the gate drive circuit is used to connect to the state signal of the synchronous rectifier tube, and the first output end is used to connect to the drive signal generator of the synchronous rectifier tube; When the state signal of the synchronous rectifier is a conduction signal, the gate drive circuit controls the logic control circuit to enter a first working state; After the logic control circuit enters the first working state, it detects the driving signal of the clamping tube of the clamped LLC converter and controls the minimum on-time generating circuit to start timing with a preset first minimum on-time; When the logic control circuit detects a rising edge of the driving signal of the clamp tube, it enters a second working state and controls the minimum on-time generating circuit to start timing with a preset second minimum on-time. After the second minimum on-time is finished, the minimum on-time generating circuit outputs a shutdown permission signal to control the gate driving circuit to output a first shutdown signal to control the synchronous rectifier tube to turn off; When the logic control circuit does not detect the rising edge of the driving signal of the clamp tube, the minimum on-time generating circuit outputs a shutdown signal to control the gate drive circuit to output a first shutdown signal to control the synchronous rectifier tube to turn off after the preset first minimum on-time timing ends.

5. The control circuit according to claim 4, characterized in that: The state signal of the synchronous rectifier includes a turn-on signal and a second turn-off signal; the gate drive circuit includes an AND gate circuit and a gate controller; The first input end of the AND gate circuit serves as the first input end of the gate drive circuit, the second input end serves as the second input end of the gate drive circuit and is used to connect to the second shutdown signal of the synchronous rectifier tube, and the output end is connected to the first input end of the gate controller; The second input end of the gate controller serves as the second input end of the gate drive circuit for connecting the conduction signal of the synchronous rectifier tube, the first output end serves as the first output end of the gate drive circuit, and the second output end serves as the second output end of the gate drive circuit.

6. The control circuit according to claim 4, characterized in that: When the state signal of the synchronous rectifier is a conduction signal, the gate drive circuit controls the logic control circuit to enter a first working state, specifically including: When the state signal of the synchronous rectifier is a conduction signal, the gate drive circuit outputs a set signal to the logic control circuit; After receiving the set signal, the logic control circuit enters a first working state and outputs a first timing signal to the minimum on-time generating circuit, so that the minimum on-time generating circuit starts timing with a preset first minimum on-time.

7. The control circuit according to any one of claims 4 to 6, characterized in that: When the gate driving circuit outputs the first shutdown signal, it also outputs a reset signal to the logic control circuit; after receiving the reset signal, the logic control circuit resets and enters a standby state.

8. The control circuit according to claim 4, characterized in that: The shutdown permission signal is a high level signal.

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