An internal delay compensation method and device for a communication system device

Abstract

The present invention relates to an internal delay compensation method and device for a communication system device. The method includes the steps of: digitizing the output clock of a clock board, obtaining a first digital timestamp based on a reference clock source, and sending the first digital timestamp to a line board; digitizing the feedback clock of the output clock of the line board, and obtaining a second digital timestamp based on the reference clock source; adjusting the output clock of the line board based on the difference between the first digital timestamp and the second digital timestamp, so that the output clock of the line board is aligned with the output clock of the clock board. Therefore, based on the present invention, there is no need to design a feedback loop on the device backplane, which simplifies the system design and reduces the design requirements for the system clock routing at the same time.

Description

Technical Field

[0001] The present invention relates to the technical field of clock synchronization, and particularly to a method and device for internal delay compensation of communication system equipment. Background Art

[0002] Currently, in the 5G high-precision clock time system, the delay of a single-node device can reach 5 ns. Therefore, it is particularly important to perform delay compensation inside the device, and the delay compensation needs to consider the delay compensation in the static state and the dynamic compensation generated with time and temperature.

[0003] In the related art, the provided delay compensation method loops back a feedback clock from the line board to the clock board, measures the delay on the clock, and then compensates for the device delay. This method requires the backplane design to have a feedback loop during system design, and has strict requirements for the receive / transmit paths of the feedback loop to be exactly the same and phase-aligned, resulting in a more complex and stringent design for the system clock routing. Summary of the Invention

[0004] Embodiments of the present invention provide a method and device for internal delay compensation of communication system equipment, which do not require a feedback loop to be designed on the device backplane, simplifying the system design while reducing the design requirements for the system clock routing.

[0005] On the one hand, embodiments of the present invention provide a method for internal delay compensation of communication system equipment, which is characterized by including the steps of:

[0006] Digitize the output clock of the clock board, obtain a first digital timestamp based on the reference clock source, and send the first digital timestamp to the line board;

[0007] Digitize the feedback clock of the output clock of the line board and obtain a second digital timestamp based on the reference clock source;

[0008] Adjust the output clock of the line board based on the difference between the first digital timestamp and the second digital timestamp so that the output clock of the line board is aligned with the output clock of the clock board.

[0009] In some embodiments, the output clock of the clock board includes a system clock used inside the device generated based on an external time source or free oscillation;

[0010] The external time source includes: a satellite positioning system clock, a synchronous Ethernet clock, or a clock specified by a communication protocol.

[0011] In some embodiments, the digitizing the output clock of the clock board and obtaining a first digital timestamp based on the reference clock source includes the steps of:

[0012] Sampling the rising edge or falling edge position information of the output clock of the clock disk based on the reference clock source to obtain the first local timestamp information;

[0013] Based on the first local timestamp information and in combination with the second timestamp information measured by the TDC, obtaining the first digital timestamp based on the reference clock source.

[0014] In some embodiments, the manner of sending the first digital timestamp to the line board includes:

[0015] Using a dedicated hardware line, bus transmission, or transmission based on the internal message channel of the device.

[0016] In some embodiments, adjusting the output clock of the line board based on the difference between the first digital timestamp and the second digital timestamp includes the steps of:

[0017] Filtering the difference and inputting it into the digital oscillator built in the line board to obtain a control word for controlling the digital oscillator;

[0018] Adjusting the output clock of the line board based on the control word.

[0019] On the other hand, an embodiment of the present invention provides an internal delay compensation device for a communication system device, which is characterized in that it includes:

[0020] A first digital timestamp generation module, which is used to digitize the output clock of the clock disk, obtain the first digital timestamp based on the reference clock source, and send the first digital timestamp to the line board;

[0021] A second digital timestamp generation module, which is used to digitize the feedback clock of the output clock of the line board and obtain the second digital timestamp based on the reference clock source;

[0022] A clock alignment module, which is used to adjust the output clock of the line board based on the difference between the first digital timestamp and the second digital timestamp so that the output clock of the line board is aligned with the output clock of the clock disk.

[0023] In some embodiments, the output clock of the clock disk includes a system clock used inside the device generated based on an external time source or free oscillation;

[0024] The external time source includes: a satellite positioning system clock, a synchronous Ethernet clock, or a clock specified by a communication protocol.

[0025] In some embodiments, the first digital timestamp generation module is further used for:

[0026] Sampling the rising edge or falling edge position information of the output clock of the clock board based on the reference clock source to obtain the first local timestamp information;

[0027] Based on the first local timestamp information, combining with the second timestamp information measured by the TDC to obtain the first digital timestamp based on the reference clock source.

[0028] In some embodiments, the method of sending the first digital timestamp to the line board includes:

[0029] Using a dedicated hardware line, bus transmission, or transmission based on the internal message channel of the device.

[0030] In some embodiments, the clock alignment module is further configured to:

[0031] Filter the difference and input it into the digital oscillator built in the line board to obtain a control word for controlling the digital oscillator;

[0032] Adjust the output clock of the line board based on the control word.

[0033] The technical solution provided by the present invention converts the analog clock into a digital timestamp, and performs timestamp phase discrimination between two timestamps by comparing the local digital timestamp with the digital timestamp of the clock board on the line board side, and adjusts the output clock of the line board based on the phase discrimination result. Therefore, there is no need to form a feedback measurement loop for the clock between the clock board and the line board. At the same time, since the system clock output by the clock board is digitized and the analog clock is converted into a digital timestamp, it avoids the path delay asymmetry during the transmission of the analog clock and the uncertain delay caused by the devices on the path, and greatly simplifies the design of the high-precision clock system. Description of the Drawings

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0035] Figure 1 A method for compensating internal delay of a communication system device provided by an embodiment of the present invention;

[0036] Figure 2 A modular block diagram for high-precision phase compensation through a feedback loop provided by an embodiment of the present invention;

[0037] Figure 3 A modular block diagram for compensating internal delay of a communication system device provided by an embodiment of the present invention;

[0038] Figure 4 Schematic diagram of TDC measurement provided by the embodiment of the present invention;

[0039] Figure 5 An internal delay compensation device for a communication system device provided by the embodiment of the present invention. Specific implementation manner

[0040] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0041] As Figure 1 shown, the embodiment of the present invention provides an internal delay compensation method for a communication system device, including the steps:

[0042] S100: Digitalize the output clock of the clock board, obtain the first digital timestamp based on the reference clock source, and send the first digital timestamp to the line board;

[0043] S200: Digitalize the feedback clock of the line board output clock and obtain the second digital timestamp based on the reference clock source;

[0044] S300: Adjust the line board output clock based on the difference between the first digital timestamp and the second digital timestamp so that the line board output clock is aligned with the output clock of the clock board.

[0045] It should be noted that the output clock of the clock board can be generated by a clock module on the clock board, and this clock module can track an external timing source or freely oscillate to generate the output clock. The clock module can be an analog PLL (Phase Locked Loop), a digital PLL or other frequency generating units.

[0046] It should be noted that the reference clock source is a high-stability clock source, which is used to provide a reference for the output clock of the clock board. It can be an OCXO (Oven Controlled Crystal Oscillator), a TCXO (Temperature Compensate X'tal (crystal) Oscillator), a temperature-compensated crystal oscillator), an XO (Crystal Oscillator), or other high-stability clock sources.

[0047] It should be noted that, as Figure 2 shown, when designing a high-precision clock time system in the related art, in order to ensure that the system clock generated by the clock board and the system clock after regeneration by the line board have as small a delay as possible, and to ensure that this delay does not change under the influence of factors such as temperature, time, and the aging of the device itself, a measurement feedback loop is usually added between the clock board and the line board to measure the phase difference (delay) between the clock board and the line board in real time, and compensation is performed on the line board side. Therefore, the design difficulties caused by the related art include: the backplane clock loop must ensure the equality of the PCB path delays between the clock board to the line board and the line board to the clock board, and between the transmit and receive directions; the electrical and temperature characteristics of the driving devices or fan-out devices in the transmit and receive directions of the feedback loop are exactly the same; it is impossible to achieve complete consistency in terms of delay and electrical and temperature characteristics, and the actual measurement error cannot reach the ps level.

[0048] At the same time, when using the feedback measurement method for the internal clock board and line board of the device based on the related art, each partition (slot) needs to feedback a clock to the clock board, and the clocks of each partition (slot) are measured in real time on the clock board. The problems caused by this are as follows: the clock board requires a large number of terminals, and each partition (slot) needs to send a feedback clock back to the clock board; the delay measurements of all partitions (slots) are completed on the clock board, resulting in poor real-time performance; there are high requirements for the wiring of the clock board and the line board, and it is required that both the clock board and all line boards need to consider the equal-delay characteristics of the transmit and feedback direction clocks for wiring.

[0049] In view of the above problems, the internal device delay compensation method provided by the embodiments of the present invention converts the analog clock into a digital time stamp, and on the line board side, the local digital time stamp is phase-detected with the digital time stamp of the clock board, and the output clock of the line board is adjusted based on the phase-detection result. Therefore, there is no need to form a clock feedback measurement loop between the clock board and the line board. At the same time, since the system clock output by the clock board is digitized and the analog clock is converted into a digital time stamp, the path delay asymmetry during the transmission of the analog clock and the uncertain delay caused by the devices on the path are avoided, greatly simplifying the design of the high-precision clock system.

[0050] In some embodiments, the output clock of the clock board is used to synchronize external SyncE (Synchronous Ethernet), PTP (Precision Time Protocol), and GPS (Global Positioning System) clocks to generate the system clock used inside the device.

[0051] As Figure 3As shown, an output clock clock_out_1 is generated on the clock module. This output clock can be generated by the clock module according to free oscillation, or can be generated by the clock module according to a synchronous input clock source (clock_in). Based on the reference clock source, precise delay measurement is performed on clock_out_1 through a TDC (Time-Digital-Converter), and the ps-level phase deviation of clock_out_1 relative to the reference clock source is measured.

[0052] In some embodiments, S100 includes the steps of:

[0053] S110: Sampling the rising edge or falling edge position information of the output clock of the clock disk based on the reference clock source to obtain the first local timestamp information;

[0054] S120: Obtaining the first digital timestamp based on the reference clock source by combining the second timestamp information measured by the TDC on the basis of the first local timestamp information.

[0055] Preferably, the TDC can be implemented by an FPGA. Both the reference clock source and clock_out_1 are sent to the TDC, and the relative phase difference between clock_out_1 and the reference clock source can be measured. Specifically, in S110, the reference clock source samples the rising edge / falling edge position information (the first local timestamp information) of clock_out_1, and then combines the fine time information (the second timestamp information) measured by the TDC to generate an internal device timestamp time stamp (i.e., the first digital timestamp), which can convert the analog clock clock_out_1 into digital information of time stamp based on the reference clock source, and send this information to the service board (line board).

[0056] Specifically, starting from the reference clock source and counting until the rising edge / falling edge of clock_out_1 is detected, a coarse time information accurate to s (accurate to seconds s) can be generated at this time. Combining the fine time information (accurate to picoseconds ps) measured by the TDC generates an internal device timestamp time stamp. As Figure 4 shown, the reference clock samples the measured clock. Relative to the starting point 0, 3 is the coarse time information. Sampling only knows which rising edge of the reference clock samples the measured clock, and the time difference shown by the dotted line cannot be determined. The time difference in the dotted line is measured by the TDC to generate a fine timestamp, and combining the coarse and fine timestamps together is the complete timestamp.

[0057] It should be noted that the internal timestamp of the device indicates that this timestamp is only used internally within the device and not provided externally. The timestamps generated by the coarse time information and the fine time information also refer to the internal timestamp of the device, or the local timestamp, which describes how the internal timestamp of the device is generated.

[0058] In some embodiments, the method of sending the first digital timestamp to the line board includes: sending via a dedicated hardware line, a bus, or based on the internal message channel of the device.

[0059] Among them, the bus can be a hardware bus or an inter-disk communication method. The timestamp information is transmitted through the communication channel between the clock board and the line.

[0060] It should be noted that in step 200, the service board (line board) uses the same reference clock source as the clock board, and also performs precise phase measurement through the TDC based on the reference clock source, and timestamp (digitize) the local clock (line board output clock) generated by the PLL of the service board.

[0061] In some embodiments, in S300, a difference calculation (phase discrimination) is performed on the digitized second digital timestamp of the service board and the first digital timestamp sent by the clock board, and the control terminal of the PLL on the line board is controlled through this difference, so as to meet the requirement that the clock clock_out_2 output by the PLL on the line board is phase-aligned with the clock clock_out_1 output by the clock board.

[0062] It should be noted that the method of generating the timestamp by the line board is the same as that of the clock board, both of which digitize (adopt) the measured clock through the reference clock. Since the clock being sampled is the feedback clock of the dpll of the line board, after the line board digitizes the feedback clock of the dpll, it is still divided into the s level and the ps level. When performing a difference calculation (phase discrimination) on the timestamps of the clock board and the line board, the seconds (s) are subtracted from the seconds (s), and the picoseconds (ps) are subtracted from the picoseconds (ps). Therefore, the difference contains differences of two levels.

[0063] Preferably, S300 includes:

[0064] S310: Filter the difference and input it into the digital oscillator built in the line board to obtain a control word for controlling the digital oscillator;

[0065] S320: Adjust the output clock of the line board based on the control word.

[0066] It should be noted that when controlling the control terminal of the PLL on the circuit board through the difference, the control method of the DPLL (Digital Phase Locked Loop) can be used. At this time, the DPLL is equivalent to a DCO (Digital Crystal Oscillator), and the output of the DCO can be controlled by adjusting the control word of the DCO. Therefore, first, the difference is filtered. There are many filtering algorithms, such as the typical PID (Proportional, Integral, Differential) filtering. The difference is sent to the PID filter, and the PID filters and converts the difference, and controls the control word of the DPLL through the output of the PID, and finally completes the control of the output clock of the DPLL.

[0067] As Figure 5 shown, the embodiment of the present invention also discloses an internal delay compensation device for a communication system device, which includes:

[0068] A first digital timestamp generation module, which is used to digitize the output clock of the clock board, obtain a first digital timestamp based on the reference clock source, and send the first digital timestamp to the circuit board;

[0069] A second digital timestamp generation module, which is used to digitize the feedback clock of the output clock of the circuit board and obtain a second digital timestamp based on the reference clock source;

[0070] A clock alignment module, which is used to adjust the output clock of the circuit board based on the difference between the first digital timestamp and the second digital timestamp so that the output clock of the circuit board is aligned with the output clock of the clock board.

[0071] In some embodiments, the output clock of the clock board includes a system clock used inside the device generated based on an external time source or free oscillation; and the external time source includes: a satellite positioning system clock, a synchronous Ethernet clock, or a clock specified by a communication protocol.

[0072] In some embodiments, the first digital timestamp generation module is further used for:

[0073] Sampling the rising edge or falling edge position information of the output clock of the clock board based on the reference clock source to obtain first local timestamp information;

[0074] Obtaining the first digital timestamp based on the reference clock source by combining the second timestamp information measured by the TDC on the basis of the first local timestamp information.

[0075] In some embodiments, the method of sending the first digital timestamp to the circuit board includes:

[0076] It is sent using a dedicated hardware line, a bus, or based on an internal message channel of the device.

[0077] In some embodiments, the clock alignment module is further configured to:

[0078] Filter the difference value and input it into a digital oscillator built in the line board to obtain a control word for controlling the digital oscillator;

[0079] Adjust the output clock of the line board based on the control word.

[0080] Those of ordinary skill in the art can understand that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, and their appropriate combinations. In the hardware implementation, the division of the functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component can have multiple functions, or a function or step can be executed by several physical components in cooperation. Some physical components or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or can be implemented as hardware, or can be implemented as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable storage medium, which can include a computer-readable storage medium (or non-transitory medium) and a communication medium (or transitory medium).

[0081] It should be noted that in the present invention, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover a non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising a..." does not exclude the existence of additional identical elements in the process, method, article or device comprising the element.

[0082] The above are only specific embodiments of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but will be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A method for internal delay compensation of a communication system device, characterized in that, It includes the steps: Digitize the output clock of the clock board, obtain a first digital timestamp based on the reference clock source, and send the first digital timestamp to the line board; Digitize the feedback clock of the line board output clock and obtain a second digital timestamp based on the reference clock source; Adjust the line board output clock based on the difference between the first digital timestamp and the second digital timestamp so that the line board output clock is aligned with the output clock of the clock board; The digitizing the output clock of the clock board and obtaining a first digital timestamp based on the reference clock source includes the steps: Sample the rising edge or falling edge position information of the output clock of the clock board based on the reference clock source to obtain first local timestamp information; Obtain the first digital timestamp based on the reference clock source by combining the second timestamp information measured by the TDC on the basis of the first local timestamp information; The adjusting the line board output clock based on the difference between the first digital timestamp and the second digital timestamp includes the steps: Filter the difference and input it into the digital oscillator built in the line board to obtain a control word for controlling the digital oscillator; Adjust the line board output clock based on the control word.

2. The internal delay compensation method for a communication system device according to claim 1, wherein, The output clock of the clock board includes a system clock used inside the device generated based on an external time source or free oscillation; The external time source includes: satellite positioning system clock, synchronous Ethernet clock or clock specified by the communication protocol.

3. A method for internal delay compensation of a communication system device as described in claim 1, characterized in that, The manner of sending the first digital timestamp to the line board includes: Sending by using a dedicated hardware line, bus or based on the internal message channel of the device.

4. An internal delay compensation device for a communication system device, characterized in that, It includes: A first digital timestamp generation module, which is used to digitize the output clock of the clock board, obtain a first digital timestamp based on the reference clock source, and send the first digital timestamp to the line board; A second digital timestamp generation module, which is used to digitize the feedback clock of the line board output clock and obtain a second digital timestamp based on the reference clock source; A clock alignment module, which is used to adjust the line board output clock based on the difference between the first digital timestamp and the second digital timestamp so that the line board output clock is aligned with the output clock of the clock board; The first digital timestamp generation module is further used for: Sampling the rising edge or falling edge position information of the output clock of the clock board based on the reference clock source to obtain first local timestamp information; Obtaining the first digital timestamp based on the reference clock source by combining the second timestamp information measured by the TDC on the basis of the first local timestamp information; The clock alignment module is further used for: Filter the difference and input it into the digital oscillator built in the line board to obtain a control word for controlling the digital oscillator; Adjust the line board output clock based on the control word.

5. The internal delay compensation device of a communication system device according to claim 4, wherein, The output clock of the clock board includes a system clock used inside the device generated based on an external time source or free oscillation; The external time source includes: satellite positioning system clock, synchronous Ethernet clock or clock specified by the communication protocol.

6. The internal delay compensation device for a communication system device according to claim 4, wherein The manner of sending the first digital timestamp to the line board includes: It is sent using a dedicated hardware line, a bus, or based on the internal message channel of the device.

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