Data cache with prediction hints for cache hits

Abstract

This describes a data cache with predictive hints for cache hits. The data cache comprises multiple cache lines, each including a data field, a tag field, and a predictive hint field. The predictive hint field is configured to store a predictive hint that indicates replacement behavior for a cache hit for that cache line. This predictive hint field is integrated with either the tag field or the path predictor field.

Description

Technical Field

[0001] This disclosure relates to data caching, and more specifically, to data caching with predictive hints for cache hits. Background Technology

[0002] Processing systems use parallel processing to improve system performance by executing multiple instructions simultaneously. Regular load instructions run to return data as quickly as possible for better performance. However, running certain load instructions as quickly as possible can degrade system performance. For example, the use of out-of-order processing, branches, jumps, speculative processing, and combinations thereof can cause instructions to run before the data is ready for use. Therefore, the results of the execution must be flushed and the instructions re-executed. This results in a degraded system performance. Attached Figure Description

[0003] This disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, by convention, the various features in the drawings are not drawn to scale. Instead, for clarity, the dimensions of the various features have been arbitrarily enlarged or reduced.

[0004] Figure 1 This is a high-level block diagram of an example of a processing system for implementing a data cache with predictive hints, according to embodiments of the present disclosure.

[0005] Figure 2 This is a high-level block diagram of an example load storage unit for implementing a data cache with predictive hints according to embodiments of the present disclosure.

[0006] Figure 3 This is a block diagram of an example data cache according to an embodiment of the present disclosure.

[0007] Figure 4 This is another block diagram of an example data cache according to an embodiment of the present disclosure.

[0008] Figure 5 This is a diagram illustrating an example technique for implementing a data cache with predictive hints, according to embodiments of the present disclosure.

[0009] Figure 6 This is another diagram of an example technique for implementing a data cache with predictive hints, according to embodiments of the present disclosure. Detailed Implementation

[0010] This document discloses systems and methods for data caches with predictive hints for cache hits. A multiprocessor processing system can include multiple processors and memory. Each processor can have a data cache including an L1 data cache. A data cache is a hardware and / or software component that stores data to enable faster servicing of future requests for that data. A data cache can be a data cache that provides predictive hints for cache hits. Predictive hints can slow down or provide alternative behavior relative to certain instructions to improve system performance.

[0011] This describes a data cache that provides predictive hints for cache hits against a data cache. The data cache comprises multiple cache lines, each including a data field, a tag field, and a predictive hint field. The predictive hint field is configured to store a predictive hint that indicates alternative behavior for a cache hit against a cache line. The predictive hint field is integrated with either the tag field or the path predictor field. The predictive hint can disable load data return, speculative storage bypass, or other alternative behaviors in cases where there is no known risk of a read-after-write operation.

[0012] These and other aspects of this disclosure are made clear in the following detailed description, the appended claims and the accompanying drawings.

[0013] As used herein, the term “processor” refers to one or more processors, such as one or more dedicated processors, one or more digital signal processors, one or more microprocessors, one or more controllers, one or more microcontrollers, one or more application processors, one or more central processing units (CPUs), one or more graphics processing units (GPUs), one or more digital signal processors (DSPs), one or more application-specific integrated circuits (ASICs), one or more dedicated standard products, one or more field-programmable gate arrays, any other type or combination of integrated circuits, one or more state machines, or any combination thereof.

[0014] The term "circuit" refers to an arrangement of electronic components (e.g., transistors, resistors, capacitors, and / or inductors) configured to perform one or more functions. For example, a circuit may include one or more transistors interconnected to form logic gates that collectively perform a logic function. For example, a processor can be a circuit.

[0015] As used herein, the terms “determine” and “identify” or any variation thereof include selecting, detecting, calculating, finding, receiving, determining, establishing, obtaining, or otherwise identifying or determining, regardless of how one or more of the devices and methods shown and described herein are used.

[0016] As used herein, the terms “example,” “implementation,” “aspect,” “feature,” or “element” indicate that they are used as examples, instances, or illustrations. Unless expressly indicated, any example, embodiment, implementation, aspect, feature, or element is independent of each other and may be used in combination with any other example, embodiment, implementation, aspect, feature, or element.

[0017] As used herein, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless otherwise specified or clear from the context, “X comprises A or B” is intended to indicate any natural inclusion substitution. That is, “X comprises A or B” is satisfied if X comprises A; X comprises B; or X comprises both A and B. Additionally, unless otherwise specified or clear from the context for the singular form, the articles “a” and “an” as used herein and in the appended claims should generally be interpreted as meaning “one or more”.

[0018] Furthermore, for simplicity of explanation, although the figures and descriptions herein may include sequences or series of steps or stages, the elements of the methods disclosed herein may occur in various orders or simultaneously. Additionally, the elements of the methods disclosed herein may occur together with other elements not explicitly presented and described herein. Moreover, it may not be required that all elements of the methods described herein implement the methods according to this disclosure. Although aspects, features, and elements are described herein in specific combinations, each aspect, feature, or element may be used independently or in various combinations with or without other aspects, features, and elements.

[0019] It should be understood that the figures and descriptions of the embodiments have been simplified to illustrate elements relevant to clear understanding, while many other elements found in typical processors have been omitted for clarity. Those skilled in the art will recognize that other elements and / or steps are desired and / or necessary in carrying out this disclosure. However, because such elements and steps are detrimental to a better understanding of this disclosure, discussion of such elements and steps is not provided herein.

[0020] Figure 1This is a high-level block diagram of an example of a processing system 1000 with predictive hints for implementing a data cache according to embodiments of the present disclosure. The processing system 1000 is capable of implementing a pipelined architecture. The processing system 1000 can be configured to decode and execute instructions of an instruction set architecture (ISA) (e.g., RISC-V instruction set). Instructions can be executed speculatively and out of order in the processing system 1000. The processing system 1000 can be a computing device, a microprocessor, a microcontroller, or an IP core. The processing system 1000 can be implemented as an integrated circuit.

[0021] The processing system 1000 includes at least one processor core 1100. The processor core 1100 can be implemented using one or more central processing units (CPUs). Each processor core 1100 can be connected to one or more memory modules 1200 via an interconnect network 1300 and a memory controller 1400. The one or more memory modules 1200 can be referred to as external memory, main memory, backup registers, coherent memory, or backup infrastructure (collectively, "backup infrastructure").

[0022] Each processor core 1100 can include an L1 instruction cache 1500, which is associated with an L1 translation back buffer (TLB) 1510 for virtual-to-physical address translation. An instruction queue 1520 buffers instructions fetched from the L1 instruction cache 1500 based on branch prediction 1525 and other fetch pipeline processes. Dequeued instructions are renamed in a renaming unit 1530 to avoid erroneous data dependencies and are then dispatched by a dispatch / retreat unit 1540 to the appropriate back-end execution units, including, for example, a floating-point execution unit 1600, an integer execution unit 1700, and a load / store execution unit 1800. A physical register file and an FP register file 1610 can be allocated to the floating-point execution unit 1600, and a physical register file and an INT register file 1710 can be allocated to the integer execution unit 1700. FP register file 1610 and INT register file 1710 are also connected to load / store execution unit 1800, which can access L1 data cache 1900 via L1 data TLB 1910. L1 data TLB 1910 is connected to L2 TLB 1920, which in turn is connected to L1 instruction TLB 1510. L1 data cache 1900 is connected to L2 cache 1930, which is connected to L1 instruction cache 1500.

[0023] The processing system 1000 and each element or component within it are illustrative and can include additional, fewer, or different devices, entities, elements, components, etc., which can be similarly or differently structured without departing from the scope of this specification and claims. Furthermore, the illustrated devices, entities, elements, and components are capable of performing other functions without departing from the scope of this specification and claims. As an illustrative example, references to a data cache include a data cache controller for operational control of the data cache.

[0024] Figure 2 This is a high-level block diagram of an example load / store unit 2000 for implementing a processing system with predictive hints for data caching according to embodiments of the present disclosure. The load / store unit 2000 may include an issue queue 2100 that stores data from... Figure 1 The dispatch / retirement unit 1540 dispatches instructions. The issue queue 2100 can issue instructions to the load / store tag pipe 2200, which can then allocate entries in the load / store data pipe 2300, the load queue 2400, the store queue 2500, and the miss status processing register (MSHR) 2600. Store instructions buffer data in the store queue 2500 until committed, and then aggregate the write when regressing to the L1 data cache 2700 or MSHR 2600.

[0025] Load / store unit 2000 and each element or component in load / store unit 2000 are illustrative and can include additional, fewer, or different devices, entities, elements, components, etc., which can be similarly or differently structured without departing from the scope of the description and claims herein. Furthermore, the illustrated devices, entities, elements, and components are capable of performing other functions without departing from the scope of the description and claims herein.

[0026] Figure 3 This is a block diagram of an example load / store unit 3000 having an L1 data cache 3100 according to an embodiment of the present disclosure. The load / store unit 3000 may include an issue queue 3200 that stores data from... Figure 1The dispatch / retirement unit 1540 dispatches instructions. The issue queue 3200 can issue instructions to the load / store tag pipeline 3300, which processes data and memory addresses through the L1 data cache 3100. Specifically, data and memory addresses are processed through the L1 data cache tag array 3110, the prediction hint array 3120, the L1-way predictor array 3130, and the L1 data cache pipeline 3140. Prediction hint entries or fields in the prediction hint array 3120 can be one or more bits, one or more fields, and / or combinations thereof, depending on the implementation of the prediction hint logic, which can be any pre-compiled hint technique, partially decoded technique, re-encoded technique, table hint technique, etc., known to those skilled in the art. In some implementations, the prediction hint entry or field is a flag. In some implementations, the prediction hint entry or field is a substitute instruction. In some implementations, the prediction hint entry or field is both a flag and a substitute instruction. In some implementations, the prediction hint entry or field is a flag, a problematic instruction, and a substitute instruction. In one implementation, the prediction hint entry or field is a problematic instruction and an alternative instruction. In another implementation, the prediction hint entry or field is a combination of a flag, a problematic instruction, and / or an alternative instruction. The L1 data cache 3100 can have multiple cache lines, each cache line including at least entries from the L1 data cache tag array 3110, entries from the prediction hint array 3120, and entries from the path predictor array 3130. In another implementation, the L1 data cache tag array 3110 and the prediction hint array 3120 are integrated arrays.

[0027] In operation, for certain defined or specified instruction types, entries in the prediction prompt array 3120 can be populated with alternative behaviors that are the opposite of normal behavior. In implementation, these certain defined or specified instruction types can be based on factors such as security concerns that repeatedly require re-running and similar considerations. Methods for determining or specifying these instruction types are known to those skilled in the art. In implementation, certain prediction prompt entries in the prediction prompt array 3120 are populated. In implementation, all prediction prompt entries in the prediction prompt array 3120 are populated.

[0028] After a cache line hit for a cache line has a filled prediction hint entry in the prediction hint array 3120, the processor or L1 data cache controller can determine whether a flag set, instruction match, alternative instruction exists, and / or execute similar prediction hint logic to perform alternative behavior, including, but not limited to, disabling load data return or performing speculative memory bypass disabling in the absence of unknown write-after-read danger.

[0029] Figure 4This is a block diagram of an example load / store unit 4000 having an L1 data cache 4100 according to an embodiment of the present disclosure. The load / store unit 4000 may include an issue queue 4200 that stores data from... Figure 1 The dispatch / retirement unit 1540 dispatches instructions. The issue queue 4200 can issue instructions to the load / store tag pipeline 4300, which processes data and memory addresses through the L1 data cache 4100. Specifically, data and memory addresses are processed through the L1 data cache tag array 4110, the L1-way predictor array 4120, the prediction hint array 4130, and the L1 data cache pipeline 4140. Prediction hint entries in the prediction hint array 4130 can be one or more bits, one or more fields, and / or combinations thereof, depending on the implementation of the prediction hint logic, which can be any pre-compiled hint technique, partially decoded technique, re-encoded technique, table hint technique, etc., known to those skilled in the art. In some implementations, the prediction hint entry or field is a flag. In some implementations, the prediction hint entry or field is a substitute instruction. In some implementations, the prediction hint entry or field is both a flag and a substitute instruction. In some implementations, the prediction hint entry or field is a flag, a problematic instruction, and a substitute instruction. In one implementation, the prediction hint entry or field is a problematic instruction and an alternative instruction. In another implementation, the prediction hint entry or field is a combination of a flag, a problematic instruction, and / or an alternative instruction. The L1 data cache 4100 can have multiple cache lines, each cache line including at least entries from the L1 data cache tag array 3110, entries from the L1-way predictor array 4120, and entries from the prediction hint array 4130. In another implementation, the L1-way predictor array 4120 and the prediction hint array 3120 are integrated arrays.

[0030] In operation, for certain defined or specified instruction types, the prediction prompt array 4130 can be populated with alternative behaviors that are the opposite of the normal behavior. In implementation, these certain defined or specified instruction types can be based on factors such as security concerns that repeatedly require re-running and similar considerations. Methods for determining or specifying these instruction types are known to those skilled in the art. In implementation, certain prediction prompt entries in the prediction prompt array 4130 are populated. In implementation, all prediction prompt entries in the prediction prompt array 4130 are populated.

[0031] After a cache line hit for a cache line has a filled prediction hint entry in the prediction hint array 4130, the processor or L1 data cache controller can determine whether a flag set, instruction match, alternative instruction exists, and / or execute similar prediction hint logic to perform alternative behavior, including, but not limited to, disabling load data return or performing speculative memory bypass disabling in the absence of unknown write-after-read danger.

[0032] Figure 5 This is a diagram of an example technique 5000 for implementing a data cache with predictive hints, according to embodiments of the present disclosure. The technique includes: 5100 populating a predictive hint field in one or more cache lines in a data cache; 5200 checking for a hit in the predictive hint field of the cache line; and 5300 performing a substitution action if the predictive hint field is populated. This is possible, for example, in... Figure 1 Processing system 1000, Figure 2 Load storage unit 2000, Figure 3 Load storage unit 3000, Figure 4 The loading storage unit 4000 and similar devices and systems implement the technology 5000.

[0033] Technology 5000 includes populating one or more cache lines in a 5100 data cache with prediction hint fields. For certain determined or specified instruction types, the prediction hint fields can be populated with alternative behavior that is the opposite of normal behavior. In implementations, these certain determined or specified instruction types can be based on factors such as instructions that repeatedly have to be re-run, instructions that can cause or lead to security problems, and similar factors. Methods for determining or specifying these instruction types are known to those skilled in the art. In some implementations, certain prediction hint fields are populated. In some implementations, all prediction hint fields are populated. In some implementations, the prediction hint fields are integrated with a data cache tag array. In some implementations, the prediction hint fields are integrated with a path predictor array.

[0034] Technique 5000 includes checking the prediction hint field in a cache line hit (5200). In the case of a cache line hit in the data cache, the prediction hint field is checked to determine whether an alternative action is available for the instruction associated with the cache line hit. In its implementation, the prediction hint field can include flags, the problematic instruction, an alternative instruction, a pointer, other similar hints, and combinations thereof.

[0035] Technique 5000 includes performing a substitution action 5300 when the prediction hint field is populated. The substitution action runs when the prediction hint field is populated. In the implementation, the prediction hint field can include a substitution instruction, a pointer, or similar functionality. In the implementation, the substitution action can be lazy loading data for the instruction, executing a different instruction, or similar functionality.

[0036] Figure 6 This is a diagram of an example technique 6000 for implementing a data cache with predictive hints, according to embodiments of the present disclosure. The technique includes: 6100 populating predictive hint fields in one or more cache lines in a data cache; 6200 checking for a hit in the predictive hint fields of the cache line; 6300 matching a problematic instruction with an issued instruction; and 6400 performing a substitution action if a match is found. This is possible, for example, in... Figure 1 Processing system 1000, Figure 2 Load storage unit 2000, Figure 3 Load storage unit 3000, Figure 4 The loading storage unit 4000 and similar devices and systems implement the technology 6000.

[0037] Technology 6000 includes filling prediction hint fields in one or more cache lines within a 6100 data cache. For certain determined or specified instruction types, the prediction hint fields can be filled with alternative behavior that is the opposite of normal behavior. In some implementations, these certain determined or specified instruction types can be based on factors such as instructions that repeatedly have to be re-run, instructions that can cause or lead to security problems, and similar factors. Methods for determining or specifying these instruction types are known to those skilled in the art. In some implementations, certain prediction hint fields are filled. In some implementations, all prediction hint fields are filled. In some implementations, the prediction hint fields are integrated with a data cache tag array. In some implementations, the prediction hint fields are integrated with a path predictor array.

[0038] Technique 6000 includes checking the prediction hint field in a cache line hit (6200). In the case of a cache line hit in the data cache, the prediction hint field is checked to determine whether an alternative action is available for the instruction associated with the cache line hit. In its implementation, the prediction hint field can include the problematic instruction, an alternative instruction, a pointer, other similar hints, and combinations thereof.

[0039] Technique 6000 includes matching problematic instructions against instructions issued by 6300. If the prediction hint field is populated, then the issued instructions are matched against the populated problematic instructions.

[0040] Technique 6000 includes performing a 6400 alternative action upon a match. The alternative action is executed when the issued instruction matches the problematic instruction. In the implementation, the prediction hint field can include an alternative instruction, a pointer, or similar functionality. In the implementation, the alternative action can be lazy-loading data for the instruction, executing a different instruction, or similar functionality.

[0041] Generally, a data cache comprises multiple cache lines, at least one of which includes a data field, a tag field, and a prediction hint field configured to store prediction hints that indicate replacement behavior for a cache hit for a cache line with a populated prediction hint field. In some implementations, the prediction hint field is integrated with the tag field. In some implementations, the data cache also includes a path predictor field, where the prediction hint field is integrated with the path predictor field. In some implementations, the data cache is an L1 data cache. In some implementations, at least one cache line is multiple cache lines. In some implementations, at least one cache line is a subset of multiple cache lines. In some implementations, prediction hints disable loading data return in cases of unknown write-after-read danger. In some implementations, prediction hints are speculative storage bypass disabled. In some implementations, some cache lines are populated with prediction hints.

[0042] Generally, a data cache includes a data array, a tag array, and a prediction hint field configured to store prediction hints that indicate replacement behavior for a cache hit against a cache line. Each cache line is associated with entries in both the data array and the tag array. In one implementation, each entry in the tag array has an integrated prediction hint field. In another implementation, some cache lines already store prediction hints. In yet another implementation, the data cache also includes a path predictor array, where each entry has an integrated prediction hint field. In one implementation, the prediction hint disables loading data in cases of unknown write-after-read risks. In another implementation, the prediction hint is a speculative storage bypass disable. In yet another implementation, some cache lines already store prediction hints.

[0043] Generally, methods for providing predictive hints using a data cache include: storing the predictive hint in predictive hint elements of certain cache lines in a tag array or path predictor used for the data cache; reading the predictive hint from the predictive hint elements in the event of a cache line hit for one of the certain cache lines; and executing replacement instruction behavior as defined by the predictive hint. In one implementation, the predictive hint disables loading data in the event of an unknown write-after-read danger. In another implementation, the predictive hint is a speculative storage bypass disable. In yet another implementation, the method further includes matching issued instructions against problematic instructions stored in the predictive hint elements.

[0044] While some embodiments herein relate to methods, those skilled in the art will appreciate that they can also be embodied as systems or computer program products. Therefore, aspects of the invention can take the form of entirely hardware embodiments, entirely software embodiments (including firmware, resident software, microcode, etc.), or embodiments combining software and hardware aspects, all of which may generally be referred to herein as “processor,” “device,” or “system.” Furthermore, aspects of the invention can take the form of computer program products embodied on one or more computer-readable media having computer-readable program code embodied thereon. Any combination of one or more computer-readable media can be utilized. The computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium can be, for example, but not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer-readable storage media include the following: electrical connections having one or more wires, portable computer floppy disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disc read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing. In the context of this document, a computer-readable storage medium can be any tangible medium capable of containing or storing programs for use by or in connection with an instruction-running system, apparatus, or device.

[0045] Computer-readable signal media may include propagated data signals in which computer-readable program code is embodied, for example, in baseband or as part of a carrier wave. Such propagated signals may take any of a variety of forms, including but not limited to electromagnetic, optical, or any suitable combination thereof. A computer-readable signal medium may be any computer-readable medium that is not a computer-readable storage medium but is capable of conveying, propagating, or delivering a program for use by or in conjunction with an instruction-running system, apparatus, or device.

[0046] Program code embodied on a computer-readable medium may be transmitted using any suitable medium, including but not limited to CD, DVD, wireless, wired lines, fiber optic cables, RF, or any suitable combination thereof.

[0047] Computer program code used to perform operations for various aspects of the present invention can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" programming language or similar languages. The program code can run entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or a connection to an external computer can be made (e.g., via the Internet using an Internet service provider).

[0048] The aspects described are based on flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, as well as combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions.

[0049] These computer program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / behaviors specified in one or more flowchart and / or block diagram frames. These computer program instructions may also be stored in a computer-readable medium that directs a computer, other programmable data processing apparatus, or other device to function in a particular manner, such that the instructions stored in the computer-readable medium produce an article of writing comprising instructions for implementing the functions / behaviors specified in one or more flowchart and / or block diagram frames.

[0050] Computer program instructions can also be loaded onto a computer, other programmable data processing apparatus or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer-implemented process, such that the instructions running on the computer or other programmable apparatus provide a process for implementing the functions / behaviors specified in one or more flowchart and / or block diagram frames.

[0051] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each box in a flowchart or block diagram may represent a module, segment, or portion of code comprising one or more operable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions indicated in the boxes may occur in a different order than that shown in the figures.

[0052] Although this disclosure has been described in conjunction with certain embodiments, it should be understood that this disclosure is not limited to the disclosed embodiments, but rather is intended to cover various modifications, combinations and equivalent arrangements included within the scope of the appended claims, the scope of which shall be given the broadest interpretation to include all such modifications and equivalent structures as permitted under law.

Claims

1. A data cache, comprising: Multiple cache lines, at least one cache line includes: Data fields; Tag field; and A prediction hint field is configured to store prediction hints for cache hit indication replacement behavior for a cache line with a filled prediction hint field, wherein the replacement behavior is executed in response to the prediction hint field being filled or in response to determining that an issued instruction matches a problematic indication stored in the filled prediction hint field.

2. The data cache according to claim 1, wherein, The prediction hint field is integrated with the label field.

3. The data cache according to claim 1 further includes: The road predictor field, wherein the prediction hint field is integrated with the road predictor field.

4. The data cache according to claim 1, wherein, The data cache is an L1 data cache.

5. The data cache according to claim 1, wherein, The at least one cache line is one of the plurality of cache lines.

6. The data cache according to claim 1, wherein, The at least one cache line is a subset of the plurality of cache lines.

7. The data cache according to claim 1, wherein, The prediction prompt disables the return of loaded data in cases where the risk of read-after-write is unknown.

8. The data cache according to claim 1, wherein, The prediction suggestion is speculative storage bypass disabled.

9. The data cache according to claim 1, wherein, Some cache lines have been filled with prediction hints.

10. A data cache, comprising: Data array; Tag array; as well as A prediction hint field is configured to store prediction hints for cache hit indication replacement actions for cache lines, wherein each cache line is associated with an entry in the data array and the tag array, and wherein the replacement action is executed in response to the prediction hint field being populated or in response to determining that an issued instruction matches a problematic indication stored in the populated prediction hint field.

11. The data cache according to claim 10, wherein, Each entry in the label array has an integrated prediction hint field.

12. The data cache according to claim 11, wherein, Some cache lines already contain prediction hints.

13. The data cache according to claim 10, further comprising: A road predictor array, wherein each entry in the road predictor array has an integrated prediction hint field.

14. The data cache according to claim 10, wherein, The prediction prompt disables the return of loaded data in cases where the risk of read-after-write is unknown.

15. The data cache according to claim 10, wherein, The prediction suggestion is speculative storage bypass disabled.

16. The data cache according to claim 10, wherein, Some cache lines already contain prediction hints.

17. A method for providing predictive hints using a data cache, the method comprising: The prediction hints are stored in the prediction hint elements of certain cache lines of one of the tag arrays or road predictors used for the data cache; In the event of a cache line hit for one of the cache lines, a prediction hint is read from the prediction hint element; as well as In response to the prediction hint field being populated or in response to determining that the issued instruction matches a problematic indication stored in the populated prediction hint field, a replacement instruction behavior is executed as defined by the prediction hint.

18. The method according to claim 17, wherein, The prediction prompt disables the return of loaded data in cases where the risk of read-after-write is unknown.

19. The method according to claim 18, wherein, The prediction suggestion is speculative storage bypass disabled.

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