Memory startup and initialization system and method

Abstract

The present application provides a system and method for efficiently and effectively booting and initializing memory. In one embodiment, a memory controller includes a normal data path and a boot path. The normal data path guides memory operations during normal memory read / write operations after the memory chip is powered on. The boot path includes a boot module, wherein the boot module guides memory boot operations during the power-on of the memory chip, including forwarding a boot pattern stored in a write pattern mode register of the memory chip and a memory address selected in the memory chip for initialization using the boot pattern. The boot pattern includes information corresponding to a suitable initial data value. The boot pattern may also include a suitable corresponding error correction code (ECC) value. The boot module may include a boot pattern register that stores the boot pattern.

Description

Technical Field

[0001] The present invention relates to the field of information processing and communication in memory. Background Art

[0002] Numerous electronic technologies, such as digital computers, calculators, audio equipment, video equipment, and telephone systems, have helped increase productivity and reduce costs in data and information analysis and communication across most areas of business, science, education, and entertainment. Electronic components are used in many critical applications (e.g., medical procedures, vehicle assistance, financial applications, etc.), which often involve storing large amounts of information. In many applications, it is crucial for the system to process information correctly and accurately. Providing correct and accurate information often depends on starting with reliable information. Establishing a reliable information configuration for volatile memory during system initialization can be problematic and difficult.

[0003] Some systems include an information verification method for verifying the accuracy of information stored in memory. One traditional method includes an error correction code (ECC) function. The ECC function may include parity checking of data bits. In some conventional memories, a predetermined number of stored data bits (e.g., 32, 64, etc.) has a corresponding predetermined number of stored ECC parity bits (e.g., 4, 8, etc.) for checking the accuracy of the data bits. The single error correction / double error correction (SEC / DEC) Hamming code used for the fourth generation double data rate memory (DDR4) interface is typically a 64-bit data interface. If the ECC function is included, an 8-bit parity bit interface is added, for a total of 72-bit interfaces. The SEC / DED of the DDR5 interface is typically a 32-bit data interface. If the ECC function is included, an 8-bit parity bit interface is added, for a total of 40-bit interfaces.

[0004] Volatile memory typically requires electrical energy to store information and does not retain information when power is removed or the system is shut down. Dynamic random access memory (DRAM) is a type of volatile memory that typically requires energy to store information in capacitive memory / storage cells, which require repeated refreshing of the cell's capacitance state. The basic operating principle of DRAM is that the charge stored in the capacitive characteristics of a memory cell corresponds to the logical state of the information bit stored in the memory cell. Due to the capacitive characteristics and features (such as charging and discharging), DRAM typically performs several operations (such as precharging, refreshing, loop amplification, etc.) that require energy to maintain and change the state of the memory cell. Therefore, when the DRAM power is turned off, the charge stored in the DRAM's capacitive characteristics dissipates or discharges, and the corresponding information is lost or disappears. This poses a particular problem for systems implementing ECC storage, because when the power is turned off, the logical value of the data bit and the corresponding ECC parity bit are completely lost.

[0005] Because the previous logical state of a memory cell disappears or is lost when the power is turned off, the values ​​of the data bits and the corresponding ECC parity bits are generally uncertain when the power is turned on in a DRAM with ECC verification. If the proper relationship between the data bits and the ECC bits is not established during memory startup or power-on, the ECC bits may indicate an error in the initial state of the information when the memory controller performs parity checking (e.g., calculating parity, etc.). The startup process is generally used to start or initialize a DRAM with ECC. Conventional startup processes generally include software / operating system (OS) methods or hardware methods.

[0006] Traditional software / operating system methods typically utilize direct memory access (DMA), central processing unit (CPU) write, or memset functionality to establish initial storage memory values. The software method typically includes system initialization, disabling ECC, software startup, and re-enabling ECC. In the DMA method, software startup typically involves writing a logic value from a fixed source address to an address within the DRAM range. In the CPU write method, software startup typically involves a 32-bit storage operation cycle from the start address to the end address of the DRAM. In the memset method, the startup operation typically involves writing from a target pointer to the start address of the DRAM, with a length equal to the size of the DRAM. The software method typically cannot start from time zero, is inefficient (e.g., low latency, low power consumption, etc.), and requires disabling and enabling ECC functionality during the startup operation.

[0007] Conventional hardware approaches typically use a memory controller to set all configured memories to default values, such as logic zero or a pre-programmed pattern. Conventional hardware approaches also attempt to set the corresponding ECC bits to valid values. While conventional hardware approaches may be more efficient than conventional software / OS approaches, conventional hardware approaches perform each write operation to the corresponding memory address, placing the corresponding data pattern on the data bus so that each write is to one address after another. Conventional hardware approaches are also typically limited to processing memory rank levels in a sequential manner. Similar to conventional software / OS approaches, conventional hardware approaches typically require disabling and enabling ECC functionality during boot operations. Summary of the Invention

[0008] The present application provides a system and method for efficiently and effectively priming and initializing memory. In one embodiment, a memory controller includes a normal data path and a boot path. The normal data path guides the memory operation during the normal memory read / write operation after the power of the memory chip is turned on. The boot path includes a boot module, wherein the boot module guides the memory boot operation during the power startup of the memory chip. The boot module may include a boot pattern register storing a boot pattern. The memory boot operation may include forwarding a boot pattern from a boot pattern register (for example, in a memory controller, etc.) to load into a write pattern mode register in the memory chip. The memory boot operation may also include selecting a memory address in the memory chip for initialization using the boot pattern. The boot pattern includes information corresponding to a suitable initial data value. The boot pattern may also include an appropriate corresponding error correction code (ECC) value.

[0009] In one embodiment, the storage module loads the boot pattern from a boot pattern register in the storage module into a write pattern mode register on the memory chip. The boot module may include: a boot range start address register storing a start address of a memory address range and a boot range end address register storing an end address of the memory address range. The memory address may be selected based on an incrementing address value from the boot range start address to the boot range end address. The boot module may include a boot level (PL) register storing a level parallelism definition value indicating a level of parallel boot write operations. In one embodiment, parallel boot write operations may be performed at a rank level. In an exemplary implementation, the memory boot module guides a write pattern operation based on a memory address. The write pattern operation may write pattern information from the write pattern register in the memory chip to a memory cell in the memory chip corresponding to the memory address. The boot module may include a boot write (MRW) command for guiding programming of the memory chip using a boot pattern, wherein the boot pattern is loaded from the boot pattern register in the memory controller boot module to the write pattern mode register in the memory chip. In one exemplary implementation, the memory is dynamic random access memory (DRAM), and the memory boot operation includes a double data rate version 5 (DDR5) error correction code (ECC) compliant write style operation.

[0010] In one embodiment, a memory startup method includes: performing a startup programming process and a boot startup control operation. The startup programming process includes programming a startup module in a memory controller using a startup pattern and memory range address information. The boot startup control operation includes: forwarding a startup pattern to be loaded into a write pattern mode register of a memory chip; generating a memory address of a memory chip to be started and initialized; and issuing a write operation command, which writes the startup pattern from the write pattern mode register in the memory chip to a storage unit in the memory chip, wherein the storage unit corresponds to the memory address. The memory chip can be one of a plurality of memory chips, and the boot startup control operation is performed on the plurality of memory chips at least partially in parallel. In an exemplary implementation, the startup operation is performed on the memory chip according to the startup pattern and the memory address. The memory controller can be one of a plurality of memory controllers, and the startup programming operation is performed on the plurality of memory controllers at least partially in parallel.

[0011] In one embodiment, the memory startup method further includes performing a startup operation on the memory chip. Performing the startup operation on the memory chip may include storing the received style information in a write style mode register on the memory chip. Performing the startup operation on the memory chip may include writing the style information from the write style mode register to a storage unit of the memory chip in response to a received write command. The storage unit may correspond to a memory address in the memory chip to be initialized and started. The memory chip may be one of a plurality of memory chips, and the startup operation is performed on the plurality of memory chips at least partially in parallel. The memory range address information may include a memory range start address and a memory range end address. Generating a memory address may include establishing a memory address based on the memory range start address and the memory range end address. Issuing a write command operation may be performed without data information on the data bus.

[0012] In one embodiment, a memory system includes a plurality of memory modules and a memory controller. The plurality of memory modules are configured to store information, wherein a first one of the plurality of memory modules includes a first plurality of memory chips, and a second one of the plurality of memory modules includes a second plurality of memory chips. The memory controller includes a startup module, wherein the startup module is configured to direct a memory startup operation during power-on of the plurality of memory modules. The memory startup operation may include forwarding a startup pattern to be stored in respective write pattern mode registers on the first group of memory chips and the second group of memory chips, and selecting memory addresses in respective first group of memory chips and second group of memory chips to be initialized using the startup pattern. The memory startup operation may also include directing a write pattern operation of information from the corresponding write pattern mode register to the corresponding selected memory address.

[0013] The first group of memory chips and the second group of memory chips can be organized into a plurality of ranks, and the write mode operation can be performed substantially in parallel at the rank level in the first group of chips and the second group of chips. By activating the corresponding plurality of rank enable signals, a plurality of the plurality of ranks can be substantially enabled simultaneously. In an exemplary implementation, a command / address bus and a data bus can communicatively couple the memory controller to the plurality of memory modules, wherein when a write mode operation command is issued, an address is generated on the command / address bus and no mode data is on the data bus.

[0014] This Summary is provided to introduce some concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings, which are included in and constitute a part of this specification, are provided for illustrative purposes only and are not intended to limit the invention to the specific implementations shown therein. Unless otherwise specified, the drawings are not drawn to scale. In the figures of the accompanying drawings, embodiments of the present application are shown by way of example and not by way of limitation, and like reference numerals in the drawings represent similar elements. Unless otherwise specified, the drawings are not necessarily drawn to scale.

[0016] Figure 1 is a block diagram of a computer system according to one embodiment.

[0017] Figure 2 is a block diagram of a startup module according to one embodiment.

[0018] Figure 3 is a block diagram of a memory system according to one embodiment.

[0019] Figure 4 is a flow chart of an exemplary memory activation method according to one embodiment.

[0020] Figure 5 is a flowchart of another exemplary memory activation method according to one embodiment.

[0021] Figure 6 A comparison is shown between a typical conventional memory startup method and a memory controller startup module method according to an embodiment.

[0022] Figure 7 is a block diagram of an exemplary computing system for storing and processing information according to one embodiment.

[0023] Figure 8 is a block diagram of an exemplary processing core configuration according to one embodiment. DETAILED DESCRIPTION

[0024] Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings. Although the present application will be described in conjunction with these embodiments, it will be appreciated that they are not intended to limit the present application to these embodiments. On the contrary, the present invention is intended to encompass substitutions, modifications, and equivalents that may be included within the scope of the invention as defined by the appended claims. In addition, in the following detailed description of the application, many specific details have been set forth to provide a thorough understanding of the present application. However, it will be appreciated that the present application can be implemented without these specific details. On the other hand, well-known methods, processes, components, and circuits are not described in detail herein to avoid unnecessarily confusing various aspects of the present application.

[0025] Some embodiments of the present application below are presented in the form of routines, modules, logic blocks and other symbolic representations of data in one or more electronic devices being operated. These descriptions and representations are means for those skilled in the art to most effectively convey the essence of their work to other persons skilled in the art. Routines, logic blocks and / or the like are herein and generally considered to be self-consistent sequences of processes or instructions that lead to desired results. These processes include physical operations of physical quantities. Typically, although not necessarily, these physical operations take the form of electrical or magnetic signals that can be stored, transmitted, compared and otherwise operated in an electronic device. For convenience, and with reference to common usage, with reference to the embodiments of the present application, these signals are referred to as data, bits, values, elements, symbols, characters, terms, numbers, character strings, etc.

[0026] However, it should be remembered that these terms are to be interpreted as referring to physical operations and quantities and are merely convenient labels and will be further interpreted according to terminology commonly used in the art. Unless otherwise clear from the following discussion, it should be understood that throughout this application, discussions using terms such as "receiving" refer to actions and processes of, for example, an electronic device, such as an electronic computing device, that processes and transforms data. Data is represented as physical (e.g., electronic) quantities within the logic circuits, registers, memory, and / or the like of the electronic device and is converted into other data similarly represented as physical quantities within the electronic device.

[0027] In this application, the use of antonymous conjunctions is intended to include conjunctions. The use of definite or indefinite articles is not intended to indicate number. In particular, reference to "the" object or "a" object is also intended to indicate one of a possible plurality of such objects. The use of the terms "comprise," "contain," "include," "include," etc. specifies the presence of the element, but does not exclude the presence or inclusion of one or more other elements and / or their groups. It should also be understood that although the terms first, second, etc. can be used here to describe various elements, such elements should not be limited by these terms. These terms are used in this article to distinguish one element from another. For example, without departing from the scope of the embodiment, the first element can be referred to as the second element, and similarly the second element can be referred to as the first element. It should also be understood that when an element is referred to as "coupled" to another element, it can be directly or indirectly connected to the other element, or there can be an intermediate element. In contrast, when an element is referred to as "directly connected" to another element, there is no intermediate element. It should also be understood that the wording and terminology used herein are for descriptive purposes and should not be considered as limiting.

[0028] The system and method are conducive to efficient and effective power startup and memory storage resource initialization. In one embodiment, the memory initialization startup system and method are faster than typical traditional systems and methods. In an exemplary embodiment, the memory initialization startup system and method are capable of loading and storing startup data in parallel (for example, in multiple memory chips, for multiple ranks, across multiple memory modules, etc.). The load and store operations can be performed independently in response to separate commands. As part of a first operation (for example, in response to a first command, a trigger, etc.), startup data can be loaded into registers on multiple memory chips. The startup data can be written from the registers on the memory chip and stored in the storage unit. The writing and storage of startup data from the register to the memory unit can be performed in response to a command / trigger without simultaneously starting the data on the data bus (for example, unlike traditional methods, etc.). Avoiding repeated switching of data on the data bus enables the initialization startup system and method to consume less power than traditional systems. In one embodiment, traditional systems disable and enable ECC operations as part of the startup memory.

[0029] Figure 11 is an exemplary block diagram of a computer system 100 according to one embodiment. Computer system 100 includes a central processing unit 110, a memory management unit 120, a memory controller 130, a memory module 140, and a memory module 150. Central processing unit 110 is communicatively coupled to memory management unit 120, and memory management unit 120 is communicatively coupled to memory controller 130. Memory controller 130 is communicatively coupled to memory module 140 and memory module 150. Memory module 140 and memory module 150 store information. Central processing unit 110 processes information stored in memory module 140 and memory module 150. Memory management unit 120 manages the storage of information in memory module 140 and memory module 150. Memory controller 130 directs access to memory module 140 and memory module 150. Memory module 140 and memory module 150 may be dual inline memory modules (DIMMs).

[0030] In one embodiment, memory controller 130 includes a normal data path 131 for directing normal data access to memory modules 140 and 150. Memory controller 130 also includes a startup operation path 132 for directing power-on and initializing startup operations in memory modules 140 and 150. In one embodiment, startup operation path 132 includes a startup module 133. Startup module 133 directs loading of startup pattern information into write pattern mode registers in memory chips on memory modules 140 and 150. Startup module 133 also directs startup operations, including generating addresses and issuing write pattern commands, instructing the memory chips to write a startup pattern from the write pattern mode register to a memory address when no data is present on the data bus.

[0031] It will be appreciated that the initialization boot system and method of the present application are compatible with various standards. In one embodiment, the initialization boot system and method are compatible with double data rate implementations. In an exemplary implementation, the initialization boot system and method are compatible with DDR5 implementations.

[0032] Figure 2 is a block diagram of an exemplary startup module 200 according to one embodiment. In one embodiment, startup module 200 is similar to startup module 133. In one exemplary embodiment, startup module 200 operates as a programmable register interface. Startup module 200 includes startup registers 210 and a startup engine 220. Startup registers 210 include a startup pattern register 211, a start startup address register 212, an end startup address register 213, and a priority register 214. Startup engine 220 includes a pattern register set (MRS) data generation component 221, a startup address generation function 222, and a startup level generation function 223. In one embodiment, startup level generation function 223 includes MRS data generation functionality (e.g., at a rank level, etc.).

[0033] The components of the startup module 200 operate in conjunction to guide the startup and initialization of the memory chip. The memory chip can be included in the memory module. The startup pattern register 211 stores startup pattern information. The start startup address register 212 stores the starting address of the startup range to be started and initialized. The end startup address register 213 stores the ending address of the startup range to be started and initialized. The priority register 214 stores an indication of the level of memory components (e.g., banks, modules, ranks, etc.) that are to be started and initialized substantially in parallel or simultaneously. The MRS data generation component 221 generates pattern register set (MRS) or memory register write (MRW) data for loading into the write pattern mode register of the memory chip based on the startup pattern information stored in the startup pattern register 211. The startup address generation function 222 generates addresses based on the information in the start startup address register 212 and the end startup address register 213. In one embodiment, the startup level generation function 223 generates command information for the parallel levels. In one exemplary embodiment, the startup level generation function 223 generates chip enable indications / signals for the levels (e.g., modules, ranks, etc.) that are enabled substantially in parallel / simultaneously.

[0034] In one embodiment, a channel may include multiple memory modules. Multiple memory modules may share an address bus and a data bus. In an exemplary implementation, multiple memory modules cannot be enabled and transmit data to different or second addresses at the same time (for example, when there are different data on the data bus, there cannot be different addresses on the shared address bus, etc.). However, in one embodiment, the boot style data is preloaded into each write style mode register on each memory chip, and a write style operation command with the same address and an enable signal of more than one channel / rank (such as a chip select ID, etc.) is issued on the address and command bus, and since there is no data on the data bus, multiple memory chips can be started in parallel.

[0035] Figure 3is a block diagram of an exemplary memory system 300 according to one embodiment. Memory system 300 includes a memory controller 310, a memory module 320, and a memory module 330. Memory controller 310 includes a normal data path 311 and a boot path, wherein the boot path includes a boot module 312. Memory module 320 includes memory chips 321 and 328, each including a write pattern mode register 322 and a write pattern mode register 329, respectively. Memory module 330 includes memory chips 331 and 338, each including a write pattern mode register 332 and a write pattern mode register 339, respectively. Memory pattern mode registers 322, 329, 332, and 339 store boot pattern information received from boot module 312. In response to receiving a pattern write command and address from boot module 312, memory chips 321, 328, 331, and 338 write the boot pattern information from each memory pattern mode register 322, 329, 332, and 339 into a memory cell, respectively.

[0036] In one embodiment, the startup module 312 issues an MRS or MRW command to program the memory chips, wherein programming the memory chips includes loading startup pattern data from registers in the startup module 312 into respective write pattern mode registers (e.g., 322, 329, 332, 339, etc.). In one exemplary embodiment, the startup pattern data is loaded substantially simultaneously (e.g., in response to a single MRS command, etc.) via a data bus to multiple DRAM chips. Substantially simultaneously loading the startup data into the respective write pattern mode registers of the multiple memory chips can avoid repeated switching on the data bus dedicated to the individual DRAM chips, as is often required in conventional methods. The startup module 312 generates a DRAM address to be started. In one exemplary embodiment, the DRAM address to be started includes an incrementing sequence of DRAM addresses corresponding to memory addresses starting from the startup address and ending at the startup address. The startup module 312 can directly send chip select or chip enable signals to each DRAM chip (e.g., 321, 331, 328, 338, etc.) substantially simultaneously and in parallel. The startup module 312 may issue a write pattern operation command to direct the writing and storage of startup pattern data from the respective write pattern mode registers into the memory cells of the respective memory chips corresponding to the DRAM addresses to be started. The indication of the DRAM addresses to be started and the write pattern operation command may be transmitted to the respective DRAM chips (e.g., 321, 331, 328, 338, etc.) via the address / command bus without simultaneously transmitting / switching pattern data on the data bus.

[0037] It is understood that different DRAM chips can be programmed with different boot patterns. In one embodiment, pattern data is loaded into the DRAMs one by one via per-DRAM addressable (PDA) mode. In an exemplary implementation, different boot information with different data patterns can be loaded into different DRAMs based on the addressing mode of the individual DRAMs.

[0038] In one embodiment, since the startup data is written from the write style mode register on the memory chip, this information is not involved in the ECC check in the memory controller, and ECC is not disabled and enabled as part of the startup process. In an exemplary embodiment, ECC can be disabled and enabled for reasons other than as part of the startup process.

[0039] Figure 4 is a flow chart of an exemplary memory startup method 400 according to one embodiment. In one embodiment, the memory startup method 400 is compatible with DDR implementations and requirements.

[0040] In block 410, a boot programming process is performed. The boot programming process includes programming a boot module in the memory controller with the boot pattern and memory range address information. The boot pattern and memory range address information are automatically generated for each region. In one exemplary implementation, the memory size is automatically determined by hardware or a software kernel. In one exemplary implementation, once the memory size is determined, the boot start and end addresses are established. In one embodiment, an isolate memory region (IMR) command is used.

[0041] In block 420, a startup control operation is performed. The boot control operation may include forwarding boot pattern data to be loaded into a write pattern mode register in a memory chip. The boot pattern data may be forwarded from a memory controller to the memory chip. In one embodiment, a pattern or memory register write (MRW) command is used to guide the loading and programming of boot pattern information into a write pattern mode register in a memory chip. The boot control operation may include generating a memory address of a memory chip to be initialized and booting with the boot pattern data. The boot control operation may include simultaneously booting multiple memory chips by enabling respective chip boot signals. Multiple memory chips may be enabled based on the level of memory components (e.g., bank, module, rank, etc.) that are booted and initialized substantially in parallel. In one embodiment, the boot control operation may include issuing a write operation command that writes the boot pattern from the write pattern mode register in the memory chip to a memory cell in the memory chip corresponding to the memory address.

[0042] The memory chip may be one of a plurality of memory chips, and a boot programming operation is performed on the plurality of memory chips at least partially in parallel. In one exemplary embodiment, the boot operation is performed on the memory chip according to the boot pattern and the memory address. The execution of the boot operation includes issuing a write command for a boot write operation and a generated address while no data information is on the data bus, and the execution of the boot operation may be performed at least partially in parallel on the plurality of memory chips. The memory range address information may include a memory range start address and a memory range end address, and generating the memory address includes establishing the memory address according to the memory range start address and the memory range end address.

[0043] In one embodiment, the boot pattern data may be the same for multiple memory addresses. In one embodiment, the boot pattern data may be different for multiple memory addresses. The similarities and differences in the boot pattern data for each memory address may be based on different levels of memory hierarchy organization. In one embodiment, the boot pattern data for multiple memory modules is the same. In one embodiment, the boot pattern data may vary for different memory modules and components within the multiple memory modules and components.

[0044] Figure 5 is a flow chart of an exemplary boot process method 500 according to one embodiment.

[0045] System initialization begins in block 510. In one embodiment, the system is powered on.

[0046] In block 520 , in response to system initialization, a DRAM initialization process is initiated.

[0047] In block 530, the boot module register is set. In one embodiment, the boot pattern is set in the boot pattern register.

[0048] In block 540, booting begins. In one embodiment, the boot pattern is loaded from the boot pattern register in the memory controller boot module to the write pattern mode register in the memory chip. In one exemplary implementation, the write pattern mode register may be included in the input / output (I / O) portion of the memory chip peripheral circuitry.

[0049] In block 550, an address is generated along with a write pattern command. In one embodiment, the address and write pattern command are sent to the memory chip while no data is on the data bus. In one exemplary embodiment, the address and write pattern command are sent to multiple memory chips substantially simultaneously and in parallel.

[0050] The boot operation is complete in block 560. In one embodiment, the system is notified that the boot operation is complete and memory is initialized.

[0051] Figure 6 The following is a comparison between a typical conventional memory startup method and a memory controller startup module method according to an embodiment. In a typical conventional startup method (e.g., Figure 6 ), ECC is disabled, rank 0 is enabled, then rank 1 is enabled, and so on. For each rank, a write command is issued while triggering the enable data on the data bus. Finally, rank 7 is enabled, and then ECC is enabled again. Compared to the traditional startup method, the exemplary new initialization startup method (e.g., Figure 6 The system and method for initializing and starting the system can save time and energy by not disabling and enabling ECC functions. In one embodiment, multiple ranks are programmed in parallel.

[0052] It should be understood that the boot system and method can be used with both ECC-compatible and non-ECC-compatible memory configurations. In one exemplary embodiment, the boot system and method are used with ECC DRAM DIMMs. In another exemplary implementation, the boot system and method are used with non-ECC DRAM DIMMs.

[0053] Figure 7 is a block diagram of an exemplary computing system 900 for storing and processing information according to one embodiment. In one embodiment, a memory chip is included in memory 904 (e.g., similar to storage systems 100, 400, etc.). Computing system 900 may include a processor 902 and memory 904. In one implementation, computing system 900 may be a server computer, a data center, a cloud computing system, a streaming service system, an internet service provider system, a cellular service provider system, etc. Processor 902 may be a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), a vector processor, a memory processing unit, etc., or a combination thereof. In one embodiment, processor 902 may include communication interfaces, such as a peripheral component interface (PCIe4) 921 and an inter-integrated circuit (I2C) interface 922, an on-chip circuit tester, such as a joint test action group (JTAG) engine 923, a direct memory access engine 924, a command processor (CP) 925, and cores 931-934. Cores 931-934 may be coupled in a directed ring bus configuration.

[0054] Continue to refer Figure 7The cores 931-934 may execute a computing device executable instruction set to perform functions including, but not limited to, executing a narrow channel conversion memory control method. These functions may be executed on a single core 931-934, distributed across multiple cores 931-934, executed on a core together with other functions, and so on. In one embodiment, initialization startup operations are performed on the memory 904.

[0055] Figure 8 1 is a block diagram of an exemplary processing core configuration 1000 according to one embodiment. In one embodiment, components of the processing core configuration 1000 participate in memory activation operations. The processing core 1000 may include a tensor engine (TE) 1010, a pooling engine (PE) 1015, a memory copy engine (ME) 1020, a sequencer (SEQ) 1025, an instruction buffer (IB) 1030, a local memory (LM) 1035, and a constant buffer (CB) 1040. The local memory 1035 may be pre-populated with model weights and stored for immediate activation during use. The constant buffer 1040 may store constants used for batch normalization, quantization, etc. The tensor engine 1010 may be used to accelerate fused convolutions and / or matrix multiplications. The pooling engine 1015 may support operations such as pooling, interpolation, and region of interest. The memory copy engine 1020 may be configured for inter-core and / or intra-core data copying, matrix transposition, etc. The tensor engine 1010, the pooling engine 1015, and the memory copy engine 1020 can run in parallel. The sequencer 1025 can orchestrate the operations of the tensor engine 1010, the pooling engine 1015, the memory copy engine 1020, the local memory 1035, and the constant buffer 1040 according to the instructions from the instruction buffer 1030. The processing core 1000 can provide efficient computation for video encoding under the operational control of fused coarse-grained instructions. A detailed description of the exemplary processing unit core 1000 is not necessary for understanding aspects of the present application and will not be described further herein.

[0056] Therefore, the initialization startup system and method are conducive to the efficient and effective start-up of power supply and initialization of memory storage resources. In one embodiment, the memory initialization startup system and method overcome many problems associated with conventional / traditional methods. For example, the initialization startup system and method can start quickly near time zero, which is different from traditional software / hardware methods. Traditional software / hardware methods have many efficiency issues in terms of delay and power consumption (for example, it is usually necessary to disable / enable ECC functions, it is not possible to start from time zero, it is not possible to parallelize at the memory controller (MC) level or the memory module level, and it requires software / operating system (SW / OS) solutions, etc.). Compared with typical traditional methods, the initialization startup system and method can achieve faster speeds and lower power consumption.

[0057] While specific embodiments of the present invention have been presented above for purposes of illustration and description, they are not intended to be exhaustive or to limit the present invention to the precise forms disclosed, and it is apparent that many modifications and variations are possible in light of the foregoing teachings. The embodiments selected and described herein are intended to better explain the principles of the present invention and its practical application, thereby enabling others skilled in the art to better utilize the present invention and various embodiments with various modifications suitable for the intended specific use. The scope of the present invention is intended to be defined by the appended claims and their equivalents.

Claims

1. A memory controller comprising: A normal data path for guiding storage operations during normal memory read / write operations after the memory chip power is turned on; and A boot path, the boot path including a boot module, wherein the boot module is used to guide memory boot operations during power-up of the memory chip, including forwarding a boot pattern to be loaded into a write pattern mode register of a memory chip and a memory address selected in the memory chip for initialization using the boot pattern. 2 . The memory controller of claim 1 , wherein the startup pattern includes information corresponding to a suitable initial data value and an ECC value for an error correction code (ECC) compatible memory. 3 . The memory controller of claim 1 , wherein the startup pattern includes information of a suitable initial data value suitable for a non-ECC compliant memory.

4. The memory controller according to claim 1 , wherein the startup module comprises a startup pattern register storing the startup pattern, and wherein the storage module directs loading the startup pattern from the startup pattern register in the storage module into a write pattern mode register on a memory chip.

5. The memory controller according to claim 1 , wherein the startup module comprises: a start range start address register, which stores the start address of a memory address range, and Start range end address register, which stores the end address of the memory address range, The memory address is selected based on the incrementing address value from the start address of the startup range to the end address of the startup range.

6. The memory controller according to claim 1, wherein: The launch module includes a rank launch level (PL) register that stores a rank level parallelism definition value indicating a level of parallel launch of write operations based on rank.

7. The memory controller of claim 1 , wherein the startup module directs a write style operation based on the memory address, wherein the write style operation writes style information stored in a write style mode register of the memory chip to a storage cell in the memory chip corresponding to the selected memory address.

8. The memory controller of claim 1 , wherein the startup module includes a startup engine that issues a memory register write (MRW) command to program the memory chip using the startup pattern boot, wherein the startup pattern is loaded from a startup pattern register of the startup module of the memory controller to a write pattern mode register in the memory chip.

9. The memory controller of claim 1, the memory being a dynamic random access memory (DRAM), and the memory startup operation comprising a double data rate version 5 (DDR5) error correction code (ECC) compliant write style operation.

10. A memory startup method, comprising: performing a boot programming process, including programming a boot module in a memory controller with the boot pattern and memory range address information; and Boot startup control operations, including: forwarding the boot pattern to be loaded into a write pattern mode register of a memory chip; and generating a memory address in the memory chip to be initialized and started; and A write operation command is issued to write the startup pattern from the write pattern mode register of the memory chip into a storage unit corresponding to the storage address in the memory chip.

11. The memory activation method according to claim 10, wherein: The memory chip is one of a plurality of memory chips, and the boot startup control operation is performed in parallel on at least part of the plurality of memory chips. 12 . The memory startup method according to claim 10 , further comprising executing a startup operation on the memory chip according to the startup pattern and the memory address.

13. The memory activation method according to claim 12, wherein: The memory chip is one of a plurality of memory chips, and a boot operation is performed on at least a portion of the plurality of memory chips in parallel.

14. The memory activation method according to claim 10, wherein: The memory range address information includes a memory range start address and a memory range end address, and generating the memory address includes establishing a memory address according to the memory range start address and the memory range end address. 15 . The memory startup method according to claim 10 , wherein issuing the write operation command is performed when there is no data information on the data bus. 16 . The memory boot method of claim 10 , wherein the memory controller is one of a plurality of memory controllers, and the boot programming operation is performed in parallel on at least part of the plurality of memory controllers.

17. A storage system comprising: a plurality of memory modules configured to store information, wherein a first one of the plurality of memory modules includes a first group of memory chips and a second one of the plurality of memory modules includes a second group of memory chips; A memory controller comprising a startup module, wherein the startup module is configured to guide a memory startup operation during power-on of the plurality of memory modules, comprising: forwarding a startup pattern to be stored in a mode register of each write mode of the first group of memory chips and the second group of memory chips, selecting a memory address in each of the first group of memory chips and the second group of memory chips to initialize using the startup pattern, and Directs write-style operations of information from the mode registers in each write mode to the corresponding selected memory address.

18. The storage system of claim 17, wherein the first group of memory chips and the second group of memory chips are organized into a plurality of ranks, and write-style operations are performed in parallel at the rank level in the first group of memory chips and the second group of memory chips.

19. The memory system of claim 18, wherein a plurality of the plurality of ranks are enabled simultaneously by asserting a corresponding plurality of rank enable signals.

20. The memory system of claim 17 , wherein a command / address bus and a data bus communicatively couple the memory controller to the plurality of memory modules, wherein a write pattern operation command accompanied by a generated address is sent on the command / address bus, and pattern data is not sent on the data bus.

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