Digital-to-analog converter and method for digital-to-analog conversion

Abstract

A DAC for use in an incremental analog-to-digital converter, iADC, configured to convert a multi-bit word (x[n]) into an analog feedback signal (y[n]). The DAC comprises a MMS logic block. It further comprises a plurality of output elements configured to generate a respective analog portion (y i [n]) based on a selection vector (s[n]), and a signal combiner for combining the analog portions (y i [n]) into the analog feedback signal (y[n]). In the MMS logic block, cascaded switching zone blocks are provided. Each switching zone block receives at least a portion of the multi-bit word (x[n]), splits the portion into two sub-portions, and forwards each sub-portion to one of a subsequent switching zone block or an output element. A weight factor (W[n]) is adjusted by multiplying the weight factor with a difference of the two sub-portions. A weight accumulator accumulates successive adjusted weight factors (W’[n]), wherein how a portion of a further multi-bit word (x[n]) is split is determined based on a sign of the weight accumulator.

Description

Technical Field

[0001] The present invention relates to a digital-to-analog converter for use in an incremental analog-to-digital converter, an incremental analog-to-digital converter, an electronic device, and a method for digital-to-analog conversion. Background Technology

[0002] Incremental analog-to-digital converters (iADCs) are used in many applications that require converting analog signals with a large dynamic range to the digital domain. An iADC is an oversampling noise-shaping converter and includes a digital-to-analog converter (DAC) in its feedback loop. iADCs can also be called incremental Σ-Δ analog-to-digital converters or incremental S / D ADCs.

[0003] As a fundamental characteristic of noise-shaping converters, DAC resolution can be lower than the resolution of the output data words after filtering. However, DAC linearity determines conversion linearity, and thus, unit DACs have been widely used in high-resolution converters in the past. Unit DACs are inherently linear. However, with scaling techniques and the resulting lower supply voltages, the quantization noise of unit DACs has begun to become a limiting factor for signal oscillation at the output of the loop filter integrator.

[0004] Multi-bit DAC designs can help mitigate this problem because each increase in the DAC bit width reduces signal sway by a factor of 2. For high-resolution multi-bit DAC designs with a dynamic range greater than approximately 72 dB, the intrinsic matching of the DAC units is insufficient to guarantee DAC linearity. Therefore, dynamic element matching characteristics are utilized to make the DAC linear by shaping the mismatch outside the signal band.

[0005] For the stability of the iADC's noise shaping loop, it is important to keep the delay between the quantizer decision and the DAC output as small as possible. Since the mismatch shaping (MMS) circuitry used for the DAC is part of the loop, it contributes to the overall delay. Furthermore, the MMS circuitry contributes to the overall hardware complexity of the iADC; complex decimation filters and high-speed clock requirements may be necessary. Summary of the Invention

[0006] The objective is to provide a digital-to-analog converter with a fast and hardware-efficient MMS implementation. A further objective is to provide a method for digital-to-analog conversion with a fast and hardware-efficient MMS implementation.

[0007] This objective is achieved through the independent claims. Other embodiments and variations are derived from the appended claims. The definitions described above also apply to the following description, unless otherwise stated.

[0008] In one embodiment of a digital-to-analog converter (DAC), the DAC is used in an incremental analog-to-digital converter (iADC). The DAC is positioned in the feedback loop of the iADC and configured to convert a multi-bit word into an analog feedback signal. In each clock cycle of the iADC's conversion period, a new multi-bit word is forwarded to the DAC. The multi-bit word represents an integer within a range of integers. The range of integers it represents depends on the number of bits in the multi-bit word. The integer range can cover 2^m+1 distinct integers, where m is a natural number. Thus, the multi-bit word has m+1 bits. For example, the multi-bit word can represent a word in the range of -4 to +4, thereby covering 9 distinct integer values. In this case, the multi-bit word comprises 4 bits.

[0009] The analog feedback signal of a DAC can be any analog signal. For example, the analog feedback signal can be a voltage, current, or charge. The analog feedback signal has a nominal discrete value that depends on an integer represented by multiple bits.

[0010] The DAC includes a mismatched integer shaping logic block. This block is configured to generate a selection vector with a predetermined number of bits based on a multi-bit word. If the multi-bit word represents an integer within a range of 2^m+1 distinct integer values, the predetermined number of bits for the selection vector can be 2^m. For example, if a 4-bit multi-bit word represents an integer in the range -4 to +4, the predetermined number of bits for the selection vector can be 8.

[0011] The DAC also includes multiple output elements. These output elements are configured to generate corresponding analog sections based on a selection vector. The number of output elements is the same as the number of bits in the selection vector. For example, if the predetermined number of bits in the selection vector is 8, then there are 8 output elements. Each bit of the selection vector is associated with a corresponding output element. If the corresponding bit of the selection vector is valid, each output element generates an analog section. If the corresponding bit of the selection vector is invalid, the output element does not generate an analog section, or generates an analog section with the opposite sign. Furthermore, the analog section has the same physical unit as the analog feedback signal. This means that, for example, if the analog feedback signal is a voltage, then the analog section is also a voltage. All output elements are designed to generate the same nominal analog section. However, due to manufacturing processes, all output elements generate nominal analog sections with inherent mismatch errors. The output element can be, for example, a 1-bit DAC.

[0012] The DAC also includes a signal combiner. The signal combiner is configured to combine the analog portions generated by the output elements into an analog feedback signal. The signal combiner sums all analog portions from the output elements. For example, if the analog portions are current or charge loads, the signal combiner could be a line vertex from the output elements.

[0013] Mismatched integer logic blocks comprise a predetermined number of switching blocks. The number of switching blocks is based on the number of output elements, and thus also on the number of bits in a multi-bit word. If the number of output elements is 2^m, the number of switching blocks is 2^m - 1. For example, if the number of output elements is 8, there are 7 switching blocks.

[0014] Each switching block includes a first input for receiving signals and first and second outputs for forwarding signals. Switching blocks are cascaded. This means that switching blocks can be arranged in numbered layers. The first layer of switching blocks includes one switching block that receives a multi-bit word. The two outputs of the first-layer switching block can be connected to the corresponding first input of the second-layer switching block. Similarly, the output of the second-layer switching block can be connected to the first input of the third-layer switching block, and so on. This means that the number of switching blocks doubles with each layer. The output of the switching block in the last layer is connected to an output element. The number of layers of switching blocks depends on the number of bits in the multi-bit word. A multi-bit word includes m+1 bits, resulting in m layers. For example, if the multi-bit word includes 2 bits, there is only one layer of switching blocks, i.e., only one switching block. The output of this one switching block is directly connected to an output element, i.e., in this case, two output elements. Generally, each output of a switching block in a certain layer is connected to the corresponding input of a switching block in a subsequent layer, or connected to an output element.

[0015] Each switching block is configured to receive at least a portion of a multi-bit word, to divide that portion into two sub-parts, and to forward each sub-part to another subsequent switching block or one of the corresponding output elements. Each switching block receives at least a portion of the multi-bit word through a first input. Each switching block forwards the sub-parts of the multi-bit word to a subsequent switching block or one of the output elements through a corresponding output. The first switching block, i.e., the first-level switching block, receives the complete multi-bit word. Subsequent switching blocks receive portions or sub-parts of the multi-bit word, respectively. The division of the portion of the multi-bit word is configured such that the two sub-parts together constitute a portion of the multi-bit word. The division of the multi-bit word portion can be equal or non-equal. This means that the two sub-parts can have equal or unequal values. In particular, if the portion of the multi-bit word represents an odd integer, the two sub-parts can have unequal values. For example, if the portion of the multi-bit word is a 4-bit expression "0111" representing the integer 7, it can be divided into "011" and "100" representing the digits 3 and 4 respectively, and vice versa.

[0016] In each switching block, the weighting factor is adjusted by multiplying the difference between the two sub-parts by a weighting factor. The weighting factor can be a number represented by another multi-bit word. The weighting factor is forwarded to each switching block. The weighting factor can be the same for every switching block. A new weighting factor is provided in each clock cycle of the iADC conversion cycle. The weighting factor can change with each clock cycle of the iADC conversion cycle. The adjusted weighting factor is the original weighting factor multiplied by the difference between the two sub-parts divided from the multi-bit word.

[0017] Each switching block includes a weight accumulator configured to accumulate successive adjusted weight factors. This means that successive adjusted weight factors are summed by the weight accumulator. The accumulated adjusted weight factors can be stored in a register. Depending on the previous adjusted weight factors, the sum of the adjusted weight factors can have a positive or negative sign. Based on the sign of the accumulator, it is determined how to segment the remaining multi-bit words arriving in the corresponding switching block in subsequent clock cycles within the iADC's conversion cycle.

[0018] This means that in the case of non-equal splitting of a multi-bit word portion, either the first or second sub-part is selected as larger than the corresponding other sub-part. For example, if a multi-bit word of "0111" is split into sub-parts "011" and "100", the sign of the weight accumulator can be used to determine which sub-part becomes "011" and which becomes "100". Adding an adjusted weight factor to the weight accumulator can be done after determining how the current multi-bit word portion is split. The weight accumulator can converge to 0 until the last clock cycle of the iADC conversion cycle. When the weight accumulator for each swap block has converged to 0, the mismatch error has also converged to 0.

[0019] MMS is implemented through a mismatch shaping logic block that includes a swapping block. As mentioned above, each output element generates a nominal analog portion with an inherent mismatch error, which affects the linearity of the DAC. By generating selection vectors to activate the corresponding output elements, the overall mismatch error can be mitigated or even eliminated, which improves the linearity of the DAC. The MMS logic provides for activating output elements in a suitable alternating manner.

[0020] iADCs typically include a decimation filter. For power-efficient implementations, the decimation filter of an iADC is a cascade of integrators. In this way, when the iADC order is higher than one, the sampling conversion error of the first clock cycle is weighted more heavily than the sampling conversion error of the last clock cycle. The MMS logic described above takes this into account by setting a weighting factor. This means that the mismatch shaping logic implements a weighted distribution of output element activation.

[0021] Furthermore, the MMS logic described above can be implemented in a very hardware-efficient manner. The circuit complexity of the MMS logic block can be low, i.e., the number of gates can be small. There is no high-speed clock requirement for the MMS logic block; it can operate at the same clock speed as the iADC. This also means that the latency of the mismatch shaping logic block can be kept very low. Moreover, there is no need for decimation filters that require a higher oversampling ratio (OSR) than the basic requirements, or complex decimation filters.

[0022] The method of splitting a multi-bit word into parts defines the ratio between the resulting sub-parts. Specifically, it determines whether one sub-part becomes larger than the other, and if so, which one is larger than the other. The splitting is implemented by a swap block or by components included in a swap block.

[0023] According to at least some embodiments, segmenting a multi-bit word or a portion thereof is performed in one or more steps. This means that two sub-parts can be created directly by segmenting the parts. However, it is also feasible to first generate preliminary sub-parts and then further refine them to obtain the actual sub-parts.

[0024] Therefore, the swap block may include one or more operators configured to generate two sub-parts. For example, the swap region may include division, multiplication, addition, and / or subtraction mechanisms to process the corresponding multi-bit words or portions of multi-bit words input.

[0025] In some implementations, each swap block includes a divider and an optional adder. The divider may be formulated as a right shift operator. The adder may be formulated as a summation operator to add the remainder, such as the least significant bit (LSB), to one of the initial sub-parts. However, different implementations are also possible.

[0026] In other words, the initial sub-part is generated by the divider. Possibly, a remainder is added to or subtracted from the initial sub-part, resulting in one of the actual sub-parts. This means that a sub-part can be a modified version of the initial sub-part. The actual sub-part is formed by modifying the initial sub-part. The sub-part can also be called the resulting sub-part. The resulting sub-part of the swap block is forwarded to one of the corresponding subsequent swap blocks or output elements. However, it is possible for the initial sub-part to be identical to the resulting sub-part. This is the case, for example, if no remainder is added to or subtracted from the initial sub-part, or if the remainder is zero.

[0027] In some embodiments, a new weighting factor is provided in each clock cycle of the iADC conversion cycle, wherein successive weighting factors decrease according to a monotonically decreasing function. This means that the weighting factor of one clock cycle is equal to or less than the weighting factor of the corresponding previous clock cycle. Successive weighting factors may decrease according to a predetermined function, such as a quadratic function. Weighting factors may be provided collectively for all switching blocks. The weighting factors may be provided by a weight generator. The weight generator may include memory elements storing the weighting factors for each clock cycle. This means that the weighting factors may be hard-coded on the memory elements. Alternatively, the weight generator operates as described below.

[0028] According to some implementations, the weight accumulator is reset after each conversion cycle.

[0029] In one embodiment, each switching block further includes a second input for providing a weighting factor. The weighting factor can be a number represented by another multi-bit word. The weighting factor can be forwarded to each switching block simultaneously. The weighting factor can be the same for each switching block. A new weighting factor is provided at each clock cycle of the iADC conversion period. The weighting factor can vary with each clock cycle of the iADC conversion period.

[0030] In one embodiment, each exchange block further includes a third input for providing a clock signal, which serves as an adjusted weighting factor for accumulation by the weight accumulator. The adjusted weighting factor can be applied simultaneously within each exchange block. The clock signal can be such that, after determining how to segment the current multi-bit word portion, the adjusted weighting factor is added to the weight accumulator.

[0031] In some implementations, each swap block also includes a detector configured to detect whether the integer represented by the portion of the multi-bit word reaching the swap block is even or odd. This means the detector checks whether the represented integer is divisible by 2. If there is no remainder after division by 2, the integer is even. If there is a remainder after division by 2, the integer is odd.

[0032] In some implementations, each swap block also includes a divider configured to divide a portion of a multi-bit word into two preliminary sub-parts, each preliminary sub-part having a smaller absolute value than the portion of the multi-bit word. Furthermore, each preliminary sub-part has fewer bits than the portion of the multi-bit word.

[0033] In some implementations, each swap block also includes a selector configured to select one of the preliminary sub-parts based on the sign of the weight accumulator. For example, if the sign of the weight accumulator is positive, the first preliminary sub-part is selected, while if the sign of the weight accumulator is negative, the second preliminary sub-part is selected, and vice versa.

[0034] In some implementations, each swap block also includes an adder configured to add the remainder of the division performed by the divider to the initial sub-part selected by the selector. By adding the remainder of the multi-bit word portion division to one of the initial sub-parts, the two resulting sub-parts together constitute the multi-bit word portion. Furthermore, by adding the remainder of the multi-bit word portion division to one of the initial sub-parts, one of the sub-parts becomes larger. Which sub-part becomes larger is determined by the selector, based on the sign of the weight accumulator. In the case of no remainder, no number is added to the initial sub-part. Due to the algorithm in each swap block, the two resulting sub-parts of the multi-bit word can have equal or unequal values. In particular, if the part of the multi-bit word represents an even integer, the two sub-parts can have equal values. If the part of the multi-bit word represents an odd integer, the two sub-parts have unequal values. In the case of unequal values ​​of the two sub-parts, the selector determines which sub-part is larger than the other based on the sign of the weight accumulator.

[0035] Typically, each swap block is implemented using hardware components. However, swap blocks can also be implemented using software.

[0036] Through a segmentation algorithm, a multi-bit word can be converted into multiple unit words. Specifically, each of the two sub-parts can include one less bit than the multi-bit word portion. If the output element is a 1-bit DAC, each sub-part of the multi-bit word forwarded by the last layer's switching block to the corresponding output element includes 1 bit. Furthermore, by using a weighted accumulator-based selector, each in the output element can be triggered as frequently as needed to mitigate or eliminate mismatch errors.

[0037] In another embodiment, an additional offset is added to the weight accumulator before using the sign to control the selector. The offset can be random or pseudo-random. Thus, the offset either keeps the sign of the weight accumulator unchanged or changes the sign of the weight accumulator. Therefore, the offset can influence the selector's choice of the initial sub-part to which the remainder is to be added.

[0038] If the offset is reasonably small, it will not affect the circuit's performance. Periodic noise patterns can be reduced by using an additional offset.

[0039] In one embodiment, the divider in each swap block is configured to split a portion of a multi-bit word into two preliminary sub-parts with equal values. This splitting is achieved by right-shifting the bits of the multi-bit word and assigning the result to the two preliminary sub-parts. This means that if a portion of the multi-bit word represents an even integer, the divider divides that integer by 2 and assigns the result to the two preliminary sub-parts. This provides two equal sub-parts, leaving a remainder of 0. However, if a portion of the multi-bit word represents an odd integer, the divider divides that integer by 2, rounds the result down, and assigns it to the two preliminary sub-parts. This provides two equal preliminary sub-parts, but leaves a remainder of 1.

[0040] In some embodiments, the adder in each swap block is configured to add the remainder of the division performed by the divider to the initial sub-part selected by the selector. As described above, the remainder is 0 when the multi-word part represents an even integer. The remainder is 1 when the multi-word part represents an odd integer. By adding the remainder of the multi-word part to one of the initial sub-parts, the two resulting sub-parts are added together to form the multi-word part.

[0041] This partitioning logic further simplifies the implementation of the switching blocks. This means that the complexity of the MMS logic block can be reduced. By reducing circuit complexity, the latency of the MMS logic block can also be reduced.

[0042] In one embodiment, the first switching block, i.e., the switching block that receives complete multi-bit words, includes an additional detector configured to detect a sequence of multi-bit words representing even integers greater than the minimum but less than the maximum integer in the integer range. This is equivalent to an integer that is not the minimum or maximum integer in the integer range. In this document, the multi-bit words undergo the switching block at different clock cycles of the iADC's conversion period. The sequence of multi-bit words representing even integers may include at least two consecutive multi-bit words representing even integers.

[0043] For each r-th multi-bit word in the detected sequence, the adder of the first swap block is configured to add the unit to one of two preliminary sub-parts. The subtractor is configured to subtract the unit from the other preliminary sub-part. r is a natural number. For example, r could be 2. The selector determines the corresponding preliminary sub-part based on the sign of the weight accumulator, i.e., the preliminary sub-part to which the unit is to be added and the preliminary sub-part to which the unit is to be subtracted.

[0044] For example, if the 4-bit expression "0110" representing the integer 6 is the r-th multi-word of the detected sequence, the two resulting sub-parts can be the 3-bit expressions "010" and "100" representing the numbers 2 and 4, respectively. Thus, the multi-word representing an even integer is effectively divided into two sub-parts with unequal values. The weighting factor is adjusted by multiplying it by the difference between the two sub-parts (i.e., +2 or -2 respectively).

[0045] In another embodiment, at least two exchange blocks include an additional detector configured to detect sequences of multi-bit words representing even integers that are not the smallest or largest integer in the integer range. For each r-th multi-bit word in the detected sequence, where r is a natural number, an adder is configured to add the unit to one of the two preliminary sub-parts, and a subtractor is configured to subtract the unit from the other preliminary sub-part, wherein a selector determines the corresponding preliminary sub-part based on the sign of the weighted accumulator. Thus, the multi-bit word representing an even integer is effectively segmented into two sub-parts with unequal values.

[0046] By detecting multi-bit word sequences that represent even integers that do not represent the smallest or largest integer in the integer range, and by splitting every r-th multi-bit word of the detected sequence into two parts with unequal values, the convergence time of the MMS logic can be shortened, which means that mismatch errors can be mitigated more quickly.

[0047] In one embodiment, the first exchange block, i.e. the exchange block that receives the complete multi-bit word, includes an additional detector configured to detect multi-bit words representing even integers that are not the smallest or largest integer in the range of integers.

[0048] The first swap block also includes a dither, which randomly determines multi-bit words to be detected by another detector, splitting them into two parts with equal or unequal values. For example, the dither generates a random number centered at approximately 0 and determines how to split even-numbered multi-bit words based on the sign of the random number.

[0049] In the event that the jitter determines unequal partitions, the adder of the first swap block is configured to add the cell to one of the two initial subparts. The subtractor is configured to subtract the cell from the other initial subpart.

[0050] The selector, based on the sign of the weighted accumulator, determines the corresponding preliminary sub-parts: the preliminary sub-parts to add cells to and the preliminary sub-parts to subtract cells from. This effectively splits a multi-bit word representing an even integer into two sub-parts with unequal values.

[0051] In another embodiment, at least two swap blocks include additional detectors configured to detect multi-bit words representing even integers that are not the smallest or largest integer in the integer range. The at least two swap blocks also include a dither, wherein the dither randomly determines even multi-bit words detected by the additional detectors, splitting them into two portions having equal or unequal values. Adders in the at least two swap blocks are configured to add a unit to one of the two preliminary sub-parts, while subtractors are configured to subtract the unit from the other preliminary sub-part, wherein a selector determines the corresponding preliminary sub-part based on the sign of a weighted accumulator. Thus, multi-bit words representing even integers are effectively split into two sub-parts with unequal values.

[0052] By detecting multi-bit words representing even integers and randomly determining whether to split the even multi-bit words into two parts with equal or unequal values, the convergence time of MMS logic can be shortened, which means that mismatch errors can be eliminated more quickly.

[0053] In one embodiment, the DAC further includes a weight generator configured to provide successive weight factors for each clock cycle in the iADC's conversion period. The weight factors can be numbers represented by additional multi-bit words. The weight factors are generated jointly for all switching blocks. In a given clock cycle, the weight factors can be the same for every switching block. A new weight factor is provided in each clock cycle of the iADC's conversion period.

[0054] The weighting factor can vary with each clock cycle of the iADC's conversion period, or it can remain constant. In particular, the weight generator generates a weighting factor that monotonically decreases with respect to subsequent clock cycles.

[0055] The weighting factor can be reduced according to a predetermined function. This predetermined function can be based on the quantity of the integral stage of the weight generator. Typically, the weighting factor is generated by the same quantity of the integral stage as that in the decimation filter of the iADC, to match the weighting of the DAC and the decimation filter. The weighting factor thus decays with a quadratic curve in the case of a second-order decimation filter, or with a cubic curve in the case of a third-order decimation filter.

[0056] Typically, for an iADC, the total number of clock cycles in the conversion cycle is the OSR. The weighting factor of the last clock cycle in an iADC conversion cycle must be 1, while the weighting factor of the first clock cycle in an iADC conversion cycle is the largest. Theoretically, the weighting factor W of the first clock cycle can be calculated as follows:

[0057]

[0058] Where OSR is the oversampling ratio, Z is the integral series of the weight generator, and "!" denotes the factorial function. However, the size and bit width of the weight factor can be significantly reduced without significantly degrading the signal, resulting in a smaller value for the weight factor.

[0059] As the weighting factor decreases with each subsequent clock cycle, and as the weighting factor is adjusted in each swap block by multiplying the two sub-parts of a multi-bit word by the difference between them (which can be positive or negative), the weight accumulator converges to 0. Once the weight accumulator converges to 0 in each swap block, the mismatch error is eliminated.

[0060] By using a weight generator that produces monotonically decreasing weighting factors, it is considered that in the iADC, the first DAC feedback value is weighted more than the last feedback value. Due to the MMS logic, this weighting is taken into account to generate a selection vector. Each output element is triggered as frequently as needed to mitigate or eliminate mismatch errors.

[0061] In one embodiment, the weight generator further includes a generator input that receives a digital starting factor. The digital starting factor can be another multi-bit word. The digital starting factor is configured to iteratively calculate successive weight factors according to a predetermined function. In one example of this embodiment, the digital starting factor is hard-coded in an integration register included in the weight generator. In this case, no generator input is required.

[0062] In some embodiments, the weight generator further includes a generator output that provides weight factors. The generator output can be connected to a second input of the swap block to provide weight factors. At each clock cycle of the iADC's conversion period, the generator output provides updated weight factors. The generator output collectively provides weight factors for each swap block.

[0063] In some embodiments, the weight generator further includes at least one integration stage that couples the generator input to the generator output. However, the weight generator may include more than one integration stage. Typically, the weight generator includes the same number of integration stages as the decimation filter of the iADC to match the weighting of the DAC and the decimation filter. However, the weight generator may also include more or fewer integration stages. For example, the weight generator may include three integration stages. As mentioned above, in the case of three integration stages, the successive weighting factors decay according to a cubic curve.

[0064] In some embodiments, each integration stage further includes a stage input for receiving digital input signals, either from a generator input or from a previous integration stage. Each integration stage also includes a stage output for providing a digital output signal, either to a subsequent integration stage or the generator output. This means that the stage input of the first integration stage is connected to the generator input. The stage inputs of subsequent integration stages are connected to the stage outputs of previous integration stages. The stage output of the final integration stage is connected to the generator output.

[0065] In some embodiments, each integration stage further includes a stage combiner configured to combine the digital input signal and feedback from the digital output signal. Specifically, the stage combiner subtracts the digital input signal from the feedback from the digital output signal.

[0066] In some embodiments, each integration stage further includes a register configured to process a combination of digital input signals and feedback from digital output signals, the register providing the digital output signals.

[0067] Typically, weight generators are implemented in software. However, weight generators can also be implemented using hardware components.

[0068] A weight generator produces monotonically decreasing weight factors. These weight factors can be forwarded to each exchange block to support MMS logic, including a weighting algorithm. The predetermined function upon which the weight factors are decremented can be controlled by an integral-level quantity.

[0069] In one embodiment, the weight generator forwards the corresponding weight factor for a given clock cycle of the conversion period to each switching block. In this paper, the generator output providing the weight factor is connected to a second input for each switching block. The generator output provides a different weight factor for each clock cycle of the iADC's conversion period. The generator output collectively provides the weight factor for each switching block.

[0070] Since each switching block can operate with the same weighting factor, circuit complexity can be further simplified.

[0071] In one embodiment, the DAC is integrated into the iADC. The iADC also includes inputs for providing analog input signals. The analog input signals can be any analog signal, such as current, voltage, or charge.

[0072] In some embodiments, the iADC also includes a combiner configured to combine an analog input signal and an analog feedback signal from a DAC. The analog feedback signal from the DAC has the same physical units as the analog input signal. For example, if the analog input signal is a voltage, the analog feedback signal from the DAC is also a voltage. The iADC combiner is connected to the input of the iADC, and the signal combiner is connected to the DAC.

[0073] In some embodiments, the iADC further includes a loop filter configured to filter a combination of the analog input signal and the analog feedback signal. Loop filters for incremental analog-to-digital conversion are known to those skilled in the art. The loop filter may be of higher order.

[0074] In some embodiments, the iADC further includes an N-level quantizer for generating multi-bit words based on the output of the loop filter. The multi-bit word represents an integer within a range of integers. The range of integers represented depends on the number of bits in the multi-bit word. The N-level quantizer can generate multi-bit words representing at least N distinct integers, where N is a natural number.

[0075] In some embodiments, the iADC further includes a feedback path comprising a DAC. The DAC is configured to convert a multi-bit word from an N-stage quantizer into an analog feedback signal for a combiner used by the iADC. The DAC is described in detail above.

[0076] In some embodiments, the iADC further includes a decimation filter configured to filter multiple bits to generate a digital system output signal. Typically, the decimation filter is implemented as a cascade of integrators. The magnitude of the integrator stage of the decimation filter can be adjusted to match the magnitude of the integrator stage of the weight generator. Decimation filters are known to those skilled in the art.

[0077] iADCs can be used in applications requiring the conversion of analog signals with a large dynamic range into the digital domain. An iADC is an oversampled noise-shaping converter, and its analog circuitry is very similar to a sigma-delta (S / D) modulator. Unlike S / D modulators, the iADC is reset after each conversion, thus removing the correlation between conversions. This feature allows iADCs to be used in systems where uncorrelated signals are multiplexed into a single ADC.

[0078] In one embodiment, the iADC is integrated into an electronic device. Furthermore, the electronic device is connected to at least one sensor, wherein the iADC is configured to perform analog-to-digital conversion on a signal provided by the at least one sensor. The sensor can be any environmental sensor that generates analog signals (e.g., voltage, current, or charge load). For example, the sensor can be an optical sensor, such as a photodiode or an array of photodiodes. The sensor can also be based on a resistor bridge. In one embodiment, the iADC can be a 16-bit analog-to-digital converter with a conversion rate of 100,000 samples per second (100 kSPS).

[0079] By using an iADC in an electronic device connected to at least one sensor, environmental parameters such as electromagnetic radiation can be measured and further processed in digital circuitry.

[0080] In another embodiment, the iADC is integrated into a current-to-digital converter integrated circuit, which also includes a current-to-voltage converter, wherein the iADC is configured to convert the output of the current-to-voltage converter into a digital representation.

[0081] By using a current-to-digital converter, current can be converted into a voltage signal, which can then be converted into a digital signal.

[0082] A digital-to-analog conversion method is also provided. All the features described for the digital-to-analog converter are also described for the digital-to-analog conversion method, and vice versa.

[0083] The digital-to-analog conversion method includes converting a multi-bit word representing an integer within a range of integers into an analog feedback signal for an incremental analog-to-digital converter (iADC). The method also includes generating a selection vector with a predetermined number of bits based on the multi-bit word. Generating the selection vector can be implemented using a mismatched shaping logic block comprising a predetermined number of swap blocks. Both the mismatched shaping logic block and the swap blocks can be implemented in software.

[0084] The method also includes generating a corresponding analog portion based on a selection vector. Generating the analog portion is implemented using multiple output elements. The method further includes combining the analog portions into an analog feedback signal.

[0085] The generation of the selection vector also includes successively dividing the multi-bit word into corresponding parts and sub-parts. For example, a part of a multi-bit word or a multi-bit word may be forwarded to a switching block, then the part is divided into two sub-parts, and each sub-part is then forwarded to a corresponding subsequent switching block, or forwarded to one of the output elements.

[0086] The generation of the selection vector also includes adjusting the weighting factor by multiplying the difference between the two corresponding sub-parts by a weighting factor. For example, in each swap block, they are adjusted by multiplying the difference between the two sub-parts generated in the corresponding swap block by a weighting factor.

[0087] Accumulate successively adjusted weighting factors. Based on the sign of the accumulated adjusted factors, determine how to segment the additional multi-bit words of subsequent clock cycles within the iADC's conversion cycle. For example, in each switching block, adjusted weighting factors can be accumulated in a weight accumulator. Like switching blocks, the weight accumulator can be implemented in software.

[0088] This digital-to-analog conversion method achieves MMS (Mismatched Selective Motion). By generating selection vectors to activate the corresponding output elements, the overall mismatch error can be mitigated or even eliminated, improving the DAC's linearity. Furthermore, by incorporating a weighted algorithm into MMS, the sampling conversion error of the first clock cycle is taken into account as being weighted much more heavily than that of the last clock cycle. This method is easy to implement and can be implemented quickly. This means that latency can be kept very low.

[0089] In another embodiment, the method further includes providing a new weighting factor in each clock cycle of the iADC's conversion period. Successive weighting factors decrease according to a monotonically decreasing function.

[0090] In another embodiment of the method, the method further includes generating successive weighting factors for each clock cycle of the iADC conversion cycle using a weight generator. The weight generator can be implemented in software. The generation of weighting factors also includes receiving a digital start factor at the generator input. Alternatively, the digital start factor can be hard-coded in a register, eliminating the need for a generator input. At least one integration stage is provided, which couples the generator input to the generator output. At the stage input of the integration stage, a digital input signal from the generator input or from a previous integration stage is received. The digital input signal is combined with feedback from a digital output signal. After processing the combination of the digital input signal and the feedback from the digital output signal, a digital output signal can be provided at the stage output. The digital output signal is provided to a subsequent integration stage or the generator output. The generation of weighting factors also includes providing weighting factors at the generator output.

[0091] By generating successive weighting factors for each clock cycle of the iADC conversion cycle, it is taken into account that in the iADC, the first DAC feedback value of the conversion is weighted more than the last feedback value. The weighting factors can be generated according to a predetermined function that supplements the weighting of the DAC feedback values. For example, the weighting factors decrease according to a monotonically decreasing function.

[0092] In another embodiment of the method, it is detected whether the integer represented by a portion of the multi-bit word of the input corresponding exchange block is even or odd. The portion of the multi-bit word is divided into two preliminary sub-parts with equal values. The division can be achieved by a right shift operation. This means dividing the represented integer by 2 and rounding it down. If the integer represented by the multi-bit word is even, a remainder of 0 is left from the division. If the integer represented by the multi-bit word is odd, the remainder is 1. Then, a preliminary sub-part is selected based on the accumulated sign of the adjusted weighting factors. The remainder of the division is added to the preliminary sub-part selected based on the accumulated sign of the adjusted weighting factors.

[0093] This algorithm enables the implementation of sub-parts with one less bit than the multi-bit word part, which are generated by segmenting the multi-bit word part. Furthermore, the algorithm is easy to implement and does not consume much time during execution. Since an initial sub-part is selected based on the sign of the weighted accumulator, the weight of the DAC feedback value at that specific clock cycle within the iADC's conversion period is taken into account.

[0094] In another implementation of the method, in the first exchange block, a sequence of multi-bit words representing even integers that are not the smallest or largest integer in the integer range is detected. The multi-bit words in the sequence reach the exchange block in a subsequent clock cycle of the iADC conversion period. For each r-th multi-bit word of the detected sequence, where r is a natural number, a unit is added to one of two preliminary sub-parts and subtracted from the other preliminary sub-part, wherein the corresponding preliminary sub-part is selected based on the cumulative sign of an adjusted weighting factor. This algorithm enables faster MMS convergence.

[0095] In another implementation of the method, in the first exchange block, multi-bit words representing even integers that are not the smallest or largest integer in the integer range are detected. Furthermore, the detected multi-bit words representing even integers are randomly divided into equal or unequal values. In the case of unequal divisions, a unit is added to one of two preliminary sub-parts and subtracted from the other preliminary sub-part, wherein the corresponding preliminary sub-parts are based on the accumulated sign of an adjusted weighting factor. Moreover, this algorithm allows for faster MMS convergence.

[0096] The method can be implemented using a DAC according to any of the above embodiments. Further implementations of the method will be apparent to those skilled in the art who have read the various embodiments of the DAC described above. Attached Figure Description

[0097] The improved conversion concept will be described in more detail below with reference to the accompanying drawings, for several embodiments. The same reference numerals indicate signals, elements, or components having the same function. If signals, elements, or components correspond to each other functionally, they are not necessarily described repeatedly in each of the following figures.

[0098] Figure 1 A schematic diagram of an incremental analog-to-digital converter (iADC) is shown.

[0099] Figure 2 A schematic diagram of one embodiment of a digital-to-analog converter (DAC) is shown.

[0100] Figure 3 The selection vector is shown according to one embodiment of a digital-to-analog converter (DAC).

[0101] Figure 4 A schematic diagram of a switching block according to one embodiment of a digital-to-analog converter (DAC) is shown.

[0102] Figure 5 A schematic diagram of a switching block according to another embodiment of a digital-to-analog converter is shown.

[0103] Figure 6 shows the following based on Figure 5 Two flowcharts for even-value detection in an embodiment.

[0104] Figure 7 A schematic diagram of a weight generator according to one embodiment of a digital-to-analog converter (DAC) is shown.

[0105] Figure 8 A schematic diagram of an electronic device according to one embodiment is shown. Detailed Implementation

[0106] exist Figure 1 The diagram shows a schematic of an incremental analog-to-digital converter (iADC). Since the conceptual principles of iADC are known to those skilled in the art, only a rough illustration is provided.

[0107] iADC 1 includes an input 2 for providing an analog input signal A. iADC also includes a feedback path 3 with a digital-to-analog converter DAC 4. For each clock cycle n in the iADC's conversion cycle, DAC 4 provides an analog feedback signal y[n]. Both the input signal A and the analog feedback signal y[n] are forwarded to a combiner 5 of iADC 1. Combiner 5 sums the analog input signal A and the inverted analog feedback signal y[n] and forwards the combined signal C to a loop filter 6. This means the combiner subtracts the analog feedback signal y[n] from the analog input signal A. Loop filter 6 is configured to filter the combined signal C according to a known filtering technique. The filtered signal F is then forwarded to an N-stage quantizer 7. In each clock cycle n, the N-stage quantizer 7 generates a multi-bit word x[n] from the filtered signal F. Depending on the number of significant bits in the multi-bit word, the multi-bit word x[n] can represent N distinct integers, where N is a natural number. The multi-bit word x[n] is forwarded through feedback path 3 to DAC 4, which is configured to convert the multi-bit word x[n] into an analog feedback signal y[n].

[0108] The DAC 4 in feedback path 3 includes a mismatch shaping logic block 8. The mismatch shaping logic block is configured to generate a selection vector s[n] with a predetermined number of bits. This number of bits is based on a multi-bit word x[n]. DAC 4 also includes multiple output elements 9 and a signal combiner 10. The number of output elements 9 corresponds to the number of bits in the selection vector s[n]. The output elements 9 are configured to generate a corresponding analog portion y based on the selection vector s[n]. i[n], where i is the number of output element 9. This means that each of the selection vectors s[n] is associated with the corresponding output element 9. If the corresponding bit of the selection vector s[n] is valid, each output element 9 generates the analog part y. i [n]. If the corresponding bit of the selected vector s[n] is invalid, output element 9 will not generate the analog part y. i [n], or generate the analog part y with the opposite sign. i [n]. The signal combiner 10 will combine all the analog components y generated by the output element 9. i [n] are combined to form an analog feedback signal y[n]. This means that the signal combiner 10 sums all the analog parts y. i [n].

[0109] The iADC 1 also includes a decimation filter 11. The decimation filter 11 receives a multi-bit word x[n] for each clock cycle n of the iADC 1's conversion cycle. The decimation filter 11 is configured to filter the multi-bit word x[n] to generate the digital system output signal D. The filtering techniques that can be used with the decimation filter 11 are generally known to those skilled in the art.

[0110] exist Figure 2 The diagram illustrates one embodiment of a DAC 4. In this example, the DAC 4 has a limited resolution. However, the DAC 4 can be easily adjusted to achieve lower or higher resolutions. Therefore, Figure 2 The schematic diagram shown should be understood as an exemplary embodiment without loss of generality.

[0111] DAC 4 comprises several components: a mismatch shaping logic block 8, multiple output elements 9, and a signal combiner 10. These components are connected via multiple signals. The mismatch shaping logic block 8 includes a predetermined number of cascaded switching blocks 12. The number of switching blocks 12 is predetermined by multi-bit words representing integers within a range of integers. For the same reason, the number of output elements 9 is predetermined. In this example, the mismatch shaping logic block 8 includes seven switching blocks 12a to 12g and eight output elements 9a to 9h.

[0112] pass Figure 2 The DAC is capable of converting multi-bit words x[n] representing integers covering a range of nine distinct integers. The integers covered by the range correspond to the levels of an N-level quantizer 7. In this example, an N-level quantizer 7 is a 9-level quantizer that generates 4-bit words.

[0113] The swap blocks are cascaded in a 12-level configuration to form a swap block layer L. j The first layer L1 of the swap block includes a swap block 12a. From layer L... j To layer L j+1The number of swap blocks 12 is doubled. Thus, in this example, the second layer L2 includes two swap blocks 12b to 12c, and the third layer L3 includes four swap blocks 12d to 12g.

[0114] exist Figure 2 In this configuration, the number of bits for the input and output signals of each switching block is indicated by the numbers on the edges of the signal lines. Switching block 12a of the first layer L1 receives a multi-bit word x[n] from an N-stage quantizer; in this example, the multi-bit word is a 4-bit signal. The multi-bit word x[n] is divided by switching block 12a into two parts x[n]. 1234 [n] and x 5678 [n], they are forwarded to exchange blocks 12b to 12c of the second layer L2. The part of the multi-bit word x[n] 1234 [n] and x 5678 [n] is a 3-bit signal, thus having one less bit than a multi-bit word x[n]. In the next step, part of x... 1234 [n] is divided into sub-parts x by the swapped block 12b. 12 [n] and x 34 [n], while part of x 5678 [n] is divided into sub-parts x by the swapped block 12c. 56 [n] and x 78 [n]. Subpart x 12 [n]、x 34 [n]、x 56 [n], and x 78 [n] is a 2-bit signal. They are forwarded to switching blocks 12d through g in Layer 3 (L3). Switching block 12d divides the sub-part x12[n] into further sub-parts x1[n] and x2[n], each of which is a 1-bit signal. Switching block 12e then divides the sub-part x... 34 [n] is divided into further sub-parts x3[n] and x4[n], each of which is a 1-bit signal. Exchange block 12f divides sub-part [n]56[n] into further sub-parts x5[n] and x6[n], each of which is a 1-bit signal. Exchange block 12g divides sub-part x... 78 [n] is divided into further sub-parts x7[n] and x8[n], each of which is a 1-bit signal.

[0115] like Figure 3 As shown, each further sub-part x 1-8 [n] is the element of the selected vector s[n]. Each further sub-part x 1-8 [n] is forwarded to the corresponding output elements 9a-h. Output element 9 can be a 1-bit DAC. This depends on the selection vector s[n], which includes further sub-parts x.1-8 The bit of the vector [n] is selected to trigger output element 9. If the corresponding bit of vector s[n] is selected, i.e. x i [n] is valid, and each output element 9 generates an analog portion y. i [n]. If we choose the corresponding bit of vector s[n], i.e. x i [n] is invalid; output element 9 does not generate the analog part y. i [n], or generate the analog part y with the opposite sign. i [n].

[0116] Signal combiner 10 will combine all the analog components y generated by output element 9 i [n] are combined to form the analog feedback signal y[n]. The analog feedback signal y[n] is also forwarded to the combiner 5 of the iADC.

[0117] exist Figure 3 The image shows an example of a selection vector s[n]. In this example, the selection vector s[n] has at least eight elements x. i [n], which controls at least eight output elements 9. In DAC 4, there is a ratio... Figure 2 In the case of higher resolution DAC 4, mismatch logic block 8 includes more than seven switching blocks 12 and more than eight output elements 9. In this case, the number of elements included in the selection vector s[n] is the same as the number of output elements 9, which is indicated by the point at the end of the selection vector s[n].

[0118] exist Figure 4 The diagram illustrates an exemplary switching block 12 according to one embodiment of DAC 4. The shown switching block 12 should be understood as an exemplary embodiment based on the basic idea of ​​the proposed MMS logic. For those skilled in the art reading this document, the proposed MMS logic differs from... Figure 4 However, other implementations with the same functionality will become obvious.

[0119] Furthermore, the shown swap block 12 can be any swap block 12 in the mismatch shaping logic block 8 of DAC 4. This means Figure 4 The swap block 12 can be set at any level L of the mismatch shaping logic block 8. j In the middle. Exchange block 12 has at least a portion of x for receiving a multi-bit word x[n] or a multi-bit word x[n]. k The first input to [n] is 13. Without loss of generality, Figure 4 The switching block 12 receives the input signal, which includes a portion of the multi-bit word x[n]. abcd [n], and has L digits, where L is a natural number greater than 1.

[0120] The switching block 12 also includes a second input 14 for providing a weighting factor W[n] for each clock cycle n in the conversion cycle of iADC 1. The weighting factor W[n] can be a signal comprising K bits, where K is a natural number. The switching block also includes a third input 15 for providing a clock signal CLK.

[0121] The part of the multi-bit word x[n] abcd [n] is forwarded to detector 16. Detector 16 detects part x. abcd [n] indicates whether the integer is even or odd. If part x abcd [n] represents an even integer, and detector 16 outputs "0". Otherwise, if part x abcd [n] represents an odd integer, and detector 16 outputs "1". The output of detector 16 can be interpreted as part of x. abcd The remainder ε of division of [n].

[0122] The part of the multi-bit word x[n] abcd [n] is also forwarded to divider 17. Divider 17 will divide part of x abcd [n] is divided into two equal preliminary sub-parts x. ab [n] and x cd [n]. The partition can be achieved by right-shifting the part x. abcd This is implemented using the bits of [n]. This means that it is achieved by a portion of x. abcd The integer represented by [n] is divided by 2 and rounded down. The result of this division is assigned to two initial sub-parts x. ab [n] and x cd [n]. In part of x abcd When [n] represents an even integer, the division leaves a remainder ε=0, meaning the two initial sub-parts x ab [n] and x cd [n] together are part of x abcd [n]. In part of x abcd [n] represents the case where the division leaves a remainder ε=1 when the number of integers is odd. As mentioned above, this remainder ε is output by detector 16.

[0123] The swap block 12 also includes an adder 18. Adder 18 is configured to add the remainder ε of the division performed by divider 17 to one x in the initial sub-part. ab [n] or x cd [n]. The adder includes a first AND gate 19 and a second AND gate 20. One of the input terminals of the first AND gate 19 is inverted. The remainder ε of the output of the detector 16 is forwarded to the non-inverted input terminal of the two AND gates 19 and 20. The adder also includes a configuration to add the remainder ε to the first preliminary sub-part x. abThe first addition operator 21 of [n]. The output of the first AND gate 19 is connected to the first addition operator 21. The adder also includes a configuration to add the remainder ε to the second preliminary sub-part x. cd The second addition operator 22 of [n]. The output of the second AND gate 20 is connected to the second addition operator 22.

[0124] Exchange block 12 also includes an x ​​configured to select the remainder ε to be added from the initial sub-part. ab [n] or x cd Selector 23 for [n]. In this paper, the selection is based on the adjusted weighting factor W[n] accumulated from the previous clock cycles. If the remainder ε is to be added to the first preliminary sub-part x ab [n], selector 23 outputs 0. Conversely, if the remainder ε is to be added to the second preliminary sub-part x cd [n], Selector 23 outputs 1. The selection signal δ of the output of selector 23 is forwarded to another corresponding input terminal of the AND gates 19 and 20 of adder 18. Thus, the selection signal δ is forwarded to the inverted input terminal of the first AND gate 19 and the non-inverted second input terminal of the second AND gate 20.

[0125] Only when both input terminals of one of the AND gates 19 and 20 are "1" will the corresponding AND gate forward the "1" to the corresponding addition operators 21 and 22, respectively, causing the addition to the corresponding preliminary subpart x. ab [n] or x cd [n]. This means that when the remainder ε is "0", no addition is made. When the remainder ε is "1" and the selection signal δ is "0", the first AND gate is activated, thus becoming "1", since the selection signal δ is inverted. When the remainder ε is "1" and the selection signal δ is "1", the second AND gate is activated.

[0126] Exchange block 12 also includes forwarding the first sub-part x ab The first output of [n] is 24. The swap block 12 also includes forwarding the second sub-part x. cd The second output of [n] is 25. Two sub-parts x ab [n]、x cd [n] has L-1 bits, thus it is more than the part of the multi-bit word x[n] x. abcd [n] is one place short. Furthermore, in some x... abcd When [n] represents an even integer, the two sub-parts x ab [n]、x cd [n] have equal values. In part x abcd [n] represents the sub-part x when it is an odd integer. ab [n]、xcd One of [n] is 1 greater than the corresponding other.

[0127] The weighting factor W[n] provided by the second input 14 of the swap block 12 is used by sub-parts x of the two outputs. ab [n]、x cd The difference between [n] is multiplied by it to adjust. This is achieved using a first logical operator 26 and a second logical operator 27. The first logical operator 26 is connected to a selection signal δ for evaluation. If the selection signal δ is "0", the weight factor W[n] is multiplied by -1 and forwarded to the second logical operator 27. If the selection signal δ is "1", the weight factor W[n] is multiplied by +1, i.e., remains unchanged, and forwarded to the second logical operator 27. The second logical operator 27 receives the remainder ε for evaluation. If due to part x abcd Since the integer represented by [n] is odd, the remainder is "1". Therefore, the second logical operator 27 outputs the weighting factor W'[n] adjusted by the first logical operator 26. If due to part of x... abcd Since the integer represented by [n] is even, the remainder is "0", so the weight factor W[n] is multiplied by 0 and forwarded further. In this case, the second logical operator 27 outputs "0".

[0128] The exchange block 12 also includes a weight accumulator 28 configured to accumulate successive adjusted weight factors W'[n]. The weight accumulator 28 includes an addition operator 29 and a storage 30. The addition operator 29 adds the adjusted weight factor W'[n] from the second logical operator 27 and the accumulated adjusted weight factor W'[n] from the previous clock cycle output by the storage 30. n-1 This sum is then stored in storage 30 as the new accumulated R. n-1 This is used for the next clock cycle n+1. Store 30 received clock signal CLK to store the new accumulated R on time. n-1 The new accumulated R n-1 The storage is made into storage 30 by selecting the initial sub-part x by selector 23. ab [n]、x cd One of [n] is implemented later. Storage 30 will accumulate the adjusted weighting factors W'[n] R. n-1 Forwarded to selector 23 for use in subsequent clock cycles n+1.

[0129] exist Figure 5 The diagram shows another exemplary switching block 12 according to one embodiment of DAC 4. Specifically, Figure 5 The switching block 12 can be the first layer L1 switching block 12 of the mismatched integer logic block 8 that receives multiple bits x[n].

[0130] Figure 5 Exchange block 12 and Figure 4 The difference between the switching block 12 and the original block 12 is that it also includes an additional detector 41 for receiving multi-bit words. In one embodiment, the additional detector 41 detects sequences of multi-bit words x[n] representing even integers that are not the smallest or largest integer in the integer range. In another embodiment, the additional detector 41 detects multi-bit words x[n] representing even integers that are not the smallest or largest integer in the integer range and includes a jitter 42 that randomly determines how to segment the detected multi-bit words. Depending on the detection, the additional detector 41 outputs either "0" or "1". The output signal is denoted as unit u. The additional detector 41 is described in more detail in FIG. 6.

[0131] Figure 5 Exchange block 12 and Figure 4 The difference also lies in the inclusion of OR gate 43. The first input terminal of OR gate 43 is connected to the output of another detector 41. The second input terminal is connected to detector 16. The output terminal of OR gate 43 is connected to the corresponding input terminals of the AND gates 19 and 20 of adder 18. This means that in this embodiment, adder 18 is also configured to add the unit u output by the other detector 41 to one of the two preliminary sub-parts x generated by divider 17. 1234 [n] or x 5678 [n].

[0132] Figure 5 The swap block 12 also includes a subtractor 44. The subtractor 44 is configured to subtract from another x in the corresponding two initial sub-parts. 1234 [n] or x 5678 [n] Subtract unit u. Subtractor 44 includes a first AND gate 45 and a second AND gate 46. One of the input terminals of the second AND gate 46 is inverted. The unit u output by the additional detector 41 is forwarded to a non-inverted input terminal of each of the two AND gates 45 and 46. Subtractor 44 also includes a subtractor configured to subtract from the first preliminary sub-section x. 1234 [n] Subtracts the first difference operator 47 from unit u. The output of the first AND gate 45 is connected to the first difference operator 47. The subtractor 44 also includes a subtractor configured to subtract from the second preliminary sub-part x. 5678 [n] Subtract the second difference operator 48 from unit u. The output of the second AND gate 48 is connected to the second difference operator 48.

[0133] The selection signal δ output by selector 23 is forwarded to another corresponding input terminal of AND gates 45 and 46 of subtractor 44. Thus, the selection signal δ is forwarded to the inverting input terminal of the second AND gate 46 and the non-inverting second input terminal of the first AND gate 45.

[0134] Figure 5 The exchange block 12 also includes a third logical operator 49 positioned between the first logical operator 26 and the second logical operator 27. The third logical operator 49 is connected to the output of another detector 41, namely unit u, for evaluation. If unit u is "0", the adjusted weight factor W'[n] from the first logical operator 26 is multiplied by 1, i.e., remains unchanged, and is forwarded to the second logical operator 27. If unit u is "1", the adjusted weight factor W'[n] from the first logical operator 26 is multiplied by 2 and is forwarded to the second logical operator 27.

[0135] Figure 6a shows a flowchart of the logic operation of another detector 41 according to one embodiment. This embodiment refers to another detector 41 for detecting sequences of multi-bit words x[n] that represent even integers that are not the smallest or largest integers in the integer range.

[0136] The additional detector 41 receives a multi-bit word x[n]. In the first step, it checks whether the multi-bit word represents an even integer. If the multi-bit word x[n] does not represent an even integer, the counter EvenCNT, which initially has a value of 0, is reset to 0, and the additional detector 41 outputs "0", resulting in an equal split. If the multi-bit word x[n] represents an even integer, the counter is incremented by 1. In the latter case, in the second step, it checks whether the counter EvenCNT is greater than the parameter CNTLimit. For example, the parameter CNTLimit can be 1 if each second multi-bit word x[n] of the detected sequence should be split into parts with unequal values. If the timer EvenCNT is less than or equal to the parameter CNTLimit, the additional detector 41 outputs "0". Otherwise, in the third step, it checks whether the integer represented by the multi-bit word x[n] is less than the maximum value of the integer range and greater than the minimum value of the integer range. If so, the additional detector 41 outputs "1", resulting in an unequal split. Otherwise, the additional detector 41 outputs "0". The order of the second and third steps can be swapped without affecting the overall result. The third step can also be performed before the first step without significantly impacting overall performance.

[0137] Figure 6b shows a flowchart of the logic operation of another detector 41 according to another embodiment. This embodiment refers to another detector 41 that detects a multi-bit word x[n] representing an even integer that is not the smallest or largest integer in the integer range, wherein a dither 42 randomly determines how to segment the detected multi-bit word.

[0138] Another detector 41 receives a multi-bit word x[n]. In the first step, it checks whether the multi-bit word x[n] represents an even integer. If the multi-bit word x[n] does not represent an even integer, the other detector 41 outputs "0". Otherwise, the dither 42 randomly determines how to split the multi-bit word x[n], that is, to split it into two sub-parts with equal or unequal values. The dither 42 can be a random number generator that generates random numbers between 0 and 1. If the random number is less than 0.5, the other detector 41 outputs "0", resulting in an equal split. Otherwise, in the next step, it checks whether the integer represented by the multi-bit word x[n] is less than the largest integer in the integer range and greater than the smallest integer in the integer range. If so, the other detector 41 outputs "1", resulting in an unequal split. Otherwise, the other detector 41 outputs "0". The order of the steps can be rearranged without affecting the overall functionality.

[0139] exist Figure 7 The diagram shows a weight generator 31 according to one embodiment of DAC 4. Figure 7 The weight generator 31 shown represents a preferred embodiment of the weight generator 31. However, different embodiments are also possible. For example, the weight generator 31 may include a memory element (not shown) in which different weight factors W[n] are stored.

[0140] Figure 7 The weight generator 31 includes a generator input 32 for receiving a digital start factor 33. The start factor 33 may be provided by external hardware or external software, or it may be hard-coded in an integration register within the weight generator. For each clock cycle n, the start factor is required to successively calculate a monotonically decreasing weight factor W[n]. To this end, the weight generator 31 includes a generator output 34 for forwarding the weight factor W[n] to a second input 14 of the switching block 12.

[0141] Figure 7The weight generator 31 includes three integration stages 35a to 35c that couple the generator inputs to the generator outputs. As labeled for the first integration stage 35a, each integration stage 35 includes a stage input 36. The stage input 36 receives a corresponding digital input signal from the generator input 32 or from a previous integration stage 35. As also labeled for the first integration stage 35a, each integration stage 35 also includes a stage output 37. The stage output 37 provides a digital output signal for a corresponding subsequent integration stage 35 or generator output 34. This means that the digital output signal of the final integration stage 35c is the weighting factor W[n]. Each integration stage 35 also includes a stage combiner 38 configured to combine the digital input signals and feedback from the digital output signals. For the first integration stage 35a, the stage combiner 38 is labeled. Specifically, the stage combiner 38 subtracts the digital input signal from the feedback from the digital output signal. Each integration stage 35 also includes a register 39 configured to process the combination of the digital input signals and feedback from the digital output signals. The register 39 provides a corresponding digital output signal for each integration stage 35. Each register receives register factors 40a to 40c. For the first clock cycle n = 1 in the iADC 1 conversion cycle, register factors 40a to 40c may be required to initialize register 39 with initial values. Register factors 40a to 40c can be derived from the initial factor 33 and the condition that the weighting factor W[n] of the OSR in the last clock cycle n = 1 in the iADC 1 conversion cycle. For each new conversion cycle of iADC 1, i.e., for each clock cycle n = 1, register 39 of each integrator stage 35 can be reinitialized. However, reinitialization can also occur at other time intervals. For example, reinitialization occurs every Xth conversion cycle. For example, register 39 can be reinitialized after every second or third conversion cycle. The exact timing of reinitialization has no significant impact on the functionality of the iADC.

[0142] Figure 8 A schematic diagram of an exemplary embodiment of an electronic device (50) including an iADC (1) and connected to at least one sensor (51) is shown. The iADC (1) is configured to perform analog-to-digital conversion on the signal provided by the at least one sensor (51).

[0143] For the purpose of familiarizing the reader with the novel aspects of the ideas described herein, embodiments of the DAC disclosed herein are discussed. Although preferred embodiments have been shown and illustrated, those skilled in the art may make numerous changes, alterations, equivalents, and substitutions to the disclosed concepts without necessarily departing from the scope of the claims.

[0144] It should be understood that this disclosure is not limited to the disclosed embodiments and the content specifically shown and described above. Rather, features that can be advantageously combined in separate dependent claims or recited in the specification may be included. Furthermore, the scope of this disclosure includes variations and modifications that will be obvious to those skilled in the art and fall within the scope of the appended claims.

[0145] The term "comprising" as used in the claims or description does not exclude other elements or steps of the corresponding feature or procedure. When the terms "a" or "an" are used in conjunction with features, they do not exclude a plurality of such features. Furthermore, any reference numerals in the claims should not be construed as limiting the scope.

[0146] This patent application claims priority to European Patent Application No. 19219980.0, the disclosure of which is incorporated herein by reference.

[0147] Figure Labels

[0148] 1 Incremental Analog-to-Digital Converter (iADC)

[0149] 2iADC input

[0150] 3iADC feedback path

[0151] 4 Digital-to-Analog Converter (DAC)

[0152] 5iADC combiner

[0153] 6-loop filter

[0154] 7N-level quantizer

[0155] 8 mismatched integer logic blocks

[0156] 9 output components

[0157] 10DAC signal combiner

[0158] 11 Decimation Filter

[0159] 12 swap blocks

[0160] The first input of the 13-swap block

[0161] 14. Second input of the swap block

[0162] The third input of the 15-swapping block

[0163] Detector of 16 swap blocks

[0164] 17-swapping block divider

[0165] Adder for 18 swap blocks

[0166] The first AND gate of the 19 adders

[0167] The second AND gate of the 20 adder

[0168] The first addition operator of the 21 adders

[0169] The second addition operator of the 22 adder

[0170] 23 Selector for swapped blocks

[0171] The first output of the 24-swap block

[0172] The second output of the 25-swapping block

[0173] 26 First logical operator for swapping blocks

[0174] 27. Second logical operator for swapping blocks

[0175] Weight accumulator for 28 swapped blocks

[0176] 29. Addition operator for weighted accumulators

[0177] Storage of 30-weight accumulator

[0178] 31 Weight Generator

[0179] 32 Generator Input

[0180] 33. Numerical starting factor of the weight generator

[0181] 34 Generator Output

[0182] Integral stage of 35 weight generator

[0183] 36-level integral input

[0184] 37-point level output

[0185] 38-integral-level combiner

[0186] 39 Integral-level registers

[0187] 40 register factor

[0188] 41 Other registers

[0189] 42 jitter

[0190] 43OR Gate

[0191] 44 Subtractors

[0192] The first AND gate of the 45 subtractor

[0193] The second AND gate of the 46 subtractor

[0194] 47. First Difference Operator of Subtractors

[0195] The second difference operator of the 48 subtractors

[0196] 49. Third logical operator for swapping blocks

[0197] 50 electronic devices

[0198] 51 sensors

[0199] A simulated input signal

[0200] y[n] is the analog feedback signal.

[0201] u unit signal

[0202] Signal of combination C

[0203] F is the filtered signal

[0204] x[n] multi-bit word

[0205] s[n] selects the vector

[0206] y i [n] Simulation Part

[0207] L j Layer of swapped blocks

[0208] x k [n] Parts / subparts of a multi-bit word

[0209] W[n] weight factor

[0210] W'[n] is the adjusted weighting factor.

[0211] CLK clock signal

[0212] Remainder of ε division

[0213] δ selection signal

[0214] R n-1 Cumulative adjusted weighting factors

Claims

1. A digital-to-analog converter (DAC) (4) for use in an incremental analog-to-digital converter (iADC) (1), the DAC (4) being configured to convert a multi-bit word (x[n]) into an analog feedback signal (y[n]), the multi-bit word (x[n]) representing an integer in an integer range, the DAC (4) comprising: - Mismatched integer logic block (8), configured to generate a selection vector (s[n]) with a predetermined number of bits based on the multi-bit word (x[n]). - Multiple output elements (9) configured to generate corresponding analog parts (y) based on the selection vector (s[n]). i [n]), and - Signal combiner (10), which is used to combine the analog part (y i [n]) are combined to form the analog feedback signal (y[n]). In the mismatched integer logic block (8): - A predetermined number of exchange blocks (12) are cascaded to form a layer (L) of exchange blocks (12). - Each switching block (12) is configured to receive at least a portion of the multi-bit word (x[n]), divide the portion into two sub-parts, and forward each sub-part, wherein the switching block (12) of the preceding layer is configured to forward the sub-part to another switching block (12) of the following layer, and the switching block (12) of the last layer is configured to forward the sub-part to one of the output elements (9). - In each exchange block (12), the weight factor (W[n]) is adjusted by multiplying the difference between the two sub-parts by the weight factor (W[n]), wherein in each clock cycle of the iADC (1) conversion cycle, a new weight factor (W[n]) is provided by the weight generator (31), wherein successive weight factors decrease according to a monotonically decreasing function, and - Each switching block (12) includes a weight accumulator (28) configured to accumulate successive adjusted weight factors (W'[n]), wherein the sign of the weight accumulator (28) is used to determine how to segment the portion of the additional multi-bit word (x[n]) that comes into the corresponding switching block (12) in the subsequent clock cycle of the iADC (1) during the conversion period.

2. The DAC (4) according to claim 1, wherein the DAC (4) further comprises a weight generator (31), wherein, The weight generator (31) is reinitialized at predetermined time intervals.

3. The DAC (4) according to any one of claims 1 to 2, wherein, Each swap block also includes: - A divider (17) configured to divide the portion of the multi-bit word (x[n]) into two preliminary sub-parts with equal values. - Selector (23), configured to select one of the preliminary sub-parts, the selection being based on the sign of the weight accumulator (28), and - Adder (18), which is configured to add the remainder (ε) of the division performed by the divider (17) to the initial sub-part selected by the selector (23).

4. The DAC (4) according to any one of claims 1 to 2, wherein, Each swap block (12) also includes: - First input (13) for receiving the portion of the multi-bit word (x[n]). - A second input (14) for providing the weighting factor (W[n]). - A third input (15) is used to provide a clock signal, which is provided to the weight accumulator (28) to accumulate the adjusted weight factor (W'[n]). - Detector (16), configured to detect whether the integer represented by the portion of the multi-bit word (x[n]) is even or odd. - A divider (17) configured to divide the portion of the multi-bit word (x[n]) into two preliminary sub-parts, the absolute value of which is smaller than the portion of the multi-bit word (x[n]). - Selector (23), configured to select one of the preliminary sub-parts, the selection being based on the sign of the weight accumulator (28), and - Adder (18), configured to add the remainder (ε) of the division performed by the divider (17) to the initial sub-part selected by the selector (23), - Used to forward the first output (24) of the first sub-part. - Used to forward the second output (25) of the second sub-part.

5. The DAC (4) according to claim 4, wherein, In each swap block (12): - The divider (17) is configured to divide the portion of the multi-bit word (x[n]) into two preliminary sub-parts with equal values, and - The adder (18) is configured to add the remainder (ε) of the division performed by the divider (17) to the initial sub-part selected by the selector (23).

6. The DAC (4) according to claim 3, wherein, In the first exchange block that receives the multi-bit word (x[n]): - An additional detector (41) is configured to detect sequences of multi-bit words (x[n]) representing even integers greater than the smallest integer in the integer range but less than the largest integer in the integer range, and - For each r-th multi-word (x[n]) of the detected sequence, where r is a natural number, the adder (18) is configured to add a unit (u) to one of the two preliminary sub-parts, and the subtractor (44) is configured to subtract the unit (u) from the other preliminary sub-part, wherein the selector (23) determines the corresponding preliminary sub-part based on the sign of the weight accumulator (28).

7. The DAC (4) according to claim 3, wherein, In the first exchange block that receives the multi-bit word (x[n]): - An additional detector (41) is configured to detect a multi-bit word (x[n]) representing an even integer greater than the smallest integer in the range but less than the largest integer in the range. - The jitter (42) randomly determines to divide the multi-bit word (x[n]) detected by the additional detector (41) into two parts that have equal or unequal values ​​respectively, and - In the case that the jitter (42) determines that the segments are not equal, the adder (18) is configured to add the unit (u) to one of the two preliminary sub-segments, and the subtractor (44) is configured to subtract the unit (u) from the other preliminary sub-segment, wherein the selector (23) determines the corresponding preliminary sub-segment based on the sign of the weight accumulator (28).

8. The DAC (4) according to any one of claims 1 to 2, wherein the DAC (4) further comprises being configured to provide a successive weighting factor (W[n]) for each clock cycle in the conversion period of the iADC (1), wherein, The weight generator (31) generates a monotonically decreasing weight factor (W[n]).

9. The DAC (4) according to claim 8, wherein, The weight generator (31) includes: - Receive generator input (32) of the numeric starting factor (33). - Provide the generator output (34) for the weight factor (W[n]). - At least one integration stage (35) that couples the generator input (32) to the generator output (34), the integration stage (35) further comprising: - Stage input (36) for receiving digital input signals from the generator input (32) or from the previous integration stage (35), respectively. - Stage output (37) for providing digital output signals to the subsequent integration stage (35) or the generator output (34), respectively. - A stage combiner (38) configured to combine the digital input signal and feedback from the digital output signal, and - A register (39) configured to process a combination of the digital input signal and feedback from the digital output signal, the register (39) providing the digital output signal.

10. The DAC (4) according to claim 8, wherein, The weight generator forwards the corresponding weight factor (W[n]) for a given clock cycle of the conversion period to each of the exchange blocks (12).

11. An incremental analog-to-digital converter (iADC) (1) comprising a DAC (4) according to any one of claims 1 to 10, wherein the iADC (1) further comprises: - Input (2) used to provide analog input signal (A) - A combiner (5) configured to combine the analog input signal (A) and the analog feedback signal (y[n]) from the DAC (4). - A loop filter (6) configured to filter the combination of the analog input signal (A) and the analog feedback signal (y[n]). - An N-level quantizer (7) for generating the multi-bit word (x[n]) based on the output of the loop filter (6). - Including the feedback path (3) of the DAC (4), the DAC (4) being configured to convert a multi-bit word (x[n]) from the N-stage quantizer (7) into an analog feedback signal (y[n]) for the combiner of the iADC (1), and - Set as a decimation filter (11) to filter the multi-bit word (x[n]) to generate the digital system output signal.

12. An electronic device comprising the iADC (1) according to claim 11, the electronic device further connected to at least one sensor, wherein, The iADC (1) is configured to perform analog-to-digital conversion on the signal provided by the at least one sensor.

13. A digital-to-analog conversion method for converting a multi-bit word (x[n]) representing an integer within a range of integers into an analog feedback signal (y[n]) of an incremental analog-to-digital converter (iADC) (1), the digital-to-analog conversion method comprising: - Generate a selection vector (s[n]) with a predetermined number of bits based on the multi-bit word (x[n]). - Based on the selection vector (s[n]), the corresponding simulation part (y) is generated through multiple output elements (9). i [n]), - The simulation part (y) i [n]) are combined to form the analog feedback signal (y[n]). The generation of the selection vector (s[n]) includes: - Divide the multi-bit word (x[n]) into corresponding parts and sub-parts in succession. - The weighting factor (W[n]) is adjusted by multiplying the difference between the two corresponding sub-parts by a weighting factor (W[n]), wherein a new weighting factor (W[n]) is provided in each clock cycle of the iADC (1) conversion cycle, wherein the successive weighting factors (W[n]) decrease according to a monotonically decreasing function, and - Accumulate successive adjusted weighting factors (W'[n]), wherein, based on the accumulated sign of the adjusted weighting factors (W[n]), determine how to divide the additional multi-bit word (x[n]) in a subsequent clock cycle during the conversion period of the iADC (1).

14. The method of claim 13, further comprising: By using a weight generator (31), a successive weight factor (W[n]) is generated for each clock cycle in the conversion period of the iADC (1). The generation of the weight factor (W[n]) further includes: - In the generator input (32), receive the numeric starting factor. - Provide at least one integration stage (35) that couples the generator input (32) to the generator output (34). - At the stage input (36) of the integration stage (35), a digital input signal is received from the generator input (32) or from the previous integration stage (35). - Combine the digital input signal and the feedback from the digital output signal, - At the stage output (37) of the integrator stage (35), the digital output signal is provided for the subsequent integrator stage (35) or the generator output (34) by processing a combination of the digital input signal and feedback from the digital output signal, and - The weighting factor (W[n]) is provided at the generator output (34).

15. The method according to any one of claims 13 to 14, further comprising: - Detect whether the integer represented by the portion of the multi-bit word (x[n]) arriving at the corresponding exchange block (12) is even or odd. - Divide the portion of the multi-bit word (x[n]) into two preliminary sub-parts with equal values. - Based on the accumulated sign of the adjusted weighting factors (W'[n]), a preliminary sub-part is selected, and - Add the remainder (ε) of the segmentation to the selected initial sub-part.

16. The method of claim 15, further comprising, in the first exchange block receiving the multiple bits (x[n]): - Detect sequences of multi-bit words (x[n]) representing even integers greater than the smallest integer in the range but less than the largest integer in the range, and - For each r-th multi-word (x[n]) of the detected sequence, where r is a natural number, add a unit (u) to one of the two preliminary sub-parts and subtract the unit (u) from the other preliminary sub-part, wherein the corresponding preliminary sub-part is selected based on the sign of the accumulated weighting factor (W'[n]).

17. The method of claim 15, further comprising, in the first exchange block receiving the multiple bits (x[n]): - Detect a multi-bit word (x[n]) representing an even integer greater than the smallest integer in the range but less than the largest integer in the range. - Randomly determine the multi-bit word (x[n]) representing an even integer to be detected, and split it into two parts that have equal or unequal values, and - In the case of unequal division, add a unit (u) to one of the two preliminary sub-parts and subtract the unit (u) from the other preliminary sub-part, wherein the corresponding preliminary sub-part is selected based on the sign of the accumulated weighting factor (W'[n]).

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