Test circuit, test method and device employing the same

Abstract

The application provides a test circuit, a test method and a test device. The test circuit comprises: a first detection oscillator comprising 2N+1 first inverting units connected in sequence, each first inverting unit being composed of a transistor, and the first detection oscillator being configured to generate and output a first oscillation frequency; and a second detection oscillator comprising 2N+1 second inverting units connected in sequence, each second inverting unit being composed of a transistor, wherein N is a positive integer greater than or equal to 1, the second detection oscillator is configured to generate and output a second oscillation frequency, and the parasitic capacitance of the second inverting unit is different from that of the first inverting unit; and a change relationship between the parasitic capacitance and the inverter delay is determined according to the detected first oscillation frequency and the detected second oscillation frequency. The scheme solves the problem that the scheme for analyzing the influence of structural changes in the oscillator on the device delay in the prior art is relatively single.

Description

Technical Field

[0001] This application relates to the field of semiconductor testing, and more specifically, to a test circuit, a test method using the test circuit, a test apparatus, a test system, and a memory. Background Technology

[0002] In the prior art, oscillators are usually used to analyze the effect of lightly doped drains on device delay. For example, multi-fan-out ring oscillators can be used to analyze the effect of structural changes on device delay. However, the inventors have found that the prior art uses a fan-out ring oscillator to analyze the effect of structure on device delay, which is relatively simple.

[0003] The information disclosed above in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0004] The main objective of this application is to provide a test circuit, a test method using the test circuit, a test device, a test system, and a memory to address the problem that existing technologies offer limited solutions for analyzing the impact of device structure on device delay.

[0005] To achieve the above objectives, according to one aspect of this application, a test circuit is provided, comprising: a first detection oscillator including 2N+1 cascaded first inverting units, each first inverting unit being composed of a transistor, the first detection oscillator being used to generate and output a first oscillation frequency; a second detection oscillator including 2N+1 cascaded second inverting units, each second inverting unit being composed of a transistor, wherein N is a positive integer greater than or equal to 1, the second detection oscillator being used to generate and output a second oscillation frequency, the parasitic capacitance of the second inverting units being different from that of the first inverting units; and determining the relationship between the parasitic capacitance and the inverter delay based on the detected first oscillation frequency and the detected second oscillation frequency.

[0006] Furthermore, in the 2N+1 cascaded first inverting units, the first-stage first inverting unit includes a first controllable NOT gate, and the remaining first inverting units include a first NOT gate; wherein, the first NOT gate is a first CMOS inverter, and the first CMOS inverter includes a first NMOS transistor and a first PMOS transistor; in the 2N+1 cascaded second inverting units, the second inverter in the first-stage second inverting unit is a second controllable NOT gate, and the remaining second inverting units are second NOT gates; wherein, the second NOT gate is a second CMOS inverter, and the second CMOS inverter includes a second NMOS transistor and a second PMOS transistor; the parasitic capacitance of the second inverting unit is different from that of the first inverting unit, including: the parasitic capacitance of the second CMOS inverter is different from that of the first CMOS inverter.

[0007] Furthermore, the parasitic capacitance of the second CMOS inverter differs from that of the first CMOS inverter in that at least one of the first, second, and third capacitors of the second CMOS inverter is different from that of the first CMOS inverter, wherein the first capacitor is the direct coupling capacitance between the source region and / or drain region and the gate, the second capacitor is the junction capacitance between the drain region and the substrate, and the third capacitor is the coupling capacitance between the source contact structure and / or drain contact structure and the gate.

[0008] Furthermore, the first difference between the second CMOS inverter and the first CMOS inverter is at least such that the first capacitor and the second capacitor of the second CMOS inverter are different from those of the first CMOS inverter. The first difference includes: the active region of the first MOS transistor is a single active region; the active region of the second MOS transistor includes at least two spaced sub-active regions distributed along a first direction; the sum of the lengths of all the sub-active regions of the second MOS transistor in the first direction is the same as the length of the active region of the first MOS transistor in the first direction; other structural parameters of each sub-active region of the first MOS transistor are the same as those of the active region of the second MOS transistor; the drain contact structure is not provided on some of the sub-active regions of the second MOS transistor; the first direction is the width direction of the channel of the first MOS transistor; wherein the first MOS transistor is the first NMOS transistor and the second MOS transistor is the second NMOS transistor; and / or, the first MOS transistor is the first PMOS transistor and the second MOS transistor is the second PMOS transistor.

[0009] Furthermore, apart from the active region, the first MOS transistor and the second MOS transistor have the same structure and dimensions.

[0010] Furthermore, a second difference between the first CMOS inverter and the second CMOS inverter causes the third capacitor of the first CMOS inverter and the second CMOS inverter to be different. The second difference includes at least one of the following: the side area of ​​the drain contact structure of the first MOS transistor is not equal to the side area of ​​the drain contact structure of the second MOS transistor; the side area of ​​the source contact structure of the first MOS transistor is not equal to the side area of ​​the source contact structure of each of the second MOS transistors, wherein the first MOS transistor is the first NMOS transistor and the second MOS transistor is the second NMOS transistor; and / or, the first MOS transistor is the first PMOS transistor and the second MOS transistor is the second PMOS transistor, wherein the side area is calculated by defining the length of the contact structure in a first direction and the length in a second direction, the first direction being the width direction of the channel of the first MOS transistor and the second direction being the height direction of the first MOS transistor.

[0011] Furthermore, the lateral area of ​​the drain contact structure of each first MOSFET is not equal to the lateral area of ​​the drain contact structure of each second MOSFET, including one of the following: the length of the drain contact structure of each first MOSFET in the first direction is not equal to the length of the drain contact structure of each second MOSFET in the first direction, and the length of the drain contact structure of each first MOSFET in the second direction is equal to the length of the drain contact structure of each second MOSFET in the second direction; or the length of the drain contact structure of each first MOSFET in the first direction is equal to the length of the drain contact structure of each second MOSFET in the first direction, and the length of the drain contact structure of each first MOSFET in the second direction is not equal to the length of the drain contact structure of each second MOSFET in the second direction. The side area of ​​the source contact structure of each first MOSFET is not equal to the side area of ​​the source contact structure of each second MOSFET, including one of the following: the length of the source contact structure of each first MOSFET in the first direction is not equal to the length of the source contact structure of each second MOSFET in the first direction, and the length of the source contact structure of each first MOSFET in the second direction is equal to the length of the source contact structure of each second MOSFET in the second direction; or the length of the source contact structure of each first MOSFET in the first direction is equal to the length of the source contact structure of each second MOSFET in the first direction, and the length of the source contact structure of each first MOSFET in the second direction is not equal to the length of the source contact structure of each second MOSFET in the second direction.

[0012] Furthermore, a third difference between the first CMOS inverter and the second CMOS inverter makes the second capacitors of the first CMOS inverter and the second CMOS inverter different. The third difference includes: the predetermined length of the active region of the first MOS transistor in the third direction is not equal to the predetermined length of the second MOS transistor in the third direction, the predetermined length being the length of the active region from the target center point to one edge of the drain contact structure, the target center point being the midpoint between the source contact structure and the drain contact structure, wherein the first MOS transistor is the first NMOS transistor and the second MOS transistor is the second NMOS transistor; and / or, the first MOS transistor is the first PMOS transistor and the second MOS transistor is the second PMOS transistor, the third direction being perpendicular to the first direction and the second direction, the first direction being the width direction of the channel of the first MOS transistor and the second direction being the height direction of the first MOS transistor.

[0013] Furthermore, the first controllable NOT gate is a first NAND gate. The first input terminal of the first NAND gate receives an enable signal to control the first detection oscillator to generate an oscillation signal. The second input terminal and output terminal of the first NAND gate are cascaded with the other 2N first NOT gates to form a ring oscillation circuit. The first power supply terminals of the first NAND gate and the 2N first NOT gates are respectively connected to a first power supply voltage. The second power supply terminals of the first NAND gate and the 2N first NOT gates are respectively connected to a second power supply voltage. The source of the first PMOS transistor of the first CMOS inverter is the first power supply terminal, and the source of the first NMOS transistor of the first CMOS inverter is the second power supply terminal.

[0014] Furthermore, in the 2N+1 first inverting units, in addition to the first-stage first inverting unit, each stage of the first inverting unit also includes multiple first fan-out CMOS inverters. The first fan-out CMOS inverter is connected to the corresponding first CMOS inverter input terminal, the first power supply terminal of the multiple first fan-out CMOS inverters is connected to a third power supply voltage, and the second power supply terminal of the multiple first fan-out CMOS inverters is connected to a second power supply voltage.

[0015] Furthermore, the test circuit also includes at least one third detection oscillator, which is composed of 2N+1 cascaded third inverting units. The 2N+1 third inverting units of the third detection oscillator correspond one-to-one with the 2N+1 first inverting units in the first detection oscillator, and the parasitic capacitance of the third inverting unit is different from that of the first and second inverting units.

[0016] To achieve the above objectives, according to one aspect of this application, a test method using the aforementioned test circuit is provided. The test method includes: acquiring the output frequency of a first detection oscillator to obtain a first output frequency; acquiring the output frequency of a second detection oscillator to obtain a second output frequency; calculating a first delay and a second delay based at least on the number of inverters (2N+1) in the detection oscillators, the first output frequency, and the second output frequency; and determining the change in the second delay relative to the first delay caused by different parasitic capacitances, wherein the first delay is the delay of a first CMOS inverter, and the second delay is the delay of a second CMOS inverter.

[0017] Further, determining the change in the second delay relative to the first delay caused by the difference in parasitic capacitance includes: obtaining the difference between the second capacitance of the first CMOS inverter and the parasitic capacitance of the second CMOS inverter, wherein the parasitic capacitance includes at least one of the following: a first capacitance, a second capacitance, and a third capacitance, wherein the first capacitance is the direct coupling capacitance between the source region and / or the drain region and the gate, the second capacitance is the junction capacitance between the drain region and the substrate, and the third capacitance is the coupling capacitance between the source contact structure and / or the drain contact structure and the gate; and determining the effect of the change in the second capacitance on the delay of the CMOS inverter in the detection oscillator based on the difference in parasitic capacitance, the value N, the first output frequency, and the second output frequency.

[0018] Further, obtaining the difference between the second capacitance of the first CMOS inverter and the parasitic capacitance of the second CMOS inverter includes: calculating the equivalent capacitance of the first CMOS inverter based on the first output frequency and the effective drive current of the first detection oscillator to obtain a first equivalent capacitance; calculating the equivalent capacitance of the second CMOS inverter based on the second output frequency and the effective drive current of the second detection oscillator to obtain a second equivalent capacitance; and calculating the difference between the first equivalent capacitance and the second equivalent capacitance to obtain the difference in parasitic capacitance.

[0019] According to another aspect of this application, a test apparatus employing the aforementioned test circuit is provided. The test apparatus includes: a first acquisition unit for acquiring the output frequency of a first detection oscillator to obtain a first output frequency; a second acquisition unit for acquiring the output frequency of a second detection oscillator to obtain a second output frequency; and a determination unit for calculating a first delay and a second delay based at least on the number of inverters in the detection oscillator (2N+1), the first output frequency, and the second output frequency, and determining the change in the second delay relative to the first delay caused by different parasitic capacitances, wherein the first delay is the delay of the first CMOS inverter, and the second delay is the delay of the second CMOS inverter.

[0020] According to another aspect of this application, a testing system is provided, including a testing device and the aforementioned testing circuit, wherein the output terminals of the testing device and the testing circuit are communicatively connected, and the testing device is used to perform the aforementioned testing method.

[0021] According to another aspect of this application, a memory is provided, including a test circuit, said test circuit being the test circuit described above.

[0022] By applying the technical solution of this application, the number of inverting units in the first detection oscillator and the second detection oscillator are the same, and the connection method of the inverting units is also the same. The only difference is that the structures that cause the parasitic capacitance between the first detection oscillator and the second detection oscillator are different. Specifically, the structures affecting the parasitic capacitance in the CMOS inverter in the first detection oscillator and / or the CMOS inverter in the second detection oscillator are different. In this way, the effect of the structural change of the CMOS inverter on the inverter delay can be determined based on the difference between the first oscillation frequency output by the first detection oscillator and the second oscillation frequency output by the second detection oscillator. This increases the number of solutions for analyzing the effect of structural changes in the oscillator on the device delay and solves the problem that the solutions for analyzing the effect of structural changes in the oscillator on the device delay in the prior art are relatively simple. Attached Figure Description

[0023] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0024] Figure 1 A schematic diagram of an embodiment of a test circuit according to this application is shown;

[0025] Figure 2 A schematic diagram of the structure of another embodiment of a test circuit according to this application is shown;

[0026] Figure 3 A schematic diagram of the structure of another embodiment of the test circuit according to this application is shown;

[0027] Figure 4 A schematic diagram of the structure of another embodiment of a test circuit according to this application is shown;

[0028] Figure 5 A schematic diagram of the parasitic capacitance in a MOSFET is shown.

[0029] Figures 6 and 7 respectively show two CMOS inverters with a first difference;

[0030] Figures 8 to 10 show two CMOS inverters with a second difference;

[0031] Figures 11 and 12 show two CMOS inverters with a third difference;

[0032] Figure 13 A flowchart illustrating one embodiment of the testing method according to this application is shown;

[0033] Figure 14 A structural block diagram of one embodiment of the test week according to this application is shown.

[0034] The above figures include the following reference numerals:

[0035] 100. First detection oscillator; 200. Second detection oscillator; 300. Third detection oscillator; 1. Inverter; 2. First stage first inverting unit; 3. Remaining first inverting units; 4. First stage second inverting unit; 5. Remaining second inverting units; 10. First CMOS inverter; 20. First NAND gate; 30. First power supply voltage terminal; 40. Second power supply voltage terminal; 50. Second CMOS inverter; 60. Third power supply voltage terminal; 70. First fan-out CMOS inverter; 80. Third CMOS inverter; 11. First NMOS transistor; 12. First PMOS transistor; 13. Input terminal; 14. Output terminal; 111. Active region; 112. Source region; 113. Drain region; 114. Source contact structure; 115. Drain contact structure; 116. Gate; 117. Metal interconnect structure; 1110. Sub-active region; 51. Second NMOS transistor; 52. Second PMOS transistor. Detailed Implementation

[0036] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0037] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0038] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0039] As described in the background section, existing methods for analyzing the impact of device structure on device delay are relatively simple. To address the aforementioned technical problems, this application proposes a test circuit, a test method using the test circuit, an apparatus, a system, and a memory.

[0040] In one typical embodiment of this application, a test circuit is provided. Figures 1 to 4 As shown, the circuit includes at least two detection oscillators, namely a first detection oscillator 100 and a second detection oscillator 200. The first detection oscillator 100 includes 2N+1 cascaded first inverting units (specifically including a first-stage first inverting unit 2 and the remaining first inverting units 3), each first inverting unit being composed of a transistor. The first detection oscillator 100 is used to generate and output a first oscillation frequency. The second detection oscillator 200 includes 2N+1 cascaded second inverting units (specifically including a first-stage second inverting unit 4 and the remaining second inverting units 5), each second inverting unit being composed of a transistor, where N is a positive integer greater than or equal to 1. The second detection oscillator 200 is used to generate and output a second oscillation frequency. The parasitic capacitance of the second inverting units is different from that of the first inverting units. Based on the detected first oscillation frequency and the detected second oscillation frequency, the relationship between the parasitic capacitance and the inverter delay is determined. Thus, based on the first oscillation frequency output by the test circuit and the detected second oscillation frequency, the relationship between the parasitic capacitance and the CMOS inverter delay can be determined.

[0041] In the above scheme, the number of inverters in the first detection oscillator 100 and the second detection oscillator 200 are the same, and the connection method of the inverter units is also the same. The difference lies in the parasitic capacitance of the second inverter unit and the first inverter unit. In this way, the difference between the first oscillation frequency output by the first detection oscillator 100 and the second oscillation frequency output by the second detection oscillator 200 can be used to determine the effect of the structural change of the inverter unit (i.e. the difference between the first inverter unit and the second inverter unit) on the inverter delay. This increases the scheme for analyzing the effect of structural changes in the oscillator on the device delay and solves the problem that the existing schemes for analyzing the effect of structural changes in the oscillator on the device delay are relatively simple.

[0042] In the aforementioned 2N+1 cascaded inverting units (specifically, the first inverting unit or the second inverting unit), since each inverting unit includes at least one inverter, both the first detection oscillator 100 and the second detection oscillator 200 include 2N+1 cascaded inverters. That is, each detection oscillator includes at least 2N+1 cascaded inverters. These 2N+1 cascaded inverters can all be CMOS inverters, or some can be CMOS inverters and some can not be CMOS inverters. The specific settings can be adjusted according to the actual situation.

[0043] In one specific embodiment of this application, such as Figures 1 to 4 As shown, in the 2N+1 cascaded first inverting units, the first-stage first inverting unit includes a first controllable NOT gate, and the remaining first inverting units 3 include first NOT gates; wherein, the first NOT gate is a first CMOS inverter 10, and the first CMOS inverter includes a first NMOS transistor 11 and a first PMOS transistor 12; in the 2N+1 cascaded second inverting units, the second inverter in the first-stage second inverting unit 4 is a second controllable NOT gate, and the remaining second inverting units 5 are second NOT gates; wherein, the second NOT gate is a second CMOS inverter 50, and the second CMOS inverter includes a second NMOS transistor 51 and a second PMOS transistor 52; the parasitic capacitance of the second inverting unit differs from that of the first inverting unit, including that the parasitic capacitance of the second CMOS inverter is different from that of the first CMOS inverter. In this scheme, the relationship between the parasitic capacitance and the delay of the CMOS inverter can be determined based on the first oscillation frequency output by the test circuit and the detected second oscillation frequency.

[0044] In another specific embodiment of this application, such as Figures 1 to 4 As shown, the first controllable NOT gate is a first NAND gate 20. The first input terminal of the first NAND gate 20 receives an enable signal to control the first detection oscillator 100 to generate an oscillation signal. The second input and output terminals of the first NAND gate 20 are cascaded with the other 2N first NOT gates to form a ring oscillation circuit. The first power supply terminals of the first NAND gate 20 and the 2N first NOT gates (first CMOS inverters 10) are respectively connected to the first power supply voltage terminal 30. The second power supply terminals of the first NAND gate and the 2N first NOT gates are respectively connected to the second power supply voltage terminal 40. The source contact structure of the first PMOS transistor 12 of the first CMOS inverter 10 is the first power supply terminal, and the source contact structure of the first NMOS transistor 11 of the first CMOS inverter 10 is the second power supply terminal. By setting the first inverter of the 2N+1 cascaded first inverters as the first NAND gate 20, the operation of the entire test circuit can be controlled more flexibly and conveniently through the enable terminal of the first NAND gate 20.

[0045] In another embodiment of this application, such as Figure 2As shown, among the 2N+1 first inverting units, in addition to the first-stage first inverting unit 2, each stage of the first inverting unit also includes multiple first fan-out CMOS inverters 70. The first fan-out CMOS inverters 70 are connected to the input terminals of the corresponding first CMOS inverters 10. The first power supply terminals of the multiple first fan-out CMOS inverters 70 are connected to the third power supply voltage terminal 60, and the second power supply terminals of the multiple first fan-out CMOS inverters 70 are connected to the second power supply voltage terminal 40. The power supply terminals of each inverter 1 whose output terminal (floating) is not connected to the output terminal of the detection oscillator are connected to the first power supply voltage terminal 30 and the third power supply voltage terminal 60, respectively. This ensures that the effective drive current measured from the first power supply voltage terminal does not include the current of the inverters without output (i.e., the first fan-out CMOS inverter), avoiding the problem of an overestimation of the detected effective drive current. This ensures that the effective drive current measured from the first power supply voltage terminal is more accurate, and that the equivalent capacitance of the CMOS calculated based on this effective drive current and the output frequency of the detection oscillator is more accurate. This allows for a more accurate analysis of the impact of CMOS capacitance changes on the delay of the detection oscillator. In this embodiment, two... Figure 2 The detector oscillator shown.

[0046] In addition, in the above embodiments, at least the first detection oscillator 100 is a multi-fan-out detection oscillator. Of course, the other detection oscillator in the test circuit, namely the second detection oscillator 200, can be multi-fan-out or not. Those skilled in the art can select the second detection oscillator 200 as a multi-fan-out or not multi-fan-out detection oscillator according to the actual situation.

[0047] It should also be noted that the detection oscillators in the test circuit of this application are not limited to two, but can also be three or more. Those skilled in the art can appropriately increase the number of detection oscillators according to the actual content to be tested, which will not be elaborated here.

[0048] In one embodiment of this application, such as Figure 4As shown, the above test circuit also includes at least one third detection oscillator 300. The third detection oscillator 300 is composed of 2N+1 cascaded third inverting units. The 2N+1 third inverting units of the third detection oscillator 300 correspond one-to-one with the 2N+1 first inverting units in the first detection oscillator 100, and the parasitic capacitances of the third inverting units are different from those of the first and second inverting units. In this embodiment, the structures of the first detection oscillator 100 and the third detection oscillator 300 are basically the same (the difference being the different parasitic capacitances of their inverting units). If the first detection oscillator 100 is a multi-fan-out detection oscillator, then the third detection oscillator 300 is also a multi-fan-out detection oscillator. Thus, the only difference between the first detection oscillator 100 and the third detection oscillator 300 is the different parasitic capacitances of their inverting units, thereby allowing for a more accurate analysis of the impact of changes in parasitic capacitance on the delay of the inverter.

[0049] In a more specific embodiment, such as Figure 4 As shown, the difference between the first detection oscillator 100 and the third detection oscillator 300 lies only in the parasitic capacitance of the first and second CMOS inverters. The difference between the second detection oscillator 200 and the first detection oscillator 100 lies only in the fact that the second detection oscillator 200 is not multi-fan-out. Since the only difference between the first detection oscillator 100 and the third detection oscillator 300 is the equivalent input capacitance of the CMOS inverter (where the equivalent input capacitance of the CMOS inverter in the first detection oscillator 100 is 3Cin and the equivalent input capacitance of the third detection oscillator 300 is Cin), the equivalent capacitance of each detection oscillator can be calculated based on the output power and effective drive current of the first detection oscillator 100 and the third detection oscillator 300. The equivalent capacitance is the sum of the equivalent input capacitance and other capacitances. Based on these relationships, Cin and other capacitances can be calculated, where the other capacitances are the sum of the equivalent output capacitance Cout and the subsequent parasitic capacitance Cp. Therefore, the influence of Cin and other capacitances on the delay of the detection oscillator can be directly analyzed. Where Cs = Cin + Cout + Cp, and Cs is the equivalent capacitance of the CMOS in the detection oscillator.

[0050] It should be noted that the number of detection oscillators in the test circuit of this application is not limited to two or three, but can also be more than three. The structure of each detection oscillator can be determined according to the actual situation, and can be multi-fan-out or single-fan-out, and is not limited to these. Figures 1 to 4 The structure, for example, for a test circuit that only includes two detection oscillators, can also include a multi-fan-out detection oscillator and a single-fan-out detection oscillator.

[0051] Specifically, the difference in parasitic capacitance between the second CMOS inverter and the first CMOS inverter can include: the second CMOS inverter differing from at least one of the first capacitor, the second capacitor, and the third capacitor of the first CMOS inverter. That is, it can differ only in the first capacitor, only in the second capacitor, only in the third capacitor, or only in the first and second capacitors, or only in the first and third capacitors, or only in the second and third capacitors. Of course, it can also differ in all three capacitors. This can be achieved by using multiple detection oscillators, which can be grouped in pairs, with each pair of oscillators having only one variable. For example, Figure 5 As shown, the first capacitor Cdo is the direct coupling capacitance between the source region 112 and / or the drain region and the gate 116. That is, the first capacitor can be the direct coupling capacitance Cdos between the source region 112 and the gate 116, or it can be the direct coupling capacitance Cdod between the drain region and the gate 116, or it can be the sum of the direct coupling capacitances Cdos and Cdod between the source region 112 and the gate 116 and the drain region 113 and the gate 116. The second capacitor Cj is the junction capacitance between the drain region 113 and the substrate. The third capacitor is the coupling capacitance between the source contact structure 114 and / or the drain contact structure 115 and the gate 116. That is, the third capacitor Cco can be the coupling capacitance Ccos between the source contact structure 114 and the gate 116, or it can be the coupling capacitance Ccod between the drain contact structure 115 and the gate 116, or it can be the sum of the coupling capacitances Ccos and Ccod between the source contact structure 114 and the gate 116. Figure 5 The first direction, the second direction, and the third direction are also shown in the text. The first to third directions mentioned later in this application can be found in [reference needed]. Figure 5 The description.

[0052] Specifically, Cin = Cgg + Cdos + Ccos, Cout = Cdod + Ccod + Cj, where Cgg is the gate oxide capacitance, Cdos is the direct coupling capacitance between the source region 112 and the gate 116, Cdod is the direct coupling capacitance between the drain region and the gate 116, Ccos is the coupling capacitance between the source contact structure 114 and the gate 116, and Ccod is the coupling capacitance between the drain contact structure 115 and the gate 116. Cdo and Cj are related to the ion angle, dose, type, and implantation temperature of the lightly doped drain (LDD) and Halo doped ions. The effect of LDD on the delay of the detection oscillator can be analyzed by adjusting Cdo and Cj. For example, two detection oscillators can be built, the difference between the two detection oscillators being the different doses of LDD in the CMOS inverters. The different doses of LDD in the CMOS inverters result in different Cdo and Cj between the two CMOS inverters. By detecting the output frequencies of the two oscillating inverters, the difference in delay of the CMOS inverters in the two detection oscillators can be determined, thereby determining the effect of the different doses of LDD on the delay of the CMOS inverters.

[0053] In one specific embodiment of this application, the first difference between the second CMOS inverter and the first CMOS inverter 10 is at least such that the first capacitor and the second capacitor of the second CMOS inverter 50 are different from those of the first CMOS inverter 10. The first difference includes: as shown in Figures 6 and 7, the active region 111 of the first MOS transistor is a single active region 111, and the active region 111 of the second MOS transistor includes at least two spaced sub-active regions 1110 distributed along a first direction. The sum of the lengths of all sub-active regions 1110 of the second MOS transistor in the first direction is equal to... The active region 111 of the first MOS transistor has the same length in the first direction. The other structural parameters of each sub-active region 1110 of the first MOS transistor are the same as those of the active region 111 of the second MOS transistor. Some sub-active regions 1110 in the second MOS transistor do not have drain contact structures 115. The first direction is the width direction of the channel of the first MOS transistor. The first MOS transistor is a first NMOS transistor 11, and the second MOS transistor is a second NMOS transistor 51; and / or, the first MOS transistor is a first PMOS transistor 12, and the second MOS transistor is a second PMOS transistor 52. The scheme includes several scenarios: First, as shown in Figure 6, the active region 111 of the first NMOS transistor 11 is a single-piece structure, as shown in Figure 6(a), and the active region 111 of the second NMOS transistor 51 includes multiple sub-active regions 1110, as shown in Figure 6(b); Second, the active region 111 of the second NMOS transistor 51 is a single-piece structure, and the active region 111 of the first NMOS transistor 11 includes multiple sub-active regions 1110; Third, as shown in Figure 7, the active region 111 of the first PMOS transistor 12 is a single-piece structure, as shown in Figure 7(a), and the active region 111 of the second PMOS transistor 52 includes multiple sub-active regions 1110, as shown in Figure 7(b); Fourth, the active region 111 of the second PMOS transistor 52 is a single-piece structure, and the active region 111 of the first PMOS transistor 12 includes multiple sub-active regions 1110. Of course, this also includes combinations of the first and third cases, combinations of the first and fourth cases, combinations of the second and third cases, and combinations of the second and fourth cases. Specifically, this can be achieved using more detection oscillators. Multiple detection oscillators can be grouped in pairs, and each group of oscillators can have only one variable. In this scheme, by adjusting the active region 111 in the second MOS transistor into multiple sub-active regions 1110, the direct coupling capacitance between the drain and gate 116 of the second preset MOS transistor, as well as the junction capacitance between the drain and active region 111, differs from that of the first preset MOS transistor. This results in different parasitic capacitances between the first CMOS inverter 10 and the second CMOS inverter 50. Furthermore, based on the output frequencies of the two corresponding detection oscillators, the impact of changes in the first and second capacitances on the delay of the detection oscillators can be analyzed. Moreover, the method of adjusting the different structures of the two CMOS inverters in this scheme is relatively simple and easier to implement.

[0054] It should be noted that although the number of sub-active regions 1110 shown in the figures of this application is two, in reality, there can be three or more, and the specific number can be set according to actual needs. In addition, in the structures shown in Figures 6 and 7, the active region 111 is divided into two sub-active regions 1110. Thus, the first capacitor and the second capacitor of the corresponding CMOS inverter are both half of the active region 111 of the integrated structure. Taking Figure 6 as an example, the active region 111 of the first NMOS transistor 11 shown in Figure 6(a) is an integrated structure, and the active region 111 of the second NMOS transistor 51 shown in Figure 6(b) includes two sub-active regions 1110. The first capacitor and the second capacitor of the first CMOS inverter 10 are Cdo and Cj, respectively. Since the drain region in one of the sub-active regions of the second NMOS transistor 51 is provided with a drain contact structure, no conductive channel is actually formed between the drain region and the source region corresponding to the sub-active region. Therefore, the Cdo and Cj corresponding to the sub-active region are 0. Therefore, the first capacitor and the second capacitor of the second CMOS inverter 50 are Cdo / 2 and Cj / 2, respectively.

[0055] Furthermore, in the specific embodiments described above, the first difference is not limited to making the first capacitor and the second capacitor different, but can also make other parasitic capacitances different, such as making the third capacitor different. Correspondingly, the first difference is not limited to the difference in the active region 111, but also includes other differences that can make, for example, the third capacitor different. The specific structural differences that make the third capacitor different are described below.

[0056] Of course, the first difference in this application can also be that the first capacitor and the second capacitor are different, while the other parasitic capacitances are the same. In this way, the influence of the change of the first capacitor and the second capacitor on the device delay of the detection oscillator can be directly determined. In this embodiment, it is required that the structure and size of the first MOS transistor and the second MOS transistor are the same except for the active region 111, that is, everything else is the same.

[0057] In another specific embodiment of this application, a second difference between the first CMOS inverter 10 and the second CMOS inverter 50 is that the third capacitors of the first CMOS inverter 10 and the second CMOS inverter 50 are different. The second difference includes at least one of the following: the lateral area of ​​the drain contact structure 115 of the first MOS transistor is not equal to the lateral area of ​​the drain contact structure 115 of the second MOS transistor, and the lateral area is calculated by the length of the contact structure in a first direction and the length in a second direction, where the first direction is the width direction of the channel of the first MOS transistor and the second direction is the height direction of the first MOS transistor; the lateral area of ​​the source contact structure 114 of the first MOS transistor is not equal to the lateral area of ​​the source contact structure 114 of each of the second MOS transistors. Wherein, the first MOS transistor is a first NMOS transistor 11, and the second MOS transistor is a second NMOS transistor 51; and / or, the first MOS transistor is a first PMOS transistor 12, and the second MOS transistor is a second PMOS transistor 52. Figures 8 to 10 illustrate three different schemes. In Figure 8, the source contact structure 114 of the second NMOS transistor 51 is not equal to the source contact structure 114 of the first NMOS transistor 11. In Figure 9, the source contact structure 114 of the second PMOS transistor 52 is not equal to the source contact structure 114 of the first PMOS transistor 12. In Figure 10, the drain contact structure 115 of the second NMOS transistor 51 is not equal to the drain contact structure 115 of the first NMOS transistor 11, and the drain contact structure 115 of the second PMOS transistor 52 is not equal to the drain contact structure 115 of the first PMOS transistor 12. In this scheme, by adjusting the side area of ​​the source contact structure 114 and / or the side area of ​​the drain contact structure 115 in the two MOS transistors, the coupling capacitance between the source contact structure 114 and the gate 116 and / or the coupling capacitance between the drain contact structure 115 and the gate 116 are different. In this scheme, only the side area of ​​the source contact structure 114 and / or the side area of ​​the drain contact structure 115 need to be adjusted so that the coupling capacitance between the source contact structure and / or the drain contact structure and the gate in one CMOS inverter changes relative to the other (the ratio of side area adjustment is proportional to the ratio of third capacitance change; if the side area is adjusted to half of the other, then the third capacitance is also half of the other). This makes the third capacitance between the first CMOS inverter 10 and the second CMOS inverter 50 different. Based on the output frequency of the two corresponding detection oscillators, the effect of the change in third capacitance on the delay of the detection oscillator can be analyzed.

[0058] It should also be noted that the difference between the lateral area of ​​the drain contact structure 115 and the lateral area of ​​the source contact structure 114 is not limited to that shown in Figures 8 to 10. That is, the difference shown in Figures 8 to 10 is that the lateral area of ​​one of them is half of the other (the source contact structure 114 of the second NMOS transistor 51 in Figure 8(b) is half of the source contact structure 114 of the first NMOS transistor 11 in Figure 8(a), and the source contact structure 114 of the second PMOS transistor 52 in Figure 9(b) is half of the source contact structure 114 of the first NMOS transistor 11 in Figure 9(a)). The source contact structure 114 of the first PMOS transistor 12 is half of the source contact structure 114 of the first NMOS transistor 11 in Figure 10(b), and the drain contact structure 115 of the second NMOS transistor 51 in Figure 10(a) is half of the drain contact structure 115 of the first NMOS transistor 11 in Figure 10(a), and the drain contact structure 115 of the second PMOS transistor 52 is half of the drain contact structure 115 of the first PMOS transistor 12. However, in practical applications, it is not limited to half, and other ratios may be used. Those skilled in the art can set appropriate ratios according to actual conditions. In addition, the difference in side area is actually proportional to the difference in third capacitor. In the structure shown in Figure 8, the area of ​​the source contact structure 114 of the second NMOS transistor 51 is half of the area of ​​the source contact structure 114 of the first NMOS transistor 11. Correspondingly, the third capacitor of the second CMOS inverter 50 is also half of the third capacitor of the first CMOS inverter 10.

[0059] In the above embodiments, the first MOS transistor can be either a first NMOS transistor 11 or a first PMOS transistor 12, and the second MOS transistor can be either a second NMOS transistor 51 or a second PMOS transistor 52. Therefore, embodiments with different third capacitors for the first and second MOS transistors actually include several cases. Specifically, in the first case, the second difference is that the lateral area of ​​the drain contact structure 115 of the first NMOS transistor 11 is not equal to the lateral area of ​​the drain contact structure 115 of the second NMOS transistor 51; in the second case, the second difference is that the lateral area of ​​the source contact structure 114 of the first NMOS transistor 11 is not equal to the lateral area of ​​the source contact structure 115 of the second NMOS transistor 51. The second difference is that the side area of ​​the drain contact structure 115 of the first PMOS transistor 12 is not equal to the side area of ​​the drain contact structure 115 of the second PMOS transistor 52; the third difference is that the side area of ​​the source contact structure 114 of the first PMOS transistor 12 is not equal to the side area of ​​the source contact structure 114 of the second PMOS transistor 52; the fifth difference includes that the side area of ​​the drain contact structure 115 of the first NMOS transistor 11 is not equal to the side area of ​​the drain contact structure 115 of the second NMOS transistor 51, and the side area of ​​the source contact structure 114 of the first NMOS transistor 11 is not equal to the side area of ​​the source contact structure 114 of the second NMOS transistor 51. The lateral area of ​​structure 114; The sixth case, the second difference includes: the lateral area of ​​the drain contact structure 115 of the first NMOS transistor 11 is not equal to the lateral area of ​​the drain contact structure 115 of the second NMOS transistor 51, and the lateral area of ​​the drain contact structure 115 of the first PMOS transistor 12 is not equal to the lateral area of ​​the drain contact structure 115 of the second PMOS transistor 52; The seventh case, the second difference includes: the lateral area of ​​the drain contact structure 115 of the first NMOS transistor 11 is not equal to the lateral area of ​​the drain contact structure 115 of the second NMOS transistor 51, and the lateral area of ​​the source contact structure 114 of the first PMOS transistor 12 is not equal to the lateral area of ​​the source contact structure 114 of each of the second PMOS transistors 52. Side area; Eighth case, the second difference includes: the side area of ​​the source contact structure 114 of the first NMOS transistor 11 is not equal to the side area of ​​the source contact structure 114 of each of the second NMOS transistors 51, and the side area of ​​the drain contact structure 115 of the first PMOS transistor 12 is not equal to the side area of ​​the drain contact structure 115 of the second PMOS transistor 52; Ninth case, the second difference includes: the side area of ​​the source contact structure 114 of the first NMOS transistor 11 is not equal to the side area of ​​the source contact structure 114 of each of the second NMOS transistors 51, and the side area of ​​the source contact structure 114 of the first PMOS transistor 12 is not equal to the side area of ​​the source contact structure 114 of each of the second PMOS transistors 52.The tenth scenario, the second distinction, includes: the lateral area of ​​the drain contact structure 115 of the first PMOS transistor 12 is not equal to the lateral area of ​​the drain contact structure 115 of the second PMOS transistor 52, and the lateral area of ​​the source contact structure 114 of the first PMOS transistor 12 is not equal to the lateral area of ​​the source contact structure 114 of each of the second PMOS transistors 52. It also includes schemes combining any three of the first to fourth scenarios, and schemes combining the first to fourth scenarios, which will not be elaborated here.

[0060] To establish a second difference between the first CMOS inverter 10 and the second CMOS inverter 50, various specific implementation schemes are available. Specifically, one of the following schemes allows the lateral area of ​​the drain contact structure 115 of the first MOSFET to be different from the lateral area of ​​the drain contact structures of each of the second MOSFETs:

[0061] The length of the drain contact structure of each first MOS transistor in the first direction is not equal to the length of the drain contact structure of each second MOS transistor in the first direction, and the length of the drain contact structure of each first MOS transistor in the second direction is equal to the length of the drain contact structure of each second MOS transistor in the second direction, as shown in Figure 10.

[0062] The length of the drain contact structure of each first MOS transistor in the first direction is equal to the length of the drain contact structure of each second MOS transistor in the first direction, and the length of the drain contact structure of each first MOS transistor in the second direction is not equal to the length of the drain contact structure of each second MOS transistor in the second direction.

[0063] The side-side area of ​​the source contact structure of each first MOSFET is not equal to the side-side area of ​​the source contact structure of each second MOSFET, including one of the following:

[0064] The length of the source contact structure of each first MOS transistor in the first direction is not equal to the length of the source contact structure of each second MOS transistor in the first direction, and the length of the source contact structure of each first MOS transistor in the second direction is equal to the length of the source contact structure of each second MOS transistor in the second direction, as shown in Figures 8 and 9.

[0065] The length of the source contact structure of each first MOS transistor in the first direction is equal to the length of the source contact structure of each second MOS transistor in the first direction, and the length of the source contact structure of each first MOS transistor in the second direction is not equal to the length of the source contact structure of each second MOS transistor in the second direction.

[0066] In another specific embodiment of this application, a third difference between the first CMOS inverter 10 and the second CMOS inverter 50 is that the second capacitors of the first CMOS inverter 10 and the second CMOS inverter 50 are different. The third difference includes: the predetermined length of the active region 111 of the first MOS transistor in the third direction is not equal to the predetermined length of the second MOS transistor in the third direction. The predetermined length is the length of the active region from the target center point to one edge of the drain contact structure. The target center point is the midpoint between the source contact structure 114 and the drain contact structure 115. The first MOS transistor is the first NMOS transistor 11, and the second MOS transistor is the second NMOS transistor 51; and / or, the first MOS transistor is the first PMOS transistor 12, and the second MOS transistor is the second PMOS transistor 52. The third direction is perpendicular to the first direction and the second direction, respectively. The first direction is the width direction of the channel of the first MOS transistor, and the second direction is the height direction of the first MOS transistor. Specifically, as shown in Figures 11 and 12, in Figure 11, the predetermined length of the active region 111 of the first NMOS transistor 11 in the third direction is different from the predetermined length of the active region 111 of the second NMOS transistor 51 in the third direction (specifically, in Figure 11(a), the predetermined length of the active region 111 of the first NMOS transistor 11 in the third direction is half of the predetermined length of the active region 111 of the second NMOS transistor 51 in the third direction in Figure 11(b);), and in Figure 12, the predetermined length of the active region 111 of the first PMOS transistor 12 in the third direction is different from the predetermined length of the active region 111 of the second PMOS transistor 52 in the third direction (specifically, in Figure 12(a), the predetermined length of the active region 111 of the first PMOS transistor 12 in the third direction is half of the predetermined length of the active region 111 of the second PMOS transistor 52 in the third direction). In this scheme, by adjusting the length (i.e., the predetermined length) of the active region 111 near the drain contact structure 115, the junction capacitance (i.e., the second capacitance) of the drain region and the active region 111 is made different. Subsequently, based on the output frequencies of the two corresponding detection oscillators, the effect of the change in the second capacitance on the delay of the detection oscillator can be analyzed separately. In this scheme where the parasitic capacitance between the first CMOS inverter 10 and the second CMOS inverter 50 is different, only the predetermined length of the active region 111 needs to be adjusted, making this scheme easier to implement.

[0067] It should be noted that the difference in the predetermined length in this application is not limited to the difference between Figure 11 and Figure 12, but can be any other numerical variation. Those skilled in the art can determine the difference in the predetermined length based on the actual content to be analyzed, which will not be elaborated here.

[0068] Furthermore, the difference in the predetermined length is proportional to the difference in the second capacitor. For example, as shown in Figures 11 and 12, the predetermined length of the active region 111 of the first NMOS transistor 11 is L, and the predetermined length of the active region 111 of the second NMOS transistor 51 is 2L. Since the length of the active region is the same as the length of the substrate, the predetermined length of the substrate of the second NMOS transistor 51 in the third direction is also twice that of the first NMOS transistor 11. The area of ​​the drain region remains unchanged, and the area of ​​the substrate on the drain region side becomes twice the original area, making the second capacitor of the second CMOS twice that of the second capacitor of the first CMOS.

[0069] It should also be noted that the only difference between the two CMOS inverters in Figures 6 and 7 of this application is the difference shown in the active region 111; all other structures are the same. Similarly, the only difference between the two CMOS inverters in Figures 8 to 10 is the area of ​​the source contact structure 114 or the area of ​​the drain contact structure 115 shown in the figures; all other structures are the same. Likewise, the only difference between the two CMOS inverters in Figures 11 and 12 is the difference in the preset length shown in the figures; all other structures are the same. Of course, in practical applications, the differences shown in these figures can be combined according to the analytical needs, allowing for analysis from multiple perspectives. For example, the differences shown in Figure 6 and Figure 8 can be combined simultaneously, etc., which will not be listed here.

[0070] It should also be noted that Figures 6 to 11 also show the metal interconnect structure 117, the input terminal 13, the output terminal 14, and the second power supply voltage terminal 40.

[0071] In another typical embodiment of this application, a test method using any type of test circuit is also provided, such as... Figure 13 As shown, the above test methods include:

[0072] Step S101: Obtain the output frequency of the first detection oscillator 100 to obtain the first output frequency;

[0073] Step S102: Obtain the output frequency of the second detection oscillator 200 to obtain the second output frequency;

[0074] Step S103: Calculate the first delay and the second delay based at least on the number of inverters 2N+1 in the detection oscillator, the first output frequency, and the second output frequency, and determine the change in the second delay relative to the first delay caused by the different parasitic capacitances. The first delay is the delay of the first CMOS inverter, and the second delay is the delay of the second CMOS inverter.

[0075] In the above test method, the output frequencies of the two detection oscillators are first obtained. Since the parasitic capacitances of the two detection oscillators in the test circuit are different, the first delay and the second delay are calculated based on the number of inverters in each detection oscillator and the two output frequencies. This way, the influence of the different parasitic capacitances on the delay can be determined.

[0076] It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0077] Specifically, the formula for calculating the delay is: Where f is the output frequency of the detection oscillator, D is the delay of each inverter, and η is the division factor. The first and second delays are calculated using this formula, allowing analysis of the impact of changes in parasitic capacitance on the delay.

[0078] In another specific embodiment of this application, determining the change in the second delay relative to the first delay caused by the difference in parasitic capacitance includes: obtaining the difference between the second capacitance of the first CMOS inverter and the parasitic capacitance of the second CMOS inverter, wherein the parasitic capacitance includes at least one of the following: a first capacitance, a second capacitance, and a third capacitance, wherein the first capacitance is the direct coupling capacitance between the source region and / or the drain region and the gate, the second capacitance is the junction capacitance between the drain region and the substrate, and the third capacitance is the coupling capacitance between the source contact structure and / or the drain contact structure and the gate; and determining the effect of the change in the second capacitance on the delay of the CMOS inverter in the detection oscillator based on the difference in parasitic capacitance, N, the first output frequency, and the second output frequency. In this method, the difference in parasitic capacitance of the CMOS inverters in the two detection oscillators can be calculated, so that the relationship between the difference in parasitic capacitance and the difference in delay can be analyzed, thereby analyzing the effect of parasitic capacitance on delay in more detail.

[0079] Optionally, obtaining the difference between the second capacitance of the first CMOS inverter and the parasitic capacitance of the second CMOS inverter includes: calculating the equivalent capacitance of the first CMOS inverter based on the first output frequency and the effective drive current of the first detection oscillator 100 to obtain the first equivalent capacitance; and calculating the equivalent capacitance of the second CMOS inverter based on the second output frequency and the effective drive current of the second detection oscillator 200 to obtain the second equivalent capacitance. Specifically, the formula for calculating the equivalent capacitance Cs is as follows: Where IDDA is the switching current of the CMOS inverter, IDDQ is the quiescent current of the CMOS inverter, and VDD is the voltage at the first power supply terminal mentioned above; the difference between the first equivalent capacitance and the second equivalent capacitance is calculated to obtain the difference in parasitic capacitance. Alternatively, Cs can be calculated using D = Rsw × Cs.

[0080] In a more specific embodiment, the differences in parasitic capacitance corresponding to only the first difference (only the first capacitor and the second capacitor are different), the differences in parasitic capacitance corresponding to only the second difference (only the third capacitor is different), and the differences in parasitic capacitance corresponding to only the third difference (only the second capacitor is different) can be calculated, thereby allowing analysis of the impact of each different capacitor on the delay. Of course, the impact of other parasitic capacitance differences on the delay can also be calculated according to the actual situation, and is not limited to the cases mentioned.

[0081] To analyze the relationship between the input capacitance and the delay of the detection oscillator, such as Figure 4 As shown, in one embodiment of this application, the test circuit includes two... Figure 2 The detection oscillators shown (the first detection oscillator 100 and the third detection oscillator 300, differing only in the parasitic capacitance of the first CMOS inverter and the second CMOS inverter) and one Figure 4The detection oscillator (second detection oscillator 200, differing from the first detection oscillator 100 only in that the second detection oscillator 200 is not multi-fan-out) has 2N+1 inverters that correspond one-to-one with the 2N+1 inverters in the first detection oscillator 100, and the power supply voltage of each inverter in the second detection oscillator 200 is the same as the power supply voltage of each inverter in the first detection oscillator 100. The difference between the first detection oscillator 100 and the third detection oscillator 300 is that the equivalent input capacitance between the first CMOS inverter and the third CMOS inverter 80 (the CMOS inverter in the third detection oscillator 300) is different, specifically the first capacitor and / or the third capacitor are different. The first capacitor is the direct coupling capacitance between the source region and the gate, and the third capacitor is the coupling capacitance between the source contact structure and the gate. After determining the change in the second delay relative to the first delay caused by the difference in parasitic capacitance, the method further includes: calculating based on the first output frequency and the effective drive current of the first detection oscillator 100. The equivalent capacitance of the first CMOS inverter is calculated as follows: Cs1 is obtained. Based on the second output frequency and the effective drive current of the second detection oscillator 200, the equivalent capacitance of the second CMOS inverter, Cs2, is calculated. Based on the output frequency and effective drive current of the third detection oscillator 300, the equivalent capacitance of the third CMOS inverter 80, Cs3, is calculated. The third CMOS inverter 80 is the CMOS inverter of the third detection oscillator 300. The specific method for calculating the equivalent capacitance is referenced in the formula above. Based on the first and second equivalent capacitances, the equivalent input capacitance and other capacitances of the first CMOS inverter are calculated. The other capacitances are the sum of the equivalent output capacitance and the subsequent parasitic capacitance. Since the second detection oscillator 200 is a cascaded series of 2N+1 inverters from the first detection oscillator 100, the equivalent input capacitance of the first CMOS inverter is 3Cin. The equivalent input capacitance of the CMOS inverter of the second detection oscillator 200 is Cin. Therefore, based on Cs... 1＝ 3Cin + Cout1 + Cp1, Cs 2＝ Cin and Cout1 + Cp1 are calculated from Cin + Cout2 + Cp2, where Cout1 = Cout2 and Cp1 = Cp2. Based on the third equivalent capacitor, the equivalent input capacitor of the first CMOS inverter 10, and other capacitors, the equivalent input capacitor of the third CMOS inverter 80 is calculated. Because the equivalent input capacitor 3Cin of the first CMOS inverter 10 and the equivalent input capacitor Cin3 of the third CMOS inverter 80 are different, Cout1 = Cout3 and Cp1 = Cp3. Based on Cs... 3＝ Cin3+Cout3+Cp3 and Cs 1＝3Cin + Cout1 + Cp1 can be used to calculate Cin3, which allows us to analyze the relationship between different equivalent input capacitances and delays.

[0082] In another typical embodiment of this application, a test apparatus employing any type of test circuit is provided, such as... Figure 14 As shown, the testing device includes a first acquisition unit 01, a second acquisition unit 02, and a determination unit 03. The first acquisition unit 01 is used to acquire the output frequency of the first detection oscillator 100 to obtain the first output frequency. The second acquisition unit 02 is used to acquire the output frequency of the second detection oscillator 200 to obtain the second output frequency. The determination unit 03 calculates the first delay and the second delay based at least on the number of inverters 2N+1 in the detection oscillator, the first output frequency, and the second output frequency, and determines the change of the second delay relative to the first delay caused by the different parasitic capacitances. The first delay is the delay of the first CMOS inverter, and the second delay is the delay of the second CMOS inverter.

[0083] In the aforementioned test apparatus, the output frequencies of the two detection oscillators are first obtained. Since the parasitic capacitances of the two detection oscillators in the test circuit are different, the first delay and the second delay are then calculated based on the number of inverters in each detection oscillator and the two output frequencies. This allows us to determine the effect of the different parasitic capacitances on the delay.

[0084] In another specific embodiment of this application, the determining unit is further configured to perform: obtaining the difference between the second capacitance of the first CMOS inverter and the parasitic capacitance of the second CMOS inverter, wherein the parasitic capacitance includes at least one of the following: a first capacitor, a second capacitor, and a third capacitor, wherein the first capacitor is the direct coupling capacitance between the source region and / or the drain region and the gate, the second capacitor is the junction capacitance between the drain region and the substrate, and the third capacitor is the coupling capacitance between the source contact structure and / or the drain contact structure and the gate; and determining the effect of the change in the second capacitor on the delay of the CMOS inverter in the detection oscillator based on the difference in parasitic capacitance, N, the first output frequency, and the second output frequency. In this method, the difference in parasitic capacitance of the CMOS inverters in the two detection oscillators can be calculated, so that the relationship between the difference in parasitic capacitance and the difference in delay can be analyzed, thereby analyzing the effect of parasitic capacitance on delay in more detail.

[0085] Optionally, obtaining the difference between the second capacitance of the first CMOS inverter and the parasitic capacitance of the second CMOS inverter includes: calculating the equivalent capacitance of the first CMOS inverter based on the first output frequency and the effective drive current of the first detection oscillator 100 to obtain the first equivalent capacitance; and calculating the equivalent capacitance of the second CMOS inverter based on the second output frequency and the effective drive current of the second detection oscillator 200 to obtain the second equivalent capacitance. Specifically, the formula for calculating the equivalent capacitance Cs is as follows: Where IDDA is the active mode current, IDDQ is the quiescent mode current, and VDD is the voltage at the first power supply terminal mentioned above; the difference between the first equivalent capacitance and the second equivalent capacitance is calculated to obtain the difference in parasitic capacitance. Alternatively, Cs can be calculated using D = Rsw × Cs.

[0086] In a more specific embodiment, the differences in parasitic capacitance corresponding to only the first difference (only the first capacitor and the second capacitor are different), the differences in parasitic capacitance corresponding to only the second difference (only the third capacitor is different), and the differences in parasitic capacitance corresponding to only the third difference (only the second capacitor is different) can be calculated, thereby allowing analysis of the impact of each different capacitor on the delay. Of course, the impact of other parasitic capacitance differences on the delay can also be calculated based on actual conditions, and is not limited to the cases mentioned above.

[0087] In another typical embodiment of this application, a testing system is also provided, which includes a testing device and any of the above-described testing circuits. The output terminals of the testing device and the testing circuit are communicatively connected, and the testing device is used to perform any of the above-described testing methods.

[0088] This testing system can quantitatively analyze the impact of structural changes in a CMOS inverter on its delay by comparing the difference between the first oscillation frequency output by the first detection oscillator 100 and the second oscillation frequency output by the second detection oscillator 200. This increases the number of methods for analyzing the impact of structural changes in an oscillator on device delay and solves the problem that existing technologies have relatively limited methods for analyzing the impact of structural changes in an oscillator on device delay.

[0089] In another typical embodiment of this application, a memory is provided that includes a test circuit, which is any of the test circuits described above.

[0090] Since the aforementioned memory includes the aforementioned test circuit, it can determine the impact of structural changes in the CMOS inverter on the inverter delay based on the difference between the first oscillation frequency output by the first detection oscillator 100 and the second oscillation frequency output by the second detection oscillator 200. This increases the number of solutions for analyzing the impact of structural changes in the oscillator on the device delay and solves the problem that the existing solutions for analyzing the impact of structural changes in the oscillator on the device delay are relatively limited.

[0091] In the above embodiments of the present invention, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0092] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units described above can be a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, or indirect coupling or communication connection between units or modules, and may be electrical or other forms.

[0093] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0094] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0095] If the integrated units described above are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention.

[0096] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0097] 1) In the test circuit of this application, the number of inverters in the first detection oscillator 100 and the second detection oscillator 200 are the same, and the connection method of the inverter units is also the same. The difference lies in the parasitic capacitance of the second inverter unit and the first inverter unit. In this way, the difference between the first oscillation frequency output by the first detection oscillator 100 and the second oscillation frequency output by the second detection oscillator 200 can be used to determine the effect of the structural change of the inverter unit (i.e. the difference between the first inverter unit and the second inverter unit) on the inverter delay. This increases the number of solutions for analyzing the effect of structural changes in the oscillator on the device delay and solves the problem that the solutions for analyzing the effect of structural changes in the oscillator on the device delay in the prior art are relatively simple.

[0098] 2) In the test method of this application, the output frequencies of the two detection oscillators are first obtained. Since the parasitic capacitances of the two detection oscillators in the above test circuit are different, the first delay and the second delay are calculated according to the number of inverters in each detection oscillator and the two output frequencies. In this way, the influence of the different parasitic capacitances on the delay can be determined.

[0099] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A test circuit, characterized by include: The first detection oscillator includes 2N+1 first inverting units cascaded in sequence, each of the first inverting units being composed of a transistor. The first detection oscillator is used to generate and output a first oscillation frequency. The second detection oscillator includes 2N+1 second inverting units cascaded in sequence. Each second inverting unit is composed of a transistor, where N is a positive integer greater than or equal to 1. The second detection oscillator is used to generate and output a second oscillation frequency. The parasitic capacitance of the second inverting unit is different from that of the first inverting unit. Based on the detected first oscillation frequency and the detected second oscillation frequency, the relationship between the parasitic capacitance and the inverter delay is determined, where N is a positive integer greater than or equal to 1; In the 2N+1 cascaded first inverting units, the first-stage first inverting unit includes a first controllable NOT gate, and the remaining first inverting units include a first NOT gate; wherein, the first NOT gate is a first CMOS inverter, and the first CMOS inverter includes a first NMOS transistor and a first PMOS transistor; In 2N+1 cascaded second inverting units, the second inverter in the first stage of the second inverting unit is a second controllable NOT gate, and the remaining second inverting units are second NOT gates; wherein, the second NOT gate is a second CMOS inverter, and the second CMOS inverter includes a second NMOS transistor and a second PMOS transistor; The parasitic capacitance of the second inverting unit is different from that of the first inverting unit, including: the parasitic capacitance of the second CMOS inverter is different from that of the first CMOS inverter; The parasitic capacitance of the second CMOS inverter differs from that of the first CMOS inverter in that: the second CMOS inverter differs from at least one of the first, second, and third capacitors of the first CMOS inverter, wherein the first capacitor is the direct coupling capacitance between the source region and / or drain region and the gate, the second capacitor is the junction capacitance between the drain region and the substrate, and the third capacitor is the coupling capacitance between the source contact structure and / or drain contact structure and the gate. The first difference between the second CMOS inverter and the first CMOS inverter is at least such that the first capacitor and the second capacitor of the second CMOS inverter are different from those of the first CMOS inverter, and the first difference includes: The first MOSFET has a single active region, while the second MOSFET has an active region comprising at least two spaced sub-active regions distributed along a first direction. The sum of the lengths of all the sub-active regions of the second MOSFET in the first direction is the same as the length of the active region of the first MOSFET in the first direction. Other structural parameters of each sub-active region of the first MOSFET are the same as those of the active region of the second MOSFET. A portion of the sub-active regions in the second MOSFET do not have the drain contact structure. The first direction is the width direction of the channel of the first MOSFET. Wherein, the first MOS transistor is the first NMOS transistor, and the second MOS transistor is the second NMOS transistor; and / or, the first MOS transistor is the first PMOS transistor, and the second MOS transistor is the second PMOS transistor.

2. The test circuit of claim 1, wherein, Apart from the active region, the first MOS transistor and the second MOS transistor have the same structure and dimensions.

3. The test circuit of claim 1, wherein, A second difference between the first CMOS inverter and the second CMOS inverter causes the third capacitor of the first CMOS inverter to be different from that of the second CMOS inverter, and the second difference includes at least one of the following: The side area of ​​the drain contact structure of each first MOS transistor is not equal to the side area of ​​the drain contact structure of each second MOS transistor. The lateral area of ​​the source contact structure of each first MOS transistor is not equal to the lateral area of ​​the source contact structure of each second MOS transistor. Wherein, the first MOS transistor is the first NMOS transistor, and the second MOS transistor is the second NMOS transistor; and / or, the first MOS transistor is the first PMOS transistor, and the second MOS transistor is the second PMOS transistor, and the side area is calculated from the length of the contact structure in a first direction and the length in a second direction, wherein the first direction is the width direction of the channel of the first MOS transistor, and the second direction is the height direction of the first MOS transistor.

4. The test circuit according to claim 3, characterized in that, The lateral area of ​​the drain contact structure of each first MOSFET is not equal to the lateral area of ​​the drain contact structure of each second MOSFET, including one of the following: The length of the drain contact structure of each first MOS transistor in the first direction is not equal to the length of the drain contact structure of each second MOS transistor in the first direction, and the length of the drain contact structure of each first MOS transistor in the second direction is equal to the length of the drain contact structure of each second MOS transistor in the second direction. The length of the drain contact structure of each first MOS transistor in the first direction is equal to the length of the drain contact structure of each second MOS transistor in the first direction, and the length of the drain contact structure of each first MOS transistor in the second direction is not equal to the length of the drain contact structure of each second MOS transistor in the second direction. The lateral area of ​​the source contact structure of each of the first MOSFETs is not equal to the lateral area of ​​the source contact structure of each of the second MOSFETs, including one of the following: The length of the source contact structure of each first MOS transistor in the first direction is not equal to the length of the source contact structure of each second MOS transistor in the first direction, and the length of the source contact structure of each first MOS transistor in the second direction is equal to the length of the source contact structure of each second MOS transistor in the second direction. The length of the source contact structure of each first MOS transistor in the first direction is equal to the length of the source contact structure of each second MOS transistor in the first direction, and the length of the source contact structure of each first MOS transistor in the second direction is not equal to the length of the source contact structure of each second MOS transistor in the second direction.

5. The test circuit of claim 1, wherein, A third difference between the first CMOS inverter and the second CMOS inverter is that the second capacitor of the first CMOS inverter and the second CMOS inverter are different, and the third difference includes: The predetermined length of the active region of the first MOSFET in the third direction is not equal to the predetermined length of the second MOSFET in the third direction. The predetermined length is the length of the active region from the target center point to one side edge of the drain contact structure. The target center point is the midpoint between the source contact structure and the drain contact structure. Wherein, the first MOS transistor is the first NMOS transistor, and the second MOS transistor is the second NMOS transistor; and / or, the first MOS transistor is the first PMOS transistor, and the second MOS transistor is the second PMOS transistor, and the third direction is the length direction of the channel of the first MOS transistor.

6. The test circuit of any one of claims 1 to 3, wherein, The first controllable NOT gate is a first NAND gate. The first input terminal of the first NAND gate receives an enable signal to control the first detection oscillator to generate an oscillation signal. The second input terminal and output terminal of the first NAND gate are cascaded with the other 2N first NOT gates to form a ring oscillation circuit. The first power supply terminals of the first NAND gate and the 2N first NOT gates are respectively connected to a first power supply voltage. The second power supply terminals of the first NAND gate and the 2N first NOT gates are respectively connected to a second power supply voltage. The source of the first PMOS transistor of the first CMOS inverter is the first power supply terminal, and the source of the first NMOS transistor of the first CMOS inverter is the second power supply terminal.

7. The test circuit of claim 1, wherein, In the 2N+1 first inverting units, in addition to the first inverting unit of the first stage, each first inverting unit also includes a plurality of first fan-out CMOS inverters. The plurality of first fan-out CMOS inverters are connected to the corresponding first CMOS inverter input terminals. The first power supply terminals of the plurality of first fan-out CMOS inverters are connected to a third power supply voltage. The second power supply terminals of the plurality of first fan-out CMOS inverters are connected to a second power supply voltage.

8. The test circuit of claim 1, wherein, The test circuit further includes at least one third detection oscillator, which is composed of 2N+1 cascaded third inverting units. The 2N+1 third inverting units of the third detection oscillator correspond one-to-one with the 2N+1 first inverting units in the first detection oscillator, and the parasitic capacitance of the third inverting unit is different from that of the first and second inverting units.

9. A test circuit, characterized by include: The first detection oscillator includes 2N+1 first inverting units cascaded in sequence, each of the first inverting units being composed of a transistor. The first detection oscillator is used to generate and output a first oscillation frequency. The second detection oscillator includes 2N+1 second inverting units cascaded in sequence. Each second inverting unit is composed of a transistor, where N is a positive integer greater than or equal to 1. The second detection oscillator is used to generate and output a second oscillation frequency. The parasitic capacitance of the second inverting unit is different from that of the first inverting unit. Based on the detected first oscillation frequency and the detected second oscillation frequency, the relationship between the parasitic capacitance and the inverter delay is determined, where N is a positive integer greater than or equal to 1; In the 2N+1 cascaded first inverting units, the first-stage first inverting unit includes a first controllable NOT gate, and the remaining first inverting units include a first NOT gate; wherein, the first NOT gate is a first CMOS inverter, and the first CMOS inverter includes a first NMOS transistor and a first PMOS transistor; In 2N+1 cascaded second inverting units, the second inverter in the first stage of the second inverting unit is a second controllable NOT gate, and the remaining second inverting units are second NOT gates; wherein, the second NOT gate is a second CMOS inverter, and the second CMOS inverter includes a second NMOS transistor and a second PMOS transistor; The parasitic capacitance of the second inverting unit is different from that of the first inverting unit, including: the parasitic capacitance of the second CMOS inverter is different from that of the first CMOS inverter; The parasitic capacitance of the second CMOS inverter differs from that of the first CMOS inverter in that: the second CMOS inverter differs from at least one of the first, second, and third capacitors of the first CMOS inverter, wherein the first capacitor is the direct coupling capacitance between the source region and / or drain region and the gate, the second capacitor is the junction capacitance between the drain region and the substrate, and the third capacitor is the coupling capacitance between the source contact structure and / or drain contact structure and the gate. A second difference between the first CMOS inverter and the second CMOS inverter causes the third capacitor of the first CMOS inverter to be different from that of the second CMOS inverter, and the second difference includes at least one of the following: The side area of ​​the drain contact structure of each first MOS transistor is not equal to the side area of ​​the drain contact structure of each second MOS transistor. The lateral area of ​​the source contact structure of each first MOS transistor is not equal to the lateral area of ​​the source contact structure of each second MOS transistor. Wherein, the first MOS transistor is the first NMOS transistor, and the second MOS transistor is the second NMOS transistor; and / or, the first MOS transistor is the first PMOS transistor, and the second MOS transistor is the second PMOS transistor, and the side area is calculated from the length of the contact structure in a first direction and the length in a second direction, where the first direction is the width direction of the channel of the first MOS transistor, and the second direction is the height direction of the first MOS transistor; The lateral area of ​​the drain contact structure of each first MOSFET is not equal to the lateral area of ​​the drain contact structure of each second MOSFET, including one of the following: The length of the drain contact structure of each first MOS transistor in the first direction is not equal to the length of the drain contact structure of each second MOS transistor in the first direction, and the length of the drain contact structure of each first MOS transistor in the second direction is equal to the length of the drain contact structure of each second MOS transistor in the second direction. The length of the drain contact structure of each first MOS transistor in the first direction is equal to the length of the drain contact structure of each second MOS transistor in the first direction, and the length of the drain contact structure of each first MOS transistor in the second direction is not equal to the length of the drain contact structure of each second MOS transistor in the second direction. The lateral area of ​​the source contact structure of each of the first MOSFETs is not equal to the lateral area of ​​the source contact structure of each of the second MOSFETs, including one of the following: The length of the source contact structure of each first MOS transistor in the first direction is not equal to the length of the source contact structure of each second MOS transistor in the first direction, and the length of the source contact structure of each first MOS transistor in the second direction is equal to the length of the source contact structure of each second MOS transistor in the second direction. The length of the source contact structure of each first MOS transistor in the first direction is equal to the length of the source contact structure of each second MOS transistor in the first direction, and the length of the source contact structure of each first MOS transistor in the second direction is not equal to the length of the source contact structure of each second MOS transistor in the second direction.

10. A test method employing the test circuit according to any one of claims 1 to 9, characterized by, The testing method includes: Obtain the output frequency of the first detection oscillator to obtain the first output frequency; Obtain the output frequency of the second detection oscillator to obtain the second output frequency; Based at least 2N+1 of the number of inverters in the detection oscillator, the first output frequency, and the second output frequency, calculate the first delay and the second delay, and determine the change of the second delay relative to the first delay caused by the different parasitic capacitances. The first delay is the delay of the first inverting unit, and the second delay is the delay of the second inverting unit.

11. The test method of claim 10, wherein, In 2N+1 cascaded first inverting units, the first-stage first inverting unit includes a first controllable NOT gate, and the remaining first inverting units include first NOT gates; wherein the first NOT gate is a first CMOS inverter, and the first CMOS inverter includes a first NMOS transistor and a first PMOS transistor. In 2N+1 cascaded second inverting units, the second inverter in the first-stage second inverting unit is a second controllable NOT gate, and the remaining second inverting units are second NOT gates; wherein the second NOT gate is a second CMOS inverter, and the second CMOS inverter includes a second NMOS transistor and a second PMOS transistor. The parasitic capacitance of the second inverting unit differs from that of the first inverting unit, meaning the parasitic capacitance of the second CMOS inverter is different from that of the first CMOS inverter. Determining the change in the second delay relative to the first delay due to different parasitic capacitances includes: The difference between the parasitic capacitance of the first CMOS inverter and the parasitic capacitance of the second CMOS inverter is obtained. The parasitic capacitance includes at least one of the following: a first capacitor, a second capacitor, and a third capacitor. The first capacitor is the direct coupling capacitance between the source region and / or the drain region and the gate. The second capacitor is the junction capacitance between the drain region and the substrate. The third capacitor is the coupling capacitance between the source contact structure and / or the drain contact structure and the gate. Based on the difference in parasitic capacitance, the value N, the first output frequency, and the second output frequency, the effect of the change in the second capacitance on the delay of the CMOS inverter in the detection oscillator is determined.

12. The test method of claim 11, wherein, Obtaining the difference between the second capacitor of the first CMOS inverter and the parasitic capacitance of the second CMOS inverter includes: Based on the first output frequency and the effective drive current of the first detection oscillator, the equivalent capacitance of the first CMOS inverter is calculated to obtain the first equivalent capacitance. Based on the second output frequency and the effective drive current of the second detection oscillator, the equivalent capacitance of the second CMOS inverter is calculated to obtain the second equivalent capacitance; The difference between the first equivalent capacitance and the second equivalent capacitance is calculated to obtain the difference in parasitic capacitance.

13. A testing apparatus employing the testing circuit according to any one of claims 1 to 9, characterized in that, The testing apparatus includes: The first acquisition unit is used to acquire the output frequency of the first detection oscillator and obtain the first output frequency. The second acquisition unit is used to acquire the output frequency of the second detection oscillator and obtain the second output frequency. The determining unit calculates a first delay and a second delay based at least on the number of inverters in the detection oscillator (2N+1), the first output frequency, and the second output frequency, and determines the change in the second delay relative to the first delay caused by the different parasitic capacitances. The first delay is the delay of the first CMOS inverter, and the second delay is the delay of the second CMOS inverter.

14. A testing system, characterized in that, The device includes a testing apparatus and a testing circuit according to any one of claims 1 to 9, wherein the output terminals of the testing apparatus and the testing circuit are communicatively connected, and the testing apparatus is used to perform the testing method according to any one of claims 10 to 12.

15. A memory, comprising a test circuit, characterized in that, The test circuit is the test circuit according to any one of claims 1 to 9.

Images