Instructions and logic to perform floating point and integer operations for machine learning

Abstract

One embodiment provides a machine learning hardware accelerator including a compute unit having an adder and a multiplier shared between an integer datapath and a floating point datapath, high bits of input operands to the multiplier to be gated during floating point operations.

Description

[0001] This application is a divisional application of the same patent application filed on April 27, 2018, with application number 201810394160.7.

[0002] Cross-references

[0003] This application claims the benefit of U.S. Provisional Application No. 62 / 491,699, filed April 28, 2017, which is incorporated herein by reference. Technical Field

[0004] The embodiments generally relate to data processing, and more specifically to data processing via a general-purpose graphics processing unit. Background Technology

[0005] Current parallel graphics data processing includes developing systems and methods to perform specific operations on graphics data, such as linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc. Traditionally, graphics processors (GPUs) use fixed-function computing units to process graphics data; however, recently, partial programmability of GPUs has been made, enabling such processors to support a wide variety of operations for processing vertex and fragment data.

[0006] To further enhance performance, graphics processing units (GPUs) typically implement processing techniques such as attempting to process as much graphics data as possible across different parts of the graphics pipeline in parallel. Parallel GPUs with a Single Instruction Multiple Thread (SIMT) architecture are designed to maximize the amount of parallel processing in the graphics pipeline. In a SIMT architecture, groups of parallel threads attempt to execute program instructions together synchronously as often as possible to increase processing efficiency. A general overview of the software and hardware used in SIMT architectures can be found in Shane Cook's CUDA Programming, Chapter 3, pp. 37–51 (2013) and / or Nicholas Wilt's CUDA Handbook, A Comprehensive Guide to GPU Programming, Sections 2.6.2–3.1.2 (June 2013). Attached Figure Description

[0007] A more specific description of the invention can be obtained by referring to the embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the drawings illustrate only typical embodiments and are therefore not intended to limit the scope of all embodiments.

[0008] Figure 1 This is a block diagram illustrating a computer system configured to implement one or more aspects of the embodiments described herein.

[0009] Figures 2A-2D A parallel processor component according to an embodiment is shown.

[0010] Figures 3A-3B This is a block diagram of a graphics multiprocessor according to an embodiment.

[0011] Figures 4A-4F An example architecture is shown in which multiple GPUs are communicatively coupled to multiple multi-core processors.

[0012] Figure 5 A graphics processing pipeline according to an embodiment is shown.

[0013] Figure 6 A machine learning software stack according to an embodiment is shown.

[0014] Figure 7 A highly parallel general-purpose graphics processing unit according to an embodiment is shown.

[0015] Figure 8 A multi-GPU computing system according to an embodiment is shown.

[0016] Figures 9A-9B The layers of a demonstration deep neural network are shown.

[0017] Figure 10 An example recurrent neural network is shown.

[0018] Figure 11 The training and deployment of a deep neural network are illustrated.

[0019] Figure 12 This is a block diagram illustrating distributed learning.

[0020] Figure 13 A sample reasoning on-chip system (SOC) suitable for performing reasoning using a trained model is shown.

[0021] Figure 14 This is a block diagram of a multiprocessor unit according to an embodiment.

[0022] Figures 15A-15B The design of a logic unit for performing fused integer and floating-point multiplication-addition operations according to an embodiment is shown.

[0023] Figure 16 A fused multiply-accumulate logic unit with merged floating-point and integer data paths is shown according to an embodiment.

[0024] Figures 17A-17B A logic unit including merged computing circuitry according to an embodiment is shown to perform a floating-point and integer fused multiplication and accumulation operation.

[0025] Figure 18A-18B illustrates a data processing system and associated computational and logic units that perform accelerated training and inference operations for machine learning.

[0026] Figure 19 Details of the activation instruction module according to an embodiment are shown.

[0027] Figure 20 A random quantization unit according to an embodiment is shown.

[0028] Figure 21 An FPU encoding and configuration module according to one embodiment is shown.

[0029] Figure 22 The logic for processing instructions using a dynamically configurable computing unit according to an embodiment is shown.

[0030] Figures 23A-23B This is a flowchart illustrating the logic for performing sparse computation operations within a GPGPU provided by the embodiments described herein.

[0031] Figure 24 This is a block diagram of a processing system according to an embodiment.

[0032] Figure 25 This is a block diagram of a processor according to an embodiment.

[0033] Figure 26 A block diagram of a graphics processor according to an embodiment.

[0034] Figure 27 This is a block diagram of a graphics processing engine for a graphics processor according to some embodiments.

[0035] Figure 28 This is a block diagram of a graphics processor provided by an additional embodiment.

[0036] Figure 29 The diagram illustrates thread execution logic including an array of processing elements employed in some embodiments.

[0037] Figure 30 This is a block diagram illustrating a graphics processor instruction format according to some embodiments.

[0038] Figure 31 This is a block diagram of a graphics processor according to another embodiment.

[0039] Figures 32A-32B The graphics processor command format and command sequence are illustrated according to some embodiments.

[0040] Figure 33 An exemplary graphical software architecture for a data processing system is shown according to some embodiments.

[0041] Figure 34 This is a block diagram illustrating a development system for an IP core according to an embodiment.

[0042] Figure 35 This is a block diagram illustrating an exemplary system-on-chip integrated circuit according to an embodiment.

[0043] Figure 36 This is a block diagram illustrating an additional graphics processor according to an embodiment.

[0044] Figure 37 This is a block diagram illustrating an additional exemplary graphics processor of a system-on-a-chip integrated circuit according to an embodiment. Detailed Implementation

[0045] In some embodiments, a graphics processing unit (GPU) is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to the host processor / core via a bus or another interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU may be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., within the package or chip). Regardless of how the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a job descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0046] In the following description, numerous specific details are set forth to provide a more thorough understanding. However, it will be apparent to those skilled in the art that the embodiments described herein can be practiced without one or more of these specific details. In other instances, well-known features have not been described to avoid obscuring the details of embodiments of the invention.

[0047] System Overview

[0048] Figure 1This is a block diagram illustrating a computing system 100 configured to implement one or more aspects of the embodiments described herein. The computing system 100 includes a processing subsystem 101 having one or more processors 102 communicating via interconnect paths and a system memory 104, the interconnect paths including a memory hub 105. The memory hub 105 may be a separate component within a chipset assembly or may be integrated within the one or more processors 102. The memory hub 105 is coupled to an I / O subsystem 111 via a communication link 106. The I / O subsystem 111 includes an I / O hub 107 that enables the computing system 100 to receive input from one or more input devices 108. Additionally, the I / O hub 107 enables a display controller to provide output to one or more display devices 110A, which may be included within the one or more processors 102. In one embodiment, the one or more display devices 110A coupled to the I / O hub 107 may include local, internal, or embedded display devices.

[0049] In one embodiment, the processing subsystem 101 includes one or more parallel processors 112 coupled to a memory hub 105 via a bus or other communication link 113. The communication link 113 can be one of any number of standards-based communication link technologies or protocols (such as, but not limited to, PCI Express), or it can be a vendor-specific communication interface or communication architecture. In one embodiment, the one or more parallel processors 112 form a compute-intensive parallel or vector processing system including a large number of processing cores and / or processing clusters, such as integrated many-core (MIC) processors. In one embodiment, the one or more parallel processors 112 form a graphics processing subsystem that can output pixels to one of the one or more display devices 110A coupled via an I / O hub 107. The one or more parallel processors 112 may also include a display controller and a display interface (not shown) to enable direct connections to one or more display devices 110B.

[0050] Within the I / O subsystem 111, system storage unit 114 can be connected to I / O hub 107 to provide storage for computing system 100. I / O switch 116 can be used to provide an interface mechanism to enable connectivity between I / O hub 107 and other components that can be integrated into the platform (such as network adapter 118 and / or wireless network adapter 119) and various other devices that can be added via one or more plug-in devices 120. Network adapter 118 can be an Ethernet adapter or another wired network adapter. Wireless network adapter 119 can include one or more of the following: Wi-Fi, Bluetooth, Near Field Communication (NFC), or other network devices including one or more radio devices.

[0051] The computing system 100 may include other components not explicitly shown, such as USB or other port connections, optical storage drives, video capture devices, etc., and may also be connected to the I / O hub 107. Any suitable protocol can be used, such as PCI (Peripheral Component Interconnect) based protocols (e.g., PCI-Express), or any other bus or point-to-point communication interface and / or (multiple) protocols, such as NV-Link high-speed interconnects or interconnect protocols known in the art, to implement [the connection / connection]. Figure 1 The communication paths that connect the various components in the system.

[0052] In one embodiment, the one or more parallel processors 112 incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitute a graphics processing unit (GPU). In another embodiment, the one or more parallel processors 112 incorporate circuitry optimized for general-purpose processing while maintaining the underlying computing architecture described in more detail herein. In yet another embodiment, components of the computing system 100 may be integrated with one or more other system elements on a single integrated circuit. For example, the one or more parallel processors 112, memory hub 105, processor(s)102, and I / O hub 107 may be integrated into a system-on-a-chip (SoC) integrated circuit. Alternatively, components of the computing system 100 may be integrated into a single package to form a system-in-package (SIP) configuration. In one embodiment, at least a portion of the components of the computing system 100 may be integrated into a multi-chip module (MCM), which may interconnect with other multi-chip modules to form a modular computing system.

[0053] It will be understood that the computing system 100 shown herein is illustrative and variations and modifications are possible. The connectivity topology can be modified as desired, including the number and arrangement of bridges, the number of processors(102), and the number of parallel processors(112). For example, in some embodiments, system memory 104 is connected directly to processors(102) rather than via bridges, while other devices communicate with system memory 104 via memory hub 105 and processors(102). In other alternative topologies, parallel processors(112) are connected to I / O hub 107 or directly to one of the processors(102), rather than to memory hub 105. In other embodiments, I / O hub 107 and memory hub 105 may be integrated into a single chip. Some embodiments may include two or more sets of processors(102) attached via multiple sockets, which may be coupled to two or more instances of parallel processors(112).

[0054] Some of the specific components shown in this document are optional and may not be included in all implementations of the computing system 100. For example, any number of plug-in cards or peripherals may be supported, or some components may be eliminated. Furthermore, some architectures may use different terminology with... Figure 1 The components shown are similar to those in the diagram. For example, in some architectures, the memory hub 105 may be referred to as the Northbridge, while the I / O hub 107 may be referred to as the Southbridge.

[0055] Figure 2A A parallel processor 200 according to an embodiment is illustrated. Various components of the parallel processor 200 can be implemented using one or more integrated circuit devices such as a programmable processor, an application-specific integrated circuit (ASIC), or a field-programmable gate array (FPGA). According to an embodiment, the illustrated parallel processor 200 is... Figure 1 The variants of the one or more parallel processors 112 shown in the figure.

[0056] In one embodiment, the parallel processor 200 includes a parallel processing unit 202. This parallel processing unit includes an I / O unit 204 that enables communication with other devices, including other instances of the parallel processing unit 202. The I / O unit 204 may be directly connected to other devices. In one embodiment, the I / O unit 204 is connected to other devices via the use of a hub or switch interface, such as a memory hub 105. The connection between the memory hub 105 and the I / O unit 204 forms a communication link 113. Within the parallel processing unit 202, the I / O unit 204 is connected to a host interface 206 and a memory crossbar switch 216, wherein the host interface 206 receives commands relating to performing processing operations, and the memory crossbar switch 216 receives commands relating to performing memory operations.

[0057] When host interface 206 receives a command buffer via I / O unit 204, host interface 206 can route work operations for executing those commands to front end 208. In one embodiment, front end 208 is coupled to scheduler 210, which is configured to distribute commands or other work items to processing cluster array 212. In one embodiment, scheduler 210 ensures that processing cluster array 212 is properly configured and in an active state before distributing tasks to the processing clusters of processing cluster array 212. In one embodiment, scheduler 210 is implemented via firmware logic executed on a microcontroller. The microcontroller-implemented scheduler 210 can be configured to perform complex scheduling and work distribution operations at both coarse and fine granular levels, enabling context switching and rapid preemption of threads that can execute on processing array 212. In one embodiment, host software can check for workloads available for scheduling on processing array 212 via one of a plurality of graphics processing doorbells. The workload can then be automatically distributed across processing array 212 by the scheduler 210 logic within the scheduler microcontroller.

[0058] Processing cluster array 212 may include up to "N" processing clusters (e.g., clusters 214A, 214B to 214N). Each cluster 214A-214N of processing cluster array 212 can execute a large number of concurrent threads. Scheduler 210 may use various scheduling and / or work distribution algorithms to allocate work to clusters 214A-214N of processing cluster array 212, the algorithms of which may vary depending on the workload generated by each type of program or computation. Scheduling may be handled dynamically by scheduler 210 or may be partially assisted by compiler logic during the compilation of program logic configured for execution by processing cluster array 212. In one embodiment, different clusters 214A-214N of processing cluster array 212 may be assigned to process different types of programs or to perform different types of computations.

[0059] The processing cluster array 212 can be configured to perform various types of parallel processing operations. In one embodiment, the processing cluster array 212 is configured to perform general-purpose parallel computing operations. For example, the processing cluster array 212 may include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations including physical operations, and performing data transformations.

[0060] In one embodiment, the processing cluster array 212 is configured to perform parallel graphics processing operations. In embodiments where the parallel processor 200 is configured to perform graphics processing operations, the processing cluster array 212 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic, tessellation logic, and other vertex processing logic for performing texture operations. Additionally, the processing cluster array 212 may be configured to execute graphics processing-related shader programs, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. The parallel processing unit 202 may transfer data from system memory via I / O unit 204 for processing. During processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 222) and then written back to system memory.

[0061] In one embodiment, when the parallel processing unit 202 is used to perform graphics processing, the scheduler 210 may be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations across multiple clusters 214A-214N of the processing cluster array 212. In some embodiments, portions of the processing cluster array 212 may be configured to perform different types of processing. For example, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen-space operations to produce a rendered image for display. Intermediate data generated by one or more of the clusters 214A-214N may be stored in a buffer to allow intermediate data to be transferred between the clusters 214A-214N for further processing.

[0062] During operation, the processing cluster array 212 may receive processing tasks to be executed via scheduler 210, which receives commands defining the processing tasks from front-end 208. For graphics processing operations, a processing task may include data to be processed, as well as state parameters defining how the data should be processed (e.g., what program to execute) and an index of commands, such as surface (patch) data, primitive data, vertex data, and / or pixel data. Scheduler 210 may be configured to obtain an index corresponding to the task or may receive an index from front-end 208. Front-end 208 may be configured to ensure that the processing cluster array 212 is configured to be active before a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.) is initiated.

[0063] Each of one or more instances of parallel processing unit 202 may be coupled to parallel processor memory 222. Parallel processor memory 222 may be accessed via memory crossbar switch 216, which receives memory requests from processing cluster array 212 and I / O unit 204. Memory crossbar switch 216 may access parallel processor memory 222 via memory interface 218. Memory interface 218 may include multiple partition units (e.g., partition units 220A, 220B through 220N), each of which may be coupled to a portion (e.g., memory cell) of parallel processor memory 222. In one implementation, the number of partition units 220A-220N is configured to be equal to the number of memory cells, such that a first partition unit 220A has a corresponding first memory cell 224A, a second partition unit 220B has a corresponding memory cell 224B, and the Nth partition unit 220N has a corresponding Nth memory cell 224N. In other embodiments, the number of partition units 220A-220N may not be equal to the number of memory devices.

[0064] In various embodiments, memory cells 224A-224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, memory cells 224A-224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Those skilled in the art will appreciate that the specific implementation of memory cells 224A-224N can vary and can be selected from a variety of conventional designs. Rendering targets such as frame buffers or texture maps can be stored across memory cells 224A-224N, allowing partitioning cells 220A-220N to write portions of each rendering target in parallel to efficiently utilize the available bandwidth of parallel processor memory 222. In some embodiments, local instances of parallel processor memory 222 may be excluded to support a unified memory design utilizing system memory along with local cache memory.

[0065] In one embodiment, any one of the clusters 214A-214N of the processing cluster array 212 can process any data to be written to memory cells 224A-224N within the parallel processor memory 222. The memory crossbar switch 216 can be configured to transfer the output of each cluster 214A-214N to any partition cell 220A-220N or another cluster 214A-214N, which can perform additional processing operations on the output. Each cluster 214A-214N can communicate with the memory interface 218 via the memory crossbar switch 216 to read from or write to various external memory devices. In one embodiment, the memory crossbar switch 216 has a connection to the memory interface 218 for communication with I / O unit 204, and a connection to a local instance of the parallel processor memory 222, thereby enabling processing units within different processing clusters 214A-214N to communicate with system memory or other memory that is not local to the parallel processing unit 202. In one embodiment, the memory crossbar switch 216 can use virtual channels to separate traffic flows between clusters 214A-214N and partition units 220A-220N.

[0066] Although a single instance of the parallel processing unit 202 is shown within the parallel processor 200, any number of instances of the parallel processing unit 202 may be included. For example, multiple instances of the parallel processing unit 202 may be provided on a single plug-in card, or multiple plug-in cards may be interconnected. Even if different instances of the parallel processing unit 202 have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences, these different instances may be configured to interoperate. For example, and in one embodiment, some instances of the parallel processing unit 202 may include higher precision floating-point units relative to other instances. Systems combining one or more instances of the parallel processing unit 202 or the parallel processor 200 can be implemented in a variety of configurations and form factors, including but not limited to desktop computers, laptop or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0067] Figure 2B This is a block diagram of partitioning unit 220 according to an embodiment. In one embodiment, partitioning unit 220 is... Figure 2AAn example of one of partition units 220A-220N. As shown, partition unit 220 includes an L2 cache 221, a frame buffer interface 225, and a ROP 226 (raster operation unit). The L2 cache 221 is a read / write cache configured to perform load and store operations received from memory crossbar switch 216 and ROP 226. The L2 cache 221 outputs read miss and urgent write-back requests to the frame buffer interface 225 for processing. Updates can also be sent to the frame buffer via the frame buffer interface 225 for processing. In one embodiment, the frame buffer interface 225 interfaces with one of the memory cells in the parallel processor memory, such as (e.g., within parallel processor memory 222). Figure 2A The memory cells are 224A-224N.

[0068] In graphics applications, ROP 226 is a processing unit that performs raster operations such as stencil printing, z-checking, and blending. ROP 226 then outputs the processed graphics data, which is stored in graphics memory. In some embodiments, ROP 226 includes compression logic for compressing depth or color data written to memory and decompressing depth or color data read from memory. The compression logic can be lossless compression logic utilizing one or more of a variety of compression algorithms. The type of compression performed by ROP 226 can vary based on the statistical characteristics of the data to be compressed. For example, in one embodiment, Δ color compression is performed on depth and color data on a per-tile basis.

[0069] In some embodiments, ROP 226 is included in each processing cluster (e.g., Figure 2A The data is stored within clusters 214A-214N rather than within partition units 220. In such embodiments, read and write requests for pixel data are transmitted via memory crossbar switch 216, rather than pixel fragment data. The processed graphics data can be displayed on a display device (such as...). Figure 1 On one or more display devices 110, it is routed for further processing by processor(s) 102, or routed for use by... Figure 2A Further processing is performed within one of the processing entities of the parallel processor 200.

[0070] Figure 2C This is a block diagram of a processing cluster 214 within a parallel processing unit according to an embodiment. In one embodiment, the processing cluster is... Figure 2AAn instance of one of the processing clusters 214A-214N. Processing cluster 214 can be configured to execute multiple threads in parallel, where the term "thread" refers to an instance of a specific program executing on a specific set of input data. In some embodiments, a Single Instruction Multiple Data (SIMD) instruction issuing technique is used to support the parallel execution of a large number of threads without providing multiple independent units of instruction. In other embodiments, Single Instruction Multiple Threading (SIMT) technique is used to support the parallel execution of a large number of generally synchronous threads using a common unit of instruction configured to issue instructions to a set of processing engines within each of the processing clusters. Unlike a SIMD execution regime where all processing engines typically execute the same instructions, SIMT execution allows different threads to more easily follow divergent execution paths through a given thread program. Those skilled in the art will understand that a SIMD processing regime represents a subset of the functionality of a SIMT processing regime.

[0071] The operation of cluster 214 can be controlled via pipeline manager 232, which distributes processing tasks to the SIMT parallel processors. Pipeline manager 232... Figure 2A The scheduler 210 receives instructions and manages the execution of those instructions via the graphics multiprocessor 234 and / or texture unit 236. The graphics multiprocessor 234 shown is an exemplary instance of a SIMT parallel processor. However, various types of SIMT parallel processors with different architectures can be included within the processing cluster 214. One or more instances of the graphics multiprocessor 234 can be included within the processing cluster 214. The graphics multiprocessor 234 can process data, and the data crossover switch 240 can be used to distribute the processed data to one of several possible destinations, including other shader units. The pipeline manager 232 can facilitate the distribution of processed data by specifying a destination for the processed data to be distributed via the data crossover switch 240.

[0072] Each graphics multiprocessor 234 within the processing cluster 214 may include a set of identical functional execution logic (e.g., arithmetic logic units, load-memory units, etc.). The functional execution logic can be configured in a pipelined manner, where new instructions can be issued before previous instructions are completed. The functional execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, shift operations, and computation of various algebraic functions. In one embodiment, the same functional unit hardware can be used to perform different operations, and any combination of functional units may exist.

[0073] Instructions transmitted to processing cluster 214 constitute threads. A collection of threads executing across a set of parallel processing engines is a thread group. Thread groups execute the same program on different input data. Each thread within a thread group can be assigned to a different processing engine within graphics multiprocessor 234. A thread group may include fewer threads than the number of processing engines within graphics multiprocessor 234. When a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycle in which the thread group is processed. A thread group may also include more threads than the number of processing engines within graphics multiprocessor 234. When a thread group includes more threads than the number of processing engines within graphics multiprocessor 234, processing can be performed in consecutive clock cycles. In one embodiment, multiple thread groups can be executed concurrently on graphics multiprocessor 234.

[0074] In one embodiment, the graphics multiprocessor 234 includes an internal cache memory for performing load and store operations. In one embodiment, the graphics multiprocessor 234 may forgo the internal cache and instead use a cache memory within the processing cluster 214 (e.g., L1 cache 308). Each graphics multiprocessor 234 is also able to access partition units shared across all processing clusters 214 and that can be used to transfer data between threads (e.g., ...). Figure 2A The L2 cache is located within partition units 220A-220N. The graphics multiprocessor 234 can also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. Any memory outside of the parallel processing unit 202 can be used as global memory. Embodiments where the processing cluster 214 includes multiple instances of the graphics multiprocessor 234 can share common instructions and data that can be stored in the L1 cache 308.

[0075] Each processing cluster 214 may include an MMU 245 (Memory Management Unit) configured to map virtual addresses to physical addresses. In other embodiments, one or more instances of the MMU 245 may reside in Figure 2A The memory interface 218 is located within the MMU 245. The MMU 245 includes a set of page table entries (PTEs) used to map virtual addresses to physical addresses of tiles and optionally to cache line indices. The MMU 245 may include address translation lookaside buffers (TLBs) or caches, which may reside within the graphics multiprocessor 234, L1 cache, or processing cluster 214. Physical addresses are processed to distribute surface data access locality, allowing efficient request interleaving between partition units. Cache line indices can be used to determine whether a request for a cache line is a hit or a miss.

[0076] In graphics and computing applications, processing cluster 214 can be configured such that each graphics multiprocessor 234 is coupled to texture unit 236 for performing texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. Texture data is read from an internal texture L1 cache (not shown) or, in some embodiments, from an L1 cache within the graphics multiprocessor 234 and from an L2 cache, local parallel processor memory, or system memory, as needed. Each graphics multiprocessor 234 outputs a processed task to data crossover switch 240 to provide the processed task to another processing cluster 214 for further processing or to store the processed task in an L2 cache, local parallel processor memory, or system memory via memory crossover switch 216. preROP 242 (pre-raster operation unit) is configured to receive data from graphics multiprocessor 234 and direct the data to ROP units, which may be associated with partitioning units as described herein (e.g., Figure 2A The partition units 220A-220N are located together. The preROP 242 unit can perform optimizations for color blending, organize pixel color data, and perform address translation.

[0077] It will be understood that the core architecture described herein is illustrative and variations and modifications are possible. Any number of processing units, such as graphics multiprocessors 234, texture units 236, preROP 242, etc., can be included within processing cluster 214. Furthermore, although only one processing cluster 214 is shown, the parallel processing units as described herein can include any number of instances of processing cluster 214. In one embodiment, each processing cluster 214 can be configured to operate independently of other processing clusters 214 using separate and distinct processing units, L1 caches, etc.

[0078] Figure 2D A graphics multiprocessor 234 according to one embodiment is illustrated. In such embodiments, the graphics multiprocessor 234 is coupled to a pipeline manager 232 of a processing cluster 214. The graphics multiprocessor 234 has an execution pipeline including, but not limited to, an instruction cache 252, an instruction unit 254, an address mapping unit 256, a register file 258, one or more general-purpose graphics processing unit (GPGPU) cores 262, and one or more load / store units 266. The GPGPU cores 262 and the load / store units 266 are coupled to a cache memory 272 and a shared memory 270 via a memory and cache interconnect 268.

[0079] In one embodiment, instruction cache 252 receives a stream of instructions to be executed from pipeline manager 232. The instructions are cached in instruction cache 252 and dispatched for execution by instruction unit 254. Instruction unit 254 can dispatch instructions into thread groups (e.g., warps), where each thread in the warp is assigned to a different execution unit within GPGPU core 262. Instructions can access any address space in the local, shared, or global address space by specifying an address within a unified address space. Address mapping unit 256 can be used to translate addresses in the unified address space into different memory addresses accessible by load / store unit 266.

[0080] Register file 258 provides a set of registers for the functional units of graphics multiprocessor 324. Register file 258 provides temporary storage for operands on data paths connected to functional units of graphics multiprocessor 324 (e.g., GPGPU core 262, load / store unit 266). In one embodiment, register file 258 is partitioned between each functional unit such that each functional unit is allocated a dedicated portion of register file 258. In another embodiment, register file 258 is partitioned between different thread bundles being executed by graphics multiprocessor 324.

[0081] Each GPGPU core 262 may include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 324. According to embodiments, the GPGPU core 262 may be similar in architecture or may differ in architecture. For example, and in one embodiment, a first portion of the GPGPU core 262 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. The graphics multiprocessor 324 may additionally include one or more fixed-function or special-function units for performing specific functions such as copying rectangles or pixel blending operations. In one embodiment, one or more of the GPGPU cores may also include fixed-function or special-function logic.

[0082] In one embodiment, GPGPU core 262 includes SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, GPGPU core 262 can physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. The SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or can be automatically generated when executing programs written and compiled for Single Program Multiple Data (SPMD) or SIMT architectures. Multiple threads of a program configured for a SIMT execution model can be executed via a single SIMD instruction. For example, in one embodiment, eight SIMT threads performing the same or similar operations can be executed in parallel via a single SIMD8 logic unit.

[0083] The memory and cache interconnect 268 is an interconnect network that connects each functional unit of the graphics multiprocessor 324 to the register file 258 and shared memory 270. In one embodiment, the memory and cache interconnect 268 is a cross-switch interconnect that allows the load / store unit 266 to perform load and store operations between the shared memory 270 and the register file 258. The register file 258 can operate at the same frequency as the GPGPU core 262, thus data transfers between the GPGPU core 262 and the register file 258 have very low latency. The shared memory 270 can be used to enable communication between threads executing on functional units within the graphics multiprocessor 234. For example, the cache memory 272 can be used as a data cache to cache texture data transferred between functional units and texture units 236. The shared memory 270 can also be used as a cached, managed program. In addition to automatically cached data stored in the cache memory 272, threads executing on the GPGPU core 262 can also programmatically store data in the shared memory.

[0084] Figures 3A-3B An additional graphics multiprocessor according to an embodiment is shown. The illustrated graphics multiprocessors 325 and 350 are... Figure 2C Variants of the graphics multiprocessor 234. The graphics multiprocessors 325 and 350 shown can be configured as streaming multiprocessors (SM) capable of executing a large number of execution threads simultaneously.

[0085] Figure 3A A graphics multiprocessor 325 according to an additional embodiment is shown. The graphics multiprocessor 325 includes... Figure 2DThe graphics multiprocessor 234 may include multiple additional instances of execution resource units. For example, the graphics multiprocessor 325 may include multiple instances of instruction units 332A-332B, register files 334A-334B, and texture units (multiple) 344A-344B. The graphics multiprocessor 325 may also include multiple sets of graphics or compute execution units (e.g., GPGPU cores 336A-336B, GPGPU cores 337A-337B, GPGPU cores 338A-338B) and multiple sets of load / store units 340A-340B. In one embodiment, the execution resource units have a common instruction cache 330, a texture and / or data cache memory 342, and a shared memory 346.

[0086] Various components can communicate via interconnect structure 327. In one embodiment, interconnect structure 327 includes one or more cross switches to enable communication between various components of the graphics multiprocessor 325. In one embodiment, interconnect structure 327 is a separate high-speed network structure layer on which each component of the graphics multiprocessor 325 is stacked. Components of the graphics multiprocessor 325 communicate with remote components via interconnect structure 327. For example, GPGPU cores 336A-336B, 337A-337B, and 3378A-338B can each communicate with shared memory 346 via interconnect structure 327. Interconnect structure 327 can arbitrate communication within the graphics multiprocessor 325 to ensure fair bandwidth allocation among components.

[0087] Figure 3B A graphics multiprocessor 350 according to an additional embodiment is illustrated. This graphics processor includes multiple sets of execution resources 356A-356D, each set of execution resources including multiple instruction units, register files, GPGPU cores, and load memory units, such as… Figure 2D and Figure 3A As shown, execution resources 356A-356D can operate in harmony with texture units(s) 360A-360D for texture operations, while sharing instruction cache 354 and shared memory 362. In one embodiment, execution resources 356A-356D can share instruction cache 354, shared memory 362, and multiple instances of texture and / or data cache memories 358A-358B. Various components can be connected via... Figure 3A The interconnect structure 327 communicates with the similar interconnect structure 352.

[0088] Those skilled in the art will understand that Figure 1 , 2AThe architectures described in -2D and 3A-3B are descriptive and not limiting within the scope of embodiments of the invention. Therefore, the techniques described herein can be implemented on any properly configured processing unit, including but not limited to one or more mobile application processors, one or more desktop computer or server central processing units (CPUs) (including multi-core CPUs), one or more parallel processing units (such as...) Figure 2A Parallel processing unit 202), and one or more graphics processors or dedicated processing units, without departing from the scope of the embodiments described herein.

[0089] In some embodiments, a parallel processor or GPGPU, as described herein, is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to the host processor / core via a bus or other interconnect, such as a high-speed interconnect like PCIe or NVLink. In other embodiments, the GPU may be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., within the package or chip). Regardless of how the GPU is connected, the processor core may assign work to the GPU in the form of a sequence of commands / instructions contained in a job descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0090] Technologies for GPU-to-host processor interconnects

[0091] Figure 4A An exemplary architecture is shown in which multiple GPUs 410-413 are communicatively coupled to multiple multi-core processors 405-406 via high-speed links 440-443 (e.g., bus, point-to-point interconnect, etc.). In one embodiment, the high-speed links 440-443 support communication throughput of 4GB / s, 30GB / s, 80GB / s, or higher, depending on the implementation. Various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. However, the basic principles of the invention are not limited to any particular communication protocol or throughput.

[0092] Additionally, in one embodiment, two or more of GPUs 410-413 are interconnected via high-speed links 444-445, which may be implemented using the same or different protocols / links as those used for high-speed links 440-443. Similarly, two or more of multi-core processors 405-406 may be connected via high-speed link 433, which may be a symmetric multiprocessor (SMP) bus operating at 20GB / s, 30GB / s, 120GB / s, or higher. Alternatively, Figure 4A All communication between the various system components shown can be accomplished using the same protocol / link (e.g., via a common interconnect structure). However, as mentioned, the basic principles of the invention are not limited to any particular type of interconnect technology.

[0093] In one embodiment, each multi-core processor 405-406 is communicatively coupled to processor memories 401-402 via memory interconnects 430-431, and each GPU 410-413 is communicatively coupled to GPU memories 420-423 via GPU memory interconnects 450-453. Memory interconnects 430-431 and 450-453 may utilize the same or different memory access technologies. By way of example and not limitation, processor memories 401-402 and GPU memories 420-423 may be volatile memories, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high-bandwidth memory (HBM), and / or may be non-volatile memories, such as 3D XPoint or Nano-RAM. In one embodiment, a portion of the memory may be volatile memory and another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0094] As described below, although the various processors 405-406 and GPUs 410-413 can be physically coupled to specific memories 401-402 and 420-423 respectively, a unified memory architecture can be implemented, in which the same virtual system address space (also known as the “effective address” space) is distributed across all the various physical memories. For example, each of the processor memories 401-402 can include 64GB of system memory address space, and each of the GPU memories 420-423 can include 32GB of system memory address space (resulting in a total of 256GB of addressable memory in this example).

[0095] Figure 4BAdditional details of the interconnection between a multi-core processor 407 and a graphics acceleration module 446 according to one embodiment are shown. The graphics acceleration module 446 may include one or more GPU chips integrated on a line card coupled to the processor 407 via a high-speed link 440. Alternatively, the graphics acceleration module 446 may be integrated on the same package or chip as the processor 407.

[0096] The processor 407 shown includes multiple cores 460A-460D, each having translational backstops 461A-461D and one or more caches 462A-462D. The cores may include various other components for executing instructions and processing data (e.g., instruction fetch units, branch prediction units, decoders, execution units, reordering buffers, etc.), which are not shown to avoid obscuring the basic principles of the invention. Caches 462A-462D may include Level 1 (L1) and Level 2 (L2) caches. Additionally, one or more shared caches 426 may be included in the cache hierarchy and shared by the set of cores 460A-460D. For example, one embodiment of the processor 407 includes 24 cores, each having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one of the L2 and L3 caches is shared by two adjacent cores. The processor 407 and graphics accelerator integrated module 446 are connected to the system memory 441, which may include processor memories 401-402.

[0097] Data and instructions stored in various caches 462A-462D, 456 and system memory 441 are maintained in consistency via inter-core communication through a coherence bus 464. For example, each cache may have associated cache coherence logic / circuit to communicate via the coherence bus 464 in response to a detected read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented via the coherence bus 464 to snoop on cache accesses. Cache snooping / coherence techniques are well understood by those skilled in the art and will not be described in detail herein to avoid obscuring the basic principles of the invention.

[0098] In one embodiment, proxy circuitry 425 communicatively couples graphics acceleration module 446 to coherence bus 464, thereby allowing graphics acceleration module 446 to participate in cache coherence protocols as a peer of the core. Specifically, interface 435 provides connectivity to proxy circuitry 425 via high-speed link 440 (e.g., PCIe bus, NVLink, etc.), and interface 437 connects graphics acceleration module 446 to high-speed link 440.

[0099] In one implementation, the accelerator integrated circuit 436 provides cache management, memory access, context management, and interrupt management services for multiple graphics processing engines 431, 432, and N of the graphics acceleration module 446. Each of the graphics processing engines 431, 432, and N may include a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 431, 432, and N may include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and bit-block transfer engines. In other words, the graphics acceleration module may be a GPU with multiple graphics processing engines 431-432, and N, or the graphics processing engines 431-432, and N may be separate GPUs integrated in a common package, line card, or chip.

[0100] In one embodiment, accelerator integrated circuit 436 includes a memory management unit (MMU) 439 for performing various memory management functions such as virtual-to-physical memory translation (also known as effective-to-real memory translation) and memory access protocols for accessing system memory 441. MMU 439 may also include a translation back buffer (TLB) (not shown) for caching virtual / effective-to-physical / real address translations. In one implementation, cache 438 stores commands and data for efficient access by graphics processing engines 431-432, N. In one embodiment, data stored in cache 438 and graphics memories 433-434, N is kept consistent with core caches 462A-462D, 456 and system memory 411. As mentioned, this can be accomplished via proxy circuit 425, which represents cache 438 and memories 433-434, N in participating in cache coherency mechanisms (e.g., sending updates to cache 438 related to modifications / accesses to cache lines on processor caches 462A-462D, 456 and receiving updates from cache 438).

[0101] A set of registers 445 stores context data for threads executed by graphics processing engines 431-432, N, and context management circuitry 448 manages the thread context. For example, context management circuitry 448 can perform save and restore operations to save and restore the context of various threads during context switching (e.g., where a first thread is saved and a second thread is saved so that the second thread can be executed by the graphics processing engine). For example, during a context switch, context management circuitry 448 can store the current register value to a designated area in memory (e.g., identified by a context pointer). It can then restore the register value upon returning to that context. In one embodiment, interrupt management circuitry 447 receives and processes interrupts received from system devices.

[0102] In one implementation, the MMU 439 translates the virtual / effective address from the graphics processing engine 431 into a real / physical address in system memory 411. One embodiment of the accelerator integrated circuit 436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 446 and / or other accelerator devices. The graphics accelerator module 446 may be dedicated to a single application executing on processor 407, or it may be shared among multiple applications. In one embodiment, a virtualized graphics execution environment is presented, where the resources of graphics processing engines 431-432, N are shared with multiple applications or virtual machines (VMs). Resources may be subdivided into "slices," which are allocated to different VMs and / or applications based on processing requirements and priorities associated with the VMs and / or applications.

[0103] Therefore, the accelerator integrated circuit acts as a bridge to the system of the graphics acceleration module 446, and provides address translation and system memory caching services. Additionally, the accelerator integrated circuit 436 can provide virtualization facilities for the host processor to manage the virtualization of the graphics processing engine, interrupts, and memory management.

[0104] Because the hardware resources of graphics processing engines 431-432, N are explicitly mapped to the actual address space seen by the host processor 407, any host processor can directly address these resources using valid address values. In one embodiment, one function of the accelerator integrated circuit 436 is the physical separation of graphics processing engines 431-432, N, so that they appear as independent units to the system.

[0105] As mentioned, in the illustrated embodiment, one or more graphics memories 433-434, M are coupled to each of the graphics processing engines 431-432, N, respectively. Graphics memories 433-434, M store instructions and data being processed by each of the graphics processing engines 431-432, N. Graphics memories 433-434, M can be volatile memories, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memories, such as 3D XPoint or Nano-RAM.

[0106] In one embodiment, to reduce data traffic on the high-speed link 440, a biasing technique is used to ensure that the data stored in the graphics memories 433-434, M is the data that will be most frequently used by the graphics processing engines 431-432, N and that the cores 460A-460D preferably do not use (or at least not frequently use). Similarly, the biasing mechanism attempts to keep the data required by the cores (and preferably not the graphics processing engines 431-432, N) within the core caches 462A-462D, 456 and system memory 411.

[0107] Figure 4C Another embodiment in which the accelerator integrated circuit 436 is integrated within the processor 407 is shown. In this embodiment, the graphics processing engines 431-432, N communicate directly with the accelerator integrated circuit 436 via a high-speed link 440 through interfaces 437 and 435 (again, which can utilize any form of bus or interface protocol). The accelerator integrated circuit 436 can perform operations related to... Figure 4B The operations described are the same, but given their close proximity to the coherence bus 462 and caches 462A-462D, 426, they may be performed with higher throughput.

[0108] One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). The shared programming model may include a programming model controlled by accelerator integrated circuit 436 and a programming model controlled by graphics acceleration module 446.

[0109] In one embodiment of the dedicated process model, graphics processing engines 431-432, N are dedicated to a single application or process within a single operating system. This single application can aggregate requests from other applications to graphics engines 431-432, N, thereby providing virtualization within a VM / partition.

[0110] In a dedicated process programming model, the graphics processing engines 431-432,N can be shared by multiple VM / application partitions. This shared model requires the hypervisor to virtualize the graphics processing engines 431-432,N to allow access by each operating system. For single-partition systems without a hypervisor, the graphics processing engines 431-432,N are owned by the operating system. In both cases, the operating system can virtualize the graphics processing engines 431-432,N to provide access to each process or application.

[0111] For a shared programming model, the graphics acceleration module 446 or the separate graphics processing engines 431-432, N use a process handle to select a process element. In one embodiment, the process element is stored in system memory 411 and can be addressed using the effective address to actual address translation techniques described herein. The process handle may be an implementation-specific value provided to the host process when registering its context with the graphics processing engines 431-432, N (i.e., invoking system software to add a process element to the process element list). The lower 16 bits of the process handle may be the offset of the process element within the process element list.

[0112] Figure 4D An example accelerator integration slice 490 is shown. As used herein, a “slice” includes a designated portion of the processing resources of the accelerator integrated circuit 436. The application-effective address space 482 within system memory 411 stores process elements 483. In one embodiment, process element 483 is stored in response to a GPU call 481 from an application 480 executing on processor 407. Process element 483 contains the process state for the corresponding application 480. The job descriptor (WD) 484 contained in process element 483 may be a single job requested by the application, or it may contain a pointer to a job queue. In the latter case, WD 484 is a pointer to a job request queue in the application's address space 482.

[0113] The graphics acceleration module 446 and / or separate graphics processing engines 431-432, N can be shared by all or a subset of processes in the system. Embodiments of the invention include infrastructure for establishing process states and sending WD484 to the graphics acceleration module 446 to initiate work in a virtualized environment.

[0114] In one implementation, the dedicated process programming model is implementation-specific. In this model, a single process owns either the graphics acceleration module 446 or a separate graphics processing engine 431. Because the graphics acceleration module 446 is owned by a single process, the hypervisor initializes the accelerator integrated circuit 436 for the owned partition, and the operating system initializes the accelerator integrated circuit 436 for the owning process when the graphics acceleration module 446 is assigned.

[0115] In operation, the WD acquisition unit 491 in the accelerator integrated slice 490 acquires the next WD 484, which includes an instruction for a task to be performed by one of the graphics processing engines in the graphics acceleration module 446. Data from the WD 484 can be stored in register 445 and used by the MMU 439, interrupt management circuitry 447, and / or context management circuitry 448, as shown. For example, one embodiment of the MMU 439 includes a segment / page walk circuitry for accessing segment / page tables 486 within the OS virtual address space 485. The interrupt management circuitry 447 can handle interrupt events 492 received from the graphics acceleration module 446. When performing graphics operations, the effective address 493 generated by the graphics processing engines 431-432,N is translated into an actual address by the MMU 439.

[0116] In one embodiment, the same set of registers 445 is copied for each graphics processing engine 431-432, N, and / or graphics acceleration module 446, and this same set of registers 445 can be initialized by a hypervisor or operating system. Each of these copied registers can be included in the accelerator integration slice 490. Table 1 shows example registers that can be initialized by a hypervisor.

[0117] Table 1 - Registers initialized by the supervisor

[0118]

[0119] Table 2 shows example registers that can be initialized by the operating system.

[0120] Table 2 - Registers initialized by the operating system

[0121]

[0122] In one embodiment, each WD 484 is specific to a particular graphics acceleration module 446 and / or graphics processing engine 431-432, N. It contains all the information required for the graphics processing engine 431-432, N to do its work, or it may be a pointer to a memory location of a command queue that has been set up to perform the work.

[0123] Figure 4E Additional details of one embodiment of the shared model are shown. This embodiment includes a hypervisor physical address space 498 in which a list of process elements 499 is stored. The hypervisor physical address space 498 is accessible via a hypervisor 496, which is used for virtualization of the graphics acceleration module engine of operating system 495.

[0124] The shared programming model allows all or a subset of processes from all or a subset of partitions in the system to use the graphics acceleration module 446. There are two programming models in which the graphics acceleration module 446 is shared by multiple processes and partitions: time-slice sharing and graphics-oriented sharing.

[0125] In this model, the hypervisor 496 owns the graphics acceleration module 446 and makes its functionality available to all operating systems 495. To enable the graphics acceleration module 446 to support virtualization performed by the hypervisor 496, the graphics acceleration module 446 may comply with the following requirements: 1) Application job requests must be autonomous (i.e., no state maintenance is required between jobs), or the graphics acceleration module 446 must provide context saving and restoration mechanisms. 2) The graphics acceleration module 446 guarantees completion of application job requests within a specified timeframe, including any transition failures, or the graphics acceleration module 446 provides the ability to preemptively process jobs. 3) When operating in a directed shared programming model, fairness of the graphics acceleration module 446 must be guaranteed between processes.

[0126] In one embodiment, for the shared model, application 480 is required to make an operating system call 495 using the graphics acceleration module 446 type, working descriptor (WD), authority mask register (AMR) value, and context save / restore region pointer (CSRP). The graphics acceleration module 446 type describes the target acceleration function for the system call. The graphics acceleration module 446 type can be a system-specific value. The WD is formatted specifically for the graphics acceleration module 446 and can take the form of a graphics acceleration module 446 command, a valid address pointer to a user-defined structure, a valid address pointer to a command queue, or any other data structure describing the work to be performed by the graphics acceleration module 446. In one embodiment, the AMR value is the AMR state for the current process. The value passed to the operating system is similar to that set by the application. If the implementation of the accelerator integrated circuit 436 and the graphics acceleration module 446 does not support the User Authority Mask Override Register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. Before placing the AMR in process element 483, hypervisor 496 may optionally apply the Current Privilege Mask Overwrite Register (AMOR) value. In one embodiment, CSRP is one of the registers 445 that contains the effective address of a region in the applied address space 482 for use by enabling graphics acceleration module 446 to save and restore context state. This pointer is optional if saving state between jobs or when a job is preempted is not required. The context save / restore region may be pinned system memory.

[0127] Upon receiving a system call, the operating system 495 can verify that application 480 has been registered and granted permission to use the graphics acceleration module 446. The operating system 495 then uses the information shown in Table 3 to invoke the hypervisor 496.

[0128] Table 3 - Parameters for OS to Call the Management Program

[0129]

[0130] Upon receiving a hypervisor call, hypervisor 496 verifies that operating system 495 has been registered and granted permission to use graphics acceleration module 446. Hypervisor 496 then places process element 483 into a linked list of process elements corresponding to the graphics acceleration module 446 type. Process elements may include the information shown in Table 4.

[0131] Table 4 - Process Element Information

[0132]

[0133] In one embodiment, the hypervisor initializes multiple accelerator integration slice 490 registers 445.

[0134] like Figure 4F As shown, one embodiment of the invention employs a unified memory addressable via a shared virtual memory address space for accessing physical processor memories 401-402 and GPU memories 420-423. In this implementation, operations performed on GPUs 410-413 utilize the same virtual / effective memory address space to access processor memories 401-402, and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 401, a second portion to second processor memory 402, a third portion to GPU memory 420, and so on. The entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memories 401-402 and GPU memories 420-423, allowing any processor or GPU to access that memory using virtual addresses mapped to any physical memory.

[0135] In one embodiment, the bias / coherence management circuitry 494A-494E within one or more of the MMUs 439A-439E ensures cache coherence between the host processor (e.g., 405) and the cache of the GPUs 410-413, and implements biasing techniques that indicate the physical memory where certain types of data should be stored. While in Figure 4FSeveral instances of bias / coherence management circuitry 494A-494E are shown, but the bias / coherence circuitry can be implemented within the MMU of one or more host processors 405 and / or within the accelerator integrated circuit 436.

[0136] One embodiment allows GPU-attached memories 420-423 to be mapped as a portion of system memory and accessed using shared virtual memory (SVM) technology without suffering the typical performance drawbacks associated with system-wide cache coherence. The ability to access GPU-attached memories 420-423 as system memory without the heavy overhead of cache coherence provides a favorable operating environment for GPU offloading. This arrangement allows host processor 405 software to set operands and access computation results without the overhead of traditional I / O direct memory access (DMA) data copying. Such traditional copying involves driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are inefficient compared to simple memory access. Meanwhile, the ability to access GPU-attached memories 420-423 without cache coherence overhead can be critical for the execution time of offloading computations. For example, in scenarios with heavy streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPUs 410-413. The efficiency of operand setting, the efficiency of result access, and the efficiency of GPU computation all play a role in determining the effectiveness of GPU offloading.

[0137] In one implementation, the choice between GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table can be used, which may be a 1- or 2-bit page-granular structure per GPU-attached memory page (i.e., controlled at the memory page level). The bias table can be implemented within the stolen memory range of one or more GPU-attached memories 420-423, with or without a bias cache in GPUs 410-413 (e.g., caching frequently / recently used entries of the bias table). Alternatively, the entire bias table can be maintained within the GPU.

[0138] In one implementation, the bias table entries associated with each access to GPU-attached memory 420-423 are accessed prior to the actual access to GPU memory, resulting in the following operations: First, local requests from GPUs 410-413 that have found their pages in the GPU bias are forwarded directly to the corresponding GPU memory 420-423. (E.g., via a high-speed link as discussed above) Local requests from GPUs that have found their pages in the host bias are forwarded to processor 405. In one embodiment, a request from processor 405 that has found the requested page in the host processor bias completes like a normal memory read. Alternatively, requests involving GPU bias pages can be forwarded to GPUs 410-413. If the GPU is not currently using the page, the GPU can then translate the page into a host processor bias.

[0139] The page bias state can be changed through software-based mechanisms, hardware-assisted software mechanisms, or, for a limited set of cases, purely hardware-based mechanisms.

[0140] One mechanism for changing the bias state involves an API call (such as OpenCL), which in turn invokes the GPU's device driver. The device driver then sends a message to the GPU instructing it to change the bias state (or enqueues a command descriptor). For certain transitions, a cache dump clearing operation is performed on the host machine. This cache dump clearing operation is required for transitions from host processor 405 bias to GPU bias, but not for the reverse transition.

[0141] In one embodiment, cache coherence is maintained by temporarily rendering GPU bias pages that the host processor 405 cannot cache. To access these pages, the processor 405 may request access from the GPU 410, which may or may not grant access immediately, depending on the implementation. Therefore, to reduce communication between the processor 405 and the GPU 410, it is advantageous to ensure that the GPU bias pages are those required by the GPU but not by the host processor 405, and vice versa.

[0142] Graphics processing pipeline

[0143] Figure 5 A graphics processing pipeline 500 according to an embodiment is illustrated. In one embodiment, a graphics processor may implement the illustrated graphics processing pipeline 500. The graphics processor may be included in a parallel processing subsystem (such as...) as described herein. Figure 2A Within the parallel processor 200, which in one embodiment is Figure 1Variations of the (multiple) parallel processors 112. Various parallel processing systems can be implemented via parallel processing units (e.g., as described herein) Figure 2A One or more instances of parallel processing units 202 are used to implement the graphics processing pipeline 500. For example, shader units (e.g., Figure 2C or Figure 2D The graphics multiprocessor 234 can be configured to perform the functions of one or more of the vertex processing unit 504, tessellation control processing unit 508, tessellation evaluation processing unit 512, geometry processing unit 516, and fragment / pixel processing unit 524. The functions of the data assembler 502, primitive assemblers 506, 514, 518, tessellation unit 510, rasterizer 522, and raster operation unit 526 can also be handled by a processing cluster (e.g., Figure 2C Other processing engines and corresponding partition units (e.g., within the processing cluster 214) Figure 2A The graphics processing pipeline 500 can be implemented using partition units 220A-220N. The graphics processing pipeline 500 can also be implemented using dedicated processing units for one or more functions. In one embodiment, one or more portions of the graphics processing pipeline 500 can be executed by parallel processing logic within a general-purpose processor (e.g., CPU). In one embodiment, one or more portions of the graphics processing pipeline 500 can access on-chip memory (e.g., memory interface 528) via memory interface 528. Figure 2A The parallel processor memory 222 in the memory interface 528 may be a parallel processor memory 222 in the memory interface 528. Figure 2A An example of memory interface 218.

[0144] In one embodiment, the data assembler 502 is a processing unit that collects vertex data of surfaces and primitives. The data assembler 502 then outputs vertex data, including vertex attributes, to the vertex processing unit 504. The vertex processing unit 504 is a programmable execution unit that executes a vertex shader program to light and transform the vertex data as specified by the vertex shader program. The vertex processing unit 504 reads data stored in a cache, local, or system memory for use in processing the vertex data and can be programmed to transform the vertex data from an object-based coordinate representation to world space coordinate space or a normalized device coordinate space.

[0145] The first instance of the primitive assembler 506 receives vertex attributes from the vertex processing unit 504. The primitive assembler 506 reads the stored vertex attributes as needed and constructs graphical primitives for processing by the tessellation control processing unit 508. Graphical primitives include elements such as triangles, line segments, points, patches, etc., supported by various graphics processing application programming interfaces (APIs).

[0146] The tessellation control processing unit 508 treats input vertices as control points for a geometric patch. These control points are transformed from an input representation of the patch (e.g., the patch's basis) into a representation suitable for use in a surface evaluation performed by the tessellation evaluation processing unit 512. The tessellation control processing unit 508 can also calculate a tessellation factor for the edges of the geometric patch. The tessellation factor is applied to a single edge and quantifies the view-dependent level of detail associated with that edge. The tessellation unit 510 is configured to receive the tessellation factor for the edges of the patch and subdivide the patch into multiple geometric primitives, such as lines, triangles, or quadrilaterals, which are then transmitted to the tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on the parameterized coordinates of the subdivided patch to generate vertex attributes and a surface representation for each vertex associated with the geometric primitives.

[0147] A second instance of the primitive assembler 514 receives vertex attributes from the tessellation evaluation processing unit 512, reads stored vertex attributes as needed, and constructs graphical primitives for processing by the geometry processing unit 516. The geometry processing unit 516 is a programmable execution unit that executes a geometry shader program to transform the graphical primitives received from the primitive assembler 514 as specified by the geometry shader program. In one embodiment, the geometry processing unit 516 is programmed to subdivide the graphical primitives into one or more new graphical primitives and calculate parameters for rasterizing the new graphical primitives.

[0148] In some embodiments, the geometry processing unit 516 can add or delete elements in the geometry flow. The geometry processing unit 516 outputs parameters and vertices specifying new graphic primitives to the primitive assembler 518. The primitive assembler 518 receives the parameters and vertices from the geometry processing unit 516 and constructs graphic primitives for processing by the viewport scaling, cull, and clip unit 520. The geometry processing unit 516 reads data stored in the parallel processor memory or system memory for use in processing geometry data. The viewport scaling, cull, and clip unit 520 performs clipping, cull, and viewport scaling and outputs the processed graphic primitives to the rasterizer 522.

[0149] Rasterizer 522 can perform depth picking and other depth-based optimizations. Rasterizer 522 also performs scan transformations on new graphic primitives to generate fragments and outputs those fragments and associated overlay data to fragment / pixel processing unit 524. Fragment / pixel processing unit 524 is a programmable execution unit configured to execute fragment shader programs or pixel shader programs. Fragment / pixel processing unit 524 transforms fragments or pixels received from rasterizer 522 as specified by the fragment or pixel shader program. For example, fragment / pixel processing unit 524 can be programmed to perform operations including but not limited to texture mapping, shading, blending, texture correction, and perspective correction to produce shaded fragments or pixels output to raster operation unit 526. Fragment / pixel processing unit 524 can read data stored in parallel processor memory or system memory for use when processing fragment data. Fragment or pixel shader programs can be configured to shade at sample, pixel, tile, or other granularities according to a sampling rate configured for the processing unit.

[0150] The raster operation unit 526 is a processing unit that performs raster operations, including but not limited to stencil printing, z-checking, and blending, and outputs pixel data as processed graphic data for storage in a graphics memory (e.g., as shown in the image). Figure 2A Parallel processor memory 222 in the memory, and / or such as Figure 1 The data is stored in system memory 104 for display on one or more display devices 110 or for further processing by one or more processors 102 or one of parallel processors 112. In some embodiments, raster operation unit 526 is configured to compress z-or color data written to memory and decompress z-or color data read from memory.

[0151] Machine Learning Overview

[0152] Machine learning algorithms are algorithms that can learn from a set of data. Implementations of machine learning algorithms can be designed to model high-level abstractions within a dataset. For example, image recognition algorithms can be used to determine which of several categories a given input belongs to; regression algorithms can output numerical values ​​given input; and pattern recognition algorithms can be used to generate translated text or perform text-to-speech and / or speech recognition.

[0153] A demonstrative type of machine learning algorithm is the neural network. Many types of neural networks exist; a simple type is the feedforward network. A feedforward network can be implemented as a non-cyclic graph, where nodes are arranged in layers. Typically, a feedforward network topology includes an input layer and an output layer, separated by at least one hidden layer. The hidden layer transforms the input received by the input layer into a representation useful for generating the output in the output layer. Network nodes are fully connected to nodes in adjacent layers via edges, but there are no edges between nodes within a single layer. Data received at the nodes in the input layer of the feedforward network is propagated (i.e., “feedforward”) to the nodes in the output layer via activation functions that compute the state of nodes in each consecutive layer of the network based on coefficients (“weights”), each coefficient associated with one of the edges connecting those layers. Depending on the specific model represented by the algorithm being executed, the output from a neural network algorithm can take various forms.

[0154] Before a machine learning algorithm can be used to model a specific problem, it is trained using a training dataset. Training a neural network involves choosing a network topology, using a set of training data representing the problem being modeled by the network, and adjusting the weights until the network model exhibits minimal error across all instances of the training dataset. For example, during supervised learning training for a neural network, the output generated by the network in response to an input representing an instance in the training dataset is compared to the “correct” labeled output for that instance. An error signal representing the difference between the output and the labeled output is calculated, and the weights associated with the connections are adjusted to minimize the error as the error signal is backpropagated through the layers of the network. The network is considered “trained” when the error of each output generated based on instances of the training dataset is minimized.

[0155] The accuracy of a machine learning algorithm can significantly impact the quality of the dataset used to train it. The training process can be computationally intensive and may take a considerable amount of time on a conventional general-purpose processor. Therefore, parallel processing hardware is used to train many types of machine learning algorithms. This is particularly useful for optimizing the training of neural networks, as the computations performed when adjusting the coefficients in the neural network naturally facilitate parallel implementation. Specifically, many machine learning algorithms and software applications have been adapted to use parallel processing hardware within general-purpose graphics processing devices.

[0156] Figure 6This is a generalized diagram of the machine learning software stack 600. The machine learning application 602 can be configured to train a neural network using a training dataset or to implement machine intelligence using a trained deep neural network. The machine learning application 602 may include specialized software that can be used to train the neural network prior to deployment and / or the training and inference capabilities of the neural network. The machine learning application 602 can implement any type of machine intelligence, including but not limited to image recognition, mapping and localization, autonomous navigation, speech synthesis, medical imaging, or language translation.

[0157] Hardware acceleration for machine learning applications 602 can be enabled via the machine learning module 604. The machine learning module 604 provides a library of machine learning primitives. Machine learning primitives are the fundamental operations typically performed by machine learning algorithms. Without the machine learning module 604, developers of machine learning algorithms would be required to create and optimize the main computational logic associated with their algorithms, and then re-optimize that logic when a new parallel processor is developed. Instead, machine learning applications can be configured to use the primitives provided by the machine learning module 604 to perform the necessary computations. Exemplary primitives include tensor convolution, activation functions, and pooling, which are computational operations performed when training convolutional neural networks (CNNs). The machine learning module 604 can also provide primitives to implement basic linear algebra subroutines performed by many machine learning algorithms, such as matrix and vector operations.

[0158] Machine learning module 604 can process input data received from machine learning application 602 and generate appropriate input for compute module 606. Compute module 606 can abstract the basic instructions provided to GPGPU driver 608, enabling machine learning module 604 to utilize hardware acceleration via GPGPU hardware 610 without requiring machine learning module 604 to be very familiar with the architecture of GPGPU hardware 610. Furthermore, compute module 606 enables hardware acceleration for machine learning module 604 across various types and generations of GPGPU hardware 610.

[0159] GPGPU Machine Learning Acceleration

[0160] Figure 7 The illustration depicts a highly parallel general-purpose graphics processing unit (GPGPU) 700 according to an embodiment. In one embodiment, the GPGPU 700 can be configured to be particularly efficient in handling computational workloads associated with training deep neural networks. Additionally, the GPGPU 700 can be directly linked to other instances of GPGPUs to create a multi-GPU cluster, thereby improving the training speed of particularly deep neural networks.

[0161] The GPGPU 700 includes a host interface 702 for enabling connectivity with a host processor. In one embodiment, the host interface 702 is a PCI Express interface. However, the host interface can also be a provider-specific communication interface or communication structure. The GPGPU 700 receives commands from the host processor and uses a global scheduler 704 to distribute the execution threads associated with those commands to a group of compute clusters 706A-706H. The compute clusters 706A-706H share a cache memory 708. The cache memory 708 can act as an advanced cache within the cache memory of the compute clusters 706A-706H.

[0162] The GPGPU 700 includes memories 714A-714B, which are coupled to the computing cluster 706A-H via a set of memory controllers 712A-712B. In various embodiments, memories 714A-714B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM) (including graphics double data rate (GDDR) memory) or 3D stacked memory (including, but not limited to, high bandwidth memory (HBM)).

[0163] In one embodiment, each computing cluster 706A-706H includes a set of graphics multiprocessors, such as Figure 4A The graphics multiprocessor 400 of the computing cluster includes multiple types of integer and floating-point logic units that can perform computational operations at a range of precisions, including precision suitable for machine learning computations. For example, in one embodiment, at least a subset of the floating-point units in each of the computing clusters 706A-706H can be configured to perform 16-bit or 32-bit floating-point operations, while different subsets of the floating-point units can be configured to perform 64-bit floating-point operations.

[0164] Multiple instances of GPGPU 700 can be configured to operate as a computing cluster. The communication mechanisms used by the computing cluster for synchronization and data exchange vary across embodiments. In one embodiment, multiple instances of GPGPU 700 communicate via host interface 702. In one embodiment, GPGPU 700 includes an I / O hub 709 that couples GPGPU 700 to GPU link 710, which enables direct connections to other instances of GPGPU. In one embodiment, GPU link 710 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 700. In one embodiment, GPU link 710 is coupled to a high-speed interconnect to transfer data to and receive data from other GPGPUs or parallel processors. In one embodiment, multiple instances of GPGPU 700 reside in a separate data processing system and communicate via a network device accessible via host interface 702. In one embodiment, GPU link 710 may be configured to enable connections to a host processor, in addition to or as an alternative to host interface 702.

[0165] While the illustrated configuration of the GPGPU 700 can be configured to train neural networks, one embodiment provides an alternative configuration of the GPGPU 700 that can be configured for deployment within a high-performance or low-power inference platform. In the inference configuration, the GPGPU 700 includes fewer compute clusters 706A-706H compared to the training configuration. Additionally, the memory technology associated with the memories 714A-714B may differ between the inference and training configurations. In one embodiment, the inference configuration of the GPGPU 700 may support inference-specific instructions. For example, the inference configuration may provide support for one or more 8-bit integer dot product instructions, which are typically used during inference operations against a deployed neural network.

[0166] Figure 8 The illustration shows a multi-GPU computing system 800 according to an embodiment. The multi-GPU computing system 800 may include a processor 802 coupled to a plurality of GPGPUs 806A-806D via a host interface switch 804. In one embodiment, the host interface switch 804 is a PCI express switch device that couples the processor 802 to a PCI express bus through which the processor 802 can communicate with the group of GPGPUs 806A-806D. Each of the plurality of GPGPUs 806A-806D may be... Figure 7Examples of GPGPU 700. GPGPU 806A-806D can be interconnected via a set of high-speed point-to-point GPU-to-GPU links 816. High-speed GPU-to-GPU links can be via dedicated GPU links (such as... Figure 7 The P2P GPU link 816 is connected to each of the GPGPUs 806A-806D. The P2P GPU link 816 enables direct communication between each of the GPGPUs 806A-806D without requiring communication via the host interface bus to which the processor 802 is connected. In cases where GPU-to-GPU traffic involves the P2P GPU link, the host interface bus can still be used for system memory access or, for example, communication with other instances of the multi-GPU computing system 800 via one or more network devices. While in the illustrated embodiment the GPGPUs 806A-806D are connected to the processor 802 via the host interface switch 804, in one embodiment the processor 802 includes direct support for the P2P GPU link 816 and can be directly connected to the GPGPUs 806A-806D.

[0167] Machine learning neural network implementation

[0168] The computational architectures provided by the embodiments described herein can be configured to perform parallel processing of a type particularly well-suited for training and deploying neural networks for machine learning. Neural networks can be generalized as networks with graph-like relationships. As is well known in the art, there are various types of neural network implementations used in machine learning. An exemplary type of neural network is the feedforward network as previously described.

[0169] The second exemplary type of neural network is the Convolutional Neural Network (CNN). CNNs are specialized feedforward neural networks designed for processing data with known grid-like topologies, such as image data. Therefore, CNNs are commonly used in computational vision and image recognition applications, but they can also be used in other types of pattern recognition, such as speech and language processing. Nodes in the input layer of a CNN are organized into a set of "filters" (feature detectors excited by receptive fields found in the retina), and the output of each set of filters is propagated to nodes in successive layers of the network. The computation for a CNN involves applying convolutional mathematics to each filter to produce its output. Convolution is a specialized kind of mathematical operation performed by two functions to produce a third function, which is a modified version of one of the two original functions. In convolutional network terminology, the first function of the convolution can be called the input, and the second function can be called the convolution kernel. The output can be called a feature map. For example, the input to a convolutional layer can be a multidimensional array of data that defines various color components of the input image. The convolution kernel can be a multidimensional array of parameters, which are adapted through a training process for the neural network.

[0170] Recurrent Neural Networks (RNNs) are a class of feedforward neural networks that include feedback connections between layers. RNNs enable modeling of sequential data by sharing parameter data across different parts of the neural network. The architecture of an RNN includes recurrent loops. A loop represents the effect of a variable's current value on its own value at future times, because at least a portion of the output data from the RNN is used as feedback to process subsequent inputs in the sequence. This feature makes RNNs particularly useful for language processing due to the variable nature that language data can include.

[0171] The following diagrams illustrate exemplary feedforward, CNN, and RNN networks, and describe the general process for training and deploying each of those types of networks, respectively. It will be understood that these descriptions are illustrative and non-limiting with respect to any particular embodiment described herein, and that the concepts illustrated can generally be applied to deep neural networks and machine learning techniques.

[0172] The exemplary neural network described above can be used to perform deep learning. Deep learning is machine learning performed using deep neural networks. In contrast to shallow neural networks that contain only a single hidden layer, the deep neural networks used in deep learning are artificial neural networks composed of multiple hidden layers. Training deeper neural networks is generally more computationally intensive. However, the additional hidden layers of the network enable multi-step pattern recognition, which results in reduced output error compared to shallow machine learning techniques.

[0173] Deep neural networks used in deep learning typically include a front-end network that performs feature recognition coupled to a back-end network representing a mathematical model. This mathematical model can perform operations (e.g., object classification, speech recognition, etc.) based on the feature representations provided to it. Deep learning enables machine learning to be performed without requiring hand-crafted feature engineering on the model. Instead, deep neural networks can learn features based on statistical structure or correlations within the input data. The learned features can be fed to a mathematical model, which can map the detected features to its output. The mathematical models used by the network are generally specialized for the specific task to be performed, and different models will be used to perform different tasks.

[0174] Once a neural network is structured, a learning model can be applied to it to train it to perform a specific task. The learning model describes how to adjust the weights within the model to reduce the network's output error. Backpropagation of error is a common method used to train neural networks. An input vector is presented to the network for processing. The network's output is compared to the expected output using a loss function, and an error value is calculated for each neuron in the output layer. The error values ​​are then backpropagated until each neuron has an associated error value that roughly represents its contribution to the original output. The network can then learn from those errors using algorithms such as stochastic gradient descent to update the neural network's weights.

[0175] Figures 9A-9B The diagram illustrates a demonstration convolutional neural network. Figure 9A The diagram illustrates the various layers within a CNN. (Example:) Figure 9A As shown, the exemplary CNN used for modeling image processing can receive input 902, which describes the red, green, and blue (RGB) components of an input image. Input 902 can be processed by multiple convolutional layers (e.g., convolutional layer 904, convolutional layer 906). The output from the multiple convolutional layers can optionally be processed by a set of fully connected layers 908. Neurons in a fully connected layer have full connections to all activation functions in the previous layer, as previously described for feedforward networks. The output from the fully connected layer 908 can be used to generate an output from the network. Matrix multiplication can be used instead of convolution to compute activations within the fully connected layer 908. Not all CNN implementations use fully connected layers 908. For example, in some implementations, convolutional layers 906 can generate the CNN output.

[0176] Convolutional layers are sparsely connected, unlike the traditional neural network configuration found in fully connected layers (908). Traditional neural network layers are fully connected, so that each output unit interacts with each input unit. However, convolutional layers are sparsely connected because the output of a convolution of a domain (rather than the corresponding state value of each node in the domain) is fed to nodes in subsequent layers, as illustrated. The kernels associated with the convolutional layers perform convolution operations, the output of which is sent to the next layer. Dimensionality reduction performed within convolutional layers is one aspect that enables CNNs to scale to handle large images.

[0177] Figure 9B The diagram illustrates a demonstration computation phase within a convolutional layer of a CNN. The input 912 to the CNN's convolutional layer can be processed in three stages within convolutional layer 914. These three stages may include a convolutional stage 916, a detector stage 918, and a pooling stage 920. Convolutional layer 914 can then output the data to successive convolutional layers. The final convolutional layer of the network can generate output feature map data or provide input to fully connected layers, for example, to generate classification values ​​for the input to the CNN.

[0178] Several convolutions are performed in parallel within convolution stage 916 to produce a set of linear activations. Convolution stage 916 may include affine transformations, which are any transformations that can be specified as a linear transformation plus translation. Affine transformations include rotation, translation, scaling, and combinations of these transformations. The convolution stage computes the output of a function (e.g., a neuron) connected to a specific region in the input, which can be determined as a local region associated with the neuron. The neuron computes the dot product between the neuron's weights and the region in the local input to which the neuron is connected. The output from convolution stage 916 defines a set of linear activations processed by successive stages of convolutional layer 914.

[0179] Linear activations can be processed by detector stage 918. In detector stage 918, each linear activation is processed by a nonlinear activation function. The nonlinear activation function adds nonlinearity to the overall network without affecting the receptive field of the convolutional layers. Several types of nonlinear activation functions can be used. One specific type is the Modified Linear Unit (ReLU), whose usage is defined as... f(x) =max( 0 , x The activation function is used to threshold the activation at zero.

[0180] Pooling stage 920 uses a pooling function that replaces the output of convolutional layer 906 with a generalized statistic of the nearby output. The pooling function can be used to introduce translation invariance into the neural network, such that small translations of the input do not change the pooling output. Local translation invariance can be useful in scenarios where the presence of a feature in the input data is more important than the precise location of that feature. Various types of pooling functions can be used during pooling stage 920, including max pooling, average pooling, and l2-norm pooling. Additionally, some CNN implementations do not include a pooling stage. Instead, such implementations substitute and add convolutional stages with increased strides relative to the previous convolutional stages.

[0181] The output from convolutional layer 914 can then be processed by the next layer 922. The next layer 922 can be either an additional convolutional layer or a fully connected layer 908. For example, Figure 9A The first convolutional layer 904 can output to the second convolutional layer 906, and the second convolutional layer can output to the first layer in the fully connected layer 908.

[0182] Figure 10The diagram illustrates a demonstrative recurrent neural network 1000. In a recurrent neural network (RNN), the network's previous state influences the output of the network's current state. RNNs can be constructed in various ways using a variety of functions. The use of RNNs generally revolves around using mathematical models to predict the future based on previous input sequences. For example, an RNN can be used to perform statistical language modeling to predict an upcoming word given a previous sequence of words. The illustrated RNN 1000 can be described as having an input layer 1002 that receives an input vector, a hidden layer 1004 that implements a recursive function, a feedback mechanism 1005 that enables a 'memory' of previous states, and an output layer 1006 that outputs the result. The RNN 1000 operates based on time steps. The feedback mechanism 1005 influences the RNN's state at a given time step based on previous time steps. For a given time step, the state of the hidden layer 1004 is defined by the previous state and the input at the current time step. The initial input (x1) at the first time step can be processed by the hidden layer 1004. The second input (x2) can be processed by hidden layer 1004 using the state information determined during the processing of the initial input (x1). The given state can be computed as... s t = f ( Ux t + Ws t-1 ),in U and W It is a parameter matrix. Function f Generally, it is nonlinear, such as the hyperbolic tangent function (Tanh) or a correction function. f (x) = max( 0 , x A variant of ). However, the specific mathematical function used in hidden layer 1004 can vary depending on the specific implementation details of RNN 1000.

[0183] In addition to the basic CNN and RNN networks described, variations of those networks can be enabled. An example RNN variant is the Long Short-Term Memory (LSTM) RNN. LSTM RNNs are capable of learning long-term dependencies that may be necessary for processing longer language sequences. A variant of CNN is the Convolutional Deep Belief Network (DBN), which has a similar structure to CNNs and is trained in a similar manner to DBNs. A DBN is a generative neural network consisting of multiple layers of random (random) variables. A DBN can be trained layer by layer using greedy unsupervised learning. The learned weights of the DBN can then be used to provide a pre-trained neural network by determining an optimal set of initial weights for the neural network.

[0184] Figure 11 The training and deployment of a deep neural network are illustrated. Once a given network has been structured for a task, it is trained using a training dataset 1102. Various training block frameworks 1104 have been developed to enable hardware acceleration of the training process. For example, Figure 6 The machine learning block 604 can be configured as a training block 604. The training block 604 can be hooked to an untrained neural network 1106 and enables the use of the parallel processing resources described herein to train the untrained neural network to generate a trained neural network 1108.

[0185] To begin the training process, initial weights can be selected randomly or by pre-training using a deep belief network. Training loops are then performed in a supervised or unsupervised manner.

[0186] Supervised learning is a learning method in which training is performed as a mediating operation, such as when the training dataset 1102 includes the input paired with the expected output, or when the training dataset includes inputs with known outputs and the outputs of the neural network are manually graded. The network processes the input and compares the resulting output with a set of expected or desired outputs. The error is then backpropagated through the system. The training block 1104 can be tuned to adjust the weights controlling the untrained neural network 1106. The training block 1104 can provide tools to monitor how well the untrained neural network 1106 converges toward a model suitable for generating correct answers based on known input data. The training process occurs repeatedly as the network weights are adjusted to improve the outputs generated by the neural network. The training process can continue until the neural network reaches the statistically expected accuracy associated with the trained neural network 1108. The trained neural network 1108 can then be deployed to implement any number of machine learning operations.

[0187] Unsupervised learning is a learning method in which a network attempts to train itself using unlabeled data. Therefore, for unsupervised learning, the training dataset 1102 will include input data without any associated output data. The untrained neural network 1106 can learn groupings within the unlabeled inputs and can determine how individual inputs relate to the overall dataset. Unsupervised training can be used to generate self-organizing maps, which are a type of trained neural network 1107 capable of performing operations useful in reducing data dimensionality. Unsupervised training can also be used to perform anomaly detection, which allows identifying data points in the input dataset that deviate from normal data patterns.

[0188] Variations in supervised and unsupervised training can also be employed. Semi-supervised learning is a technique in which the training dataset 1102 comprises a mixture of labeled and unlabeled data with the same distribution. Incremental learning is a variant of supervised learning in which the input data is continuously used to further train the model. Incremental learning enables the trained neural network 1108 to adapt to new data 1112 without forgetting the knowledge instilled within the network during initial training.

[0189] Whether supervised or unsupervised, training very deep neural networks can be computationally too intensive for a single computing node. A distributed network of computing nodes can be used instead of a single node to accelerate the training process.

[0190] Figure 12 This is a block diagram illustrating distributed learning. Distributed learning uses multiple distributed computing nodes to train models for supervised or unsupervised training of neural networks. Each distributed computing node can include one or more host processors and one or more general-purpose processing nodes, such as... Figure 7 The system features a highly parallel general-purpose graphics processing unit 700. As illustrated, distributed learning can perform model parallelism 1202, data parallelism 1204, or a combination of model and data parallelism 1204.

[0191] In model parallelism 1202, different computing nodes in a distributed system can perform training computations on different parts of a single network. For example, each layer of a neural network can be trained by different processing nodes in a distributed system. Benefits of model parallelism include the ability to scale to particularly large models. Splitting the computations associated with different layers of a neural network makes it possible to train very large neural networks where the weights of all layers are not packed into the memory of a single computing node. In some instances, model parallelism can be particularly useful in performing unsupervised training of large neural networks.

[0192] In data parallelism 1204, different nodes in a distributed network have complete instances of the model, and each node receives a different portion of the data. The results from the different nodes are then combined. While different approaches to data parallelism are possible, all data-parallel training methods require techniques for combining results and synchronizing model parameters across each node. Exemplary methods for combining data include parameter averaging and update-based data parallelism. Parameter averaging trains each node on a subset of the training data and sets global parameters (e.g., weights, biases) to the average of the parameters from each node. Parameter averaging uses a central parameter server to maintain the parameter data. Update-based data parallelism is similar to parameter averaging, except that updates to the model are transmitted instead of parameters from nodes to a parameter server. Alternatively, update-based data parallelism can be performed in a distributed manner, where updates are compressed and transmitted between nodes.

[0193] For example, combined model and data parallelism can be implemented in a distributed system where each compute node includes multiple GPUs. Each node can have a complete instance of the model, with a separate GPU within each node used to train different parts of the model.

[0194] Distributed training incurs increased overhead compared to training on a single machine. However, the parallel processors and GPGPUs described in this paper can each implement various techniques for reducing the overhead of distributed training, including techniques for enabling and accelerating high-bandwidth GPU-to-GPU data transfers and remote data synchronization.

[0195] Demonstration of machine learning applications

[0196] Machine learning can be applied to solve a wide range of technical problems, including but not limited to computer vision, autonomous driving and navigation, speech recognition, and language processing. Computer vision has traditionally been one of the most active research areas for machine learning applications. Applications of computer vision range from reproducing human visual abilities (such as face recognition) to creating new categories of visual abilities. For example, a computer vision application can be configured to identify sound waves from vibrations induced in objects visible in a video. Parallel processor-accelerated machine learning enables the training of computer vision applications using significantly larger training datasets than previously feasible, and allows the deployment of inference systems using low-power parallel processors.

[0197] Parallel processor-accelerated machine learning has applications in autonomous driving, including lane and road sign recognition, obstacle avoidance, navigation, and driving control. Accelerated machine learning techniques can be used to train driving models based on datasets that define appropriate responses to specific training inputs. The parallel processors described in this paper enable the rapid training of increasingly sophisticated neural networks for autonomous driving solutions and allow the deployment of low-power inference processors in mobile platforms suitable for integration into autonomous vehicles.

[0198] Parallel processor-accelerated deep neural networks have enabled machine learning methods for Automatic Speech Recognition (ASR). ASR involves creating functions that compute the most probable language sequence given an input speech sequence. Accelerated machine learning using deep neural networks has made it possible to replace Hidden Markov Models (HMMs) and Gaussian Mixture Models (GMMs) previously used for ASR.

[0199] Parallel processor-accelerated machine learning can also be used to accelerate natural language processing. Automatic learning programs can use statistical inference algorithms to generate models robust to erroneous or unfamiliar inputs. Exemplary natural language processor applications include automatic machine translation between human languages.

[0200] Parallel processing platforms for machine learning can be divided into training platforms and deployment platforms. Training platforms are typically highly parallel and include optimizations to accelerate multi-GPU single-node training and multi-node multi-GPU training. Exemplary parallel processors suitable for training include... Figure 7 The highly parallel general-purpose graphics processing unit 700 and Figure 8 The multi-GPU computing system 800. In contrast, deployed machine learning platforms typically include low-power parallel processors suitable for use in products such as cameras, autonomous robots, and autonomous vehicles.

[0201] Figure 13The illustration shows a demonstrative inference system-on-a-chip (SOC) 1300 suitable for performing inference using a trained model. SOC 1300 may integrate processing units including a media processor 1302, a vision processor 1304, a GPGPU 1306, and a multi-core processor 1308. SOC 1300 may additionally include on-chip memory 1305, which enables a shared on-chip data pool accessible by each of the processing units. The processing units can be optimized for low-power operation to enable deployment to a variety of machine learning platforms, including autonomous vehicles and autonomous robots. For example, one implementation of SOC 1300 can be used as part of a main control system for an autonomous vehicle. When SOC 1300 is configured for use in an autonomous vehicle, the SOC is designed and configured to comply with the relevant functional safety standards of the deployment jurisdiction.

[0202] During operation, the media processor 1302 and the vision processor 1304 can work in concert to accelerate computer vision operations. The media processor 1302 enables low-latency decoding of multiple high-resolution (e.g., 4K, 8K) video streams. The decoded video stream can be written to a buffer in on-chip memory 1305. The vision processor 1304 can then parse the decoded video and perform preliminary processing operations on the frames of the decoded video in preparation for processing them using a trained image recognition model. For example, the vision processor 1304 can accelerate convolutional operations for CNNs used to perform image recognition on high-resolution video data, while the back-end model computation is performed by the GPGPU 1306.

[0203] The multi-core processor 1308 may include control logic to assist in the sequencing and synchronization of shared memory operations and data transfers performed by the media processor 1302 and the vision processor 1304. The multi-core processor 1308 may also act as an application processor to execute software applications that can utilize the inference computing power of the GPGPU 1306. For example, at least a portion of navigation and driving logic may be implemented in software executing on the multi-core processor 1308. Such software may directly publish computational workloads to the GPGPU 1306, or may publish computational workloads to the multi-core processor 1308, which may offload at least a portion of those operations to the GPGPU 1306.

[0204] The GPGPU 1306 may include compute clusters, such as low-power configurations of compute clusters 706A-706H within a highly parallel general-purpose graphics processing unit 700. The compute clusters within the GPGPU 1306 may support instructions specifically optimized for performing inference computations on trained neural networks. For example, the GPGPU 1306 may support instructions for performing low-precision computations, such as 8-bit and 4-bit integer vector operations.

[0205] Dedicated hardware for efficient machine learning operations

[0206] The embodiments described herein provide high-level machine learning computation primitives that can be used to abstract many of the low-level computational details of performing machine learning computations. These high-level primitives enable software logic to request high-level machine learning operations while abstracting the low-level implementation details of those operations. For example, and in one embodiment, software logic can request a convolution operation on an image using a given set of filters. A single high-level instruction can be executed, having operands to define the addresses of buffers storing filter and / or kernel data, and the addresses of input and output buffers. The GPGPU can then break down the high-level convolution instruction into multiple sub-operations executed by the GPGPU's low-level computational units. In one embodiment, direct hardware support for one or more subroutines of the Basic Linear Algorithm Subroutine (BLAS) is provided, although embodiments may provide hardware support for other subroutine libraries. Compiler logic and associated runtime libraries can compile source code that utilizes the supported high-level computational subroutines and output the compiled source code (which calls into machine learning macro instruction units).

[0207] Instructions and logic used to perform computational operations for machine learning

[0208] Hardware accelerators for computer vision and machine learning can improve energy efficiency by orders of magnitude for applications such as object, face, and speech recognition. These accelerators use interconnected arrays of processing elements (PEs), where multiply-accumulate circuitry is used to map the dominant performance, area, and energy of key algorithms used in CNN computational operations. For example, some machine learning hardware accelerators use narrow bit-width (16-bit) fixed-point multiply-accumulate data path building blocks to meet tight memory, area, and power budgets for SoCs in low-power or embedded spaces. Better result quality can be achieved for certain datasets and algorithms with higher dynamic range provided by floating-point / computation, while still maintaining the same memory footprint (16-bit operands). Previous hardware solutions designed to accommodate both types of numerical computation employed separate fixed-point and floating-point data paths or PEs, resulting in high area costs for achieving this flexibility. In contrast, the embodiments described herein provide a merged integer / floating-point fused multiply-accumulate and multiply-accumulate data path that leverages existing signed integer multiply-accumulate circuitry to implement floating-point mantissa multiply-accumulate operations. In one embodiment, floating-point support is enabled in the combined floating-point / integer unit without increasing input / output data width or data memory footprint by adding only the circuitry required for alignment / normalization shift and exponentiation units. A single control signal is used to switch between floating-point and integer calculation modes on a per-cycle basis.

[0209] The combined integer / floating-point units provided by the embodiments are supplemented by various types of machine learning acceleration units that can be integrated into GPGPUs. The embodiments described herein provide logic for enabling additional instructions to combine fusion-multiply-add operations with neural network activation functions such as modified linear unit functions (RELU), sigmoid functions, or hard sigmoid functions.

[0210] One embodiment enables an extension of 16-bit floating-point encoding to support alternative encodings from the standard IEEE 754 half-precision floating-point format. The IEEE half-precision floating-point format specifies 1 sign bit, 5 exponent bits, and 10 fractional bits. The embodiments described herein can selectively support alternative encodings for FP16 data based on the pattern of the data to be encoded. In one embodiment, a supported alternative format specifies 1 sign bit, with 8 exponent bits and 7 fractional bits. One embodiment allows encoding with 1 sign bit, 3 exponent bits, and 12 fractional bits. In such embodiments, different instruction sets support different floating-point encodings, allowing developers to select the encoding based on instructions specified in the program code. In one embodiment, different floating-point encodings can be used when rounding or downsampling floating-point data, for example, from an accumulated 32-bit floating-point value to a 16-bit value.

[0211] The merged floating-point unit described herein can selectively perform 16-bit integer or floating-point operations on a per-cycle basis. One embodiment enables dynamic reconfiguration of the floating-point unit described herein to enable multi-format support. For example, using a multi-channel configuration, the 16-bit integer or floating-point unit can be configured to perform two-channel 32-bit operations or four-channel 64-bit operations. Such logic enables floating-point logic optimized for low-precision inference operations to be clustered for higher-precision training operations.

[0212] One embodiment provides a random rounding unit and a statistical accumulator for low-precision networks. Random rounding enables increased accuracy of classical quantization and rounding for low-precision deep neural networks. The rounding unit can operate in different modes. A first mode uses a random number generator to control the random mode of the rounding unit. A second mode uses the probability distribution of the output on subsequent inputs and utilizes a near-data statistical estimator unit coupled to GPGPU memory.

[0213] The techniques described herein can be implemented within a general-purpose computing system with machine learning optimizations provided via machine learning accelerator units. The multiprocessors provided by the embodiments described herein... Figure 14 As shown in the image.

[0214] Figure 14 This is a block diagram of a multiprocessor unit 1400 according to an embodiment. The multiprocessor unit 1400 may be... Figure 2D This is a variation of the graphics multiprocessor 234. The multiprocessor unit 1400 includes a fetch and decode unit 1402, a branch unit 1404, a register file 1406, a thread manager 1406, a single instruction multithreaded unit (SIMT unit 1410), and a voltage and frequency manager 1420. The fetch and decode unit 1402 can fetch instructions for execution by the multiprocessor unit 1400. The branch unit 1404 can calculate instruction pointer adjustments based on executed jump instructions. The register file 1406 can store general-purpose and architecture registers used by the SIMT unit 1410. The thread manager 1406 can distribute and redistribute threads among the compute units of the SIMT unit 1410. In one embodiment, the SIMT unit 1410 is configured to execute a single instruction as multiple threads, where each thread of the instruction is executed by a separate compute unit. In one embodiment, each of computing units 1411 to 1418 includes an integer ALU (e.g., ALUs 1411A-1418A) and a floating-point unit (e.g., FPUs 1411B-1418B). The voltage and frequency of each computing unit 1411-1418 within the SIMT unit 1410 can be dynamically managed by a voltage and frequency manager 1420, which can increase or decrease the voltage and clock frequency supplied to the various computing units when components of the computing units are enabled and disabled.

[0215] In some previously enabled configurations, each compute unit could execute a single thread of integer or floating-point instructions. If any of the ALUs 1411A-1418A are assigned to execute a thread of integer instructions, the corresponding FPUs 1411B-FPU 1418B cannot be used for executing a thread of floating-point instructions and may be power-gated during the operation of the corresponding ALUs 1411A-ALU 1418A. For example, when the ALU 1411A can execute a thread of integer instructions while the FPU 1413B executes a thread of floating-point instructions, the FPU 1411B is power-gated while the ALU 1411A is active. The embodiments described herein overcome such limitations by, for example, enabling the ALU 1411A to execute a thread of instructions while the FPU 1411B executes a thread of different instructions. Furthermore, one embodiment provides support for mixed-precision or mixed-data-type operands, allowing a single compute unit to perform operations simultaneously on instructions with both floating-point and integer operands and / or operands with different precisions.

[0216] The embodiments described herein enable increased operational throughput for compute unit clusters by making all logical units within each compute unit available for computational execution. In such embodiments, logical units within a compute unit, designed to selectively perform computations at multiple precisions or multiple data types, can be configured to perform multiple simultaneous operations for each precision or data type supported by the compute unit. For a given compute unit 1411-1418, ALUs 1411A-1418A can perform integer operations, while FPUs 1411B-1418B perform floating-point operations. These operations can be performed for a single instruction or for multiple instructions. In one embodiment, a new class of mixed-precision instructions is enabled, where one or more operands have one data type or precision, while one or more different operands have different data types or precisions. For example, an instruction can accept two or more multi-element operands including floating-point and integer data types, and a single instruction can be executed on a per-data-type or per-precision basis.

[0217] Reconfigurable 16-bit floating-point / integer fused multiply-add unit

[0218] The logic unit designs provided by the embodiments described herein have both single-cycle and multi-cycle latency, while also having single-cycle throughput for both fused multiply-add (e.g., 3 operand inputs that are not dependent across cycles) and multiply-accumulate (e.g., 2 operand inputs that are data-dependent across cycles). In contrast, logic unit designs known in the art implement fused multiply-add without considering multi-cycle latency and single-cycle throughput multiply-accumulate operations, which can be limiting factors for the execution of critical machine learning operations (e.g., dot product operations).

[0219] One embodiment described herein provides a merged integer / floating-point multiply-accumulate data path that utilizes existing signed integer multiply-accumulate circuitry to also implement floating-point mantissa multiply-accumulate operations. Floating-point support is enabled by adding only the circuitry required for alignment / normalization shifts and exponentiation units. Input / output data widths and data memory footprints remain the same, with only a single control signal required to switch between the two computation modes on a per-cycle basis.

[0220] One embodiment provides a merged 16-bit integer / float-point multiply-accumulate design that improves upon conventional single-cycle designs with separate integer / float-point data paths. The design described herein implements multiply-accumulate circuitry with merged int16 / float16 data paths, reducing the total area by up to 29%. One embodiment provides an improved floating-point data path with alignment only for the addend, along with a combination of negation and rounding incrementers that contribute 11% to the total area reduction. One embodiment provides a multiply-accumulate variant with two inputs and two-cycle latency, offering single-cycle throughput. One embodiment provides an alternative circuitry that significantly increases accumulation accuracy by doubling the accumulator width at only 11% of the increased area.

[0221] Figures 15A-15B The design of a logic unit for performing fused integer and floating-point multiplication-addition operations is shown according to an embodiment. Figure 15AA conventional design of logic unit 1500 is shown, enabling fused multiply-add operations while maintaining full intermediate product accuracy and range. A fused multiply-add operation (o = a * b + c) is performed on three 16-bit input operands 1501 in either IEEE half-precision floating-point (float16) or signed 16-bit integer (int16) mode. The inputs are provided to either the 16-bit floating-point data path 1510 or the 16-bit integer data path 1520, where the output port (o 1530) selects the appropriate result (f16 1518 or i16o 1528) based on the operation mode 1532. The int16 result (i16o 1528) is selected and rounded to the nearest high half of the 32-bit signed integer result (isum 1525) generated by the signed 16bx16b multiplier 1521 and the 32b adder 1522. The float16 data path 1510 right shifts (1511) the mantissa of the smaller of the product of the unsigned 11bx11b multiplier 1617 and right-shifts the addend before processing the product via the 22-bit mantissa adder 1513 for alignment at the alignment shifter 1512A. A 22-bit leading zero predictor (LZA 1519) predicts the position of the most significant bit of the floating-point addition result performed by the 22-bit mantissa adder 1513 based on the input to the adder. A left shift (1514) is performed by the normalization shifter 1515 before the intermediate result is provided to the rounding logic 1516.

[0222] Figure 15B This is a block diagram of the multiply-add logic unit 1540 according to an embodiment. Figure 15B The logic unit 1540 maintains a separate 16-bit floating-point / integer circuit while improving the floating-point data path of the logic unit 1500. In one embodiment, the design of the logic unit 1540 removes the alignment shifter 1512B from the critical path by performing alignment only on the addend (in parallel with the multiplication operation (1541)). This results in a wider 33-bit layout and requires only an 11-bit incrementer for the higher bits. Furthermore, for the subtraction operation, the output of the adder can be inverted to produce an unsigned mantissa. In one embodiment, the incrementer is removed from the critical path of the data path of the logic unit 1540 by combining the increment operation with a final rounding incrementer (1542). Instead, Figure 15A Logic unit 1500 requires the incrementer to perform any required binary two's complement inversion operation after the adder. The reduction in the critical path of the 16-bit floating-point data path of logic unit 1540 results in smaller gates and allows for an 11% reduction in area associated with logic unit 1500 while maintaining the same single-cycle latency.

[0223] Figure 16A fused multiply-add logic unit 1600 with merged floating-point and integer data paths is shown according to an embodiment. A 16-bit × 16-bit signed multiplier 1602A and a 32-bit adder 1604 of the integer data path are reused for floating-point mantissa operations, where the high operand bits are gated to produce an 11-bit mantissa (1602B) result. When floating-point mode is enabled, input switches 1601A-1601C are used to redirect the high 6 bits of the input operands (a, b, c) to the exponent unit 1608. The sign and exponent values ​​from the input are packaged and provided to the exponent unit 1608 via a fixed 3-bit sign operand bus 1609A and a 15-bit exponent bus 1609B. For 16-bit floating-point operations, the shared 32-bit adder uses a 1-bit incrementer 1605 to create the high bits (multiple) of a 33-bit sum (multiple) 1606. Bypass circuitry (1610A, 1610B) within the exponent unit 1608 and in the alignment shifter 1612 and normalization shifter 1613 ensures fixed alignment / normalization with minimal switching activity in those units used for integer mode, while zero high mantissa bits ensure no switching activity in the unused portion of the multiplier in floating-point mode. Rounding logic 1616 and the incrementer of the floating-point data path are reused in integer mode to round the lower 10 bits of the integer result i16o. The higher 6 bits of i16o are calculated by mapping this operation to the existing exponent incrementer 1611, which also performs any rounding overflow operations from the mantissa data path in floating-point mode. When processing is complete, a 16-bit floating-point or integer value can be provided via output 1630.

[0224] Figure 17A A logic unit 1700, according to an embodiment, includes merging computation circuitry to perform floating-point and integer fused-multiply-accumulate operations. The logic unit 1700 includes an exponent unit 1708 and a mantissa unit 1709, two 16-bit input ports 1701, and a 16-bit output port 1730. Input port 1701 includes switches for switching the sign bit and exponent bit of input data to the exponent unit 1708. The exponent unit 1708 and mantissa unit 1709 are used when performing integer operations. In one embodiment, the logic unit supports an 8.8-input and 16.0-output format for 16-bit fixed-point mode. The logic unit 1700 supports two-cycle latency and single-cycle throughput requirements. Some of the illustrated circuitry is shared between operating modes, including signed multipliers 1702A-1702B and a 32-bit adder 1704 for both integer and floating-point modes. During the accumulation phase in the second cycle, the 16-bit accumulator input 1703A is asserted, where the accumulator value is fed to the 32-bit adder 1704. The high 10 bits of the accumulator input 1703A (e.g., c[15:6]) are dedicated to 16-bit integer operations. For both computation modes, multiplication is performed in the first cycle, and addition / rounding is performed in the second cycle.

[0225] Figure 17A The logic unit 1700 uses three key technologies to enable efficient merging design. First, for accumulation operations... Figure 16 Direct pipelined implementation of a single-cycle merge design would halve throughput in the first cycle through addend alignment, or increase cycle time in the critical path of the second cycle through right shift computation and 33-bit alignment. Instead, the design of logic unit 1700 leverages the timing / region non-criticality of exponent unit 1708 to pre-compute the larger (or smaller) mantissa and right shift amount of alignment shifter 1713. In one embodiment, logic unit 1700 performs two-cycle operation while maintaining single-cycle throughput by feeding the output back to the second cycle as addend input, selecting the smaller mantissa for 22-bit alignment only, and pre-computes the smaller mantissa / right shift amount in the first cycle using the multiplier output and accumulator exponent previously computed by the second stage.

[0226] Second, the round-to-nearest operation in the 16-bit integer mode utilizes the 8.8 fixed-point format and eliminates the need to map integer rounding to a floating-point rounding incrementer. The same rounding operation is achieved by inserting a 1 instead of a 0 at bit position 15 via multiplexer logic 1705 before the adder.

[0227] Third, the trigger is reused for the mutual exclusion signal between the two modes, such as the high 10b of exponentiation (e.g., Eun 1707, right shift 1710) and product (1711). Timing path reduction in the second cycle is also achieved by combining the invert / round incrementer and by using optimization based on far / near paths to reduce the critical path through the alignment shifter 1713 and the normalization shifter 1714.

[0228] like Figure 17BAs shown, the accuracy of the two-cycle multiply-accumulate design is significantly increased by simply doubling the width of the accumulator to 32 bits. The accumulator can accumulate a 16-bit integer result based on an intermediate result with a 5-bit exponent and a 22-bit mantissa (implicit leading 1s are not stored), in a 16.16 fixed-point format and a 16-bit floating-point result. In various embodiments, the 22-bit mantissa of the intermediate result can be rounded, truncated, or quantized to an IEEE standard mantissa. The design of logic unit 1740 primarily limits the cost of doubling the accumulator to the output flip-flops and the final incrementer in the mantissa data path, since the remaining data path after the multiplier has already been adapted for the additional width used for the product. In one embodiment, higher accuracy enables rounding to be simplified to simple truncation to generate a 16-bit output 1750 from the 32-bit accumulator. The post-exponent normalized incrementer is removed from the exponent unit 1708 in logic unit 1740. Conversely, when the adder's output is to be inverted, the inverting increment 1742 performs a final increment on the mantissa to compute the two's complement. During the accumulation phase in the second cycle, the 32-bit accumulator input 1703B is asserted, where the accumulator's value is provided to the 32-bit adder 1704. The high 10 bits of the accumulator input 1703B (e.g., c[31:22]) are dedicated to 16-bit integer operations. The combined total area of ​​this design is relative to Figure 17A The design of the logic unit 1700 shows only an 11% increase in area, while doubling the accumulator accuracy.

[0229] Although the above description is provided for 16-bit operands, these techniques can be easily extended to larger data widths to achieve similar goals. Furthermore, while IEEE half-precision output is described, the designs described herein can also be adapted to support non-standard floating-point formats. Additionally, different non-standard floating-point formats can be used for intermediate values, as described below.

[0230] The embodiments described above provide various implementations of a reconfigurable 16-bit floating-point / integer fused multiply-add unit that offer several advantages over existing designs. The proposed design does not affect the memory footprint of either floating-point or integer storage. The proposed design only increases the multiplier area without changing the remainder of the floating-point data path. In contrast, logic designs known in the art extend the entire floating-point significant bits / mantissa to the same width as integers, while additional storage areas for the sign and exponent are separate and dedicated only to floating-point numbers, causing an increase in the floating-point storage footprint and register file size. Existing designs also increase the width of the entire mantissa data path, which can cause a significant increase in area. A single cycle (e.g., Figure 16 (Logic unit 1600) and multi-cycle (e.g., Figure 17A Logic unit 1700 and Figure 17BThe logic unit 1740 is designed in a multi-cycle manner, where the output is generated in each cycle after an initial wait time. Figure 17B The Logic Unit 1740 provides a consolidated floating-point / integer multiply-accumulate design with a local accumulator width twice the width of the input operands. This enables much higher accumulation accuracy for operations like dot products without impacting the memory footprint of the input operands and affecting only a small fraction of the design (for only 11% of the total area). Furthermore, each logic unit maps a portion of the integer operation onto an existing exponent data path to maximize circuit reuse when reconfigured for integer mode. Additionally, for floating-point operations with subtraction, Figure 15B Logic unit 1540 and Figure 17A To reduce latency and area, the 1700 binary two's complement increment is combined into the rounding increment.

[0231] Machine learning data processing systems and acceleration logic

[0232] One embodiment uses Figure 14 Multiprocessor unit 1400 and Figure 15A-17B One or more floating-point / integer logic units can be used as building blocks for machine learning data processing systems, which include hardware, software, and firmware optimized to perform the types of computational operations typically performed when using deep neural networks for training or inference. Figures 18A-18B The diagram illustrates a data processing system and associated computational and logical units used, for example, to perform accelerated training and inference operations for machine learning via the use of deep neural networks. Figure 18A An exemplary machine learning data processing system provided by the embodiments described herein is shown. Figure 18B The components of a machine learning accelerator according to one embodiment are shown.

[0233] Figure 18AThe data processing system 1800 is a heterogeneous processing system with a GPGPU 1820 including machine learning acceleration logic, a processor 1802, and a unified memory 1810. The processor 1802 and GPGPU 1820 can be any processor and GPGPU / parallel processor as described herein. The processor 1802 can execute instructions stored in system memory 1812 for compiler 1815. Compiler 1815 executes on processor 1802 to compile source code 1814A into compiled code 1814B. Compiled code 1814B can include code that can be executed by processor 1802 and / or code that can be executed by GPGPU 1820. During compilation, compiler 1815 can perform operations to insert metadata, including hints about the level of data parallelism present in compiled code 1814B and / or hints about data locality associated with threads to be dispatched based on compiled code 1814B. Compiler 1815 can include information required to perform such operations or operations that can be performed with the help of runtime library 1816. The runtime library 1816 can also facilitate compiler 1815 to compile source code 1814A, and can also include instructions for linking runtime with compiled code 1814B to facilitate the execution of compiled instructions on GPGPU 1820.

[0234] Unified memory 1810 represents a unified address space that can be accessed by processor 1802 and GPGPU 1820. Unified memory includes system memory 1812 and GPGPU memory 1818. GPGPU memory 1818 includes GPGPU local memories 1834A-1834B within GPGPU 1820 and may also include some or all of the memory in system memory 1812. For example, compiled code 1814B stored in system memory 1812 may also be mapped to GPGPU memory 1818 for access by GPGPU 1820.

[0235] The GPGPU 1820 includes multiple compute blocks 1824A-1824N, which can be Figure 2A The processing clusters 214A-214N may include instances of one or more of the graphics multiprocessor 234 described herein. In various embodiments, the compute blocks 1824A-1824N include... Figures 17A-17BThe GPGPU 1820 includes one or more computational units within its logical units. It also includes a power and performance module 1826, a cache memory 1827, and a collection of registers 1825 that can be used as shared resources for computation blocks 1824A-1824N. In one embodiment, registers 1825 include directly and indirectly accessible registers, wherein indirectly accessible registers can be optimized for matrix computation operations. The power and performance module 1826 can be configured to adjust the power delivery and clock frequency of computation blocks 1824A-1824N to power-gated idle parts within computation blocks 1824A-1824N under heavy workloads. The GPGPU 1820 includes GPGPU local memory 1828, which is a physical memory module that shares a graphics card or multi-chip module with the GPGPU 1820.

[0236] In one embodiment, the GPGPU 1820 includes hardware logic including an instruction fetch and decode unit 1821, a scheduler controller 1822, and a machine learning accelerator 1823. The instruction fetch and decode unit 1821 is an instruction fetch and decode unit that includes logic for fetching and decoding instructions (including machine learning-specific instructions) that can define complex, customizable behaviors. These instructions can cause the computation logic to schedule a set of operations to be executed via one or more computation blocks 1824A-1824N via the scheduler controller 1822. In one embodiment, the scheduler controller 1822 is an ASIC configurable to perform high-level scheduling operations. In another embodiment, the scheduler controller 1822 is a microcontroller or a low-per-instruction-energy processing core capable of executing instructions loaded from a firmware module.

[0237] In one embodiment, some functions to be performed by computation blocks 1824A-1824N can be directly scheduled to machine learning accelerator 1823 or offloaded to machine learning accelerator 1823. Machine learning accelerator 1823 includes processing element logic configured to efficiently execute matrices and other computational operations typically performed during machine learning.

[0238] In some embodiments, the GPGPU 1820 additionally includes a statistics unit 1829 configurable as a near-data computation unit. For example, the statistics unit 1829 may be integrated into or propagated across one or more memory controllers of the GPGPU local memory 1828. In one embodiment, the statistics unit 1829, when enabled by the machine learning accelerator 1823, can be used to determine the probability distribution of weighted or activated mapped data when performing machine learning operations written to or read from the GPGPU local memory 1828. The statistics unit 1829 includes features for determining whether data accessed in the GPGPU local memory 1828 falls within one or more statistical distributions (e.g., Gaussian, unified, Poisson, etc.) based on address and data patterns during memory accesses. In one embodiment, for at least a subset of memory accesses, statistics (e.g., mean, median, pattern, standard deviation, etc.) may be collected during a sampling period. The statistics unit 1829 may be configured such that collecting statistics does not significantly increase the latency of memory accesses performed by the memory controller hosting the statistics unit 1829. Statistical information can be provided to machine learning accelerator 1823 periodically, or machine learning accelerator 1823 can request data from the statistical unit. In one embodiment, the statistical unit 1829 can examine data associated with memory access for a known set of possible distributions. A vector including a set of probabilities associated with each known possible distribution can be provided to machine learning accelerator 1823 periodically or upon request. In various embodiments, machine learning accelerator 1823 can use the probability and / or statistical information provided by the statistical unit 1829 for various operations. In one embodiment, such as Figure 18B and Figure 20 As further described, the machine learning accelerator 1823 can use data provided by the statistics unit 1829 to perform random rounding during the quantization of a low-precision neural network.

[0239] Figure 18A The machine learning accelerator 1823 in Figure 18B Further details are shown below. In one embodiment, the machine learning accelerator 1823 includes an activation instruction module 1832, an FPU encoding and configuration module 1834, a random quantization unit 1838, and a cache memory 1836, which are shared among various modules within the machine learning accelerator 1823.

[0240] The activation instruction module 1832 includes logic for ordering the execution of combined fused multiply-add and activation operations in response to a single instruction. In response to decoding of the FMAC or FMADD activation function on the GPGPU 1820, the scheduler unit 1822 can schedule the operation via the machine learning accelerator 1823. The machine learning accelerator 1823 can perform a set of fused multiply-add or fused multiply-accumulate operations on two or three input operands per thread or vector element via the activation instruction module 1832, and for each thread or element, provide the output to hardware logic configured to execute one of a plurality of optional activation functions. Different activation functions can be associated with different instructions, or a single instruction can include a field for enabling the selection of an activation function. In one embodiment, the activation instruction module can perform vector or wrapping operations to generate intermediate FMADD or FMAC results and store the intermediate results in cache memory 1836. The activation instruction module 1832 can then apply the activation function to the intermediate data. The activation functions supported by the demonstration include the modified linear unit (RELU) function of equation (1), the sigmoid function of equation (2), or the hard sigmoid function of equation (3).

[0241]

[0242] The FPU encoding and configuration module 1834 includes logic for defining parameters for the dynamic configuration of floating-point units within compute blocks 1824A-1824N of the GPGPU 1820. In one embodiment, Figure 16 and Figures 17A-17B Certain dynamic aspects of the merged integer / floating-point units can be configured via the FPU encoding and configuration module 1834. For example, compute blocks 1825A-1824N can be over-provisioned to include more compute units than can be maximally active at any given GPGPU 1820 power budget. However, the FPU encoding and configuration module 1834 can configure the dynamic floating-point units to gate certain logic blocks to operate with reduced precision and reduced power consumption. The reduced precision and power requirements per unit allow a larger number of units to be online, allowing a larger number of threads to perform lower-precision operations. For example, and in one embodiment, a logic unit that can be configured to perform 16-bit integer operations can be configured to perform 8-bit integer operations, reducing power requirements. In one embodiment, dual 8-bit integer operations can be performed, increasing throughput without significantly increasing power consumption. In one embodiment, multiple half-precision logic units can work in parallel to perform single-precision or double-precision floating-point operations. In one embodiment, higher-precision operations can be performed via multiple channels through the logic units.

[0243] In one embodiment, the FPU encoding and configuration module 1834 can also configure floating-point encoding methods supported by the floating-point unit. In addition to the IEEE 754 floating-point standard for half-precision, single-precision, and double-precision encoding of floating-point values, a large number of alternative encoding formats can be supported based on the dynamic range of the data currently being processed. For example, based on the dynamic range and / or distribution of a given dataset, data can be quantized more accurately from higher to lower precision by using more or fewer bits for the exponent or mantissa data. In one embodiment, a supported alternative format specifies a 1-bit sign, an 8-bit exponent, and a 7-bit fractional component. One embodiment allows encoding with a 1-bit sign, a 3-bit exponent, and a 12-bit fractional component. In such embodiments, different instruction sets support different floating-point encodings, allowing developers to select an encoding based on instructions specified in the program code. In one embodiment, different floating-point encodings can be used when rounding or downsampling floating-point data, for example, from an accumulated 32-bit floating-point value to a 16-bit value. In one embodiment, the statistics unit 1829 can be used to determine which 16-bit encoding is best suited for a given block of data.

[0244] In one embodiment, the machine learning accelerator 1823 additionally includes a random quantization unit 1838 to enable random quantization for machine learning operations. The random quantization unit 1838 can be used to enable random rounding during quantization operations. One embodiment uses a random number generator to enable random rounding, where small values ​​can be used to determine the rounding probability. One embodiment utilizes a statistics unit 1829 to determine a probability distribution associated with a set of output data from a given layer of the neural network. For each layer, a probability density of data values ​​can be determined, where the probability density is determined by statistical properties, including the mean, standard deviation, and variance of the data determined for each layer of the neural network. Using such data, random rounding can be performed in a manner that does not alter the probability distribution of the data within each layer of the neural network.

[0245] Figure 19 Details of the activation instruction module 1832 according to an embodiment are shown. The activation instruction module 1832 includes logic for ordering the execution of combined fused multiplication-addition activations in response to a single instruction. In response to... Figure 18AThe decoding of the FMAC / FMADD+ activation function by the instruction fetching and decoding unit 1821 can be dispatched to the activation instruction module 1832 via the machine learning accelerator 1823. Upon receiving the instruction, the machine learning accelerator 1823 can use the fused multiply-add / fused multiply-accumulate thread scheduler unit 1902 to schedule the set of fused multiply-add or fused multiply-accumulate operations used to compute units within computation blocks 1824A-1824N. In one embodiment, intermediate data output from computation blocks 1824A-1824N can be stored in a cache memory 1836 within the machine learning accelerator 1823. In one embodiment, blocks of intermediate data can be processed in a streaming manner within the activation instruction module 1832. In one embodiment, the intermediate data can represent the activation mapping to which the nonlinearity of the activation function will be applied. One of the activation functions can be selected by the activation function logic 1904A-1904N. The activation function can be selected based on a specific instruction processed by the activation instruction module 1832 or by parameters supplied by the instruction. Specific instructions can be formatted based on any instruction format described in this article.

[0246] Floating-point operations at various points include rounding. Rounding is used in floating-point calculations because floating-point numbers have a finite number of digits and cannot accurately represent all real numbers. Therefore, when a number is assigned the task of representing a value that requires more digits than the selected floating-point format allows, the remaining digits are omitted, and the number is rounded to the nearest value that can be represented by the floating-point format. The specific number that can be represented depends on the selected floating-point format.

[0247] Various methods can be implemented for rounding during floating-point calculations. The embodiments described herein include hardware logic for performing random rounding for machine learning operations. Unlike other rounding methods (rounding to the nearest number or strictly up or down), random methods round numbers randomly. The embodiments described herein enable random rounding for the quantization of data values ​​used in deep neural networks. A rounding unit is provided that enables hardware random rounding using one of multiple rounding modes. One embodiment uses a random number generator to enable random rounding. A rounding probability can be determined using a small number. A random number can be compared to the rounding probability to determine which of the most recently representable values ​​to round during quantization. Alternatively, one embodiment utilizes statistical accumulator / estimater logic to determine a probability distribution associated with a set of output data from a given layer of the neural network. For each layer, a probability density of the data value distribution can be determined, where the probability density is defined by the mean, standard deviation, and variance of the data determined for each layer of the neural network. Using such data, random rounding can be performed in a manner that does not alter the probability distribution of each layer of the neural network.

[0248] Figure 20A random quantization unit 1838 according to an embodiment is shown. In one embodiment, the random quantization unit 1838 is used to quantize raw output data generated within a layer of a neural network into a format used by the next layer of the neural network. For example, computational operations used to generate the output data can be processed with higher precision, and the results can be quantized to lower precision before being provided as input to the next layer. In one embodiment, the output 2002B from a given layer n is processed, for example, in 32 bits and quantized into a 16-bit data type by the quantization unit 2004. The quantization operation can utilize random rounding, which can be implemented via a random rounding unit 2009. The quantized and rounded values ​​can then be provided to the next layer (layer N + 1) 2010 of the neural network.

[0249] In various embodiments, the random quantization unit 1838 may perform random rounding via the use of a random number generator 2006. In floating-point arithmetic, rounding aims to transform a given value x into a value z with a specified number of significant digits, where z is a multiple of a number m, which depends on the magnitude of x. The number m is a power of the base of the floating-point representation (typically 2 or 10). The number z is a representable value close to the value x. The value x is rounded up or down so that the value z is based on a random value selected by the random number generator 2006. The generated random value is compared with the fractional part between the significant representations. The fractional part can be used as the probability of rounding up or down to the nearest representable value. The gap between representable values ​​during quantization depends on the encoding format of the floating-point representation at the appropriate position. As an example, if the quantization is to round to an integer value with a fractional value of 0.3, the probability of rounding up may be equal to 30%, while the probability of rounding down may be equal to 70%. In such scenarios (where the random number generator 2006 is a properly verified true random number generator), the random rounding unit 2009 will round up or down proportionally to the decimal value.

[0250] Alternatively, the random rounding unit 2009 may utilize a statistical accumulator / estimater 2008, which in one embodiment is as follows: Figure 18A The near-data statistics unit 1829 is used in the process. The statistical accumulator / estimater 2008 can analyze the output from the previous layers 2002A-2002B to determine the distribution associated with the neural network data. The random rounding unit 2009 can then round the data during quantization so that the quantized data has a distribution similar to the pre-quantized data.

[0251] Figure 21An FPU encoding and configuration module 1834 according to one embodiment is illustrated. In one embodiment, the GPU encoding and configuration module 1834 includes an FPU configuration module 2102 and an FPU encoding module 2104. The FPU configuration module 2102 can be configured to execute 16-bit integer logic units to perform 8-bit integer operations (including double 8-bit integer operations). In one embodiment, multiple half-precision logic units can work in parallel to perform single-precision or double-precision floating-point operations. The FPU encoding module 2104 can be configured to configure a specific floating-point encoding format used within computation blocks 1824A-1824N during data computation. In one embodiment, the FPU encoding module 2104 can configure one or more of the computation blocks 1824A-1824N in response to an instruction specifying that input or output data should be stored in a non-standard floating-point format. The computation block used to execute the instruction can then be configured to interpret the data in the non-standard format before the operation of executing the instruction. In one embodiment, the FPU encoding module 2104 configures one or more of the computation blocks to use a floating-point encoding format that can most efficiently store the data to be processed. Such determinations can be performed in part based on probability and statistical information provided by the statistics unit 1829, which can function as a near-data computation unit within the memory controller 2106 of the GPGPU local memory 1828.

[0252] Figure 22 Logic 2200 is illustrated according to an embodiment, which uses a dynamically configurable computing unit to process instructions. Logic 2200 may be a GPGPU and / or a GPGPU multiprocessor (such as...) as described herein. Figure 14 The multiprocessor unit 1400 or Figure 18A The hardware or firmware logic within the GPGPU 1820. As shown in block 2202, logic 2200 is configured to fetch and decode a single instruction to perform a combined multiplication-addition operation on a set of operands. As shown in block 2204, logic 2200 can then issue a single instruction for execution by a compute unit for execution by a dynamically configurable compute unit. As shown in block 2206, logic 2200 can then configure one or more logic units of the compute unit to perform the operation with respect to the precision and data type of the operands. As shown in block 2208, logic 2200 can then execute a single instruction in the compute unit to generate an output based on multiplication and addition operations.

[0253] In one embodiment, the combined multiplication and addition operation performed in block 2202 can be a fused floating-point operation including a single rounding. For example, the multiplication and addition operation can be a fused multiplication-addition or a fused multiplication-accumulation operation. The combined multiplication and addition operation can also be an integer operation. Integer operations can include a rounding operation between multiplication and addition. The rounding can be performed by inserting zeros at the most significant bit position of the integer data type via a multiplexer within the logic unit. Within the logic unit, the multiplexer can be located after the multiplier and before the adder.

[0254] In one embodiment, the dynamically configurable logic unit of block 2204 is a combined floating-point and integer logic unit configurable to perform integer or floating-point operations. For example, the dynamically configurable logic unit could be... Figure 16 Logic unit 1600 Figure 17A 1700 or Figure 17B One of 1740. A computing unit may include multiple different instances of such logic units. In one embodiment, the logic unit is configurable on a per-cycle basis. In one embodiment, the logic unit is a first logic unit configured to perform a single-cycle fused multiply-accumulate operation using multipliers and adders shared between floating-point and integer data paths. In one embodiment, the logic unit is a second logic unit configured to perform a two-cycle fused multiply-accumulate operation with single-cycle throughput. In one embodiment, the logic unit is a third logic unit configured to perform a two-cycle fused multiply-accumulate operation, wherein the third logic includes an accumulator with twice the bit width of its input and output operands. In one embodiment, the die area of ​​the third logic unit is at most 11 percent larger than the die area of ​​the second logic unit.

[0255] The dynamically configurable logic units described herein can be configured to perform integer or floating-point operations. In one embodiment, one or more of the logic units can be configured to perform operations with multiple different precisions. In one embodiment, the logic units can be used to perform operations with multiple different precisions via multi-cycle operations. In one embodiment, different floating-point encodings can be selected, including IEEE 754 half-precision floating-point format, single-precision floating-point format, and double-precision floating-point format. Non-standard floating-point formats can also be used, where different bit allocations are used for the exponent and mantissa of the floating-point value.

[0256] In one embodiment, the output based on the multiplication and addition operations can then be further processed by an activation function. For example, in response to a single instruction, an FMADD or FMAC operation can be scheduled by the FMADD / FMAC thread scheduler unit, such as... Figure 19 As shown in the diagram. The output of such an operation can be provided to activation function logic (e.g., as shown in the diagram). Figure 19The activation function logic 1904 in the middle is used to generate activation mapping data for neuron activation data.

[0257] Figure 23A Logic 2300 for executing machine learning instructions according to an embodiment is illustrated. Logic 2300 may be a GPGPU and / or a GPGPU multiprocessor (such as...) as described herein. Figure 14 The multiprocessor unit 1400, or Figure 18A The hardware or firmware logic within the GPGPU 1820. As shown in block 2302, logic 2300 is configured to fetch and decode a single instruction to perform a set of machine learning operations via the machine learning accelerator unit. The machine learning accelerator unit includes elements of the machine learning accelerator 1823 described herein, including... Figure 18B The logic 2300 includes an activation instruction module 1832, an FPU encoding and configuration module 1834, and a random quantization unit 1838. As shown in block 2304, logic 2300 can then issue a single instruction for execution by the dynamically configurable set of computational units. As shown in block 2306, the logic can then configure the set of computational units to perform a set of machine learning operations with a higher precision than the input and output of the operations. In one embodiment, the configuration is performed by an FPU configuration module as described herein. The FPU configuration module can configure the computational units to perform convolution operations on 16-bit floating-point matrix data, for example, using 32-bit intermediate data. As shown in block 2308, logic 2300 can then quantize the higher-precision intermediate value to a lower precision before the output via random rounding logic within the machine learning accelerator. For example, random rounding can be used to quantize 32-bit intermediate data to 16 bits for the output.

[0258] Figure 23B Logic 2310 for configuring floating-point operations based on a distribution of neural network data according to an embodiment is illustrated. In one embodiment, logic 2300 includes the hardware and firmware logic and logic units described herein, including... Figure 18B and Figure 20 The random quantization unit 1838, Figure 18B The FPU encoding and configuration module 1834. Figure 20 The statistical accumulator / estimater 2008 includes in one embodiment Figure 18A Within the statistical unit 1829. The statistical unit 1829 may be a near-data computation unit included within the memory controller for the GPGPU, such as... Figure 21 As shown in the image.

[0259] As shown in block 2312, using the statistics unit, logic 2310 can determine a set of statistical measures of the neural network data stored in memory. Logic 2310 can then determine the distribution of the neural network data in memory via the statistical measures, as shown in block 2314. In one embodiment, logic 2310 can configure floating-point encoding for the computation unit to perform a set of machine learning operations, as shown in block 2316. Logic 2310 can then configure the random rounding logic within the machine learning accelerator to perform distribution-based rounding, as shown in block 2318. The random rounding logic can be configured to perform distribution-based rounding such that the probability distribution of the quantized neural network data is closer to the pre-quantized data than is possible using random number generator-based rounding techniques.

[0260] Additional demonstration graphics processing system

[0261] The details of the embodiments described above can be incorporated into the graphics processing systems and devices described below. Figures 24 to 37 The graphics processing systems and devices described herein illustrate alternative systems and graphics processing hardware that can implement any and all of the techniques described above.

[0262] Additional Exemplary Graphics Processing System Overview

[0263] Figure 24 This is a block diagram of a processing system 2400 according to an embodiment. In various embodiments, system 2400 includes one or more processors 2402 and one or more graphics processors 2408, and may be a single-processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 2402 or processor cores 2407. In one embodiment, system 2400 is a processing platform incorporated within a system-on-a-chip (SoC) integrated circuit for use in mobile devices, handheld devices, or embedded devices.

[0264] Embodiments of system 2400 may include a server-based gaming platform, a game console including a game and media console, a mobile game console, a handheld game console, or an online game console, or integrated therein. In some embodiments, system 2400 is a mobile phone, smartphone, tablet computing device, or mobile internet device. Data processing system 2400 may also include wearable devices (such as smartwatches, smart glasses, augmented reality devices, or virtual reality devices), coupled to said wearable device, or integrated within said wearable device. In some embodiments, data processing system 2400 is a television or set-top box device having one or more processors 2402 and a graphical interface generated by one or more graphics processors 2408.

[0265] In some embodiments, each of the one or more processors 2402 includes one or more processor cores 2407 for processing instructions that, when executed, perform operations for system and user software. In some embodiments, each of the one or more processor cores 2407 is configured to process a particular instruction set 2409. In some embodiments, the instruction set 2409 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computation via Very Long Instruction Word (VLIW). Multiple processor cores 2407 may each process a different instruction set 2409, which may include instructions for facilitating emulation of other instruction sets. Processor cores 2407 may also include other processing devices, such as digital signal processors (DSPs).

[0266] In some embodiments, processor 2402 includes cache memory 2404. Depending on the architecture, processor 2402 may have a single internal cache or multiple internal cache levels. In some embodiments, cache memory is shared among various components of processor 2402. In some embodiments, processor 2402 also uses an external cache (e.g., a Level 3 (L3) cache or a Last Level Cache (LLC)) (not shown), which can be shared among processor cores 2407 using known cache coherence techniques. Register file 2406 is additionally included in processor 2402 and may include different types of registers (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers) for storing different types of data. Some registers may be general-purpose registers, while others may be specific to the design of processor 2402.

[0267] In some embodiments, processor 2402 is coupled to processor bus 2410 to transmit communication signals, such as address, data, or control signals, between processor 2402 and other components in system 2400. In one embodiment, system 2400 uses an exemplary 'central' system architecture including a memory controller central hub 2416 and an input / output (I / O) controller central hub 2430. Memory controller central hub 2416 facilitates communication between memory devices and other components of system 2400, while I / O controller central hub (ICH) 2430 provides connectivity to I / O devices via a local I / O bus. In one embodiment, the logic of memory controller central hub 2416 is integrated within the processor.

[0268] Memory device 2420 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase-change memory device, or some other memory device with suitable performance to act as process memory. In one embodiment, memory device 2420 may operate as system memory of system 2400 to store data 2422 and instructions 2421 for use by the one or more processors 2402 when executing an application or process. Memory controller hub 2416 is also coupled to an optional external graphics processor 2412, which may communicate with the one or more graphics processors 2408 in processor 2402 to perform graphics and media operations.

[0269] In some embodiments, ICH 2430 enables peripheral devices to connect to memory device 2420 and processor 2402 via a high-speed I / O bus. I / O peripheral devices include, but are not limited to, an audio controller 2446, a firmware interface 2428, a wireless transceiver 2426 (e.g., Wi-Fi, Bluetooth), a data storage device 2424 (e.g., a hard disk drive, flash memory, etc.), and a legacy I / O controller 2440 for coupling legacy devices (e.g., Personal System 2 (PS / 2)) to the system. One or more Universal Serial Bus (USB) controllers 2442 connect input devices, such as a keyboard and mouse combination 2444. A network controller 2434 may also be coupled to ICH 2430. In some embodiments, a high-performance network controller (not shown) is coupled to processor bus 2410. It will be understood that the illustrated system 2400 is exemplary and not limiting, as other types of data processing systems with different configurations may also be used. For example, the I / O controller hub 2430 may be integrated within one or more processors 2402, or the memory controller hub 2416 and the I / O controller hub 2430 may be integrated into a discrete external graphics processor (such as external graphics processor 2412).

[0270] Figure 25 This is a block diagram of an embodiment of processor 2500, which has one or more processor cores 2502A-2502N, an integrated memory controller 2514, and an integrated graphics processor 2508. Figure 25Those elements having the same reference numerals (or names) as elements in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein. Processor 2500 may include, and include, additional cores 2502N, indicated by the dashed block. Each of processor cores 2502A-2502N includes one or more internal cache units 2504A-2504N. In some embodiments, each processor core may also have access to one or more shared cache units 2506.

[0271] Internal cache units 2504A-2504N and shared cache unit 2506 represent the cache memory hierarchy within processor 2500. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared intermediate cache, such as Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, wherein the highest-level cache preceding external memory is classified as LLC. In some embodiments, cache coherence logic maintains coherence between the various cache units 2506 and 2504A-2504N.

[0272] In some embodiments, the processor 2500 may further include a system agent core 2510 and a collection of one or more bus controller units 2516. The one or more bus controller units 2516 manage a set of peripheral buses, such as one or more peripheral component interconnect buses (e.g., PCI, PCI Express). The system agent core 2510 provides management functions for various processor components. In some embodiments, the system agent core 2510 includes one or more integrated memory controllers 2514 for managing access to various external memory devices (not shown).

[0273] In some embodiments, one or more of processor cores 2502A-2502N include support for simultaneous multithreading. In such embodiments, system agent core 2510 includes components for coordinating and operating processor cores 2502A-2502N during multithreaded processing. System agent core 2510 may additionally include a power control unit (PCU) including logic and components for regulating the power states of processor cores 2502A-2502N and graphics processor 2508.

[0274] In some embodiments, processor 2500 additionally includes a graphics processor 2508 for performing graphics processing operations. In some embodiments, graphics processor 2508 is coupled to a set of shared cache units 2506 and a system proxy core 2510, the system proxy core 2510 including the one or more integrated memory controllers 2514. In some embodiments, display controller 2511 is coupled to graphics processor 2508 to drive graphics processor output to one or more coupled displays. In some embodiments, display controller 2511 may be a separate module coupled to graphics processor via at least one interconnect, or it may be integrated within graphics processor 2508 or system proxy core 2510.

[0275] In some embodiments, the ring-based interconnect unit 2512 is used to couple internal components of the processor 2500. However, alternative interconnect units, such as point-to-point interconnects, switched interconnects, or other technologies, including those known in the art, may be used. In some embodiments, the graphics processor 2508 is coupled to the ring interconnect 2512 via I / O link 2513.

[0276] The exemplary I / O link 2513 represents at least one of a variety of I / O interconnects, including on-package I / O interconnects that facilitate communication between various processor components and high-performance embedded memory modules 2518 (such as eDRAM modules). In some embodiments, each processor core in processor cores 2502A-2502N and graphics processor 2508 uses embedded memory module 2518 as a shared final-level cache.

[0277] In some embodiments, processor cores 2502A-2502N are homogeneous cores executing the same instruction set architecture. In another embodiment, processor cores 2502A-2502N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more of processor cores 2502A-2502N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, processor cores 2502A-2502N are heterogeneous in terms of microarchitecture, wherein one or more cores with relatively high power consumption are coupled to one or more power cores with lower power consumption. Additionally, processor 2500 can be implemented on one or more chips or as a SoC integrated circuit having the components shown among other components.

[0278] Figure 26This is a block diagram of a graphics processor 2600, which may be a discrete graphics processing unit or a graphics processor integrated with multiple processing cores. In some embodiments, the graphics processor communicates via a memory-mapped I / O interface to registers on the graphics processor and using commands placed in processor memory. In some embodiments, the graphics processor 2600 includes a memory interface 2614 for accessing memory. The memory interface 2614 may be an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0279] In some embodiments, the graphics processor 2600 further includes a display controller 2602 for driving display output data to a display device 2620. The display controller 2602 includes hardware for one or more overlapping planes of the display and a composition of multi-layer video or user interface elements. In some embodiments, the graphics processor 2600 includes a video codec engine 2606 for encoding, decoding, or transcoding media to, from, or between one or more media encoding formats, including but not limited to Moving Picture Experts Group (MPEG) formats (such as MPEG-2), Advanced Video Coding (AVC) formats (such as H.264 / MPEG-4 AVC), and SMPTE 421 M / VC-1 and Joint Group of Picture Experts (JPEG) formats (such as JPEG and Motion JPEG (MJPEG)).

[0280] In some embodiments, the graphics processor 2600 includes a block image transfer (BLIT) engine 2604 for performing two-dimensional (2D) rasterizer operations, including, for example, bit boundary block transfer. However, in one embodiment, 2D graphics operations are performed using one or more components of a graphics processing engine (GPE) 2610. In some embodiments, the GPE 2610 is a computational engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0281] In some embodiments, GPE 310 includes a 3D pipeline 2612 for performing 3D operations such as rendering 3D images and scenes using processing functions that act on the shapes of 3D primitives (e.g., rectangles, triangles, etc.). The 3D pipeline 2612 includes programmable and fixed functional elements that perform various tasks within the elements and / or generate a large number of execution threads for the 3D / media subsystem 2615. While the 3D pipeline 2612 can be used to perform media operations, embodiments of GPE 2610 also include a media pipeline 2616 specifically designed for performing media operations such as video post-processing and image enhancement.

[0282] In some embodiments, the media pipeline 2616 includes fixed-function or programmable logic units to perform one or more specialized media operations, such as video decoding acceleration, video deinterleaving, and video encoding acceleration, in place of or on behalf of the video codec engine 2606. In some embodiments, the media pipeline 2616 additionally includes thread massing units to mass-produce threads for execution on the 3D / media subsystem 2615. The mass-produced threads perform computations for media operations on one or more graphics execution units included in the 3D / media subsystem 2615.

[0283] In some embodiments, the 3D / media subsystem 2615 includes logic for executing threads massed by the 3D pipeline 2612 and the media pipeline 2616. In one embodiment, the pipelines send thread execution requests to the 3D / media subsystem 2615, which includes thread dispatch logic for arbitrating various requests and dispatching them to available thread execution resources. Execution resources include an array of graphics execution units for processing 3D and media threads. In some embodiments, the 3D / media subsystem 2615 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory (including registers and addressable memory) for sharing data and storing output data among threads.

[0284] Additional demonstration graphics processing engine

[0285] Figure 27 This is a block diagram of a graphics processing engine 2710 of a graphics processor according to some embodiments. In one embodiment, the graphics processing engine (GPE) 2710 is... Figure 26 The image shows a version of GPE 2610. Figure 27Elements having the same reference numerals (or names) as elements in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein. For example, shown Figure 26 The 3D pipeline 2612 and media pipeline 2616. The media pipeline 2616 is optional in some embodiments of the GPE 2710 and may not be explicitly included within the GPE 2710. For example, and in at least one embodiment, a separate media and / or image processor is coupled to the GPE 2710.

[0286] In some embodiments, GPE 2710 is coupled to or includes command streamer 2703, which provides a command stream to 3D pipeline 2612 and / or media pipeline 2616. In some embodiments, command streamer 2703 is coupled to memory, which may be system memory, or one or more of internal cache memory and shared cache memory. In some embodiments, command streamer 2703 receives commands from memory and sends commands to 3D pipeline 2612 and / or media pipeline 2616. The commands are instructions obtained from a ring buffer that stores commands for 3D pipeline 2612 and media pipeline 2616. In one embodiment, the ring buffer may additionally include a batch command buffer that stores batches of multiple commands. Commands for 3D pipeline 2612 may also include references to data stored in memory, such as, but not limited to, vertex and geometry data for 3D pipeline 2612 and / or image data and memory objects for media pipeline 2616. The 3D pipeline 2612 and the media pipeline 2616 process commands and data by performing operations via logic within the respective pipelines or by dispatching one or more execution threads to the graphics core array 2714.

[0287] In various embodiments, the 3D pipeline 2612 can execute one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core array 2714. The graphics core array 2714 provides a unified block of execution resources. The multipurpose execution logic (e.g., execution units) within the graphics core array 2714 includes support for various 3D API shader languages ​​and can execute multiple concurrent execution threads associated with multiple shaders.

[0288] In some embodiments, the graphics core array 2714 further includes execution logic for performing media functions such as video and / or image processing. In one embodiment, in addition to graphics processing operations, the execution unit additionally includes general-purpose logic programmable to perform parallel general-purpose computing operations. The general-purpose logic may be related to… Figure 24 (Multiple) processor cores 2407 or such Figure 25 The general logic within the processor cores 2502A-2502N performs processing operations in parallel or in combination.

[0289] Output data generated by threads executing on the graphics core array 2714 can be output to memory in a uniform return buffer (URB) 2718. The URB 2718 can store data for multiple threads. In some embodiments, the URB 2718 can be used to send data between different threads executing on the graphics core array 2714. In some embodiments, the URB 2718 can also be used for synchronization between fixed-function logic within shared-function logic 2720 and threads on the graphics core array.

[0290] In some embodiments, the graphics core array 2714 is scalable, such that the array includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance level of the GPE 2710. In one embodiment, the execution resources are dynamically scalable, allowing execution resources to be enabled or disabled as needed.

[0291] The graphics core array 2714 is coupled to shared function logic 2720, which includes multiple resources shared among the graphics cores in the graphics core array. Shared functions within the shared function logic 2720 are hardware logic units that provide specialized supplementary functionality to the graphics core array 2714. In various embodiments, the shared function logic 2720 includes, but is not limited to, sampler 2721, math 2722, and inter-thread communication (ITC) 2723 logic. Additionally, some embodiments implement one or more caches 2725 within the shared function logic 2720. Shared functions are implemented when the requirement for a given specialized function is insufficient to be included within the graphics core array 2714. Alternatively, a single instance of the specialized function is implemented as a separate entity within the shared function logic 2720 and shared among execution resources within the graphics core array 2714. The exact set of functions shared among and included within the graphics core array 2714 varies between embodiments.

[0292] Figure 28 This is a block diagram of another embodiment of the graphics processor 2800. Figure 28Elements having the same reference numerals (or names) as elements in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein.

[0293] In some embodiments, the graphics processor 2800 includes a ring interconnect 2802, a pipeline front-end 2804, a media engine 2837, and graphics cores 2880A-2880N. In some embodiments, the ring interconnect 2802 couples the graphics processor to other processing units, which include other graphics processors or one or more general-purpose processor cores. In some embodiments, the graphics processor is one of many processors integrated within a multi-core processing system.

[0294] In some embodiments, the graphics processor 2800 receives multiple batches of commands via a ring interconnect 2802. Incoming commands are interpreted by a command streamer 2803 in a pipeline front-end 2804. In some embodiments, the graphics processor 2800 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores(a plurality of) 2880A-2880N. For 3D geometry processing commands, the command streamer 2803 supplies commands to a geometry pipeline 2836. For at least some media processing commands, the command streamer 2803 supplies commands to a video front-end 2834, which is coupled to a media engine 2837. In some embodiments, the media engine 2837 includes a video quality engine (VQE) 2830 for video and image post-processing and a multi-format encoding / decoding (MFX) engine 2833 for providing hardware-accelerated media data encoding and decoding. In some embodiments, the geometry pipeline 2836 and the media engine 2837 each generate execution threads for thread execution resources provided by at least one graphics core 2880A.

[0295] In some embodiments, the graphics processor 2800 includes scalable thread execution resources featuring modular cores 2880A-2880N (sometimes referred to as core slices), each of which has multiple sub-cores 2850A-550N, 2860A-2860N (sometimes referred to as core sub-slices). In some embodiments, the graphics processor 2800 may have any number of graphics cores 2880A to 2880N. In some embodiments, the graphics processor 2800 includes a graphics core 2880A, which has at least a first sub-core 2850A and a second sub-core 2860A. In other embodiments, the graphics processor is a low-power processor with a single sub-core (e.g., 2850A). In some embodiments, the graphics processor 2800 includes multiple graphics cores 2880A-2880N, each including a set of first sub-cores 2850A-2850N and a set of second sub-cores 2860A-2860N. Each sub-core in the first group of sub-cores 2850A-2850N includes at least a first set of execution units 2852A-2852N and media / texture samplers 2854A-2854N. Each sub-core in the second group of sub-cores 2860A-2860N includes at least a second set of execution units 2862A-2862N and samplers 2864A-2864N. In some embodiments, each sub-core 2850A-2850N and 2860A-2860N shares a set of shared resources 2870A-2870N. In some embodiments, the shared resources include shared cache memory and pixel operation logic. Other shared resources may also be included in various embodiments of the graphics processor.

[0296] Additional demonstration implementation unit

[0297] Figure 29 Thread execution logic 2900 is shown, which includes an array of processing elements employed in some embodiments of GPE. Figure 29 Elements having the same reference numerals (or names) as elements in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein.

[0298] In some embodiments, thread execution logic 2900 includes a shader processor 2902, a thread dispatcher 2904, an instruction cache 2906, a scalable array of execution units including a plurality of execution units 2908A-2908N, a sampler 2910, a data cache 2912, and a data port 2914. In one embodiment, the scalable array of execution units can be dynamically scaled by enabling or disabling one or more execution units (e.g., any of execution units 2908A, 2908B, 2908C, 2908D to 2908N-1 and 2908N) based on workload computational requirements. In one embodiment, the included components are interconnected via an interconnect structure linking to each of the components. In some embodiments, thread execution logic 2900 includes one or more connections to memory (such as system memory or cache memory) via the instruction cache 2906, the data port 2914, the sampler 2910, and one or more of the execution units 2908A-2908N. In some embodiments, each execution unit (e.g., 2908A) is an independent, programmable, general-purpose computing unit capable of executing multiple concurrent hardware threads to process multiple data elements in parallel for each thread. In various embodiments, the array of execution units 2908A-2908N is scalable to include any number of individual execution units.

[0299] In some embodiments, execution units 2908A-2908N are primarily used to execute shader programs. Shader processor 2902 can handle various shader programs and dispatch execution threads associated with the shader programs via thread dispatcher 2904. In one embodiment, the thread dispatcher includes logic for arbitrating thread requests from the graphics and media pipeline and instantiating the requested thread on one or more execution units in execution units 2908A-2908N. For example, a geometry pipeline (e.g., Figure 28 (2836) can dispatch vertex, surface subdivision, or geometry shader to thread execution logic 2900 ( Figure 29 This is used for processing. In some embodiments, the thread dispatcher 2904 can also handle a large number of requests generated from runtime threads executing shader programs.

[0300] In some embodiments, execution units 2908A-2908N support instruction sets including native support for many standard 3D graphics shader instructions, enabling the execution of shader programs from graphics libraries (e.g., Direct3D and OpenGL) with minimal translation. Execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general-purpose processing (e.g., computation and media shaders). Each of the execution units 2908A-2908N has the capability for multi-issue single-instruction multiple-data (SIMD) execution, and multi-threaded operation enables an efficient execution environment in the face of memory accesses with high latency. Each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread state. For pipelines with integer, single- and double-precision floating-point operations, SIMD branching capabilities, logical operations, transcendental operations, and other miscellaneous operation capabilities, execution is multi-issue per clock cycle. While waiting for data from either memory or a shared function, the dependency logic within execution units 2908A-2908N causes the waiting thread to sleep until the requested data has been returned. While the waiting thread is sleeping, hardware resources may be dedicated to processing other threads. For example, during the latency associated with vertex shader operations, the execution unit may execute operations on a pixel shader, fragment shader, or another type of shader program that includes different vertex shaders.

[0301] Each execution unit in the execution units 2908A-2908N operates on an array of data elements. The number of data elements is the "execution size," or the number of channels used for instructions. An execution channel is a logical unit used for execution of data element access, masking, and flow control within instructions. The number of channels may be independent of the number of physical arithmetic logic units (ALUs) or floating-point units (FPUs) for a particular graphics processor. In some embodiments, the execution units 2908A-2908N support both integer and floating-point data types.

[0302] The execution unit instruction set includes SIMD instructions. Various data elements can be stored in registers as compressed data types, and the execution unit will process these elements based on their data size. For example, when operating on a 256-bit wide vector, the 256-bit vector is stored in a register, and the execution unit operates on the vector as four separate 64-bit compressed data elements (four times the word length (QW) size), eight separate 32-bit compressed data elements (double word (DW) size), sixteen separate 16-bit compressed data elements (word (W) size), or thirty-two separate 8-bit data elements (byte (B) size). However, different vector widths and register sizes are possible.

[0303] One or more internal instruction caches (e.g., 2906) are included in the thread execution logic 2900 to cache thread instructions for the execution unit. In some embodiments, one or more data caches (e.g., 2912) are included to cache thread data during thread execution. In some embodiments, sampler 2910 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, sampler 2910 includes dedicated texture or media sampling functions to process texture or media data during the sampling process before providing sampled data to the execution unit.

[0304] During execution, the graphics and media pipeline sends thread initiation requests to thread execution logic 2900 via thread mass production and dispatch logic. Once a set of geometric objects has been processed and rasterized into pixel data, pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within shader processor 2902 is invoked to further compute output information and write the results to output surfaces (e.g., color buffer, depth buffer, stencil buffer, etc.). In some embodiments, the pixel shader or fragment shader computes values ​​of various vertex attributes to be interpolated across the rasterized objects. In some embodiments, the pixel processor logic within shader processor 2902 then executes a pixel or fragment shader program provided by an application programming interface (API). To execute the shader program, shader processor 2902 dispatches threads to execution units (e.g., 2908A) via thread dispatcher 2904. In some embodiments, pixel shader 2902 uses texture sampling logic in sampler 2910 to access texture data in a texture map stored in memory. Arithmetic operations on texture data and input geometry data calculate pixel color data for each geometric fragment, or discard one or more pixels to avoid further processing.

[0305] In some embodiments, data port 2914 provides a memory access mechanism for thread execution logic 2900 to output processed data to memory for processing on the graphics processor output pipeline. In some embodiments, data port 2914 includes or is coupled to one or more cache memories (e.g., data cache 2912) to cache data via the data port for memory access.

[0306] Figure 30This is a block diagram illustrating a graphics processor instruction format 3000 according to some embodiments. In one or more embodiments, the graphics processor execution unit supports an instruction set having instructions employing multiple formats. Solid lines indicate components generally included in the execution unit instructions, while dashed lines include optional components or those only included in a subset of the instructions. In some embodiments, the instruction format 3000 described and illustrated are macro instructions, as they are instructions supplied to the execution unit, as opposed to micro-operations caused by instruction decoding once the instruction is processed.

[0307] In some embodiments, the graphics processor execution unit natively supports instructions using a 128-bit instruction format 3010. A 64-bit compressed instruction format 3030 may be available for some instructions, depending on the selected instruction, instruction options, and number of operands. The native 128-bit instruction format 710 provides access to all instruction options, while some options and operations are restricted to the 64-bit format 3030. The native instructions available in the 64-bit format 3030 vary depending on the embodiment. In some embodiments, instructions are partially compressed using a set of index values ​​in an index field 3013. The execution unit hardware references a set of compression tables based on the index values ​​and uses the output of the compression tables to reconstruct the native instructions using the 128-bit instruction format 3010.

[0308] For each format, the instruction opcode 3012 defines the operation to be performed by the execution unit. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an add instruction, the execution unit performs a simultaneous add operation across each color channel, where each color channel represents a texture element or a picture element. By default, the execution unit executes each instruction across all data channels of the operand. In some embodiments, the instruction control field 3014 enables control over certain execution options, such as channel selection (e.g., prediction) and data channel ordering (e.g., mixing). For instructions employing the 128-bit instruction format 3010, the execution size field 3016 limits the number of data channels that will be executed in parallel. In some embodiments, the execution size field 3016 is not available for use in the 64-bit compressed instruction format 3030.

[0309] Some execution unit instructions have up to three operands, including two source operands—src0 3020 and src1 3022—and one destination 3018. In some embodiments, the execution unit supports dual-destination instructions, where one of the destinations is implicit. Data manipulation instructions may have a third source operand (e.g., SRC2 3024), where the instruction opcode 3012 determines the number of source operands. The last source operand of the instruction may be an immediate (e.g., hard-coded) value passed using the instruction.

[0310] In some embodiments, the 128-bit instruction format 3010 includes an access / addressing mode field 3026 that specifies, for example, whether to use direct register addressing mode or indirect register addressing mode. When using direct register addressing mode, the register addresses of one or more operands are provided directly by bits in the instruction.

[0311] In some embodiments, the 128-bit instruction format 3010 includes an access / addressing mode field 3026 that specifies the addressing mode and / or access mode of the instruction. In one embodiment, the access mode is used to define the data access alignment for the instruction. Some embodiments support access modes that include 16-byte aligned access modes and 1-byte aligned access modes, wherein the byte alignment of the access mode determines the access alignment of the instruction operands. For example, in a first mode, the instruction may use byte-aligned addressing for both the source and destination operands, and in a second mode, the instruction may use 16-byte aligned addressing for both the source and destination operands.

[0312] In one embodiment, the addressing mode portion of the access / addressing mode field 3026 determines whether the instruction should use direct or indirect addressing. When using direct register addressing mode, bits in the instruction directly provide the register addresses of one or more operands. When using indirect register addressing mode, the register addresses of one or more operands can be calculated based on the address register value and the address immediate number field in the instruction.

[0313] In some embodiments, instructions are grouped based on the 3012-bit opcode field to simplify opcode decoding 3040. For an 8-bit opcode, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The precise opcode grouping shown is merely illustrative. In some embodiments, the move and logic opcode group 3042 includes data move and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logic group 3042 shares five most significant bits (MSB), where move (mov) instructions are in the form of 0000xxxxb and logic instructions are in the form of 0001xxxxb. The flow control instruction group 3044 (e.g., call, jump (jmp)) includes instructions in the form of 0010xxxxb (e.g., 0x20). The miscellaneous instruction group 3046 includes a mixture of instructions, including synchronization instructions (e.g., wait, send) in the form of 0011xxxxb (e.g., 0x30). Parallel math instruction group 3048 includes component-based arithmetic instructions (e.g., addition, multiplication (mul)) in the form of 0100xxxxb (e.g., 0x40). Parallel math group 3048 performs arithmetic operations in parallel across data channels. Vector math group 3050 includes arithmetic instructions (e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). Vector math group performs arithmetic on vector operands, such as dot product calculations.

[0314] Additional sample graphical pipeline

[0315] Figure 31 This is a block diagram of another embodiment of the graphics processor 3100. Figure 31 Elements having the same reference numerals (or names) as elements in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein.

[0316] In some embodiments, the graphics processor 3100 includes a graphics pipeline 3120, a media pipeline 3130, a display engine 3140, thread execution logic 3150, and a rendering output pipeline 3170. In some embodiments, the graphics processor 3100 is a graphics processor within a multi-core processing system including one or more general-purpose processing cores. The graphics processor is controlled by writing to registers to one or more control registers (not shown) or via commands issued to the graphics processor 3100 through a ring interconnect 3102. In some embodiments, the ring interconnect 3102 couples the graphics processor 3100 to other processing components, such as other graphics processors or general-purpose processors. Commands from the ring interconnect 3102 are interpreted by a command streamer 3103, which supplies instructions to individual components of the graphics pipeline 3120 or the media pipeline 3130.

[0317] In some embodiments, command streamer 3103 guides the operation of vertex acquirer 3105, which reads vertex data from memory and executes vertex processing commands provided by command streamer 3103. In some embodiments, vertex acquirer 3105 provides vertex data to vertex shader 3107, which performs coordinate space transformation and lighting operations on each vertex. In some embodiments, vertex acquirer 3105 and vertex shader 3107 execute vertex processing instructions by dispatching execution threads to execution units 3152A-3152B via thread dispatcher 3131.

[0318] In some embodiments, execution units 3152A-3152B are arrays of vector processors having an instruction set for performing graphics and media operations. In some embodiments, execution units 3152A-3152B have an attached L1 cache 3151, which is array-specific or shared between arrays. This cache can be configured as a data cache, an instruction cache, or a single cache, which is partitioned to contain data and instructions in different partitions.

[0319] In some embodiments, the graphics pipeline 3120 includes a tessellation component for performing hardware-accelerated tessellation of 3D objects. In some embodiments, a programmable shell shader 811 configures the tessellation operation. A programmable domain shader 817 provides back-end evaluation of the tessellation output. A tessellation unit 3113 operates in the direction of the shell shader 3111 and includes dedicated logic for generating a set of detailed geometric objects based on a coarse geometry model, which is provided as input to the graphics pipeline 3120. In some embodiments, the tessellation components (e.g., shell shader 3111, tessellation unit 3113, and domain shader 3117) can be bypassed if tessellation is not used.

[0320] In some embodiments, the complete geometry object may be processed by the geometry shader 3119 via one or more threads dispatched to execution units 3152A-3152B, or it may proceed directly to the clipper 3129. In some embodiments, the geometry shader operates on the entire geometry object rather than on vertices or vertex patches as in previous stages of the graphics pipeline. If tessellation is disabled, the geometry shader 3119 receives input from the vertex shader 3107. In some embodiments, the geometry shader 3119 may be programmed by a geometry shader program to perform geometric tessellation when the tessellation unit is disabled.

[0321] Prior to rasterization, clipper 3129 processes vertex data. Clipper 3129 can be a fixed-function clipper or a programmable clipper with clipping and geometry shader capabilities. In some embodiments, the rasterizer and depth testing unit 3173 in the rendering output pipeline 3170 dispatch pixel shaders to convert geometric objects into their per-pixel representations. In some embodiments, pixel shader logic is included in thread execution logic 3150. In some embodiments, an application can bypass the rasterizer and depth testing unit 3173 and access unrasterized vertex data via outgoing unit 3123.

[0322] The graphics processor 3100 has an interconnect bus, interconnect structure, or some other interconnect mechanism that allows data and messages to be transferred between the main components of the processor. In some embodiments, execution units 3152A-3152B and(multiple) associated caches 3151, texture and media samplers 3154, and texture / sampler cache 3158 are interconnected via data port 3156 to perform memory accesses and communicate with the processor's rendering output pipeline components. In some embodiments, samplers 3154, caches 3151, 3158, and execution units 3152A-3152B each have a separate memory access path.

[0323] In some embodiments, the rendering output pipeline 3170 includes a rasterizer and a depth testing unit 3173 that converts vertex-based objects into associated pixel-based representations. In some embodiments, the rasterizer logic includes a windower / mask unit for performing fixed-function triangle and line rasterization. Associated rendering cache 3178 and depth cache 3179 are also available in some embodiments. Pixel manipulation unit 3177 performs pixel-based operations on the data; however, in some instances, pixel operations associated with 2D operations (e.g., using mixed bit-block image transfer) are performed by the 2D engine 3141, or alternatively by the display controller 3143 using an overlay display plane at display time. In some embodiments, a shared L3 cache 3175 is available for all graphics components, allowing data to be shared without using main system memory.

[0324] In some embodiments, the graphics processor media pipeline 3130 includes a media engine 3137 and a video front-end 3134. In some embodiments, the video front-end 3134 receives pipeline commands from a command streamer 3103. In some embodiments, the media pipeline 3130 includes a separate command streamer. In some embodiments, the video front-end 3134 processes a media command before sending it to the media engine 3137. In some embodiments, the media engine 3137 includes a thread mass generation function to mass-generate threads for dispatch to thread execution logic 3150 via a thread dispatcher 3131.

[0325] In some embodiments, the graphics processor 3100 includes a display engine 3140. In some embodiments, the display engine 3140 is external to the processor 3100 and coupled to the graphics processor via a ring interconnect 3102 or some other interconnect bus or structure. In some embodiments, the display engine 3140 includes a 2D engine 3141 and a display controller 3143. In some embodiments, the display engine 3140 includes dedicated logic capable of operating independently of the 3D pipeline. In some embodiments, the display controller 3143 is coupled to a display device (not shown), which may be a system-integrated display device (such as in a laptop computer) or an external display device attached via a display device connector.

[0326] In some embodiments, the graphics pipeline 3120 and media pipeline 3130 may be configured to perform operations based on multiple graphics and media programming interfaces and are not specific to any one application programming interface (API). In some embodiments, driver software for the graphics processor translates API calls specific to a particular graphics or media library into commands that can be processed by the graphics processor. In some embodiments, support is provided for OpenGL, OpenCL, and / or Vulkan graphics and computing APIs, all from the Khronos Group. In some embodiments, support may also be provided for the Direct3D library from Microsoft Corporation. In some embodiments, combinations of these libraries may be supported. Support may also be provided for the open-source computer vision library (OpenCV). Future APIs with compatible 3D pipelines will also be supported if a pipeline mapping from future APIs to the graphics processor pipeline can be made.

[0327] Graphical Pipeline Programming

[0328] Figure 32A This is a block diagram illustrating a graphics processor command format 3200 according to some embodiments. Figure 32B This is a block diagram illustrating a graphics processor command sequence 3210 according to an embodiment. Figure 32ASolid lines in the diagram indicate components that are generally included in the drawing command, while dashed lines indicate optional components or components that are included only in a subset of the drawing command. Figure 32A The example graphics processor command format 3200 includes data fields for identifying the target client 3202 of the command, the command operation code (opcode) 3204, and the command's associated data 3206. Some commands also include a sub-opcode 3205 and a command size 3208.

[0329] In some embodiments, client 3202 specifies a client unit of a graphics device that processes command data. In some embodiments, a graphics processor command parser examines the client field of each command to adjust further processing of the command and routes the command data to the appropriate client unit. In some embodiments, the graphics processor client unit includes a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline for processing commands. Once a command is received by a client unit, the client unit reads opcode 3204 and sub-opcode 3205 (if present) to determine the operation to be performed. The client unit uses information in data field 3206 to execute the command. For some commands, an explicit command size 3208 is expected to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some commands in the command based on the command opcode. In some embodiments, commands are aligned via multiples of double words.

[0330] Figure 32B The flowchart illustrates an exemplary graphics processor command sequence 3210. In some embodiments, software or firmware of a data processing system featuring an embodiment of the graphics processor uses a version of the illustrated command sequence to establish, execute, and terminate a set of graphics operations. Sample command sequences are shown and described for illustrative purposes only, as embodiments are not limited to these specific commands or this command sequence. Moreover, the commands may be issued as a batch of commands in a command sequence, such that the graphics processor will process the sequence of commands at least partially simultaneously.

[0331] In some embodiments, the graphics processor command sequence 3210 may begin with a pipeline dump clearing command 3212 to cause any active graphics pipeline to complete its current pending commands. In some embodiments, the 3D pipeline 3222 and the media pipeline 3224 do not operate simultaneously. Pipeline dump clearing is performed to cause any pending commands to be completed by the active graphics pipeline. In response to pipeline dump clearing, the command parser for the graphics processor will pause command processing until the active graphics engine completes its pending operations and the associated read cache is invalidated. Optionally, any data marked as 'dirty' in the render cache may be dumped to memory. In some embodiments, pipeline dump clearing command 3212 may be used for pipeline synchronization or before placing the graphics processor into a low-power state.

[0332] In some embodiments, a pipeline selection command 3213 is used when a sequence of commands requires the graphics processor to explicitly switch between pipelines. In some embodiments, the pipeline selection command 3213 is only required once within the execution context before a pipeline command is issued, unless the context is issuing commands for two pipelines. In some embodiments, a pipeline dump clearing command 3212 is required immediately preceding the pipeline switch via the pipeline selection command 3213.

[0333] In some embodiments, pipeline control command 3214 configures a graphics pipeline for operation and programs the 3D pipeline 3222 and the media pipeline 3224. In some embodiments, pipeline control command 3214 configures pipeline states for active pipelines. In one embodiment, pipeline control command 3214 is used for pipeline synchronization and for clearing data from one or more caches within an active pipeline before processing a batch of commands.

[0334] In some embodiments, commands specific to return buffer state 3216 are used to configure a set of return buffers for corresponding pipeline write data. Some pipeline operations require the allocation, selection, or configuration of one or more return buffers that write intermediate data to the one or more return buffers during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, return buffer state 3216 includes selecting the size and number of return buffers to be used for a set of pipeline operations.

[0335] The remaining commands in the command sequence vary depending on the active pipeline used for the operation. Based on pipeline determination 3220, the command sequence is suitable for either the 3D pipeline 3222 starting at 3D pipeline state 3230 or the media pipeline 3224 starting at media pipeline state 3240.

[0336] Commands for configuring 3D pipeline states 3230 include 3D state setting commands for vertex buffer states, vertex element states, constant color states, depth buffer states, and other state variables to be configured before processing 3D primitive commands. The values ​​of these commands are determined at least in part based on the specific 3D API in use. In some embodiments, the 3D pipeline state 3230 commands can also selectively disable or bypass certain pipeline elements if those elements will not be used.

[0337] In some embodiments, the 3D primitive 3232 command is used to submit 3D primitives to be processed by the 3D pipeline. The commands and associated parameters passed to the graphics processor via the 3D primitive 3232 command are forwarded to the vertex fetching function in the graphics pipeline. The vertex fetching function uses the 3D primitive 3232 command data to generate a vertex data structure. The vertex data structure is stored in one or more return buffers. In some embodiments, the 3D primitive 3232 command is used to perform vertex operations on the 3D primitives via a vertex shader. To process the vertex shader, the 3D pipeline 3222 dispatches shader execution threads to the graphics processor execution unit.

[0338] In some embodiments, the 3D pipeline 3222 is triggered by executing command 3234 or an event. In some embodiments, register writing triggers command execution. In some embodiments, execution is triggered by a 'go' or 'kick' command in a command sequence. In one embodiment, pipeline synchronization commands are used to trigger command execution to dump and clear the command sequence through the graphics pipeline. The 3D pipeline performs geometric processing on 3D primitives. Once the operations are complete, the resulting geometric objects are rasterized and the pixel engine colors the resulting pixels. Additional commands for controlling pixel coloring and pixel backend operations may also be included for those operations.

[0339] In some embodiments, when performing media operations, a sequence of graphics processor commands 3210 follows the media pipeline 3224 path. Generally, the specific use and manner of programming the media pipeline 3224 depends on the media or computational operation to be performed. During media decoding, specific media decoding operations can be offloaded to this media pipeline. In some embodiments, the media pipeline can also be bypassed, and media decoding can be performed wholly or partially using resources provided by one or more general-purpose processing cores. In one embodiment, the media pipeline also includes elements for general-purpose graphics processing unit (GPGPU) operations, wherein the graphics processor is used to perform SIMD vector operations using computational shader programs not explicitly associated with rendering graphics primitives.

[0340] In some embodiments, the media pipeline 3224 is configured in a manner similar to that of the 3D pipeline 3222. A set of commands for configuring the media pipeline state 3240 is dispatched or placed in a command queue before the media object command 3242. In some embodiments, the media pipeline state command 3240 includes data for configuring media pipeline elements that will be used to process media objects. This includes data for configuring video decoding and video encoding logic within the media pipeline, such as encoding or decoding formats. In some embodiments, the media pipeline state command 3240 also supports the use of one or more pointers to "indirect" state elements that contain a set of state settings.

[0341] In some embodiments, media object command 3242 supplies pointers to media objects for processing by the media pipeline. The media object includes a memory buffer containing video data to be processed. In some embodiments, all media pipeline states must be valid before issuing media object command 3242. Once the pipeline states are configured and media object command 3242 is queued, media pipeline 3224 is triggered via execution command 3244 or an equivalent execution event (e.g., register write). The output from media pipeline 3224 can then be post-processed by operations provided by 3D pipeline 3222 or media pipeline 3224. In some embodiments, GPGPU operations are configured and executed in a manner similar to media operations.

[0342] Graphical software architecture

[0343] Figure 33 An exemplary graphics software architecture of a data processing system 3300 according to some embodiments is shown. In some embodiments, the software architecture includes a 3D graphics application 3310, an operating system 3320, and at least one processor 3330. In some embodiments, the processor 3330 includes a graphics processor 3332 and one or more general-purpose processor cores 3334. The graphics application 3310 and the operating system 3320 each execute in the system memory 3350 of the data processing system.

[0344] In some embodiments, the 3D graphics application 3310 includes one or more shader programs including shader instructions 3312. The shader language instructions may be in a high-level shader language, such as High-Level Shading Language (HLSL) or OpenGL Shading Language (GLSL). The application also includes executable instructions 3314 in machine language suitable for execution by a general-purpose processor core 3334. The application also includes graphics objects 3316 defined by vertex data.

[0345] In some embodiments, the operating system 3320 is a Microsoft® Windows® operating system from Microsoft Corporation, a proprietary UNIX-like operating system, or an open-source UNIX-like operating system using a variant of the Linux kernel. The operating system 3320 may support graphics APIs 3322, such as the Direct3D API, OpenGL API, or Vulkan API. When the Direct3D API is in use, the operating system 3320 uses a front-end shader compiler 3324 to compile any shader instructions 3312 in HLSL into a lower-level shader language. This compilation may be just-in-time (JIT) compilation, or the application may perform shader pre-compilation. In some embodiments, high-level shaders are compiled into low-level shaders during the compilation of the 3D graphics application 3310. In some embodiments, the shader instructions 3312 are provided in an intermediate form, such as a version of the standard Portable Intermediate Representation (SPIR) used by the Vulkan API.

[0346] In some embodiments, the user-mode graphics driver 3326 includes a back-end shader compiler 3327 for translating shader instructions 3312 into a hardware-specific representation. When the OpenGL API is in use, shader instructions 3312 in the GLSL high-level language are passed to the user-mode graphics driver 3326 for compilation. In some embodiments, the user-mode graphics driver 3326 uses operating system kernel-mode functionality 3328 to communicate with the kernel-mode graphics driver 3329. In some embodiments, the kernel-mode graphics driver 3329 communicates with the graphics processor 3332 to dispatch commands and instructions.

[0347] IP core implementation

[0348] One or more aspects of at least one embodiment can be implemented by representative code stored on a machine-readable medium that represents and / or defines logic within an integrated circuit, such as a processor. For example, the machine-readable medium may include instructions representing various logics within a processor. When read by a machine, these instructions can cause the machine to manufacture logic for performing the techniques described herein. Such a representation (referred to as an "IP core") is a reusable unit of logic for an integrated circuit that can be stored on a tangible, machine-readable medium as a hardware model describing the structure of the integrated circuit. The hardware model can be supplied to various consumer or manufacturing facilities that load the hardware model onto a manufacturing machine that manufactures the integrated circuit. Integrated circuits can be manufactured such that the circuit performs the operations described in association with any embodiment of the embodiments described herein.

[0349] Figure 34This is a block diagram illustrating an IP core development system 3400 that can be used to fabricate integrated circuits to perform operations, according to an embodiment. The IP core development system 3400 can be used to generate modular, reusable designs that can be incorporated into larger designs or used to build entire integrated circuits (e.g., SOC integrated circuits). Design facility 3430 can generate software simulations 3410 of the IP core designs using high-level programming languages ​​(e.g., C / C++). Software simulation 3410 can be used to design, test, and verify the behavior of the IP cores using simulation model 3412. Simulation model 3412 can include functional, behavioral, and / or timing simulations. Register transfer level (RTL) designs 3415 can then be created or synthesized from simulation model 3412. RTL design 3415 is an abstraction of the behavior of an integrated circuit that models the flow of digital signals between hardware registers, including associated logic performed using the modeled digital signals. In addition to RTL design 3415, lower-level designs at the logic level or transistor level can also be created, designed, or synthesized. Therefore, specific details of the initial design and simulation may vary.

[0350] The RTL design 3415 or an equivalent can be further synthesized into a hardware model 3420 by the design facility. This hardware model 3420 can be represented using a hardware description language (HDL) or some other representation of the physical design data. The HDL can be further simulated or tested to verify the IP core design. The IP core design can be stored in non-volatile memory 3440 (e.g., hard disk, flash memory, or any non-volatile storage medium) for delivery to a third-party manufacturing facility 3465. Alternatively, the IP core design can be transmitted via a wired connection 3450 or a wireless connection 3460 (e.g., via the Internet). The manufacturing facility 3465 can then manufacture an integrated circuit at least partially based on the IP core design. The manufactured integrated circuit can be configured to perform operation according to at least one embodiment described herein.

[0351] Demonstration System-on-Chip Integrated Circuit

[0352] Figures 35-37 Exemplary integrated circuits and associated graphics processors that can be fabricated using one or more IP cores according to various embodiments described herein are shown. In addition to those shown, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0353] Figure 35This is a block diagram illustrating an exemplary system-on-a-chip integrated circuit 3500 that can be fabricated using one or more IP cores according to an embodiment. The exemplary integrated circuit 3500 includes one or more application processors 3505 (e.g., CPU), at least one graphics processor 3510, and may additionally include an image processor 3515 and / or a video processor 3520, any of which may be modular IP cores from the same or multiple different design facilities. The integrated circuit 3500 includes peripheral or bus logic, including a USB controller 3525, a UART controller 3530, an SPI / SDIO controller 3535, and an I / O controller. 2 S / I 2 C controller 3540. Additionally, the integrated circuit may include a display device 3545 coupled to one or more of a High Definition Multimedia Interface (HDMI) controller 3550 and a Mobile Industry Processor Interface (MIPI) display interface 3555. Storage may be provided by a flash memory subsystem 3560 including flash memory and a flash memory controller. A memory interface may be provided via a memory controller 3565 for access to SDRAM or SRAM memory devices. Some integrated circuits additionally include an embedded security engine 3570.

[0354] Figure 36 This is a block diagram illustrating an exemplary graphics processor 3610, a system-on-a-chip integrated circuit that can be fabricated using one or more IP cores according to an embodiment. The graphics processor 3610 may be... Figure 36 A variant of the graphics processor 3610. The graphics processor 3610 includes a vertex processor 3605 and one or more fragment processors 3615A-3615N (e.g., 3615A, 3615B, 3615C, 3615D to 3615N-1 and 3615N). The graphics processor 3610 can execute different shader programs via separate logic, such that the vertex processor 3605 is optimized to perform operations for the vertex shader program, while the one or more fragment processors 3615A-3615N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. The vertex processor 3605 performs the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. The fragment processors (multiple) 3615A-3615N use the primitive and vertex data generated by the vertex processor 3605 to produce frame buffers displayed on a display device. In one embodiment, the fragment processors (multiple) 3615A-3615N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform operations similar to those of pixel shader programs as provided in the Direct3D API.

[0355] The graphics processor 3610 additionally includes one or more memory management units (MMUs) 3620A-3620B, multiple caches 3625A-3625B, and multiple circuit interconnects 3630A-3630B. The one or more MMUs 3620A-3620B are integrated circuits 3610, including providing virtual-to-physical address mappings for vertex processors 3605 and / or / multiple fragment processors 3615A-3615N. These virtual-to-physical address mappings can reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in the one or more caches 3625A-3625B. In one embodiment, the one or more MMUs 3625A-3625B can be synchronized with other MMUs within the system, including those related to... Figure 36 The one or more application processors 3605, image processor 3615, and / or video processor 3620 are associated with one or more MMUs, enabling each processor 3605-3620 to participate in a shared or unified virtual memory system. According to an embodiment, the one or more circuit interconnects 3630A-3630B enable the graphics processor 3610 to interface with other IP cores within the SoC via the SoC's internal bus or via a direct connection.

[0356] Figure 37 This is a block diagram illustrating an additional exemplary graphics processor 3710 of a system-on-a-chip integrated circuit that can be fabricated using one or more IP cores according to an embodiment. The graphics processor 3710 may be... Figure 35 Variants of the 3510 graphics processor. The 3710 graphics processor includes... Figure 35 The integrated circuit 3500 includes one or more MMUs 3520A-3520B, caches 3525A-3525B, and interconnects 3530A-3530B.

[0357] The graphics processor 3710 includes one or more shader cores 3715A-3715N (e.g., 3715A, 3715B, 3715C, 3715D, 3715E, 3715F to 3715N-1 and 3715N), which provide a unified shader core architecture, wherein a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. The exact number of shader cores present can vary in embodiments and implementations. Additionally, the graphics processor 3710 includes an inter-core task manager 3705, which acts as a thread dispatcher for assigning execution threads to one or more shader cores 3715A-3715N, and a chunking unit 3718 for accelerating chunking operations for tile-based rendering, wherein rendering operations for a scene are subdivided in the image space, for example for utilizing local spatial coherence within the scene or for optimizing the use of internal caches.

[0358] The present invention also discloses a set of technical solutions, as follows:

[0359] 1. A machine learning hardware accelerator, comprising:

[0360] A computational unit having adders and multipliers shared between integer data paths and floating-point data paths, the multipliers being configured to gate the high bits of input operands during floating-point operations to enable computation based on the mantissa product of a first operand and a second operand.

[0361] 2. The machine learning hardware accelerator as described in technical solution 1, wherein the computing unit has a mode input to switch between integer operations and floating-point operations.

[0362] 3. The machine learning hardware accelerator as described in technical solution 2, wherein the computing unit includes an exponent unit and a mantissa unit, wherein the exponent unit and the mantissa unit are included in the floating-point data path and the integer data path.

[0363] 4. The machine learning hardware accelerator as described in technical solution 3, wherein the mode input enables the switch to provide the exponent and sign of the first operand and the second operand to the exponent unit for processing during floating-point operations.

[0364] 5. The machine learning hardware accelerator as described in technical solution 4, wherein the exponent unit includes an incrementer to increment the high-order bits of the sum output by the adder during integer operations.

[0365] 6. The machine learning hardware accelerator as described in technical solution 1, wherein the computing unit is configured to output integer results during a first period and floating-point results during a second period.

[0366] 7. The machine learning hardware accelerator as described in technical solution 1, wherein the multiplier of the computing unit performs a multiplication operation during a first phase of a fused multiplication-accumulation operation and performs an addition operation during a second phase of a fused multiplication-accumulation operation.

[0367] 8. The machine learning hardware accelerator as described in technical solution 7, wherein the first stage of the fused multiplication-accumulation operation is executed during a first clock cycle, the second stage of the fused multiplication-accumulation operation is executed during a second clock cycle, and the computing unit outputs a result during each of the first clock cycle and the second clock cycle.

[0368] 9. The machine learning hardware accelerator as described in technical solution 8, wherein the computing unit is used to output the results of the second stage during the first clock cycle.

[0369] 10. The machine learning hardware accelerator as described in technical solution 9, wherein the computing unit is used to store intermediate floating-point data in a non-IEEE format with a 22-bit mantissa.

[0370] 11. A method for accelerating machine learning operations, the method comprising:

[0371] Fetch and decode individual instructions to perform combined multiplication and addition operations on a set of operands;

[0372] The single instruction is issued for execution by the dynamically configurable computing unit;

[0373] Configure one or more logical units of the computing unit to perform operations with the data type of the operand set and the precision; and

[0374] At least a portion of the single instruction is executed at the dynamically configurable computing unit to generate and output based on the multiplication and addition operations.

[0375] 12. The method as described in technical solution 11, wherein the combined multiplication and addition operation is a fused multiplication-addition or a fused multiplication-accumulation operation.

[0376] 13. The method of claim 11, additionally includes executing at least a portion of the single instruction via a machine learning accelerator unit.

[0377] 14. The method of claim 13, wherein executing at least a portion of the single instruction comprises: quantizing an intermediate value having a first precision to a second precision lower than the first precision, the quantization comprising randomly rounding the decimal portion of the intermediate data.

[0378] 15. The method of claim 14, further comprising randomly rounding the fractional portion of the intermediate data based on a probability distribution associated with the intermediate data.

[0379] 16. A data processing system, comprising:

[0380] A non-transitory machine-readable medium for storing instructions for execution by one or more processors of the data processing system; and

[0381] A general-purpose graphics processing unit including a machine learning hardware accelerator and a dynamic precision computing unit, wherein the machine learning hardware accelerator includes hardware logic for performing multiple machine learning computation operations in response to a single instruction.

[0382] 17. The data processing system of technical solution 16, wherein the dynamic precision calculation unit includes calculation logic having adders and multipliers shared between integer data paths and floating-point data paths, and the calculation logic is configurable to generate floating-point data encoded in a non-standard format.

[0383] 18. The data processing system of claim 17, wherein the plurality of machine learning computation operations in response to a single instruction include a first operation for performing a fused multiply-accumulate operation and a second operation for applying an activation function to the output of the fused multiply-accumulate operation.

[0384] 19. The data processing system as described in technical solution 18, wherein the activation function is a sigmoid function.

[0385] 20. The data processing system of claim 18, wherein the machine learning hardware accelerator includes a random quantization unit to perform random rounding during the quantization of neural network data during the plurality of machine learning computation operations.

[0386] The embodiments described herein provide a logic unit that includes a combined integer / floating-point data path for both multiply-add (e.g., a * b + c) and multiply-accumulate (e.g., c = c + a * b) operations. In one embodiment, the addend for the addition operation is based on the accumulation of the previous operation. In one embodiment, the integer data path of the logic unit is merged into a floating-point data path having an addend-aligned operation parallel to the multiplication operation. In one embodiment, the integer data path is merged into a floating-point data path having an addend-aligned operation following the multiplication operation. The multiply-add and multiply-accumulate data paths described herein can be single-cycle or multi-cycle.

[0387] In one embodiment, during the two-cycle floating-point multiply-accumulate, the logic unit does not compare the mantissa at the beginning of the second stage (e.g., the adder stage). Instead, the logic unit pre-computes the larger (or smaller) mantissa based on the accumulator exponent from the second stage and the multiplier output calculated during the first stage.

[0388] In one embodiment, the accumulator or addend mantissa bit width is greater than the mantissa bit width of the multiplier input. In one embodiment, integer operations are mapped to floating-point units. In addition to the mantissa circuitry of the floating-point unit, some of the integer operations are also mapped to existing exponent circuitry. In one embodiment, the logic unit described herein includes multiplier and adder units shared between floating-point and integer operations and used to perform both floating-point and integer operations.

[0389] The following terms and / or examples relate to specific embodiments or examples thereof. Specific details in the examples may be used anywhere in one or more embodiments. Various features of different embodiments or examples may be combined in various ways with some of the included features and others that are excluded to suit a wide variety of different applications. Examples may include subjects such as methods, components for performing actions of methods, at least one machine-readable medium including instructions that, when executed by a machine, cause the machine to perform actions of a method, apparatus, or system according to the embodiments and examples described herein. Various components may be components for performing the described operations or functions.

[0390] One embodiment provides a machine learning hardware accelerator including a computing unit having an adder and a multiplier shared between an integer data path and a floating-point data path, wherein the high-order bits of the input operands to the multiplier are gated during floating-point operations. In one embodiment, the adder and multiplier are configured to perform both floating-point and integer operations. In one embodiment, the computing unit performs a multiply-add operation via the multiplier and adder. In one embodiment, the computing unit accepts at least two input operands. One embodiment provides a computing unit to perform a multiply-accumulate operation using two input operands and an accumulated value. One embodiment provides a computing unit to perform a multiply-add operation using three input operands. In one embodiment, the computing unit performs a multiply-accumulate operation or a multiply-add operation within a single cycle. In one embodiment, the computing unit performs a two-cycle multiply-add operation or a two-cycle multiply-accumulate operation. In one embodiment, the multiplier within the computing unit produces an output during a first cycle, and the adder produces an output during a second cycle. In one embodiment, the computation unit performs a two-cycle multiply-accumulate operation, wherein the first cycle is associated with a first logic stage, the second cycle is associated with a second logic stage, and the computation unit includes an exponent unit to pre-compute the larger mantissa and alignment shift of the second stage via the accumulated output of the previous cycle of the second stage and the multiplier output from the first stage.

[0391] In one embodiment, the integer data path is merged into a floating-point data path having an addend-aligned operation parallel to the multiplication operation. In another embodiment, the integer data path is merged into a floating-point data path having an addend-aligned operation after the multiplication operation. The computation unit may have a mode input to switch between integer and floating-point operations. In one embodiment, the computation unit may be configured for 8.8 fixed-point input and 16.0 fixed-point output.

[0392] One embodiment provides a data processing system including a non-transitory machine-readable medium for storing instructions for execution by one or more processors of the data processing system; and a general-purpose graphics processing unit including a machine learning hardware accelerator and a dynamic precision computing unit, the machine learning hardware accelerator including hardware logic to perform multiple machine learning computation operations in response to a single instruction. In one embodiment, the dynamic precision computing unit is switchable between integer operations and floating-point operations. In one embodiment, the dynamic precision computing unit includes integer data paths and floating-point data paths sharing a multiplier and an adder, wherein the multiplier performs multiplication operations on the integer data paths and floating-point data paths. In one embodiment, the floating-point data path includes an addend alignment operation performed in parallel with the multiplication operation. In one embodiment, the floating-point data path includes an addend alignment operation performed after the multiplication operation. In one embodiment, the dynamic precision computing unit is configured for single-cycle fused multiply-add operations or two-cycle fused multiply-accumulate operations.

[0393] One embodiment provides a method for accelerating machine learning operations, the method comprising: acquiring and decoding a single instruction to perform a combined multiplication and addition operation on a set of operands; issuing the single instruction for execution by a dynamically configurable computing unit; configuring one or more logical units of the computing unit to perform the operation with the precision and data type of the set of operands; and executing at least a portion of the single instruction at the dynamically configurable computing unit to generate and output based on the multiplication and addition operations.

[0394] The embodiments described herein refer to specific configurations of hardware (e.g., application-specific integrated circuits (ASICs)) configured to perform certain operations or have predetermined functionality. Such electronic devices typically include a collection of one or more processors coupled to one or more other components, such as one or more storage devices (non-transitory machine-readable storage media), user input / output devices (e.g., keyboards, touchscreens, and / or displays), and network connectivity. The coupling of the processor collection and its other components is typically via one or more buses and bridges (also known as bus controllers). Storage devices and signals carrying network traffic represent one or more machine-readable storage media and machine-readable communication media, respectively. Therefore, the storage devices of a given electronic device typically store code and / or data for execution on the one or more processors of that electronic device.

[0395] Of course, one or more parts of the embodiments may be implemented using different combinations of software, firmware, and / or hardware. Throughout this detailed description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that embodiments may be practiced without some of these specific details. In some instances, well-known structures and functions have not been described in exhaustive detail to avoid obscuring the inventive subject matter of the embodiments. Accordingly, the scope and spirit of the invention should be determined based on the following claims.

Claims

1. A graphics processor, comprising: Memory controller; as well as A graphics multiprocessor coupled to the memory controller, the graphics multiprocessor including a first circuitry configured to: Execute instructions to perform matrix operations on the first and second inputs; Intermediate data is generated based on the results of the matrix operations. Based on statistics associated with the first output data, a floating-point format is selected from multiple predefined floating-point formats; Convert the intermediate data into the selected floating-point format; as well as The converted intermediate data in the selected floating-point format is output as the second output data. The first output data includes the output generated for the first layer of the neural network. The second output data includes the output generated for the second layer of the neural network. The second layer takes the output of the first layer as its input. The statistics associated with the first output data include the dynamic range of the first output data.

2. The graphics processor as claimed in claim 1, wherein, The matrix operations include matrix multiplication.

3. The graphics processor as claimed in claim 1, wherein, The first circuit device is configured to generate the intermediate data in one of a first plurality of floating-point formats.

4. The graphics processor according to claim 3, wherein, The first plurality of floating-point formats include 16-bit and 32-bit formats.

5. The graphics processor as claimed in claim 1, wherein, The first circuit device is configured to convert the intermediate data into one of a second plurality of floating-point formats.

6. The graphics processor of claim 5, wherein, The second plurality of floating-point formats includes a plurality of floating-point formats having the same number of bits and different exponent bits.

7. The graphics processor of claim 6, wherein, The multiple floating-point formats have different mantissa bits.

8. The graphics processor of claim 1, wherein, The first output data includes data generated by the first circuit device prior to the generation of the intermediate data.

9. The graphics processor of claim 1, further comprising a second circuitry for determining statistics associated with the first output data.

10. The graphics processor of claim 9, wherein, The memory controller includes the second circuit device.

11. The graphics processor of claim 10, wherein, The memory controller is configured to determine the statistics associated with the first output data via the second circuitry during the writing of the first output data to the memory.

12. The graphics processor of claim 11, wherein, The first circuit device is configured to request the writing of the second output data to the memory via the memory controller.

13. The graphics processor of claim 12, wherein, The memory controller is configured to determine statistics related to the second output data via the second circuitry during the writing of the second output data to the memory.

14. A computing method for a graphics processor as described in any one of claims 1 to 13, comprising: Instructions are executed on the graphics processor to perform matrix operations on the first and second inputs; Intermediate data is generated based on the results of the matrix operations. Based on statistics associated with the first output data, a floating-point format is selected from multiple predefined floating-point formats; Convert the intermediate data into the selected floating-point format; as well as The converted intermediate data in the selected floating-point format is output as the second output data. The first output data includes the output generated for the first layer of the neural network. The second output data includes the output generated for the second layer of the neural network. The second layer takes the output of the first layer as its input. The statistics associated with the first output data include the dynamic range of the first output data.

15. The method of claim 14, further comprising: The intermediate data is generated using one of a plurality of floating-point formats, wherein the plurality of floating-point formats includes a 16-bit format and a 32-bit format; and The intermediate data is converted into one of a second plurality of floating-point formats, wherein the second plurality of floating-point formats includes a plurality of floating-point formats having the same number of bits and different exponent bits.

16. The method of claim 15, wherein, The multiple floating-point formats have different mantissa bits.

17. A machine-readable medium storing code that, when executed, causes a machine to perform the method as described in any one of claims 14 to 16.

18. A computing device comprising a module for performing the method as claimed in any one of claims 14 to 16.

19. A data processing system, comprising: Memory devices used to store instructions; as well as A graphics processor coupled to and configured to execute the instructions, the graphics processor including a memory controller and a graphics multiprocessor coupled to the memory controller, the graphics processor including circuitry configured to: Execute instructions to perform matrix operations on the first and second inputs; Intermediate data is generated based on the results of the matrix operations. Based on statistics associated with the first output data, a floating-point format is selected from multiple predefined floating-point formats; Convert the intermediate data into the selected floating-point format; as well as The converted intermediate data in the selected floating-point format is output as the second output data. The first output data includes the output generated for the first layer of the neural network. The second output data includes the output generated for the second layer of the neural network. The second layer takes the output of the first layer as its input. The statistics associated with the first output data include the dynamic range of the first output data.

20. The data processing system as described in claim 19, wherein, The matrix operation includes a matrix multiplication operation, and the circuitry is configured to generate the intermediate data in one of a first plurality of floating-point formats, including 16-bit and 32-bit formats.

21. The data processing system as described in claim 19, wherein, The circuitry is configured to convert the intermediate data into one of a second plurality of floating-point formats, the second plurality of floating-point formats including a plurality of floating-point formats having the same number of bits and different exponent bits.

22. The data processing system as described in claim 21, wherein, The multiple floating-point formats have different mantissa bits.

23. The data processing system of claim 19, wherein the graphics processor includes circuitry configured to determine statistics associated with the first output data.

24. The data processing system as described in claim 23, wherein, The circuitry configured to determine statistics associated with the first output data is contained in the memory controller of the graphics processor.

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