A method for preferentially loading FPGA reconfiguration and storage medium

Abstract

The application discloses a kind of priority loaded FPGA reconfiguration method and storage medium, wherein the method includes: after reconfiguration refresh controller receives reconfiguration instruction, reset reconfiguration target FPGA, reconfiguration refresh controller prohibits timing refresh;After reconfiguration refresh controller receives a frame loading frame, calculate loading frame frame check, if check is correct, then reconfiguration refresh controller calculates loading frame loading address, directly to reconfiguration target FPGA is carried out online loading;After reconfiguration refresh controller receives a frame write frame, judge received write frame frame count and the frame count that should be written currently are consistent reconfiguration refresh controller receives a frame refresh frame, calculate refresh frame frame check.The application solves the problem that traditional reconfiguration method is poor in real-time and cannot be flexibly applied to new function requirements of user.

Description

Technical Field

[0001] This invention belongs to the field of radiation-resistant design verification technology for spaceborne digital devices, and particularly relates to a priority loading FPGA reconfiguration method and storage medium. Background Technology

[0002] On-orbit reconfiguration has become standard on the vast majority of spacecraft payloads, and is an important guarantee for the flexibility of payload support services. A complete on-orbit reconfiguration process for an SRAM-based FPGA (Field Programmable Gate Array) includes updating the operating status of the target FPGA and its corresponding configuration file in memory.

[0003] A common FPGA on-orbit reconfiguration system uses a high-speed bus as the reconfiguration interface and an antifuse device as the reconfiguration refresh controller. The FPGA configuration file is stored in the corresponding memory. Typically, the FPGA configuration file is stored in non-volatile memory, primarily EEPROM (Electrically Erasable Programmable Read-Only Memory) and Nor Flash memory (Flash). EEPROM has a small single-chip capacity, making it unsuitable for miniaturized payloads; therefore, Flash will be the primary choice in the future. Common FPGA on-orbit reconfiguration systems include... Figure 1 As shown.

[0004] Traditional FPGA reconfiguration processes involve receiving the reconfiguration configuration file, directly writing it to the corresponding Flash memory, verifying the write operation, and then initiating the reconfiguration of the target FPGA. The transmission time of the reconfiguration configuration file and the Flash write time determine the reconfiguration efficiency. Due to the use of high-speed buses, the transmission time of the reconfiguration configuration file is no longer a bottleneck for improving reconfiguration efficiency. For example, the reconfiguration configuration file for a Virtex-7 FPGA is approximately 219 Mbit; if using an SPI bus with a rate of 20 Mbit / s, the transmission time can be completed in 10.95 seconds. The bottleneck for improving reconfiguration efficiency is the excessively long Flash write time. For Flash memory, the write time per address is relatively long, exceeding 50 µs. Again, using a Virtex-7 FPGA as an example, the Flash write time for the reconfiguration configuration file is approximately 24 minutes. Therefore, traditional on-orbit FPGA reconfiguration methods lack the ability to immediately enable the new state after reconfiguration, and in the event of unforeseen circumstances requiring immediate changes to onboard payload functions, they cannot cope with such situations.

[0005] To improve the reliability of FPGA on-orbit operation, payloads typically have a timed refresh function. The prerequisite for implementing timed refresh is that the configuration file loaded in the current FPGA operating state must be consistent with the refresh data; otherwise, there is a certain probability of high current flow, damaging the FPGA. Therefore, to ensure uninterrupted refresh during the reconfiguration process, a common approach is to select and switch the refresh data source among several memories, switching the refresh data source to a memory other than the one currently being rewritten, ensuring that the configuration file loaded in the current FPGA operating state is consistent with the configuration file in memory. However, this method means that until the configuration file in memory is completely updated, the FPGA can only run in the old state and cannot enable the new reconfigured state. Summary of the Invention

[0006] The technical problem solved by this invention is to overcome the shortcomings of the prior art and provide a priority loading FPGA reconfiguration method and storage medium, which solves the problems of poor real-time performance and inability to flexibly apply new user function requirements of traditional reconfiguration methods.

[0007] The objective of this invention is achieved through the following technical solution: a priority loading FPGA reconfiguration method, executed under the control of a reconfiguration refresh controller, comprising: Step 1: After receiving a reconfiguration command, the reconfiguration refresh controller resets the target FPGA and disables timed refresh; Step 2: After receiving a load frame, the reconfiguration refresh controller calculates the load frame checksum. If the checksum is correct, the reconfiguration refresh controller calculates the load frame address and directly loads it online onto the target FPGA; Step 3: Step 2 is repeated until all load frames are loaded. The target FPGA is then enabled in its new reconfigured state, and the reconfiguration refresh controller begins erasing the Flash memory storing the target FPGA configuration file; Step 4: After Flash erasure is complete, the refresh data source is set to the reconfiguration interface, and the reconfiguration refresh controller enables timed refresh; Step 5: After receiving a write frame, the reconfiguration refresh controller determines whether the received write frame count matches the current write frame count. If they match... If the frame check is correct, proceed to step six; Step six: Calculate the frame checksum of the write frame. If the checksum is correct, the reconstructed refresh controller calculates the address of the Flash memory corresponding to the target FPGA and writes the write frame to the Flash memory. Proceed to step seven; Step seven: Determine if all write frames have been written. If all write frames have been written, proceed to step twelve. If all write frames have not been written, proceed to step eight; Step eight: Determine if the current time is a refresh time. If it is a refresh time, proceed to step nine. If it is not a refresh time, proceed to step five; Step nine: Set the current frame count to be written as the frame count of the next write frame; Step ten: After receiving a refresh frame, the reconstructed refresh controller calculates the refresh frame checksum. If the checksum is correct, the reconstructed refresh controller calculates the refresh frame refresh address and uses the current refresh frame to refresh the FPGA online; Step eleven: Repeat step ten until all refresh frames have been refreshed. Read the current frame count to be written and proceed to step five; Step twelve: The reconstructed refresh controller sets the refresh data source to Flash memory. The reconstructed process is complete.

[0008] In the above-mentioned priority loading FPGA reconstruction method, in step two, if the verification fails, the reconstruction refresh controller resets the reconstruction target FPGA, reads the configuration file from the Flash corresponding to the reconstruction target FPGA, reloads the reconstruction target FPGA, sets the refresh data source of the reconstruction target FPGA to Flash, enables the timed refresh of the reconstruction refresh controller, and the reconstruction process ends.

[0009] In the above-mentioned priority loading FPGA reconfiguration method, the following step is also included between step five and step six: if the received write frame count is inconsistent with the current frame count that should be written, then request the sending of a write frame with the correct frame count, and proceed to step five.

[0010] In the above-mentioned priority loading FPGA reconstruction method, if a verification error occurs in step six, the reconstruction process ends.

[0011] In the above-mentioned priority loading FPGA reconstruction method, if a verification error occurs in step ten, the current refresh frame is discarded.

[0012] In the above-mentioned priority loading FPGA reconfiguration method, in step two, the target FPGA is directly loaded online using a parallel configuration mode.

[0013] In the above-mentioned priority loading FPGA reconstruction method, in step two, the loading frame is the reconstruction loading data frame.

[0014] In the above-mentioned priority loading FPGA reconstruction method, in step five, the write frame is the reconstruction data frame written to Flash.

[0015] In the above-mentioned priority loading FPGA reconstruction method, in step ten, the refresh frame is the refresh data frame.

[0016] One or more machine-readable media storing instructions that, when executed by one or more processors, cause the device to perform a preferred FPGA reconfiguration method.

[0017] Compared with the prior art, the present invention has the following advantages:

[0018] (1) The present invention uses a reconstruction method that loads the reconstruction configuration file first and runs the new state, and then stores the reconstruction configuration file to the corresponding Flash. This method reduces the time required to change the service functions of the onboard equipment. In other words, the activation time of the new state after the reconstruction of the target FPGA is only the time required to transmit the reconstruction configuration file via the high-speed bus. Compared with the traditional reconstruction method that stores the configuration file first and then loads and runs it, the present invention can shorten the activation time of the new state after the reconstruction of the target FPGA by at least two orders of magnitude, thereby achieving the effect of quickly changing the service functions of the onboard equipment. This greatly improves the real-time performance of the reconstruction and meets the user's need to quickly enable the new service functions after the reconstruction.

[0019] (2) By changing the refresh data source to the reconstructing interface, this invention solves the problem that when the configuration file loaded in the current running state of the FPGA is inconsistent with the configuration file stored in the corresponding Flash, that is, during the update of the configuration file stored in the Flash, the FPGA can maintain the new running state after reconstruction and the timed refresh operation can be carried out normally, thus improving the system reliability. Attached Figure Description

[0020] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0021] Figure 1 This is a diagram of an existing on-orbit reconfiguration system;

[0022] Figure 2 This is a flowchart of the FPGA reconfiguration method with priority loading provided in the embodiments of the present invention;

[0023] Figure 3 A block diagram illustrating a computing device that can be used to practice embodiments of the present invention is provided. Detailed Implementation

[0024] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the disclosure to those skilled in the art. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0025] Figure 2 This is a flowchart of the FPGA reconfiguration method with priority loading provided in this embodiment of the invention. For clarity, in the following steps, the reconfiguration loading data frame is referred to as the loading frame, the refresh data frame as the refresh frame, and the reconfiguration data frame written to Flash as the write frame. Figure 2 As shown, the method includes the following steps:

[0026] Step 1: After receiving the reconstruction instruction, the reconstruction refresh controller resets the target FPGA and disables timed refresh.

[0027] Step 2: After receiving a load frame, the reconstructing refresh controller calculates the load frame checksum. If the checksum is correct, the reconstructing refresh controller calculates the load frame address and directly loads it online to the target FPGA using a parallel configuration mode, then proceeds to Step 3. If the checksum is incorrect, a "load failed" telemetry message is returned. The reconstructing refresh controller resets the target FPGA, reads the configuration file from the corresponding Flash memory of the target FPGA, reloads the target FPGA, sets the refresh data source of the target FPGA to Flash, enables timed refresh in the reconstructing refresh controller, and the reconstructing process ends.

[0028] Step 3: Repeat Step 2 until all loading frames are loaded. The reconstructed target FPGA is enabled with the new state after reconstruction, and the reconstruction refresh controller begins to erase the Flash memory storing the reconstructed target FPGA configuration file.

[0029] Step 4: After the Flash erase is complete, the refresh data source for the target FPGA is set to the reconstruction interface, and the reconstruction refresh controller is enabled for timed refresh.

[0030] Step 5: After the reconstructed refresh controller receives a write frame, it determines whether the received write frame count is consistent with the current frame count that should be written. If the received write frame count is consistent with the current frame count that should be written, proceed to step 6.

[0031] Step 5.5: If the received write frame count is inconsistent with the current write frame count, then request the sending of a write frame with the correct frame count and proceed to step five.

[0032] Step Six: Calculate the write frame verification. If the verification is correct, the reconstructed refresh controller calculates the address to write to the corresponding Flash and writes the write frame to the Flash, then proceeds to Step Seven. If the verification fails, the telemetry returns "Failed to write configuration file to Flash", and the reconstruction process ends.

[0033] Step 7: Determine if all write frames have been written. If all write frames have been written, proceed to step 12. If all write frames have not been written, proceed to step 8.

[0034] Step 8: Determine if the current time is a refresh time. If it is a refresh time, proceed to Step 9; otherwise, proceed to Step 5.

[0035] Step 9: Set the current frame count to the frame count of the next frame to be written.

[0036] Step 10: After receiving a refresh frame, the reconfiguration refresh controller calculates the refresh frame checksum. If the checksum is correct, the reconfiguration refresh controller calculates the refresh frame address and uses the current refresh frame to refresh the FPGA online. If the checksum is incorrect, the current refresh frame is discarded.

[0037] Step 11: Repeat Step 10 until all refresh frames have been refreshed, read the current frame count that should be written, and go to Step 5.

[0038] Step 12: Reconstruct the refresh controller, set the refresh data source to Flash, return a telemetry message "Configuration file successfully written to Flash", and the reconstruction process is complete.

[0039] This invention employs a reconstruction method that first loads the reconstruction configuration file and runs the new state, then stores the reconstruction configuration file in the corresponding Flash memory. This method reduces the time required to change the onboard equipment's service functions. In other words, the activation time of the new state after reconstruction of the target FPGA is only the time required to transmit the reconstruction configuration file via the high-speed bus. Compared to the traditional reconstruction method that first stores the configuration file and then loads and runs it, this invention can shorten the activation time of the new state after reconstruction of the target FPGA by at least two orders of magnitude. This achieves the effect of quickly changing the onboard equipment's service functions, greatly improving the real-time performance of reconstruction and meeting the user's need to quickly enable the new service functions after reconstruction.

[0040] This invention solves the problem of inconsistency between the configuration file loaded in the current running state of the FPGA and the configuration file stored in the corresponding Flash memory when updating the configuration file stored in the Flash memory. This ensures that the FPGA maintains the new running state after reconstruction and that the timed refresh operation is performed normally, thereby improving system reliability.

[0041] This embodiment also provides one or more machine-readable media storing instructions that, when executed by one or more processors, cause the device to perform a prioritized FPGA reconfiguration method.

[0042] Figure 3 A structural block diagram of an exemplary computing device that can be used to practice embodiments of the present invention is shown. It will be understood that the clients, agents, and / or servers described in this disclosure can utilize... Figure 3 The computing device shown is used to implement this. For example... Figure 3 As shown, the computing device may include: a CPU (Central Processing Unit) 401, RAM (Random Access Memory) 402, ROM (Read-Only Memory) 403, a system bus 404, a hard disk controller 405, a keyboard controller 406, a serial interface controller 407, a parallel interface controller 408, a display controller 409, a hard disk 410, a keyboard 411, a serial external device 412, a parallel external device 413, and a display 414. Among these components, the CPU 401, RAM 402, ROM 403, hard disk controller 405, keyboard controller 406, serial interface controller 407, parallel interface controller 408, and display controller 409 are coupled to the system bus 404. The hard disk 410 is coupled to the hard disk controller 405, the keyboard 411 is coupled to the keyboard controller 406, the serial external device 412 is coupled to the serial interface controller 407, the parallel external device 413 is coupled to the parallel interface controller 408, and the display 414 is coupled to the display controller 409.

[0043] Several embodiments of the invention have been described above by way of example. At least some of the different blocks, operations, and techniques described above can be executed by using hardware, with a processor executing firmware instructions, a processor executing software instructions, or any combination thereof. When executed by a processor executing firmware and software instructions, the software or firmware instructions can be stored in any computer-readable storage, such as a disk, optical disk, or other storage medium, in a RAM or ROM or flash memory, a processor, a hard disk, an optical disk, a magnetic disk, etc. Similarly, the software and firmware instructions can be transmitted to a user or system by any known or desired transmission method, including, for example, on a computer-readable disk or other portable computer storage mechanism or via a communication medium. Communication media typically embody computer-readable instructions, data structures, program modules, or other data in modulated data signals, such as carrier waves or other transmission mechanisms. By way of example, and not limitation, communication media include wired media such as wired networks or single-wire connections, and wireless media such as sound, radio frequencies, infrared, and other wireless media. Thus, software and firmware instructions can be transmitted to the user or system via communication channels such as telephone lines, DSL lines, cable television lines, fiber optic cables, wireless channels, the Internet, etc. (such software is provided via portable storage media, which are considered identical or interchangeable). Software or firmware instructions may include readable instructions that, when executed by the processor, cause the processor to perform different actions.

[0044] It should be noted that embodiments of the present invention can be implemented using software, hardware, or a combination of both. The hardware portion can be implemented using dedicated logic; the software portion can be stored in memory and executed by a suitable instruction execution system, such as a microprocessor or dedicated-design hardware. Those skilled in the art will understand that the methods and systems described above can be implemented using computer-executable instructions and / or included in processor control code, for example, such code provided on a carrier medium such as a disk, CD, or DVD-ROM, a programmable memory such as read-only memory (firmware), or a data carrier such as an optical or electronic signal carrier. The devices and modules of this embodiment can be implemented using hardware circuitry such as very large-scale integrated circuits or gate arrays, semiconductors such as logic chips, transistors, or programmable hardware devices such as field-programmable gate arrays, programmable logic devices, etc., or can be implemented using software executed by various types of processors, or a combination of the aforementioned hardware circuitry and software, such as firmware.

[0045] The communication networks mentioned in the specification may include various types of networks, including but not limited to local area networks (“LAN”), wide area networks (“WAN”), IP-based networks (e.g., the Internet) and peer-to-peer networks (e.g., ad hoc peer-to-peer networks).

[0046] Furthermore, although the operations of the method of the present invention are described in a specific order in the accompanying drawings, this does not require or imply that these operations must be performed in that specific order, or that all of the operations shown must be performed to achieve the desired result. Rather, the order in which the steps described in the flowchart are performed may be changed. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, or one step may be broken down into multiple steps.

[0047] While the invention has been described with reference to several specific embodiments, it should be understood that the invention is not limited to the disclosed specific embodiments. The invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. The scope of the appended claims is to be interpreted in the broadest sense, thereby encompassing all such modifications and equivalent structures and functions.

Claims

1. A priority-loading FPGA reconfiguration method, which is executed under the control of a reconfiguration refresh controller, characterized in that... include: Step 1: After receiving the reconstruction command, the reconstruction refresh controller resets the target FPGA and disables timed refresh. Step 2: After receiving a load frame, the reconstructing and refresh controller calculates the load frame checksum. If the checksum is correct, the reconstructing and refresh controller calculates the load frame address and directly loads it online to the target FPGA. Step 3: Repeat Step 2 until all loading frames are loaded. The reconstructed target FPGA is enabled with the new state after reconstruction, and the reconstruction refresh controller begins to erase the Flash memory storing the reconstructed target FPGA configuration file. Step 4: After Flash erasure is complete, the refresh data source is set to the reconstruction interface, and the reconstruction refresh controller is enabled for timed refresh. Step 5: After the reconstructed refresh controller receives a write frame, it determines whether the received write frame count is consistent with the current frame count that should be written. If they are consistent, proceed to step 6. Step 6: Calculate the write frame verification. If the verification is correct, the reconstructed refresh controller calculates the address of the Flash corresponding to the target FPGA to be reconstructed, writes the write frame to the Flash, and proceeds to Step 7. Step 7: Determine if all write frames have been written. If all write frames have been written, proceed to step 12. If all write frames have not been written, proceed to step 8. Step 8: Determine if the current time is a refresh time. If it is a refresh time, proceed to step 9; otherwise, proceed to step 5. Step 9: Set the current frame count to the frame count of the next frame to be written; Step 10: After receiving a refresh frame, the reconfiguration refresh controller calculates the refresh frame checksum. If the checksum is correct, the reconfiguration refresh controller calculates the refresh frame address and uses the current refresh frame to refresh the FPGA online. Step 11: Repeat Step 10 until all refresh frames have been refreshed, read the current frame count that should be written, and go to Step 5; Step 12: Reconstruct the refresh controller and set the refresh data source to Flash. The reconstruction process is now complete.

2. The FPGA reconfiguration method with priority loading according to claim 1, characterized in that: In step two, if a verification error occurs, the reconstruction refresh controller resets the target FPGA, reads the configuration file from the Flash memory corresponding to the target FPGA, reloads the target FPGA, sets the refresh data source of the target FPGA to Flash, enables timed refresh by the reconstruction refresh controller, and the reconstruction process ends.

3. The FPGA reconfiguration method with priority loading according to claim 1, characterized in that: The following steps are also included between steps five and six: If the received write frame count is inconsistent with the current write frame count, then request the sending of a write frame with the correct frame count and proceed to step five.

4. The FPGA reconfiguration method with priority loading according to claim 1, characterized in that: If a verification error occurs in step six, the reconstruction process ends.

5. The FPGA reconfiguration method with priority loading according to claim 1, characterized in that: In step ten, if a verification error occurs, the current refresh frame is discarded.

6. The FPGA reconfiguration method with priority loading according to claim 1, characterized in that: In step two, the online loading is performed directly onto the target FPGA for reconstruction using a parallel configuration mode.

7. The FPGA reconfiguration method with priority loading according to claim 1, characterized in that: In step two, the loading frame is the reconstructed loading data frame.

8. The FPGA reconfiguration method with priority loading according to claim 1, characterized in that: In step five, the write frame is the reconstructed data frame written to Flash.

9. The FPGA reconfiguration method with priority loading according to claim 1, characterized in that: In step ten, the refresh frame is the refresh data frame.

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