Embedded software full-digital excitation deployment method, system, equipment and medium

Abstract

The invention relates to the technical field of embedded system development and verification, and discloses an embedded software full-digital excitation deployment method, system, device and medium, and the method comprises the steps: based on a virtualization modeling technology of a multi-core heterogeneous system, simulating a CPU architecture, an operating system, board card peripherals and peripheral interfaces of a target processor, constructing a general digital target machine; a cross-platform communication framework is established based on a real-time communication transmission technology of direct digital frequency synthesis, and real-time synchronization of data of a virtual environment and an interaction object is completed; and through cooperation of the general digital target machine and the cross-platform communication framework, full-digital deployment and verification of the embedded software are completed. According to the method, full-digital development and verification of the embedded software can be realized, a research and development mode of parallel hardware development, software development and system function verification is met, and the research and development efficiency of the embedded software is improved.

Description

Technical Field

[0001] This invention relates to the field of embedded system development and verification technology, and in particular to a fully digital stimulus deployment method, system, device and medium for embedded software. Background Technology

[0002] Traditional embedded software verification heavily relies on the physical hardware environment, and in some industries, the hardware is non-standard, highly customized, with long development and testing cycles and high costs. Currently, the existing technologies related to embedded software verification are as follows: Patent application CN116107893A discloses a heterogeneous platform embedded software testing and verification system and method, including a board integration module, an interface management module, a protocol parsing module, a device management module, a test case driving module, an interface driving module, and a receiving and display control module. The specific process is as follows: the board integration module connects to the device under test, the system starts to complete system resource self-check, adds link information, completes test node interconnection, obtains a description text file and matches the link information, generates a script file, obtains a dictionary file, determines the test case format based on the script file, adds payload data according to the test case format to form test cases, sets interaction strategies, sends test cases to the device under test, receives and displays the data reported by the device under test, and completes the test.

[0003] Patent CN112379744B discloses an integrated high-performance information processing system development and verification system and its implementation method, which relates to a development system. The hardware of the development system consists of unit cabinets, control cabinets, and auxiliary display devices. The unit cabinets house intermediate-layer FPGA units, central DSP units, peripheral interface units, integrated units, telemetry processing units, and electrical control units. The intermediate-layer FPGA units adopt an integrated chassis structure, providing unified slots for other units. The power module in the unit cabinet provides DC power to the secondary power module, which in turn provides various necessary power supplies to each unit. A monitoring and management computer is connected to the control computers of each unit via a gigabit Ethernet switch. This computer is used for recording, displaying, storing, playing back, and exporting the operating status and data of each unit.

[0004] Patent CN112463614B discloses a method for constructing a software virtualization test environment based on hardware board access. The method includes: building an embedded target processor instruction set virtual simulation environment; building an embedded system on-chip device virtual simulation environment; completing the adaptation and installation of the hardware board on the host machine, enabling operation and control of the board in the host machine's virtual environment; establishing a physical connection between the external device simulation environment and the host machine's hardware board, and establishing a communication link between the external device simulation environment and the hardware board; acquiring messages from the virtual environment to the external device simulation environment, establishing a message processing and response mechanism in the virtual environment, and completely feeding back the messages sent by the external device simulation environment to the virtual runtime environment through the hardware board; processing messages from the virtual environment to the external device simulation environment, establishing a state update mechanism in the virtual environment, and accurately feeding back the processed message results and message status from the virtual runtime environment to the external device simulation environment through the hardware board.

[0005] However, existing virtual simulation technologies based on processing boards are insufficient for achieving fully digital verification and rapid hardware adaptation and porting, exhibiting significant shortcomings in the following aspects: 1) Coordinating multi-core heterogeneous resources is difficult and dynamic load balancing is insufficient. For example, the task allocation strategies of heterogeneous cores such as ARM, DSP and PPC are highly coupled, making it difficult to dynamically adjust task migration according to real-time load, and cross-core communication efficiency is low.

[0006] 2) Lack of compatibility among multiple operating systems and contradictions in system isolation and interaction, such as differences in process scheduling and interrupt response mechanisms between Linux and real-time operating systems (such as RTEMS), leading to uncontrollable delays in cross-system service calls.

[0007] 3) Poor compatibility of peripheral communication drivers. The driver interfaces of the same peripheral (such as Ethernet / CAN controller) are not consistent under different operating systems, and the adaptation layer needs to be developed repeatedly.

[0008] 4) Embedded software has poor scalability in distributed deployment, lacks dynamic adaptation capabilities for various interactive objects (software and hardware models), is too highly customized, and cannot be connected to semi-physical devices.

[0009] In summary, existing technical solutions have significant shortcomings in areas such as elastic management of heterogeneous resources, real-time interaction across systems, high-precision synchronization reliability, flexible expansion of communication protocols, and distributed scalable deployment, and urgently need improvement. Summary of the Invention

[0010] To address the aforementioned issues, this invention proposes a fully digital stimulus deployment method, system, device, and medium for embedded software, which enables fully digital development and verification of embedded software, satisfies the parallel R&D model of hardware development, software development, and system function verification, and improves the efficiency of embedded software R&D.

[0011] The technical solution adopted in this invention is as follows: A fully digital incentive deployment method for embedded software includes: Based on virtualization modeling technology for multi-core heterogeneous systems, the CPU architecture, operating system, board peripherals and peripheral interfaces of the target processor are simulated to construct a general-purpose digital target machine; Based on direct digital frequency synthesis real-time communication transmission technology, a cross-platform communication framework is built to achieve real-time data synchronization between the virtual environment and interactive objects; Through the collaboration of the general-purpose digital target machine and the cross-platform communication framework, the fully digital deployment and verification of embedded software is completed.

[0012] Furthermore, based on virtualization modeling technology for multi-core heterogeneous systems, the CPU architecture of the target processor is simulated, including: Instruction-level simulation core: Based on dynamic binary translation technology, it simulates the multi-core architecture of the target processor and supports single-cycle multi-instruction parallel issuance and functional unit modeling; Layered modeling of the memory system: Layered modeling of the memory system, including L1 / L2 cache modeling, L3 shared memory and DDR3 modeling; Multi-core collaboration: Modeling of inter-core interrupt and shared memory synchronization primitives.

[0013] Furthermore, based on virtualization modeling technology for multi-core heterogeneous systems, the operating system, board peripherals, and peripheral interfaces of the target processor are simulated, including: Operating system adaptation: Adapts to real-time operating systems and Linux systems, supporting simulation of task scheduling, interrupt response, and system calls; Model library construction: Construct a key peripheral model library including SRIO, PCIe, timers and interrupt controllers, and then realize the simulation of the target processor's board peripherals and peripheral interfaces.

[0014] Furthermore, the construction of the general-purpose digital target machine includes operating system booting, the operating system booting including: Processor state initialization: Initialize the boot environment of the target processor, and define the processor state and the master-slave core boot order; Pre-initialization of critical peripherals: Dynamically generate device tree binary files based on command-line parameters and load them into the specified physical memory; Multi-core boot and inter-core communication synchronization: Multiple virtual CPU instances are created using the SMP option, and inter-core communication synchronization is achieved using shared memory regions and atomic operation instructions; Multi-system boot compatibility: Adapts to multiple operating systems through different boot methods.

[0015] Furthermore, the real-time communication transmission technology based on direct digital frequency synthesis establishes a cross-platform communication framework, including: improving data transmission rate through underlying model hardware acceleration, driver software optimization, and hardware platform acceleration; setting up a real-time data transmission interface to perform data synchronization between the virtual environment and actual hardware and semi-physical devices.

[0016] Furthermore, the real-time communication transmission technology based on direct digital frequency synthesis, which builds a cross-platform communication framework, also includes: digitally modeling the relevant communication interfaces, performing interface function flow simulation, instantiation application, and adaptation and expansion for different embedded boards. The relevant communication interfaces include CAN bus interface, Ethernet interface, serial port, and I2C bus interface.

[0017] An embedded software fully digital incentive deployment system includes: The board virtualization modeling module is configured to use virtualization modeling technology based on multi-core heterogeneous systems to simulate the CPU architecture, operating system, board peripherals and peripheral interfaces of the target processor and build a general-purpose digital target machine. The cross-platform communication framework building module is configured to build a cross-platform communication framework based on direct digital frequency synthesis real-time communication transmission technology, and complete the real-time data synchronization between the virtual environment and interactive objects. The fully digital deployment and verification module is configured to complete the fully digital deployment and verification of embedded software through the collaboration of the general-purpose digital target machine and the cross-platform communication framework.

[0018] Furthermore, the embedded software fully digital stimulus deployment system also includes a debugging and performance analysis module, which includes: an instruction-level debugging interface configured to perform breakpoint setting, single-step execution, and register and memory viewing; and a performance counter configured to count CPU utilization, cache hit rate, and bus transaction count.

[0019] A computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the embedded software fully digital stimulus deployment method.

[0020] A computer-readable storage medium storing a computer program that, when executed by a processor, implements the embedded software fully digital stimulus deployment method.

[0021] The beneficial effects of this invention are as follows: 1. This invention constructs a complete virtual system including a processor and its peripherals, which is compatible with various domestic operating systems. It supports the injection of various test signals or stimuli and observation of their responses, thereby enabling system-level integration testing, fault injection testing, boundary testing, etc., to discover some defects in software design and implementation early and improve software quality. On the simulation platform, the correctness and performance of the algorithm can be verified in the early stages of development, and iterative testing, parameter adjustment and optimization can be performed quickly without waiting for each lengthy hardware burning and testing cycle. This invention supports continuous integration and automated testing in a virtual environment, realizes automated regression testing, and ensures that code modifications do not introduce new problems.

[0022] 2. The fully digital simulation environment constructed by this invention supports visual analysis and can statistically analyze the performance indicators of software running on multi-core processors, such as running time, memory usage, and inter-core communication latency, providing a basis for software optimization. The fully digital simulation environment constructed by this invention helps to design and verify multi-core task partitioning, load balancing, data flow, and DMA (Direct Memory Access Configuration). Through simulation analysis data, it can guide code optimization (such as task partitioning on multiple cores, data prefetching, etc.) to maximize the processor's performance.

[0023] In summary, this invention transfers many development, debugging, and testing activities that heavily rely on physical hardware to a highly controllable, reproducible, and visualized digital simulation environment. This not only reduces R&D costs and risks, but more importantly, it comprehensively improves software development efficiency and software quality through modularization, automation, visualization, and in-depth analysis. Attached Figure Description

[0024] Figure 1 This is a flowchart of the embedded software fully digital incentive deployment method according to Embodiment 1 of the present invention.

[0025] Figure 2 This is a data communication principle diagram of Embodiment 2 of the present invention.

[0026] Figure 3 This is a schematic diagram of the interaction between components of the fully digital incentive deployment and verification platform in Embodiment 2 of the present invention. Detailed Implementation

[0027] To provide a clearer understanding of the technical features, objectives, and effects of the present invention, specific embodiments are now described. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention; that is, the described embodiments are only a part of the embodiments of the invention, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0028] Example 1 like Figure 1 As shown, this embodiment provides a fully digital incentive deployment method for embedded software, including: Based on virtualization modeling technology for multi-core heterogeneous systems, the CPU architecture, operating system, board peripherals and peripheral interfaces of the target processor are simulated to construct a general-purpose digital target machine; Based on direct digital frequency synthesis real-time communication transmission technology, a cross-platform communication framework is built to achieve real-time data synchronization between the virtual environment and interactive objects; By collaborating with a general-purpose digital target machine and a cross-platform communication framework, the fully digital deployment and verification of embedded software can be achieved.

[0029] It should be noted that the general-purpose digital target machine constructed by this method is free from dependence on specific hardware and can be adapted to various target processors of different specifications, thus improving the versatility of the method. The cross-platform communication framework is based on direct digital frequency synthesis technology, which ensures the real-time performance and accuracy of data transmission and ensures the synchronization of the virtual environment and the interactive object's state. Through a fully digital deployment and verification mode, there is no need to rely on physical hardware to build the test environment, which reduces testing costs and shortens the deployment and verification cycle.

[0030] Preferably, the CPU architecture of the target processor is simulated using virtualization modeling technology based on multi-core heterogeneous systems, including: Instruction-level simulation core: Based on dynamic binary translation technology, it simulates the multi-core architecture of the target processor and supports single-cycle multi-instruction parallel issuance and functional unit modeling; Layered modeling of the memory system: Layered modeling of the memory system, including L1 / L2 cache modeling, L3 shared memory and DDR3 modeling; Multi-core collaboration: Modeling of inter-core interrupt and shared memory synchronization primitives.

[0031] Specifically, the implementation process for simulating the CPU architecture of the target processor is as follows: Instruction-level simulation core implementation: Dynamic binary translation technology is used to analyze the multi-core architecture characteristics of the target processor and build a corresponding simulation model. This technology is used to convert the instruction set of the target processor into an instruction format that can be recognized by the simulation environment, design logic that supports single-cycle multi-instruction parallel issuance, and model the internal functional units of the processor to restore its core functions such as operation and storage.

[0032] Layered modeling of memory system: Based on the actual hierarchical structure of the memory system, simulation models of L1 / L2 cache, L3 shared memory and corresponding memory types are constructed respectively; the access rules, data interaction logic and storage mechanism of each level of memory are clarified, and core behaviors such as memory read and write, cache hit and miss are simulated to realize the layered simulation of the memory system.

[0033] Multi-core collaborative modeling: To address the inter-core communication requirements of multi-core processors, the triggering and response logic for inter-core interrupts is designed, and an interrupt handling simulation module is constructed. At the same time, shared memory synchronization primitives are modeled, and the calling method and execution flow of the primitives are defined to ensure that multi-cores can achieve data interaction and collaborative work through a standardized synchronization mechanism.

[0034] It should be noted that the aforementioned instruction-level simulation core can accurately reproduce the multi-core parallel computing characteristics of the target processor, support multi-instruction parallel processing, and improve the realism of CPU architecture simulation; the layered modeling of the memory system closely matches the actual memory structure, ensuring the simulation accuracy of memory-related operations and providing a realistic memory environment for embedded software operation; the multi-core collaborative modeling realizes accurate simulation of inter-core interrupts and shared memory synchronization, ensuring the stability and reliability of software operation under multi-core architecture.

[0035] Preferably, virtualization modeling technology based on multi-core heterogeneous systems is used to simulate the target processor's operating system, board peripherals, and peripheral interfaces, including: Operating system adaptation: Adapts to real-time operating systems and Linux systems, supporting simulation of task scheduling, interrupt response, and system calls; Model library construction: Construct a key peripheral model library including SRIO, PCIe, timers and interrupt controllers, and then realize the simulation of the target processor's board peripherals and peripheral interfaces.

[0036] Specifically, the implementation process for simulating the target processor's operating system, board peripherals, and peripheral interfaces is as follows: Operating System Adaptation: Adaptation logic is designed for the core characteristics of real-time operating systems and Linux systems respectively; the task scheduling algorithm, interrupt response mechanism and system call process of real-time operating systems are simulated, while the process management, resource allocation and system service functions of Linux systems are restored to ensure that the two systems can run normally in the simulation environment and support the calls of embedded software.

[0037] Model library construction and peripheral interface simulation: We sort out the commonly used board peripherals and peripheral interface types of the target processor, and build a model library including key peripherals such as SRIO, PCIe, timers and interrupt controllers; we define the functional implementation logic and interface interaction rules for each peripheral model, and call the corresponding peripheral model through the model library to realize the functional simulation of the board peripherals, while restoring the data transmission and control logic of the peripheral interface.

[0038] It should be noted that the above-mentioned operating system adaptation achieves compatibility with two mainstream operating systems, expands the scope of application of the method, and meets the running requirements of different embedded software; the construction of the key peripheral model library covers the core peripheral types, realizes the comprehensive simulation of board peripherals and peripheral interfaces, and ensures the accuracy of the verification of the interaction logic between embedded software and peripherals; the simulation logic of peripherals and interfaces is scalable, which facilitates the adaptation of newly added peripheral types in the future.

[0039] Preferably, constructing a general-purpose digital target machine includes operating system booting, which includes: Processor state initialization: Initialize the boot environment of the target processor, and define the processor state and the master-slave core boot order; Pre-initialization of critical peripherals: Dynamically generate device tree binary files based on command-line parameters and load them into the specified physical memory; Multi-core boot and inter-core communication synchronization: Multiple virtual CPU instances are created using the SMP option, and inter-core communication synchronization is achieved using shared memory regions and atomic operation instructions; Multi-system boot compatibility: Adapts to multiple operating systems through different boot methods.

[0040] Specifically, the specific implementation process of operating system booting includes: Processor state initialization: Identify the core startup requirements of the target processor, define the initial working state parameters and operating mode of the processor, clarify the startup order logic of the master and slave cores, and build the basic operating environment for processor startup.

[0041] Pre-initialization of critical peripherals: Parse the configuration information input from the command line, dynamically generate a device tree binary file adapted to the target processor according to the configuration logic, and load the file into the specified physical memory area according to the preset memory allocation rules, so as to provide a configuration basis for the interaction between peripherals and processor.

[0042] Multi-core boot and inter-core communication synchronization: By enabling the SMP option, multiple virtual CPU instances are created in the simulation environment to simulate the hardware structure of a multi-core processor. A dedicated shared memory region is allocated as the carrier for inter-core communication, and atomic operation instructions are used to ensure the atomicity of data read and write between cores, achieving efficient communication and state synchronization between multiple cores.

[0043] Multi-system boot compatibility: Different boot adaptation logic is designed to meet the boot process and requirements of different operating systems. By switching boot methods, the boot requirements of multiple operating systems such as real-time operating systems and Linux systems can be met.

[0044] It should be noted that the processor state initialization and critical peripheral pre-initialization mentioned above ensure the stability of the basic environment for system startup, providing reliable support for the subsequent startup process; the inter-core communication synchronization mechanism based on shared memory and atomic operation instructions ensures the efficiency and consistency of data interaction after multi-core startup; the multi-system startup compatibility design improves the flexibility of the general-purpose digital target machine and can adapt to the embedded software deployment requirements of different operating systems.

[0045] Preferably, a cross-platform communication framework is built based on real-time communication transmission technology using direct digital frequency synthesis, including: improving data transmission rate through underlying model hardware acceleration, driver software optimization, and hardware platform acceleration; setting up a real-time data transmission interface to perform data synchronization between the virtual environment and actual hardware and semi-physical devices.

[0046] Specifically, the implementation process for building a cross-platform communication framework includes: Data transmission rate improvement: Optimization efforts are carried out from three dimensions: underlying hardware, driver software, and hardware platform. At the underlying model level, hardware acceleration-related design logic is adopted to improve the parallelism of data processing; the core code of the driver software is optimized to reduce redundant operations in the data transmission process; and the inherent characteristics of the hardware platform are leveraged to explore performance potential and comprehensively improve the overall data transmission rate.

[0047] Real-time data transmission interface setup: Design a dedicated real-time data transmission interface, clearly defining the data transmission format, interaction protocol, and response mechanism. This interface establishes a connection between the virtual environment and the actual hardware / semi-physical devices, enabling real-time acquisition of runtime data from embedded software within the virtual environment, while simultaneously receiving feedback data from external interactive objects, achieving bidirectional data synchronization.

[0048] It should be noted that the above-mentioned multi-dimensional rate improvement measures effectively improve data transmission efficiency and meet the needs of real-time transmission of large amounts of data during the operation of embedded software; the dedicated real-time data transmission interface ensures the timeliness and accuracy of data synchronization, ensures a high degree of consistency between the virtual environment and the interactive object's state, and improves the reliability of verification results; the interface design is compatible with different types of interactive objects, enhancing the adaptability of cross-platform communication frameworks.

[0049] Preferably, the cross-platform communication framework built based on direct digital frequency synthesis real-time communication transmission technology also includes: digitally modeling the relevant communication interfaces, performing interface function flow simulation, instantiation application, and adaptation and expansion for different embedded boards. The relevant communication interfaces include CAN bus interface, Ethernet interface, serial port, and I2C bus interface.

[0050] Specifically, the implementation process of building a cross-platform communication framework also includes: Digital Modeling of Communication Interfaces: For commonly used communication interfaces such as CAN bus, Ethernet, serial port, and I2C bus, the functional principles and workflows are analyzed, and corresponding digital simulation models are constructed. The signal transmission, data encoding / decoding, and protocol interaction logic of each interface are simulated to recreate its core functions.

[0051] Functional process simulation and instantiation: Based on the constructed digital model, the data transmission process and interaction behavior of each communication interface in a real-world scenario are simulated. The modeled interfaces are then integrated into a cross-platform communication framework and instantiated for deployment, enabling them to receive and process interface requests from embedded software and interactive objects.

[0052] Adaptation and Expansion: A flexible interface adaptation mechanism is designed to adjust the configuration parameters and interaction logic of the interface model for different specifications of embedded boards, so as to achieve compatibility and expansion for a variety of embedded boards.

[0053] It should be noted that the above digital modeling of various commonly used communication interfaces enables accurate simulation of interface functions, ensuring the verification effect of embedded software interacting with external devices through interfaces; the instantiation application and adaptation extension mechanism improve the practicality and scalability of the communication framework, which can be adapted to different application scenarios and hardware configurations; interface simulation avoids dependence on physical interface hardware, reduces testing costs, and facilitates quick debugging of interface interaction problems.

[0054] Example 2 This embodiment is based on embodiment 1: This embodiment provides a fully digital stimulus deployment method for embedded software, which mainly consists of two important parts: processing board modeling technology for multi-core heterogeneous systems and real-time communication and transmission technology based on DDS. Specifically, this embodiment uses the FT6678 processor to illustrate the implementation process of this method in detail.

[0055] I. Modeling Methods for Processing Boards in Multi-core Heterogeneous Systems By simulating the CPU architecture, operating system, BSP, peripheral interfaces, and board peripherals of the FT6678 processor, a general-purpose digital target machine independent of the processor model and operating system is realized, completing the virtualization modeling of the processor board. The FT6678 processor board stimulus model is compatible with most commonly used domestic operating systems on the market, such as Tianmai 3 (32-bit / 64-bit) and Reworks (32-bit / 64-bit) operating systems.

[0056] This embodiment fully simulates the multi-core architecture, instruction set, memory system, and peripheral interfaces of the FT6678 CPU, runs a real-time operating system and control logic code, and interacts with the FPGA through a customized device model.

[0057] Preferably, for instructions requiring customized extensions for the FT6678 processor, the binary encoding format of the instructions (opcode, register fields, immediate numeric fields, etc.) and the specific operations executed by the instructions are parsed to implement an instruction translator that maps the instructions to TCG opcodes and Helper functions. For some VLIW (Very Long Instruction Word) instructions, they need to be broken down into multiple TCG operations or Helper calls. Some DSP algorithms are sensitive to processor performance, so when extending instructions, simple instructions are directly implemented using TCG instructions (such as tcg_gen_add_i32), while complex instructions are implemented using Helper functions to reduce the overall system overhead.

[0058] 1. Accurate simulation of multi-core architecture 1) Instruction-level simulation core: It adopts dynamic binary translation technology to realize the simulation of the 8-core C66x VLIW architecture of FT6678, supports parallel issuance of 8 instructions in a single cycle, includes accurate modeling of 4 functional units (M / L / S / D units), and controls the instruction cycle error within ±2ns.

[0059] 2) Layered modeling of the memory system: L1 / L2 cache modeling: Supports simulation of the correlation and replacement strategy between 32KB L1P / L1D cache and 256KB L2 cache, with a cache hit rate statistical error of ≤3%.

[0060] L3 Shared Memory and DDR3 Modeling: Transaction-level simulation of 4MB L3 SRAM and 8GB DDR3-1600 is achieved through large page memory mapping, with memory access latency simulation accuracy reaching ±5ns.

[0061] 3) Multi-core collaborative mechanism: Achieve accurate modeling of inter-core interrupt (IPI) and shared memory synchronization primitives (semaphores / spinlocks), with simulation error of inter-core communication delay ≤10ns.

[0062] 2. Virtual Implementation of Peripherals and Interfaces 1) Key peripheral model library: SRIO v2.1 interface: Supports 4-channel 5GB / s transmission, realizes accurate simulation of NWRITE / NREAD transaction cycle, and has a link initialization time error of ≤50μs.

[0063] PCIe Gen2 x4 interface: simulates DMA transfer and interrupt mechanism, with bus bandwidth simulation accuracy reaching more than 90% of the theoretical value.

[0064] Timer / Interrupt Controller: Implements priority scheduling of 64-bit timers and 128-channel interrupts, with an interrupt response delay error ≤100ns.

[0065] 2) Real-time operating system adaptation: It supports task scheduling simulation for real-time operating systems such as SYS / BIOS and VxWorks, with a context switching time simulation error of ≤50ns.

[0066] Implement a virtual interrupt controller and clock source for the Linux kernel, with a system call latency error of ≤200ns.

[0067] 3. Debugging and Performance Analysis 1) Instruction-level debugging interface: Integrated with GDB Server, supporting breakpoints, single-step execution, register / memory viewing, and instruction tracing latency ≤10μs.

[0068] 2) Performance counter simulation: Statistical analysis of indicators such as CPU utilization, cache hit rate, and bus transaction count, with a data sampling interval of ≤1ms.

[0069] 4. Operating system boot Based on a general-purpose ARM emulation platform, the boot code for the FT6678 platform is extended. Its core function is to initialize the boot environment of the FT6678 processor and provide support for multiple boot paths, mainly including: 1) Processor state initialization: Define processor-related structures, such as the CPUFT6678State structure, which contains all the processor's registers (general-purpose registers, status registers, and FT6678-specific control registers, 64-bit accumulators, etc.), distinguish between master and slave cores, define the startup order of master and slave cores, the initialization state of shared resources, etc., to achieve accurate modeling and initialization of the processor chip.

[0070] 2) Pre-initialization of critical peripherals: A device tree binary file (DTB) is dynamically generated based on command-line parameters and placed in a specific location in physical memory. The device tree nodes describe the memory layout, interrupt controller, and connection information, register address ranges, and interrupt signals of various other peripherals. During system startup, this DTB file is read and its addresses are passed to the booting operating system kernel.

[0071] 3) Multi-core startup and inter-core communication synchronization: Use QEMU's SMP option (-smp cores=8) to create multiple virtual CPU instances to simulate the multi-core FT6678 processor. Simulate shared cache or global memory through memory mapping regions, use atomic operation instructions to implement locks in the shared memory region, and achieve synchronization of inter-core communication.

[0072] 4) Boot compatibility with multiple operating systems: It can adapt to various domestic operating systems through different boot methods, such as the commonly used Tianmai 3 (32-bit / 64-bit) and Reworks (32-bit / 64-bit) operating systems.

[0073] This embodiment achieves comprehensive support for the FT6678 processor platform through precise instruction-level control and multi-path design. It is compatible with the standard ARM boot process and provides optimization and extension functions unique to domestic processors. It also supports booting from different operating systems (Tianmai, Ruihua, VxWorks).

[0074] II. Real-time Communication Transmission Technology Based on DDS This embodiment proposes an efficient real-time data transmission mechanism that combines hardware acceleration and optimized drivers to achieve near-realistic real-time performance. This mechanism includes: underlying model hardware acceleration to improve model execution speed, thereby increasing data transmission rate; driver software optimization to improve the efficiency of simulation environment software operation; a cross-platform communication framework to improve communication efficiency between different platforms and simulation subsystems; hardware platform acceleration to improve hardware execution speed, thereby improving the simulation system's execution speed; and a highly efficient real-time data transmission interface to ensure real-time data synchronization between the virtual environment and the actual hardware. Through hardware acceleration and optimized drivers, near-realistic real-time performance is achieved.

[0075] Preferably, the communication module encapsulates Fast DDS to implement publish and subscribe data communication, as follows: Figure 2 As shown, each node can define the data type and name through Topics, use DataWriter / DataReader to read and write the actual data, and control various communication behaviors through QoS Policies.

[0076] Preferably, it can also perform functional module modeling of the interactive objects (hardware modules) of the application software, realizing fully digital verification of the application software. It simulates the input / output interfaces of relevant hardware modules and performs digital modeling, including process modeling of functional implementation, interface modeling (CAN, Ethernet, serial port, SRIO, and I2C, etc.), supports instantiated applications, and can also interface with calls and deployments under different digital stimulus environments; it can adapt to the rapid adaptation and expansion of peripherals of different embedded boards. Users can flexibly configure the communication modules of the virtual board according to their needs, such as GPIO, serial port, Ethernet (TSN, FC), etc.

[0077] In a fully digital deployment and verification platform, the interactions between components via communication middleware are illustrated as follows: Figure 3 As shown.

[0078] Example 3 This embodiment provides an embedded software fully digital incentive deployment system, including: The board virtualization modeling module is configured to use virtualization modeling technology based on multi-core heterogeneous systems to simulate the CPU architecture, operating system, board peripherals and peripheral interfaces of the target processor and build a general-purpose digital target machine. The cross-platform communication framework building module is configured to build a cross-platform communication framework based on direct digital frequency synthesis real-time communication transmission technology, and complete the real-time data synchronization between the virtual environment and interactive objects. The fully digital deployment and verification module is configured to complete the fully digital deployment and verification of embedded software through the collaboration of a general-purpose digital target machine and a cross-platform communication framework.

[0079] Preferably, in the board virtualization modeling module, by calling the virtualization modeling technology of multi-core heterogeneous systems, the CPU architecture, operating system, board peripherals, and peripheral interfaces of the target processor are simulated according to the preset simulation logic. The simulation results of each part are integrated to generate a fully functional general-purpose digital target machine that can be adapted to various scenarios, providing a running platform for embedded software.

[0080] Preferably, in the cross-platform communication framework construction module, a cross-platform communication architecture is designed and built based on real-time communication transmission technology using direct digital frequency synthesis. Data transmission protocols and interaction rules are defined, data transmission paths are optimized, and a stable and efficient communication link is constructed to achieve real-time data synchronization between the virtual environment and interactive objects.

[0081] Preferably, in the fully digital deployment and verification module, the embedded software to be deployed is received and loaded into the general-purpose digital target machine constructed by the processing board virtualization modeling module. The cross-platform communication framework construction module coordinates the establishment of a data transmission channel, monitors the software's running status in real time, collects running data and interactive feedback, and completes the fully digital deployment and functional and performance verification of the embedded software.

[0082] It should be noted that this embodiment uses a modular design to make the system structure clear, with each module having a clearly defined responsibility, which facilitates maintenance and upgrades; the collaborative work between the modules realizes a complete process of fully digital deployment and verification of embedded software, without relying on physical hardware, thus improving the efficiency of deployment and verification; the system has strong versatility and adaptability, and can support the deployment and verification needs of various target processors and embedded software.

[0083] More preferably, the embedded software fully digital stimulus deployment system of this embodiment further includes a debugging and performance analysis module, which includes: an instruction-level debugging interface configured to perform breakpoint setting, single-step execution, and register and memory viewing; and a performance counter configured to count CPU utilization, cache hit rate, and bus transaction count.

[0084] Specifically, the implementation process of the debugging and performance analysis module includes: Instruction-level debugging interface implementation: Design breakpoint setting logic to allow users to set breakpoints at any instruction location in the embedded software; develop single-step execution control function to execute the software step by step according to the instruction sequence and provide feedback on the execution status; build register and memory viewing module to read and display the values ​​of processor registers and the data content of memory areas in real time, providing intuitive basis for debugging.

[0085] Performance counters function by defining the statistical logic for core performance metrics such as CPU utilization, cache hit rate, and bus transaction count. During the embedded software's operation, they collect real-time runtime data related to each performance metric, calculate and summarize the data according to preset statistical rules, and generate performance statistics results.

[0086] It should be noted that the aforementioned instruction-level debugging interface provides developers with precise debugging tools, facilitating the rapid location of logical errors and anomalies during the operation of embedded software; the performance counter can comprehensively and in real-time collect core performance data, providing reliable data support for developers to analyze software performance bottlenecks and optimize software operating efficiency; the integration of debugging and performance analysis functions enhances the completeness of fully digital deployment verification, helping developers create high-quality embedded software.

[0087] Example 4 This embodiment is based on embodiment 1: This embodiment provides a computer device, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the embedded software fully digital stimulus deployment method of Embodiment 1. The computer program can be in the form of source code, object code, executable file, or some intermediate form.

[0088] Example 5 This embodiment is based on embodiment 1: This embodiment provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the embedded software fully digital stimulus deployment method of Embodiment 1. The computer program can be in the form of source code, object code, executable file, or some intermediate form. The storage medium includes any entity or device capable of carrying computer program code, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium, etc.

[0089] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

[0090] It should be noted that, for the sake of simplicity, the foregoing method embodiments are described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

Claims

1. A fully digital incentive deployment method for embedded software, characterized in that, include: Based on virtualization modeling technology for multi-core heterogeneous systems, the CPU architecture, operating system, board peripherals and peripheral interfaces of the target processor are simulated to construct a general-purpose digital target machine; Based on direct digital frequency synthesis real-time communication transmission technology, a cross-platform communication framework is built to achieve real-time data synchronization between the virtual environment and interactive objects; Through the collaboration of the general-purpose digital target machine and the cross-platform communication framework, the fully digital deployment and verification of embedded software is completed.

2. The embedded software fully digital stimulus deployment method according to claim 1, characterized in that, Based on virtualization modeling technology for multi-core heterogeneous systems, the CPU architecture of the target processor is simulated, including: Instruction-level simulation core: Based on dynamic binary translation technology, it simulates the multi-core architecture of the target processor and supports single-cycle multi-instruction parallel issuance and functional unit modeling; Layered modeling of the memory system: Layered modeling of the memory system, including L1 / L2 cache modeling, L3 shared memory and DDR3 modeling; Multi-core collaboration: Modeling of inter-core interrupt and shared memory synchronization primitives.

3. The embedded software fully digital incentive deployment method according to claim 1, characterized in that, Based on virtualization modeling technology for multi-core heterogeneous systems, the operating system, board peripherals, and peripheral interfaces of the target processor are simulated, including: Operating system adaptation: Adapts to real-time operating systems and Linux systems, supporting simulation of task scheduling, interrupt response, and system calls; Model library construction: Construct a key peripheral model library including SRIO, PCIe, timers and interrupt controllers, and then realize the simulation of the target processor's board peripherals and peripheral interfaces.

4. The embedded software fully digital incentive deployment method according to claim 1, characterized in that, The construction of the general-purpose digital target machine includes operating system booting, which includes: Processor state initialization: Initialize the boot environment of the target processor, and define the processor state and the master-slave core boot order; Pre-initialization of critical peripherals: Dynamically generate device tree binary files based on command-line parameters and load them into the specified physical memory; Multi-core boot and inter-core communication synchronization: Multiple virtual CPU instances are created using the SMP option, and inter-core communication synchronization is achieved using shared memory regions and atomic operation instructions; Multi-system boot compatibility: Adapts to multiple operating systems through different boot methods.

5. The embedded software fully digital stimulus deployment method according to claim 1, characterized in that, The real-time communication transmission technology based on direct digital frequency synthesis establishes a cross-platform communication framework, including: improving data transmission rate through underlying model hardware acceleration, driver software optimization, and hardware platform acceleration; setting up a real-time data transmission interface to perform data synchronization between the virtual environment and actual hardware and semi-physical devices.

6. The embedded software fully digital stimulus deployment method according to claim 5, characterized in that, The real-time communication transmission technology based on direct digital frequency synthesis, which builds a cross-platform communication framework, also includes: digitally modeling the relevant communication interfaces, performing interface function flow simulation, instantiation application, and adaptation and expansion for different embedded boards. The relevant communication interfaces include CAN bus interface, Ethernet interface, serial port, and I2C bus interface.

7. An embedded software fully digital incentive deployment system, characterized in that, include: The board virtualization modeling module is configured to use virtualization modeling technology based on multi-core heterogeneous systems to simulate the CPU architecture, operating system, board peripherals and peripheral interfaces of the target processor and build a general-purpose digital target machine. The cross-platform communication framework building module is configured to build a cross-platform communication framework based on direct digital frequency synthesis real-time communication transmission technology, and complete the real-time data synchronization between the virtual environment and interactive objects. The fully digital deployment and verification module is configured to complete the fully digital deployment and verification of embedded software through the collaboration of the general-purpose digital target machine and the cross-platform communication framework.

8. The embedded software fully digital incentive deployment system according to claim 7, characterized in that, It also includes a debugging and performance analysis module, which includes: an instruction-level debugging interface configured to perform breakpoint setting, single-step execution, and register and memory viewing; and performance counters configured to count CPU utilization, cache hit rate, and bus transaction count.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the embedded software fully digital stimulus deployment method according to any one of claims 1-6.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the embedded software fully digital stimulus deployment method according to any one of claims 1-6.

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