SOI wafer and manufacturing method

Abstract

The present invention relates to an SOI wafer and a manufacturing method, the manufacturing method comprising: providing a first silicon wafer and a second silicon wafer; forming a bonding surface oxide layer on the bonding surface of the first silicon wafer and the bonding surface of the second silicon wafer respectively; performing plasma injection on the bonding surface of the first silicon wafer and the bonding surface of the second silicon wafer respectively; bonding the bonding surface of the first silicon wafer after the plasma injection to the bonding surface of the second silicon wafer; after bonding, performing a first thinning on the non-bonding surface of the first silicon wafer; after the first thinning, forming a dielectric layer on the non-bonding surface of the second silicon wafer. The present invention deposits a dielectric layer on the back side of the second silicon wafer of the SOI wafer, which can reduce the stress and curvature of the SOI wafer. The dielectric layer is formed after the first silicon wafer and the second silicon wafer are bonded and after the first silicon wafer is thinned for the first time, which is conducive to reducing bonding voids on the bonding surface of the first silicon wafer and the second silicon wafer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an SOI wafer and a manufacturing method thereof. Background Art

[0002] SOI (Silicon-On-Insulator) is silicon on insulating substrate, a new substrate material with a "silicon-insulator-silicon" layered structure. It is achieved by filling a layer of oxide as an insulating layer between the top silicon wafer and the bottom silicon wafer, and using the insulating layer to achieve isolation between the devices on the top silicon wafer and the bottom silicon wafer.

[0003] The existing method for manufacturing SOI wafers is as follows:

[0004] An oxide layer is formed on the surface of the top silicon wafer and the bottom silicon wafer respectively - plasma is injected into the bonding surface of the top silicon wafer and the bonding surface of the bottom silicon wafer respectively - the bonding surface of the top silicon wafer is bonded to the bonding surface of the bottom silicon wafer - the surface of the top silicon wafer is thinned to a standard thickness.

[0005] When using the above method to manufacture SOI wafers, the injection of high-energy plasma during the manufacturing process generates large stress inside the SOI wafer, which will cause the SOI wafer to have a large curvature after thinning. According to statistical measurements, the curvature can reach about -90μm (according to statistics, it is mainly distributed between -80μm and 105μm), which is not conducive to subsequent processes. Summary of the Invention

[0006] The present invention first discloses a method for manufacturing an SOI wafer, which can effectively improve the curvature of the SOI wafer, and specifically adopts the following technical solutions to achieve:

[0007] A method for manufacturing an SOI wafer, comprising:

[0008] providing a first silicon wafer and a second silicon wafer;

[0009] forming bonding surface oxide layers on the bonding surface of the first silicon wafer and the bonding surface of the second silicon wafer respectively;

[0010] performing plasma implantation on the bonding surface of the first silicon wafer and the bonding surface of the second silicon wafer respectively;

[0011] bonding the bonding surface of the first silicon wafer after the plasma injection to the bonding surface of the second silicon wafer;

[0012] After the bonding, performing a first thinning on the non-bonding surface of the first silicon wafer;

[0013] After the first thinning, a dielectric layer is formed on the non-bonding surface of the second silicon wafer.

[0014] Furthermore, the dielectric layer is a silicon dioxide layer.

[0015] Furthermore, the thickness of the dielectric layer is

[0016] Furthermore, after the dielectric layer is formed, the non-bonding surface of the first silicon wafer is thinned for the second time, and the second thinning is performed using an acidic etching solution.

[0017] Furthermore, after the second thinning, the non-bonding surface of the first silicon wafer is thinned for a third time, and the third thinning is performed by chemical mechanical thinning.

[0018] Furthermore, the non-bonding surface of the first silicon wafer and the non-bonding surface of the second silicon wafer each form a non-bonding surface oxide layer, and the dielectric layer is formed on the surface of the non-bonding surface oxide layer of the second silicon wafer.

[0019] The present invention also discloses an SOI wafer, comprising a dielectric layer, a second silicon wafer, a first oxide layer, and a first silicon wafer stacked in sequence. The SOI wafer is manufactured using the above-mentioned manufacturing method.

[0020] Furthermore, a second oxide layer is formed between the second silicon wafer and the dielectric layer.

[0021] Furthermore, the thickness of the dielectric layer is greater than the thickness of the second oxide layer.

[0022] Furthermore, the dielectric layer is a silicon dioxide layer; the thickness of the dielectric layer is

[0023] The present invention forms a dielectric layer on the non-bonding surface of the second silicon wafer. The dielectric layer is formed after the first silicon wafer and the second silicon wafer are bonded and the non-bonding surface of the first silicon wafer is thinned for the first time. The dielectric layer is used to offset the internal stress caused by the bonding of the first silicon wafer and the second silicon wafer, which has a significant effect on improving the curvature of the SOI wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A schematic diagram of a process for manufacturing an SOI wafer using a manufacturing method according to an embodiment of the present invention;

[0025] Figure 2 Schematic diagram of the structure of the SOI wafer disclosed in an embodiment of the present invention;

[0026] Figure 3 This is a curve showing the influence of the thickness of the dielectric layer on the non-bonding surface of the second silicon wafer on the curvature of the SOI wafer. DETAILED DESCRIPTION

[0027] The technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present invention.

[0028] This embodiment first discloses a method for manufacturing an SOI wafer, combining Figure 1 The manufacturing process of forming the SOI wafer is shown, and the manufacturing method of this embodiment is described as follows:

[0029] The method for manufacturing the SOI wafer in this embodiment includes the following steps:

[0030] S1: providing a first silicon wafer 100 and a second silicon wafer 200;

[0031] S2: forming bonding surface oxide layers on the bonding surface of the first silicon wafer 100 and the bonding surface of the second silicon wafer respectively;

[0032] S3: Plasma is injected into the bonding surface of the first silicon wafer 100 and the bonding surface of the second silicon wafer 200 respectively;

[0033] S4: bonding the bonding surface of the first silicon wafer 100 after plasma injection to the bonding surface of the second silicon wafer 200;

[0034] S5: After bonding is completed according to S4, the non-bonding surface of the first silicon wafer 100 is thinned for the first time;

[0035] S6: After the first thinning is completed according to S5, a dielectric layer 300 is formed on the non-bonding surface of the second silicon wafer 200.

[0036] As a further illustration of the above manufacturing method, the first silicon wafer 100 corresponds to the top silicon wafer as the device structure layer mentioned in the background technology, and the second silicon wafer 200 corresponds to the bottom silicon wafer mentioned in the background technology. The bonding surface of the first silicon wafer 100 refers to Figure 1 The bottom surface of the first silicon wafer 100 is shown. The non-bonding of the first silicon wafer 100 refers to Figure 1 The top surface of the first silicon wafer 100 is shown; the bonding surface of the second silicon wafer 200 is Figure 1 The top surface of the second silicon wafer 200, the non-bonding surface of the second silicon wafer 200 refers to Figure 1 The bottom surface of the second silicon wafer 200 is formed.

[0037] In the above step S2, the first silicon wafer 100 and the second silicon wafer 200 are usually placed in a thermal oxidation furnace tube together, and an oxide layer is formed on both sides of the first silicon wafer 100 and both sides of the second silicon wafer 200 by thermal oxidation, that is, the non-bonding surface of the first silicon wafer 100 forms a non-bonding surface oxide layer 101, and the bonding surface of the first silicon wafer 100 forms a bonding surface oxide layer 102; the non-bonding surface of the second silicon wafer 200 forms a non-bonding surface oxide layer 201, and the bonding surface of the second silicon wafer 200 forms a bonding surface oxide layer 202. Of course, if thermal oxidation is not used to form the bonding surface oxide layer in step S2, other methods can also be used to form at least one bonding surface oxide layer on the bonding surface of the first silicon wafer 100 and one bonding surface oxide layer on the bonding surface of the second silicon wafer 200. In this embodiment, the bonding surface oxide layer is formed by growing silicon dioxide by thermal oxidation in a normal pressure furnace tube, mainly because the oxide layer formed by thermal oxidation has high density and low cost.

[0038] In the above step S5 , in this embodiment, the non-bonding surface of the first silicon wafer 100 is thinned for the first time using a Taiko thinning process. After the first thinning, the remaining thickness of the first silicon wafer 100 is about 41.5 μm.

[0039] After step S5 is completed, the stress inside the SOI wafer is relatively large, resulting in an increase in the curvature of the SOI wafer. In order to eliminate the deformation caused by the tensile stress during the bonding process, this embodiment forms a dielectric layer 300 on the non-bonding surface of the second silicon wafer 200 in step S6. The dielectric layer 300 generates compressive stress on the SOI wafer. The two stresses compensate each other to improve the curvature of the SOI wafer.

[0040] Since the bonding surface oxide layer formed in step S2 of this embodiment is thermally oxidized, a non-bonding surface oxide layer 201 is formed on the non-bonding surface of the second silicon wafer 200 , and the dielectric layer 300 is formed on the surface of the non-bonding surface oxide layer 201 of the second silicon wafer 200 .

[0041] The dielectric layer 300 can be made of silicon dioxide or silicon nitride (Si3N4). Preferably, the dielectric layer 300 in this embodiment is a silicon dioxide layer; the dielectric layer 300 is formed by CVD deposition using TEOS (tetraethyl orthosilicate) as a silicon source. This is primarily because silicon dioxide has a lower dielectric constant and stronger electrostatic adsorption than Si3N4, thus preventing the dielectric layer 300 from delaminating from the non-bonded surface oxide layer 201 of the second silicon wafer 200.

[0042] The thickness variation of the dielectric layer 300 and the improvement of the SOI wafer bow (BOW) are as follows: Figure 3As shown, it can be seen that the thicker the dielectric layer 300 is deposited, the more obvious the curvature improvement effect of the SOI wafer is. According to the existing process standard for curvature of SOI wafer, the thickness of the dielectric layer 300 is controlled at It can fully meet the inspection standards.

[0043] In the above manufacturing method, after step S6 is completed to form the dielectric layer 300, the method further includes steps S7 and S8, namely:

[0044] S7: performing a second thinning on the non-bonding surface of the first silicon wafer 100. The second thinning adopts a chemical thinning method, and is performed by etching with an acidic corrosive solution.

[0045] S8: performing a third thinning on the non-bonding surface of the first silicon wafer 100, wherein the third thinning is performed by chemical mechanical polishing (CMP process).

[0046] After the third thinning, the remaining thickness of the first silicon wafer 100 is 23-27 μm. The first silicon wafer 100 of this thickness is generally suitable for manufacturing high-power switching devices, high-speed bipolar circuits, and MEMS devices as a device structure layer.

[0047] In the manufacturing method of the present invention, the formation of dielectric layer 300 is performed after step S5 because the effect of depositing dielectric layer 300 on improving the curvature of the SOI wafer is more significant for thin wafers. The inventors have discovered that if the dielectric layer 300 formation step is placed between steps S2 and S3 to improve the curvature of the SOI wafer, the presence of dielectric layer 300 before bonding will increase the curvature of the second silicon wafer 200. This will easily cause bond voids to form at the edge of the second silicon wafer 200 when the first silicon wafer 100 and the second silicon wafer 200 are bonded. These bond voids can significantly increase the scrap rate of the SOI wafer, with statistically reported scrap rates as high as 40%. Therefore, in this embodiment, the dielectric layer 300 is formed after step S5, which does not affect the curvature of the second silicon wafer 200 before bonding. The first silicon wafer 100 and the second silicon wafer 200 can maintain good flatness before bonding, and the SOI wafer formed after bonding has a low edge void rate.

[0048] After the SOI wafer forms the dielectric layer 300 through step S6, it is thinned for the second time (acid etching method) through step S7 and thinned for the third time (CMP process) through step S8. The three thinning operations reach the standard thickness requirement. If the dielectric layer 300 of the present invention is formed after step S8, the deposition process of the dielectric layer 300 will cause the risk of scratching the polished front side of the SOI wafer. If the formation of the dielectric layer 300 is performed between step S7 and step S8, the front side of the SOI wafer will also be contaminated during the formation of the dielectric layer 300. Therefore, the present invention selects the formation of the dielectric layer 300 between step S5 and step S7, which can not only optimize the curvature of the SOI wafer, but also avoid the problem of scratching and contamination of the SOI wafer surface.

[0049] The SOI wafers manufactured using the above-mentioned manufacturing method of the present invention were compared with the existing method mentioned in the background technology (hereinafter referred to as "method one") and the method in which the dielectric layer 300 is adjusted to be formed between steps S2 and S3 (hereinafter referred to as "method two") to manufacture SOI wafers. The BOW value and product yield test are compared. The comparison results are shown in Table 1.

[0050] Table 1: Comparison of SOI wafers manufactured using the manufacturing method of the present invention, method 1, and method 2

[0051] Statistics Method 1 Method 2 Method of the present invention BOW (bend) -89.3μm -34.2μm -34.6μm Product yield —— 60％ 95％

[0052] To verify the effectiveness of the manufacturing method provided by the present invention in improving SOI wafer bow, SOI wafers were manufactured using Method 1 and Method 2, respectively, and compared with the manufacturing method of the present invention. The bow of an equal number of SOI wafers manufactured using each of the three manufacturing methods was measured. The BOW value given in Table 1 is the average of the bow measurement results for the same number of SOI wafers. Table 1 also shows the bond void inspection results for the same number of SOI wafers manufactured using Method 2 and the method of the present invention. Using the same void inspection criteria, SOI wafers that did not meet the void inspection criteria were eliminated. A count of the number of SOI wafers that met the void inspection criteria was then counted, and the product yields obtained by the two methods were calculated.

[0053] Analysis of the BOW improvement effects given in Table 1 shows that Method 1 does not adopt measures to reduce the internal bonding stress of the SOI wafer, while Method 2 and the method of the present invention both adopt the method of depositing a dielectric layer 300 on the non-bonding surface of the second silicon wafer 200 of the SOI wafer to compensate for the internal bonding stress. From the BOW values ​​statistically analyzed for the three manufacturing methods given in Table 1, it can be seen that the curvature of the SOI wafers obtained by Method 2 and the method of the present invention is significantly lower than that of Method 1. The BOW value of the SOI wafer manufactured by the method of the present invention is 61.25% lower than the BOW value of Method 1, confirming that the manufacturing method of the present invention has low stress characteristics.

[0054] Analysis of the product yield improvement effect given in Table 1: In Method 1, the first silicon wafer 100 and the second silicon wafer 200 are relatively thick before bonding, and the non-bonding surface of the second silicon wafer 200 does not have an additional dielectric layer 300 deposited before bonding, which does not cause the second silicon wafer 200 to deform or bend before bonding. Therefore, the bonding surface of the first silicon wafer 100 and the bonding surface of the second silicon wafer 200 are relatively flat, with fewer bonding voids. The problem of low product yield caused by bonding void defects is not prominent. Therefore, this embodiment only conducts a statistical comparison of the product yield of SOI wafers manufactured by Method 2 and the method of the present invention. In method 2, a dielectric layer 300 is formed on the non-bonding surface of the second silicon wafer 200 before bonding. The formation of the dielectric layer 300 changes the curvature of the second silicon wafer 200 before bonding. When the first silicon wafer 100 and the second silicon wafer 200 are bonded, bonding voids are easily formed at the edge of the curved second silicon wafer 200. These bonding voids easily exceed the inspection standards for voids in existing processes, thereby significantly increasing the scrap rate of SOI wafers. The scrap rate of SOI wafers manufactured according to method 2 due to bonding voids is as high as 40% (the corresponding product yield is only about 60%). In the method of the present invention, the dielectric layer 300 formed on the non-bonding surface of the second silicon wafer 200 is formed after bonding, and will not affect the curvature of the second silicon wafer 200 before bonding. The first silicon wafer 100 and the second silicon wafer 200 can maintain good flatness before bonding. The SOI wafer edge void rate formed after bonding is low, and the scrap rate due to bonding voids is only about 5% (corresponding to a product yield of about 95%). This shows that the manufacturing method of the present invention not only improves the curvature but also significantly reduces the bonding void rate, significantly improving the yield of the SOI wafer.

[0055] This embodiment also discloses an SOI wafer manufactured by the above-mentioned SOI wafer manufacturing method, such as Figure 2 As shown, from bottom to top, it includes a dielectric layer 300, a second oxide layer, a second silicon wafer 200, a first oxide layer, and a first silicon wafer 100 stacked in sequence. The first oxide layer includes the bonding surface oxide layer 102 and the bonding surface oxide layer 202 mentioned in the manufacturing method given above, and the second oxide layer corresponds to the non-bonding surface oxide layer 201 mentioned in the manufacturing method given above.

[0056] In the SOI wafer of the above scheme, the dielectric layer 300 is a silicon dioxide layer, which is formed by using ethyl orthosilicate as a silicon source and deposited by CVD process, which can reduce stress and improve the curvature of the SOI wafer. The thickness of the dielectric layer 300 is greater than the thickness of the second oxide layer. The thickness of the dielectric layer 300 is controlled within It can meet the inspection standards for curvature values ​​in existing processes.

[0057] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A method for manufacturing an SOI wafer, characterized in that: include: providing a first silicon wafer and a second silicon wafer; forming bonding surface oxide layers on the bonding surface of the first silicon wafer and the bonding surface of the second silicon wafer respectively; forming a non-bonding surface oxide layer on the non-bonding surface of the first silicon wafer and the non-bonding surface of the second silicon wafer; performing plasma implantation on the bonding surface of the first silicon wafer and the bonding surface of the second silicon wafer respectively; bonding the bonding surface of the first silicon wafer after the plasma injection to the bonding surface of the second silicon wafer; After the bonding, performing a first thinning on the non-bonding surface of the first silicon wafer; After the first thinning, a dielectric layer is formed on the non-bonding surface of the second silicon wafer, wherein the dielectric layer is formed on the surface of the oxide layer on the non-bonding surface of the second silicon wafer; After the dielectric layer is formed, the non-bonding surface of the first silicon wafer is thinned for the second time.

2. The method for manufacturing an SOI wafer according to claim 1, wherein: The dielectric layer is a silicon dioxide layer.

3. The method for manufacturing an SOI wafer according to claim 1, wherein: The thickness of the dielectric layer is 16KÅ to 22KÅ.

4. The method for manufacturing an SOI wafer according to claim 1, wherein: The second thinning is performed using an acidic corrosive solution.

5. The method for manufacturing an SOI wafer according to claim 4, wherein: After the second thinning, the non-bonding surface of the first silicon wafer is thinned for a third time, and the third thinning is performed by chemical mechanical thinning.

6. An SOI wafer, characterized in that: The SOI wafer comprises a dielectric layer, a second silicon wafer, a first oxide layer, and a first silicon wafer stacked in sequence, and the SOI wafer is manufactured by the manufacturing method according to claim 1.

7. The SOI wafer according to claim 6, wherein: A second oxide layer is formed between the second silicon wafer and the dielectric layer.

8. The SOI wafer according to claim 7, wherein: The thickness of the dielectric layer is greater than the thickness of the second oxide layer.

9. The SOI wafer according to claim 6, wherein: The dielectric layer is a silicon dioxide layer; the thickness of the dielectric layer is 16KÅ to 22KÅ.

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