A lateral power MOSFET device and a method of manufacturing the same

Abstract

The present application relates to a kind of lateral power MOSFET device and its manufacturing method.The present application is provided with first conductive type epitaxial layer on first conductive type substrate, longitudinal trench is provided in first conductive type epitaxial layer, first gate and second gate are provided in longitudinal trench, second conductive type body region is provided on the surface of first conductive type epitaxial layer, first conductive type source and second conductive type source are provided in second conductive type body region, first conductive type source and longitudinal trench are connected, in the direction of longitudinal trench horizontal extension, first conductive type drain adjacent to longitudinal trench is also provided in second conductive type body region.The lateral power MOSFET device and its manufacturing method provided by the present application are compatible with the manufacturing method of conventional SGT MOSFET device, can simultaneously consider lateral power MOSFET device and SGT MOSFET device using a set of process flow, improve the universality of process and reduce manufacturing cost.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device and a manufacturing method thereof, in particular to a lateral power MOSFET device and a manufacturing method thereof. BACKGROUND

[0002] Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) is a voltage-controlled electronic device, generally having three ports of source, gate and drain. For power MOSFET, since it needs to bear high voltage when turned off, it is necessary to form a depletion layer with a certain chip area to withstand voltage. In particular, for lateral power MOSFET device, high voltage device means larger chip area, resulting in the increase of chip cost, but such device has the advantage of easy integration. For vertical power MOSFET device, the part of withstand voltage is transferred from lateral to vertical, which greatly reduces the area of the chip. In addition, the field plate technology commonly used in lateral power devices can greatly improve the voltage resistance efficiency of the device. By introducing this technology into vertical power devices, Shield Gate Trench MOSFET (SGTMOSFET) device structure is born.

[0003] For high-voltage drive chip or intelligent power switch with self-protection, it needs both vertical power MOSFET device to provide lower on-resistance and lateral power MOSFET device to integrate drive or protection function, that is, it needs a set of manufacturing process that can form both vertical MOSFET device and lateral power MOSFET device. SUMMARY

[0004] The purpose of the present application is to overcome the shortcomings in the prior art, provide a lateral power MOSFET device and a manufacturing method thereof, which can be compatible with the traditional SGT process, and can realize the manufacturing of lateral power MOSFET device and vertical power MOSFET device at the same time by using a set of process, so that the designed chip can realize more complex functions and reduce the chip manufacturing cost.

[0005] To achieve the above technical purposes, the technical scheme of the present application is: a lateral power MOSFET device, comprising a substrate metal, a first conductive type substrate is arranged on the substrate metal, a first conductive type epitaxial layer is arranged on the first conductive type substrate, a longitudinal trench composed of silicon dioxide insulating material is arranged in the first conductive type epitaxial layer, a first gate and a second gate composed of polysilicon material are further arranged in the longitudinal trench, the first gate is located at the upper part of the longitudinal trench, the second gate is located at the lower part of the longitudinal trench, the first gate and the second gate are separated by silicon dioxide, a second conductive type body region is further arranged on the surface of the first conductive type epitaxial layer, a heavily doped first conductive type source and a second conductive type source are further arranged on the surface of the second conductive type body region, one side of the heavily doped first conductive type source is connected with the longitudinal trench, the other side of the heavily doped first conductive type source is connected with the heavily doped second conductive type source, a first conductive type drain is further arranged on the surface of the first conductive type epitaxial layer in the direction of horizontal extension of the longitudinal trench, and the first conductive type drain is connected with the longitudinal trench.

[0006] In an embodiment of the present application, an insulating medium is further arranged on the surface of the first conductive type epitaxial layer and the longitudinal trench, and a source metal and a drain metal are further arranged on the surface of the insulating medium.

[0007] In an embodiment of the present application, the source metal is connected with the heavily doped first conductive type source and the second conductive type source through the insulating medium, and the drain metal is connected with the heavily doped first conductive type drain through the insulating medium.

[0008] In an embodiment of the present application, the depth of the first gate is less than the depth of the second conductive type body region.

[0009] In an embodiment of the present application, the depth of the first gate is greater than the depth of the heavily doped first conductive type source and the heavily doped first conductive type drain.

[0010] In an embodiment of the present application, a planar gate is further arranged on the surface of the first conductive type epitaxial layer and the longitudinal trench, the planar gate is composed of a gate oxide layer and a gate polysilicon, the gate polysilicon is above the gate oxide layer, the planar gate respectively terminates on the surface of the first conductive type source and the surface of the first conductive type drain in the direction of horizontal extension of the longitudinal trench, and the planar gate respectively terminates on the surface of the second conductive type source on both sides in the direction perpendicular to the longitudinal trench.

[0011] In one embodiment of the present application, for an N-type power semiconductor device, the first conductivity type is N-type and the second conductivity type is P-type; for a P-type power semiconductor device, the first conductivity type is P-type and the second conductivity type is N-type.

[0012] The present application also provides a method for manufacturing a lateral power MOSFET device, comprising the following steps:

[0013] Step one: select a first conductivity type substrate material and epitaxially grow a first conductivity type epitaxial layer on the surface thereof;

[0014] Step two: use a mask window to selectively etch a longitudinal trench on the upper surface of the first conductivity type epitaxial layer;

[0015] Step three: grow an oxide layer composed of silicon dioxide in the longitudinal trench, and then fill the longitudinal trench with polysilicon to the surface of the first conductivity type epitaxial layer;

[0016] Step four: remove the polysilicon on the surface of the first conductivity type epitaxial layer, further etch the polysilicon in the longitudinal trench to form a second gate, and then deposit an oxide layer in the longitudinal trench to the surface of the first conductivity type epitaxial layer;

[0017] Step five: etch the oxide layer in the longitudinal trench, and then grow a gate oxide layer in the longitudinal trench to form a gate oxide layer of a first gate;

[0018] Step six: fill the longitudinal trench with polysilicon to the surface of the first conductivity type epitaxial layer again to form a first gate, and remove the excess polysilicon;

[0019] Step seven: implant second conductivity type ions on the surface of the first conductivity type epitaxial layer, and form a second conductivity type body region after high temperature annealing; use a mask window to implant high concentration first conductivity type ions and second conductivity type ions on the surface of the second conductivity type body region respectively, and form a heavily doped first conductivity type source, a first conductivity type drain and a second conductivity type source after high temperature annealing;

[0020] Step eight: deposit an insulating medium on the surface of the first conductivity type epitaxial layer and the surface of the longitudinal trench, then selectively etch a via in the insulating medium, and then deposit metal and selectively etch the metal to form a source metal, a gate metal and a drain metal, and deposit a substrate metal under the first conductivity type substrate.

[0021] Compared with the prior art, the technical scheme of the present application has the following advantages: a lateral power MOSFET device compatible with a traditional SGT process and a process method thereof are provided, the process flow of the traditional SGT MOSFET device can be compatible, which means that full integration of the vertical power MOSFET device and the lateral power MOSFET device can be realized. For the intelligent power switch and the self-protecting power MOSFET chip, the single chip using the process can realize all functions of the driving chip + the protection chip + the high-voltage power chip, greatly reducing the complexity of system application, improving the reliability of system application and reducing the chip manufacturing cost. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to make the content of the present application more easily understood, the present application will be further described in detail below according to specific embodiments of the present application and in conjunction with the drawings, in which

[0023] Figure 1 A three-dimensional structure diagram of the device structure of the present application removing the insulating medium and the surface metal.

[0024] Figure 2 A three-dimensional structure diagram of the device structure of the present application.

[0025] Figure 3 A three-dimensional structure diagram of the traditional SGT MOSFET device structure removing the insulating medium and the surface metal.

[0026] Figure 4 A three-dimensional structure diagram of the traditional SGT MOSFET device structure.

[0027] Figure 5 A three-dimensional structure diagram of the device structure of the present application removing the insulating medium and the surface metal. DETAILED DESCRIPTION

[0028] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict. The present application will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0029] In order to make those skilled in the art better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should belong to the protection scope of the present application.

[0030] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0031] The present invention will be further described below with reference to specific accompanying drawings and embodiments.

[0032] Example 1

[0033] A lateral power MOSFET device, wherein when the device is an N-type power semiconductor device, the first conductivity type is N-type and the second conductivity type is P-type; and when the device is a P-type power semiconductor device, the first conductivity type is P-type and the second conductivity type is N-type. This embodiment uses an N-type power semiconductor device as an example. Figure 1 and Figure 2 As shown, the system includes a substrate metal 101, an N-type substrate 102 on the substrate metal 101, an N-type epitaxial layer 103 on the N-type substrate 102, and a longitudinal trench 105 composed of silicon dioxide insulating material within the N-type epitaxial layer 103. A first gate 108 and a second gate 106 composed of polysilicon are also disposed within the longitudinal trench 105. The first gate 108 is located at the upper part of the longitudinal trench 105, and the second gate 106 is located at the lower part of the longitudinal trench 105. Silicon dioxide isolates the first gate 108 and the second gate 106. A P-type body region 104 is also disposed on the surface of the N-type epitaxial layer 103, and heavily doped N-type source 109 and P-type source 107 are also disposed on the surface of the P-type body region 104. One side of the heavily doped N-type source 109 is connected to the longitudinal trench 105, and the other side of the heavily doped N-type source 109 is connected to the heavily doped P-type source 107. In the direction of the horizontal extension of the longitudinal trench 105, an N-type drain 110 is also provided on the surface of the N-type epitaxial layer 103. The N-type drain 110 is connected to the longitudinal trench 105. An insulating medium 112 is also provided on the surface of the N-type epitaxial layer 103 and the longitudinal trench 105. A source metal 113 and a drain metal 114 are also provided on the surface of the insulating medium 112. The source metal 113 passes through the insulating medium 112 and is connected to the heavily doped N-type source 109 and the P-type source 107. The drain metal 114 passes through the insulating medium 112 and is connected to the heavily doped N-type drain 110.

[0034] As shown in the drawings, the source metal 113 and the drain metal 114 of the lateral power MOSFET device are on the surface of the device, which facilitates the mutual integration between devices. Figure 2 As shown in the drawings, the source metal 113 and the drain metal 114 of the lateral power MOSFET device are on the surface of the device, which facilitates the mutual integration between devices.

[0035] When the power device of the present application is turned on, i.e. the first gate voltage of the device is greater than the threshold voltage of the device, the source is connected to a low potential (usually ground), and the drain is connected to a positive voltage. At this time, the device is turned on, the P-type body region on both sides of the first gate is inverted into an N-type channel, and the current flows from the N-type source to the N-type drain through the N-type channel. When the device is horizontally conducting current, since the substrate metal is also connected to a positive voltage, the current flowing in the horizontal direction may flow into the device, and eventually form a leakage through the substrate metal. This leakage will reduce the current capacity of the device and cause reliability problems of the device.

[0036] In order to avoid leakage as much as possible, the present embodiment improves the size of the leakage of the device by using the following scheme.

[0037] As shown in the drawings, the depth of the first gate 108 is less than the depth of the P-type body region 104, and the depth of the first gate 108 is greater than the depth of the heavily doped N-type source 109 and the heavily doped N-type drain 110. Figure 1 Figure 2 The depth of the first gate 108 is less than the depth of the P-type body region 104, which can avoid the formation of a current channel from the surface of the device to the interior of the device when the first gate is connected to a positive voltage to turn on the device. The depth of the first gate 108 is greater than the depth of the heavily doped N-type source 109 and the heavily doped N-type drain 110, which can ensure that a deep enough current channel is formed when the device is turned on, thereby improving the current capacity of the device.

[0038] For example, if the depth of the P-type body region is 5um, and the depth of the heavily doped N-type source and the heavily doped N-type drain is 1um, then the depth of the first gate is preferably 1.5um~2um.

[0039] The manufacturing method based on the present embodiment includes the following steps:

[0040] Step one: select N-type substrate 102 material and epitaxially grow N-type epitaxial layer 103 on the surface thereof;

[0041] Step two: use a mask window to selectively etch a longitudinal groove 105 on the upper surface of the N-type epitaxial layer 103;

[0042] Step three: grow an oxide layer composed of silicon dioxide in the longitudinal groove 105, and then fill polycrystalline silicon in the longitudinal groove 105 to the surface of the N-type epitaxial layer 103;

[0043] Step four: form a first gate 108 on the surface of the N-type epitaxial layer 103, and form a P-type body region 104 on the surface of the first gate 108;

[0044] ​Step four: remove the polysilicon on the surface of the N-type epitaxial layer 103, further etch the polysilicon in the longitudinal trench 105 to form the second gate 106, and then deposit an oxide layer in the longitudinal trench 105 to the surface of the N-type epitaxial layer 103;

[0045] Step five: etch the oxide layer in the longitudinal trench 105, and then grow a gate oxide layer in the longitudinal trench 105 to form the gate oxide layer of the first gate 108;

[0046] Step six: fill the longitudinal trench 105 with polysilicon again to the surface of the N-type epitaxial layer 103 to form the first gate 108, and remove the excess polysilicon;

[0047] Step seven: implant P-type ions on the surface of the N-type epitaxial layer 103, and perform high-temperature annealing to form the P-type body region 104, use a mask window to implant high-concentration N-type ions and P-type ions on the surface of the P-type body region 104 respectively, and perform high-temperature annealing to form the heavily doped N-type source 109, N-type drain 110, and P-type source 107;

[0048] Step eight: deposit an insulating medium 112 on the surface of the N-type epitaxial layer 103 and the surface of the longitudinal trench 105, then selectively etch a via on the insulating medium 112, then deposit metal and selectively etch the metal to form the source metal 113, gate metal, and drain metal 114, and deposit metal under the N-type substrate to form the substrate metal 101.

[0049] The lateral power MOSFET device and the manufacturing method thereof provided by the embodiment can be compatible with the traditional SGT MOSFET process. Here, the traditional SGT MOSFET device structure and the traditional SGT MOSFET device process method are introduced first, and then the compatibility with the present application is analyzed.

[0050] For the traditional SGT MOSFET device, taking the N-type MOSFET device as an example, as shown in FIG. 1, the device structure includes a substrate 101, a P-type body region 104, a first gate 108, a second gate 106, a N-type source 109, a N-type drain 110, and a P-type source 107. Figure 3 and Figure 4As shown, the N-type SGT MOSFET device includes a drain metal 201, an N-type substrate 202 disposed on the drain metal 201, an N-type epitaxial layer 203 disposed on the N-type substrate 202, a longitudinal trench 205 composed of silicon dioxide insulating material disposed in the N-type epitaxial layer 203, a first gate 208 and a second gate 206 composed of polysilicon material disposed in the longitudinal trench 205, the first gate 208 being located at the upper portion of the longitudinal trench 205, the second gate 206 being located at the lower portion of the longitudinal trench 205, the first gate 208 and the second gate 206 being separated by silicon dioxide, a P-type body region 204 disposed on the surface of the N-type epitaxial layer 203, a heavily doped N-type source 209 and a P-type source 207 disposed on the surface of the P-type body region 204, the heavily doped N-type source 209 and the P-type source 207 extending horizontally along the longitudinal trench 205, one side of the heavily doped N-type source 209 being connected to the longitudinal trench 205, the other side of the heavily doped N-type source 209 being connected to the heavily doped P-type source 207, an insulating medium 211 disposed on the surface of the N-type epitaxial layer 203 and the longitudinal trench 205, and a source metal 210 disposed on the surface of the insulating medium 211, the source metal 210 being connected to the heavily doped N-type source 209 and the P-type source 207 through the insulating medium 211.

[0051] The conventional SGT MOSFET device is a longitudinal device, i.e., when the device is turned on, the current flows from the source on the surface of the device to the drain on the back of the device through the channel inside the device, and the drain on the back of the device is not easy to integrate, so the conventional SGT MOSFET device is usually used as a power device alone.

[0052] The biggest difference between the structure of the conventional SGT MOSFET device and the lateral power MOSFET device provided by the present application is that the drain of the lateral power MOSFET device is designed on the surface of the device. Secondly, the depth of the first gate of the device of the present application is smaller than that of the conventional SGT MOSFET device. The above two differences can be realized by fine-tuning of the manufacturing process.

[0053] The manufacturing method of the conventional SGT MOSFET device includes the following steps:

[0054] Step one: select N-type substrate 202 material and epitaxially grow N-type epitaxial layer 203 on the surface thereof;

[0055] Step two: use a mask window to selectively etch a longitudinal trench 205 on the upper surface of the N-type epitaxial layer 203;

[0056] Step three: grow an oxide layer composed of silicon dioxide in the longitudinal trench 205, and then fill polysilicon in the longitudinal trench 205 to the surface of the N-type epitaxial layer 203.

[0057] Step four: remove the polysilicon on the surface of the N-type epitaxial layer 203, further etch the polysilicon in the longitudinal trench 205 to form the second gate 206, and then deposit an oxide layer in the longitudinal trench 205 to the surface of the N-type epitaxial layer 203;

[0058] Step five: etch the oxide layer in the longitudinal trench 205, and then grow a gate oxide layer in the longitudinal trench 205 to form the gate oxide layer of the first gate 208;

[0059] Step six: fill the longitudinal trench 205 with polysilicon again to the surface of the N-type epitaxial layer 203 to form the first gate 208, and then remove the excess polysilicon;

[0060] Step seven: implant P-type ions on the surface of the N-type epitaxial layer 203, and then perform high-temperature annealing to form the P-type body region 204. Use a mask window to implant high-concentration N-type ions and P-type ions on the surface of the P-type body region 204, respectively, and then perform high-temperature annealing to form the heavily doped N-type source 209 and the P-type source 207.

[0061] Step eight: deposit an insulating medium 211 on the surface of the N-type epitaxial layer 203 and the surface of the longitudinal trench 205, then selectively etch a via in the insulating medium 211, and then deposit metal and selectively etch the metal to form the source metal 210, the gate metal, and the drain metal 201 deposited under the N-type substrate.

[0062] Compared with the traditional SGT MOSFET manufacturing method and the manufacturing method of the lateral power MOSFET device provided by the present application, the traditional SGT manufacturing method only needs to be adjusted to realize the manufacturing of the lateral MOSFET device provided by the present application. Specifically, the following steps can be adjusted:

[0063] Step five: increase the mask window, etch away the oxide layer in the longitudinal trench of the traditional SGT MOSFET device, etch away the oxide layer in the longitudinal trench of the lateral power MOSFET device, and then grow a gate oxide layer in the longitudinal trench to form the gate oxide layer of the first gate;

[0064] Step seven: implant P-type ions on the surface of the N-type epitaxial layer, and then perform high-temperature annealing to form the P-type body region. Use a mask window to implant high-concentration N-type ions and P-type ions on the surface of the P-type body region, respectively, and then perform high-temperature annealing to form the heavily doped N-type source and the P-type source of the traditional SGT MOSFET device, and simultaneously form the heavily doped N-type source, N-type drain, and P-type source of the lateral power MOSFET.

[0065] Step eight: depositing insulating medium on the surface of the N-type epitaxial layer and the surface of the longitudinal trench, then etching through holes in the insulating medium selectively, then depositing metal and etching the metal selectively to form the source metal and the gate metal of the conventional SGT MOSFET device, and simultaneously form the source metal, the gate metal and the drain metal of the lateral power MOSFET device, and depositing metal under the N-type substrate, which is the drain metal for the conventional SGT MOSFET device and the substrate metal for the lateral power MOSFET device.

[0066] In step five, a new mask window is needed to form the first gate with smaller depth in the lateral power MOSFET device; in step seven, the N-type source and the N-type drain of the lateral power MOSFET device can share a mask window with the N-type source of the conventional SGT MOSFET device, and no additional mask window is needed; and in step eight, the source metal and the drain metal of the lateral power MOSFET device can share a mask window with the conventional SGT MOSFET device, and no additional mask window is needed.

[0067] In summary, based on the manufacturing method of the conventional SGT MOSFET device, at least one mask window is added to realize the manufacturing of the lateral power MOSFET device, and meanwhile, the manufacturing of the conventional SGT MOSFET device is not affected, i.e., the manufacturing of the conventional SGT MOSFET device and the manufacturing of the lateral power MOSFET device can be realized by using one set of processes, which greatly reduces the development cost of the new device. In addition, the manufacturing of the power MOSFET device with protection function or the smart switch chip can be realized by using the processes, and the expandability of the processes is improved.

[0068] Embodiment 2

[0069] A lateral power MOSFET device, such as Figure 5As shown, it comprises a substrate metal 301, an N-type substrate 302 provided on the substrate metal 301, an N-type epitaxial layer 303 provided on the N-type substrate 302, longitudinal grooves 305 composed of silicon dioxide insulating material provided in the N-type epitaxial layer 303, a first gate 308 and a second gate 306 composed of polysilicon material provided in the longitudinal grooves 305, the first gate 308 being located on the upper part of the longitudinal grooves 305, the second gate 306 being located on the lower part of the longitudinal grooves 305, the first gate 308 and the second gate 306 being separated by silicon dioxide, a P-type body region 304 provided on the surface of the N-type epitaxial layer 303, a heavily doped N-type source 309 and a P-type source 307 provided on the surface of the P-type body region 304, one side of the heavily doped N-type source 309 being connected with the longitudinal grooves 305, the other side of the heavily doped N-type source 309 being connected with the heavily doped P-type source 307, an N-type drain 310 provided on the surface of the N-type epitaxial layer 303 in the direction of horizontal extension of the longitudinal grooves 305, the N-type drain 310 being connected with the longitudinal grooves 305, a planar gate 311 composed of a gate oxide layer and a gate polysilicon provided on the surface of the N-type epitaxial layer 303 and the longitudinal grooves 305, the gate polysilicon being above the gate oxide layer, the planar gate 311 being terminated on the surface of the N-type source 309 and the surface of the N-type drain 310 respectively in the direction of horizontal extension of the longitudinal grooves 305, the planar gate 311 being terminated on the surface of the P-type source 307 on both sides respectively in the direction perpendicular to the longitudinal grooves 305. Insulating medium is further provided on the surface of the N-type epitaxial layer 303, the longitudinal grooves 305 and the planar gate 311, source metal and drain metal are further provided on the surface of the insulating medium, the source metal is connected with the heavily doped N-type source and the P-type source through the insulating medium, and the drain metal is connected with the heavily doped N-type drain through the insulating medium.

[0070] The embodiment is based on the embodiment 1 and further provides a planar gate, so that when the device is turned on, the current can not only flow in the device through the channel formed by the first gate, but also flow on the surface of the device through the surface channel formed by the planar gate, the current capacity of the lateral power MOSFET device is improved, and the on-resistance of the device is reduced.

[0071] The above description of the present application and its embodiments is not restrictive, and the actual structure is not limited thereto. In general, if a person skilled in the art is inspired by it, without departing from the purpose of the present application, similar structure and embodiments can be designed without creative design, which shall belong to the protection scope of the present application.

Claims

1. A method for fabricating a lateral power MOSFET device, characterized in that, The lateral power MOSFET device includes a substrate metal, on which a first conductivity type substrate is disposed, and on which a first conductivity type epitaxial layer is disposed, and in which a longitudinal trench composed of silicon dioxide insulating material is disposed, and a first gate and a second gate composed of polysilicon material are also disposed in the longitudinal trench, the first gate being located at the upper part of the longitudinal trench, the second gate being located at the lower part of the longitudinal trench, and the first gate and the second gate being isolated by silicon dioxide, and a second conductivity type body region is also disposed on the surface of the first conductivity type epitaxial layer; The feature is that a heavily doped first conductive type source and a second conductive type source are further provided on the surface of the second conductive type body region. One side of the heavily doped first conductive type source is connected to the longitudinal trench, and the other side of the heavily doped first conductive type source is connected to the heavily doped second conductive type source. In the direction of the horizontal extension of the longitudinal trench, a first conductive type drain is further provided on the surface of the first conductive type epitaxial layer, and the first conductive type drain is connected to the longitudinal trench. The first type of conductive epitaxial layer and the surface of the longitudinal trench are further provided with an insulating medium, and the surface of the insulating medium is further provided with a source metal and a drain metal; The source metal passes through the insulating medium and is connected to the heavily doped first conductivity type source and the second conductivity type source; the drain metal passes through the insulating medium and is connected to the heavily doped first conductivity type drain. The depth of the first gate is less than the depth of the second conductivity type body region; The depth of the first gate is greater than the depth of the heavily doped first conductivity type source and the heavily doped first conductivity type drain; A planar gate is also provided on the first conductivity type epitaxial layer and the surface of the longitudinal trench. The planar gate is composed of a gate oxide layer and a gate polysilicon layer. The gate polysilicon layer is above the gate oxide layer. The planar gate terminates at the first conductivity type source surface and the first conductivity type drain surface in the direction of horizontal extension of the longitudinal trench, respectively. The planar gate terminates at the second conductivity type source surfaces on both sides in the direction perpendicular to the longitudinal trench. The production method includes the following steps: Step 1: Select a substrate material of the first conductivity type and epitaxially grow an epitaxial layer of the first conductivity type on its surface; Step 2: Using a mask window, selectively etch longitudinal trenches on the upper surface of the first conductivity type epitaxial layer; Step 3: Grow an oxide layer composed of silicon dioxide in the longitudinal trench, and then fill the longitudinal trench with polysilicon up to the surface of the first conductivity type epitaxial layer; Step 4: Remove the polysilicon from the surface of the first conductivity type epitaxial layer, further etch the polysilicon in the longitudinal trench to form the second gate, and then deposit an oxide layer in the longitudinal trench onto the surface of the first conductivity type epitaxial layer. Step 5: Etch the oxide layer in the longitudinal trench, and then grow the gate oxide layer in the longitudinal trench to form the gate oxide layer of the first gate. Step 6: Refill the longitudinal trench with polysilicon up to the surface of the first conductivity type epitaxial layer to form the first gate, and remove the excess polysilicon; Step 7: Implant second conductivity type ions onto the surface of the first conductivity type epitaxial layer, and form a second conductivity type body region by high-temperature annealing. Using a mask window, implant high concentrations of first conductivity type ions and second conductivity type ions onto the surface of the second conductivity type body region, and form a heavily doped first conductivity type source, a first conductivity type drain, and a second conductivity type source after high-temperature annealing. Step 8: Deposit an insulating dielectric on the surface of the first conductivity type epitaxial layer and the surface of the longitudinal trench, then selectively etch through holes on the insulating dielectric, then deposit metal and selectively etch the metal to form source metal, gate metal and drain metal, and deposit metal under the first conductivity type substrate to form substrate metal.

2. The method for fabricating a lateral power MOSFET device according to claim 1, characterized in that, For N-type power semiconductor devices, the first conductivity type is N-type and the second conductivity type is P-type; for P-type power semiconductor devices, the first conductivity type is P-type and the second conductivity type is N-type.

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