Low-power inverter-based CTLE

Abstract

An electronic device including a continuous time linear equalizer (CTLE) is provided. An example of the continuous time linear equalizer (CTLE) includes a first inverter (402); a second inverter (404) having an input terminal (IN) for receiving an input signal; a capacitor (408) coupled between the input terminal of the first inverter (402) and the input terminal of the second inverter (404); a resistor (410) coupled between a common mode voltage (VCM) and the input terminal of the first inverter; a third inverter (406) having an output terminal for providing an output signal (Out); and a node (416) including the output terminal of the first inverter (404), the output terminal of the second inverter (402), the input terminal of the third inverter (406), and the output terminal of the third inverter.

Description

Technical Field

[0001] Examples of the present disclosure relate generally to electronic circuits, and particularly to a low-power inverter-based continuous time linear equalizer (CTLE). Background Art

[0002] The continuous-time linear equalizer (CTLE) is a core analog building block in cable receiver front-ends used for signal equalization. Various CTLE architectures have been investigated to optimize power, area, and performance. Traditional CTLE circuits employ current-mode logic (CML) circuits. Recently, CTLE designs have focused on inverter-based circuits due to their smaller chip area compared to CML-based designs. However, the power and performance of inverter-based designs depend on their topology, the number and size of inverters, and their linearity. Low-power inverter-based designs are needed for CTLEs. Summary of the Invention

[0003] An electronic device including a continuous time linear equalizer (CTLE) and techniques for providing a low-power inverter-based CTLE are described. In one example, the electronic device configured as a continuous time linear equalizer (CTLE) includes: a first inverter; a second inverter having an input to receive an input signal; a capacitor coupled between the input of the first inverter and the input of the second inverter; a resistor coupled between a common-mode voltage and the input of the first inverter; a third inverter having an output to provide an output signal; and nodes including the output of the first inverter, the output of the second inverter, the input of the third inverter, and the output of the third inverter.

[0004] In another example, an electronic device configured as a receiver includes a front-end circuit having a continuous time linear equalizer (CTLE) and a digital back-end circuit coupled to the front-end circuit. The CTLE includes: a first inverter; a second inverter having an input terminal for receiving an input signal; a capacitor coupled between the input terminal of the first inverter and the input terminal of the second inverter; a resistor coupled between a common mode voltage and the input terminal of the first inverter; a third inverter having an output terminal for providing an output signal; and a node including the output terminal of the first inverter, the output terminal of the second inverter, the input terminal of the third inverter, and the output terminal of the third inverter.

[0005] In another example, an electronic device configured as a continuous time linear equalizer (CTLE) includes: a first inverter; a second inverter having an input terminal to receive an input signal; a capacitor coupled between the input terminal of the first inverter and the input terminal of the second inverter; a first resistor coupled between a common mode voltage and the input terminal of the first inverter; a third inverter; a node including an output terminal of the first inverter, an output terminal of the second inverter, and an output terminal of the third inverter, the node providing an output signal;

[0006] and a second resistor coupled between the input terminal of the third inverter and the node.

[0007] These and other aspects can be understood with reference to the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order that the manner in which the features recited above may be understood in detail, a more particular description, briefly summarized above, may be obtained by reference to example implementations, some of which are illustrated in the accompanying drawings. It is noted, however, that the drawings illustrate only typical example implementations and are therefore not to be considered limiting of their scope.

[0009] Figure 1 is a block diagram depicting a receiver according to an example;

[0010] FIG2 is a schematic diagram depicting a CTLE according to the prior art;

[0011] FIG3 is a schematic diagram depicting a CTLE according to the prior art;

[0012] Figure 4 It is depicted based on the example Figure 1 Schematic diagram of CTLE;

[0013] Figure 5 yes Figure 4 The transfer function of the CTLE is shown in Figure 4.

[0014] Figure 6 is a schematic diagram depicting a CTLE according to another example;

[0015] Figure 7 yes Figure 6 The transfer function of CTLE is shown in Figure 2.

[0016] Figure 8 is a schematic diagram depicting a CTLE according to another example;

[0017] Figure 9 is a schematic diagram depicting a CTLE according to another example;

[0018] Figure 10is a schematic diagram depicting a VCM generator for use in the CTLE circuit described herein, according to an example;

[0019] Figure 11 is a schematic diagram depicting a CTLE according to another example;

[0020] Figure 12A is a block diagram depicting a programmable device according to an example;

[0021] Figure 12B is a block diagram depicting a programmable IC according to an example;

[0022] Figure 12C A field programmable gate array (FPGA) implementation of a programmable IC according to an example is shown.

[0023] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements of one example may be beneficially incorporated in other examples. DETAILED DESCRIPTION

[0024] Various features are described below with reference to the accompanying drawings. It should be noted that the drawings may or may not be drawn to scale, and elements of similar structure or function are represented by similar reference numerals throughout the drawings. It should be noted that the drawings are intended only to facilitate the description of the features. They are not intended to serve as an exhaustive description of the claimed invention or to limit the scope of the claimed invention. In addition, the illustrated examples do not necessarily have all the aspects or advantages shown. An aspect or advantage described in conjunction with a particular example is not necessarily limited to that example and can be practiced in any other example, even if not so stated or even if not explicitly described herein.

[0025] Figure 1 1 is a block diagram illustrating electronics configured to provide a receiver 100 according to an example. Receiver 100 includes front-end circuitry 102 and digital back-end circuitry 104. Front-end circuitry 102 includes a continuous time linear equalizer (CTLE) 106 and other components (e.g., automatic gain control circuitry, filters, other CTLEs that may be the same as or different from CTLE 106, etc.). Digital back-end circuitry 104 includes various circuitry for processing the analog signal output by front-end circuitry 102 (e.g., a sampler, an analog-to-digital converter (ADC), a decision feedback equalizer (DFE) circuit, clock and data recovery circuitry, etc.). CTLE 106 receives an input signal and operates as a high-pass filter to compensate for the low-pass characteristics of the transmission medium providing the input signal. The peak amplitude and position of the frequency response of CTLE 106 can be adjusted by control circuitry in front-end circuitry 102 and / or digital back-end circuitry 104. An example implementation of CTLE 106 is described below.

[0026] FIG2 is a schematic diagram illustrating a CTLE 200 according to the prior art. Such a circuit is described in "A 56 Gb / s 6 mW 300 μm² Inverter-Based CTLE for Short-Reach PAM2 Applications in 16 nm CMOS," presented by Zheng, Kevin, et al. at the 2018 IEEE Integrated Circuit Conference (CICC). CTLE 200 includes inverters 202, 204, 208, and 210, and a capacitor 206. The inputs of inverters 202 and 204 are coupled to receive an input signal (IN). The output of inverter 202 is coupled to node X. The output of inverter 204 is coupled to node Y. Capacitor 206 is coupled between nodes X and Y. The input and output of inverter 208 are both coupled to node X. The input and output of inverter 210 are both coupled to node Y. The output of inverter 210 provides an output signal (OUT).

[0027] Assume that inverter 204 has a transconductance gm1, inverter 202 has a transconductance gm2, and inverters 208 and 210 have transconductance gm L , capacitor 206 has a capacitance C HF CTLE 200 is an inverter-based CTLE that uses a summing topology. Peaking is achieved by adding gm2 to the high-frequency signal path through capacitor 206 (creating a "summing" topology). Low-frequency gain (G1), high-frequency gain (G2), and peaking are defined by the following equations:

[0028] G1=gm1 / gm L

[0029] G2=(gm1+gm2) / (2*gm L )

[0030] Peaking (dB) = 20*log[(gm1+gm2) / 2*gm1]

[0031] The boundary between low and high frequencies is defined by C HF and gm L Sure.

[0032] FIG3 is a schematic diagram illustrating a CTLE 300 according to the prior art. The CTLE of FIG3 uses a subtractive topology, such as that described in "An Inverter-based Analog Front End for a 56 Gb / s PAM4 Wireline Transceiver in 16 nm CMOS," presented by Zheng, Kevin, et al. at the 2018 IEEE Integrated Circuits Conference (CICC). CTLE 300 includes inverters 302, 304, 306, 308, and 310, and a capacitor 312. The inputs of inverters 302 and 308 are coupled to receive an input signal (IN). The output of inverter 302 is coupled to the input of inverter 304, the output of inverter 304, and the input of inverter 306 (referred to as node 314). The output of inverter 306 is coupled to the output of inverter 308, the input of inverter 310, and the output of inverter 310 (referred to as node 316). Node 316 provides an output signal (OUT).

[0033] Assume that the inverter 302 has a transconductance gm A , the inverter 304 has a transconductance gm B , inverter 306 has a transconductance gm2, inverter 308 has a transconductance gm1, and inverter 310 has a transconductance gm L For the CTLE 300, G1, G2, and Peak are defined by the following equations:

[0034] G1=(gm1 / gm L )–(gm A / gm B )*(gm2 / gm L )

[0035] G2=gm1 / gm L

[0036] Peak value (dB) = 20*log[(gm B *gm1) / (gm B *gm1-gm A *gm2)]

[0037] The boundary between low and high frequencies is defined by CHF and gm B Decide.

[0038] While inverter-based CTLE designs are attractive in terms of area consumption, power consumption is a major design concern. The more aggressive the equalization required, the more power the CTLE consumes. Another design concern for inverter-based CTLEs is linearity, which affects the signal-to-noise and distortion ratio (SNDR). To illustrate power estimation, assume G1 = 0 dB and G2 = 6 dB, which results in a 6 dB peak.

[0039] Consider the addition topology shown in Figure 2. In this case:

[0040] G1=gm1 / gm L =1(0dB)

[0041] G2=(gm1+gm2) / (2*gm L )=2(6dB)

[0042] gm1=gm L

[0043] gm2=3*gm L

[0044] Total gm = gm1 + gm2 + 2*gm L =gm L +3*gm L +2*gm L =6*gm L

[0045] Therefore, the transconductance of inverter 202 is 3*gm L In this example, the transconductance of inverter 204 is gm L The total device drain parasitic capacitance is about 6*Cdd; the total device gate parasitic capacitance is about 2*Cgg, where Cdd and Cgg are gm L The drain and gate capacitances of the inverters are the transconductance of the transistors. The summing topology of Figure 2 has linearity issues due to the common-mode mismatch between nodes X and Y. HF and two different gms L The DC bias conditions at the inverter, node X, and node Y are not the same. More specifically, when all components are perfectly matched, the bias conditions of the inverter are virtually identical. However, when the input swings, nonlinearity occurs. In this topology, the top path requires 3x(gm2 / gm L =3) to achieve 6dB peaking. In this case, the top path may saturate when the input swing is large. This will cause the inverter to have a very different large-signal bias compared to the bottom path.

[0046] In the subtractive topology of Figure 3, again assuming G1 = 0 dB and G2 = 6 dB, this will produce a 6 dB peak. In this case:

[0047] (1)G1=(gm1 / gm L )–(gm A / gm B )*(gm2 / gm L )=1(0dB)

[0048] (2) G2 = gm1 / gm L =2(6dB)->gm1=2*gm L

[0049] (3) From (1), gm1–(gm A / gm B )*gm2=gm L

[0050] From (2) and (3), gm2=(gm B / gm A )*gm L

[0051] Total gm = gm1 + gm2 + gm L =2*gm L +(gm B / gm A )*gm L +gm L =3*gm L +(gm B- / gm A )*gm L

[0052] If gm A =gm B , then the total gm is 4*gm L

[0053] To make a fair comparison with the adder topology of Figure 2, the subtracter topology of Figure 3 has a gm of L Should be doubled (e.g., 2*gm L ). Therefore, the inverter 306 has 2*gm L The transconductance of inverter 308 is 4*gm L The transconductance of inverter 310 is 2*gm L The transconductance of gm A =gm B , the total gm is now 8*gm LThe total device drain parasitic capacitance at the output OUT is approximately 8*Cdd; the total device gate parasitic capacitance at the output OUT is approximately 2*Cgg, where Cdd and Cgg are gm L The transconductance of the inverter is the drain and gate parasitic capacitance.

[0054] Comparing the adding topology of Figure 2 with the subtracting topology of Figure 3 , the subtracting topology improves linearity because the output of inverter 308 and the output of inverter 306 are connected together. Specifically, connecting the outputs of inverters 306 and 308 together makes their large-signal bias conditions very similar, eliminating the issues with the adding topology of Figure 2 . However, the subtracting topology of Figure 3 exhibits higher power consumption and more device parasitic capacitance to achieve the same gain-bandwidth product as the adding topology of Figure 2 .

[0055] Figure 4 1 is a schematic diagram illustrating a CTLE 106 according to an example. The CTLE 106 includes inverters 402, 404, and 406, as well as a capacitor 408 and a resistor 410. The CTLE 106 may be coupled to a VCM generator 450. Figure 10 An example VCM generator 450 is described. Those skilled in the art will appreciate that other types of common-mode voltage generators may be used. Node 412 is coupled to the input of inverter 402. Node 414 is coupled to the input of inverter 404. Capacitor 408 is coupled between nodes 412 and 414. Resistor 410 is coupled between voltage VCM and node 412. Node 414 receives an input signal (IN). The output of inverter 402 is coupled to: the output of inverter 404, the input of inverter 406, and the output of inverter 406 (referred to as node 416). Node 416 provides an output signal (OUT). Resistor 410 has a resistance R HF ; Capacitor 408 has a capacitance C HF Inverter 404 has a transconductance gm1; Inverter 402 has a transconductance gm2; Inverter 406 has a transconductance gm L .

[0056] Figure 4 The CTLE 106 shown in FIG2 employs an adding topology. In contrast to the CTLE 200 of FIG2 , capacitor 408 is provided at the input of inverters 402 and 404. In addition, Figure 4 CTLE 106 omits gm L One of the inverters (eg, inverter 208). Voltage VCM is an input common-mode voltage generated internally by front-end circuit 102. An example of generating VCM is described below.

[0057] For CTLE 106, G1 and G2 are defined by the following equations:

[0058] G1=gm1 / gm L

[0059] G2=(gm1+gm2) / gm L

[0060] Peak value (dB) = 20*log[(gm1+gm2) / gm1]

[0061] At low frequencies, the input signal is blocked by capacitor 408. At high frequencies, the input signal passes through capacitor 408. Therefore, CTLE 106 is an adding topology. The transfer function of CTLE 106 is:

[0062] (gm1 / gm L )*(1+(gm2 / gm1)*(sR HF C HF / (1+sR HF C HF ))),

[0063] where s is the complex frequency parameter.

[0064] Figure 5 yes Figure 4 Graph 500 of the transfer function of CTLE 106 is shown. Graph 500 includes a vertical axis representing gain (dB) and a horizontal axis representing frequency (logarithmic scale). Curve 502 represents the transfer function of CTLE 106, which has a gain of 20*log(G2) between frequencies F2 and F3. Between frequencies 0 and F1, the gain is 20*log(G1). Therefore, the peak value obtained is 20*log(G2 / G1) in dB. The gain decreases after frequency F3.

[0065] Assume G1 = 0dB and G2 = 6dB, which results in a 6dB peak. In this case:

[0066] G1=gm1 / gm L =1(0dB)->gm1=gm L

[0067] G2=(gm1+gm2) / gm L =2(6dB)->gm2=gm L

[0068] Total gm = gm1 + gm2 + gm L =3*gm L

[0069] To make a fair comparison with the CTLE 200 of FIG2 , the gm of the CTLE 106 is LShould be doubled (e.g., 2*gm L ). In this case, the inverter 402 has 2*gm L The transconductance of inverter 404 is 2*gm L The transconductance of inverter 406 is 2*gm L The total device drain parasitic capacitance at OUT is about 6*Cdd; the total device gate parasitic capacitance at OUT is about 2*Cgg, where Cdd and Cgg are the transconductance gm L Compared with the additive topology of Figure 2, Figure 4 The summing topology shows the same power dissipation and device parasitic capacitances, but does not have the linearity issue because the outputs of inverters 402 and 404 are connected together.

[0070] Table 1 below summarizes the CTLE 200 and Figure 4 Comparison between CTLE 106.

[0071] Table 1

[0072]

[0073] As shown in Table 1, Figure 4 The topology with CTLE 106 in FIG2 shows less power consumption than the subtractive topology and has no linearity issues as shown in the additive topology of FIG2 .

[0074] Figure 6 FIG is a schematic diagram illustrating a CTLE 600 according to another example. CTLE 600 can be used as an alternative version of CTLE 106 described above. CTLE 600 exhibits multiple peaks at low and high frequencies. Figure 4 Compared to the CTLE 106, the additional peaking is achieved by adding another inverter, resistor and capacitor.

[0075] Specifically, CTLE 600 includes inverters 602, 604, 606, and 608, resistors 610 and 612, and capacitors 614 and 616. Node 618 is coupled to the input of inverter 602. Node 620 is coupled to the input of inverter 604. Node 622 is coupled to the input of inverter 606. Capacitor 614 is coupled between nodes 618 and 620. Capacitor 616 is coupled between nodes 620 and 622. Resistor 610 is coupled between node 618 and voltage VCM. Resistor 612 is coupled between node 622 and voltage VCM. Node 624 includes the output of inverter 602, the output of inverter 604, the output of inverter 606, the input of inverter 608, and the output of inverter 608. Node 624 provides an output signal (OUT). Node 620 receives the input signal (IN). Resistors 610 and 612 each have a resistance value of R HF and R LF Capacitors 614 and 616 have capacitance values C HF and C LF Inverters 604, 602, 606 and 608 have transconductances gm1, gm2, gm3 and gm respectively. L .

[0076] Figure 7 yes Figure 6 Graph 700 of the transfer function of CTLE 600 is shown. Graph 700 includes a vertical axis representing gain (dB) and a horizontal axis representing frequency (logarithmic scale). Curve 702 represents the transfer function of CTLE 600, which has a medium gain equal to 20*log(G1) between frequencies FL2 and FH1, and a high gain equal to 20*log(G2) between frequencies FH2 and F3. Between frequencies 0 and FL1, the low gain is equal to 20*log(G0). Therefore, for peak H and peak L , the peak values obtained are 20*log(G2 / G1) and 20*log(G2 / G0), respectively, in dB. The gain drops after frequency F3. CTLE 600 can be expanded to have more peak values by adding inverter branches between the input and output (using corresponding capacitors and resistors).

[0077] Figure 8is a schematic diagram depicting a CTLE 800 according to another example. CTLE 800 can be used as an alternative to CTLE 106 described above. CTLE 800 includes inverters 802, 804, and 806, as well as a capacitor 808 and resistors 810 and 818. Node 812 is coupled to the input of inverter 802. Node 814 is coupled to the input of inverter 804. Capacitor 808 is coupled between nodes 812 and 814. Resistor 810 is coupled between voltage VCM and node 812. Node 814 receives an input signal (IN). The output of inverter 802 is coupled to the output of inverter 804 and the output of inverter 806 (referred to as node 816). Node 816 provides an output signal (OUT). Resistor 818 is coupled between node 816 and the input of inverter 806. Resistor 810 has a resistance value of R HF ; Capacitor 808 has a capacitance C HF Inverter 804 has a transconductance gm1; Inverter 802 has a transconductance gm2; Inverter 806 has a transconductance gm L , the resistor 818 has a resistance value R A CTLE 800 is similar to Figure 4 CTLE 106, but achieves bandwidth extension by using an active inductor formed by inverter 806 and resistor 818.

[0078] Figure 9 is a schematic diagram depicting a CTLE 900 according to another example. CTLE 900 includes inverters 902, 904, and 906, as well as a capacitor 908, a resistor 910, and an inductor 918. Node 912 is coupled to the input of inverter 902. Node 914 is coupled to the input of inverter 904. Capacitor 908 is coupled between nodes 912 and 914. Resistor 910 is coupled between voltage VCM and node 912. Node 914 receives an input signal (IN). The output of inverter 902 is coupled to: the output of inverter 904, the input of inverter 906, and the output of inverter 906 (referred to as node 916). Inductor 918 is coupled to node 916 and provides an output signal (OUT). Resistor 910 has a resistance value of R HF ; Capacitor 908 has a capacitance C HF Inverter 904 has a transconductance gm1; Inverter 902 has a transconductance gm2; Inverter 906 has a transconductance gm L ; and the inductor 918 has an inductance value L. The CTLE 900 is similar to Figure 4 CTLE 106 , but employs bandwidth extension using passive inductor 918 .

[0079] In a further example, various components of CTLEs 106, 600, 800, and 900 can be variable and programmable for equalization goals and applications. For CTLE 106, this includes resistor 410, capacitor 408, inverter 402, inverter 404, and inverter 406 (i.e., the inverters can have adjustable transconductance). For CTLE 600, this includes resistors 610, 612, capacitors 614, 616, and inverters 602, 604, 606, and 608. For CTLE 800, this includes resistors 810, 818, capacitor 808, and inverters 802, 804, and 806. For CTLE 900, this includes resistor 910, capacitor 908, inductor 918, and inverters 902, 904, and 906.

[0080] Figure 10 FIG2 is a schematic diagram illustrating a VCM generator 1000 for use in the CTLE circuit described herein, according to an example. VCM generator 1000 includes an inverter 1002, whose input is connected to its output to provide voltage VCM. VCM generator 1000 is implemented using a diode-based inverter. In terms of layout style and bias conditions (e.g., current density), inverter 1002 should be a replica of inverters 402, 404, and 406.

[0081] Figure 11 FIG1 is a schematic diagram illustrating a CTLE 1100 according to another example. CTLE 1100 generates a common-mode voltage VCM from a pseudo-differential output. CTLE 1100 includes inverters 1102, 1104, 1106, 1122, 1124, and 1126. CTLE 1100 also includes resistors 1110, 1130, 1137, and 1138. CTLE 1100 also includes capacitors 1108 and 1128.

[0082] Node 1112 is coupled to the input of inverter 1102. Node 1114 is coupled to the input of inverter 1104. Capacitor 1108 is coupled between nodes 1112 and 1114. Resistor 1110 is coupled between node 1114 and node 1140, which provides VCM. Node 1112 receives an input signal (INP). The output of inverter 1102 is coupled to: the output of inverter 1104, the input of inverter 1106, and the output of inverter 1106 (referred to as node 1116). Node 1116 provides an output signal (OUTN). Resistor 1110 has a resistance value of R HF ; Capacitor 1108 has a capacitance value C HF Inverter 1102 has a transconductance gm1; Inverter 1104 has a transconductance gm2; Inverter 1106 has a transconductance gm L .

[0083] Node 1132 is coupled to the input of inverter 1122. Node 1134 is coupled to the input of inverter 1124. Capacitor 1128 is coupled between nodes 1132 and 1134. Resistor 1130 is coupled between node 1132 and node 1140, which provides VCM. Node 1134 receives an input signal (INN). The output of inverter 1122 is coupled to the output of inverter 1124, the input of inverter 1126, and the output of inverter 1126 (referred to as node 1136). Node 1136 provides an output signal (OUTP). Resistor 1130 has a resistance value of R HF ; Capacitor 1128 has a capacitance value C HF Inverter 1124 has a transconductance gm1; Inverter 1122 has a transconductance gm2; Inverter 1126 has a transconductance gm L .

[0084] Resistor 1137 is coupled between node 1116 and node 1140. Resistor 1138 is coupled between node 1136 and node 1140. Node 1140 provides voltage VCM. In this pseudo-differential case, VCM is generated by self-biasing, which eliminates the power dissipation associated with using a replica diode as a VCM generator.

[0085] Figure 12A is a block diagram depicting a programmable device 54 according to an example. The programmable device 54 includes a plurality of programmable integrated circuits (ICs) 1, such as programmable ICs 1A, 1B, 1C, and 1D. In the example, each programmable IC 1 is an IC die disposed on an interposer 60. Each programmable IC 1 includes a super logic region (SLR) 53 of the programmable device 54, such as SLRs 53A, 53B, 53C, and 53D. The programmable ICs 1 are interconnected via conductors on the interposer 60, referred to as super long lines (SLLs) 52.

[0086] Figure 12Bis a block diagram depicting a programmable IC 1 according to an example. The programmable IC 1 can be used to implement a programmable device or one of the programmable ICs in programmable device 54. The programmable IC 1 includes programmable logic (PL3) (also called programmable fabric), configuration logic 25, and configuration memory 26. The programmable IC 1 can be coupled to external circuitry, such as nonvolatile memory 27, DRAM 28, and other circuitry 29. PL3 includes logic cells 30, support circuitry 31, and programmable interconnect 32. Logic cells 30 include circuitry that can be configured to implement general logic functions for multiple inputs. Support circuitry 31 includes specialized circuitry, such as transceivers, input / output blocks, digital signal processors, and memory. Logic cells and support circuitry 31 can be interconnected using programmable interconnect 32. Information used to program logic cells 30, to set parameters for support circuitry 31, and to program programmable interconnect 32 is stored in configuration memory 26. Configuration logic 25 can obtain configuration data from nonvolatile memory 27 or any other source (e.g., DRAM 28 or from other circuitry 29). In some examples, the programmable IC 1 includes a processing system (PS) 2. The PS 2 may include a microprocessor, memory, support circuits, IO circuits, etc. In some examples, the programmable IC 1 includes a network on chip (NOC) 55 and a data processing engine (DPE) array 56. The NOC 55 is configured to provide communication between subsystems of the programmable IC 1, such as communication between subsystems of the programmable IC 1, such as between the PS 2, the PL 3, and the DPE array 56. The DPE array 56 may include an array of DPEs configured to perform data processing, such as an array of vector processors. In an example, the programmable IC 1 may include one or more instances of the CTLE 106, including any example implementation thereof described herein.

[0087] Figure 12C A field programmable gate array (FPGA) implementation of a programmable IC 1 including a PL 3 is illustrated. Figure 12C The PL 3 shown in FIG can be used in any of the examples of programmable devices described herein. The PL 3 includes a number of different programmable blocks, including configurable logic blocks ("CLBs") 33, random access memory blocks ("BRAMs") 34, input / output blocks ("IOBs") 36, configuration and clock logic ("CONFIG / CLOCKS") 42, digital signal processing blocks ("DSPs") 35, specialized input / output blocks ("I / Os") 41 (e.g., configuration ports and clock ports), and other programmable logic 39, such as digital clock managers, analog-to-digital converters, system monitoring logic, etc. In an example, the programmable IC 1 can include one or more instances of the CTLE 106, including any of the example implementations thereof described herein.

[0088] In some PLs, each programmable block may include at least one programmable interconnect element ("INT") 43 having connections to inputs and outputs 48 of programmable logic elements within the same block, such as Figure 6 D is shown as an example contained at the top. Each programmable interconnect element 43 may also include a connection to an interconnect segment 49 of an adjacent programmable interconnect element in the same block or other blocks. Each programmable interconnect element 43 may also include a connection to an interconnect segment 50 of a general routing resource between logic blocks (not shown). General routing resources may include routing channels between logic blocks (not shown), which include tracks of interconnect segments (e.g., interconnect segments 50) and switch blocks (not shown) for connecting the interconnect segments. The interconnect segments of the general routing resources (e.g., interconnect segments 50) may span one or more logic blocks. The programmable interconnect elements 43, together with the general routing resources, implement a programmable interconnect structure ("programmable interconnect") for the PL shown.

[0089] In an example implementation, the CLB 33 may include a configurable logic element ("CLE") 44, which may be programmed to implement user logic plus a single programmable interconnect element ("INT") 43. The BRAM 34 may include a BRAM logic element ("BRL") 45 and one or more programmable interconnect elements. Typically, the number of interconnect elements included in a block depends on the height of the block. In the illustrated example, the BRAM block has the same height as five CLBs, but other numbers (e.g., four) may be used. In addition to an appropriate number of programmable interconnect elements, the DSP block 35 may also include a DSP logic element ("DSPL") 46. In addition to one instance of the programmable interconnect element 43, the IOB 36 may include, for example, two instances of an input / output logic element ("IOL") 47. As will be appreciated by those skilled in the art, for example, the actual I / O pads connected to the I / O logic element 47 are generally not limited to the area of the input / output logic element 47.

[0090] In the illustrated example, a columnar area near the center of the die (as shown in FIG3D ) is used for configuration, clock, and other control logic. Vertical columns 51 extending from the horizontal areas or columns are used to distribute clock and configuration signals across the width of the PL.

[0091] use Figure 12C Some PLs of the illustrated architecture include additional logic blocks that disrupt the conventional columnar structure that makes up most of the PL. The additional logic blocks can be programmable blocks and / or dedicated logic.

[0092] It should be pointed out that Figure 12CThis is intended to illustrate only an exemplary PL architecture. For example, the number of logic blocks in a row, the relative widths of the rows, the number and order of the rows, the types of logic blocks contained in the rows, the relative sizes of the logic blocks, and the number of logical blocks contained in the rows. Figure 12C The interconnect / logic implementation shown at the top is purely exemplary. For example, in a real PL, wherever a CLB appears, there is typically more than one adjacent CLB row to facilitate efficient implementation of user logic, but the number of adjacent CLB rows will vary with the overall size of the PL.

[0093] While the foregoing is directed to particular examples, other and further examples may be devised without departing from the basic scope thereof, and the scope of the same is to be determined by the claims that follow.

Claims

1. An electronic device, characterized in that: The electronic device comprises: Continuous Time Linear Equalizer (CTLE), including: a first inverter having an input connected to a first node; a second inverter having an input terminal connected to a second node, the input terminal of the second inverter being configured to receive a low-frequency component of an input signal and a high-frequency component of the input signal via the second node; a capacitor connected to the first node and the second node, wherein the capacitor is configured to block the low-frequency component to the first node and pass the high-frequency component to the first node; a first resistor coupled between a common mode voltage and the first node; a third inverter having an output terminal for providing an output signal; and A third node includes the output terminal of the first inverter, the output terminal of the second inverter, the input terminal of the third inverter, and the output terminal of the third inverter.

2. The electronic device according to claim 1, wherein The electronic device comprises: a front-end circuit having a CTLE; and A digital back-end circuit is coupled to the front-end circuit.

3. The electronic device according to any one of claims 1 and 2, characterized in that Also includes: The common mode voltage generator is coupled to the first resistor to provide the common mode voltage.

4. The electronic device according to claim 3, characterized in that The common-mode voltage generator comprises: A fourth inverter has an input terminal and an output terminal, wherein the input terminal and the output terminal of the fourth inverter are coupled and provide the common mode voltage.

5. The electronic device according to claim 4, characterized in that The fourth inverter is a replica of each of the first inverter, the second inverter, and the third inverter.

6. The electronic device according to any one of claims 1 and 2, characterized in that Also includes: a fourth inverter having an output terminal coupled to the node; an additional capacitor coupled between an input terminal of the second inverter and an input terminal of the fourth inverter; and An additional resistor is coupled between the common mode voltage and the input terminal of the fourth inverter.

7. The electronic device according to any one of claims 1 and 2, characterized in that Also includes: An inductor is coupled between the third node and the output signal.

8. The electronic device according to any one of claims 1 and 2, characterized in that The capacitor comprises a first capacitor, and wherein the CTLE further comprises: a fourth inverter; a fifth inverter having an input terminal coupled to receive an additional input signal, the input signal and the additional input signal comprising a differential signal pair; a second capacitor coupled between the input terminal of the fifth inverter and the input terminal of the fourth inverter; a second resistor coupled between the input terminal of the fourth inverter and the common mode voltage; a sixth inverter having an output terminal providing an additional output signal, the output signal and the additional output signal comprising a differential signal pair; a fourth node, comprising the output end of the fourth inverter, the output end of the fifth inverter, the input end of the sixth inverter, and the output end of the sixth inverter; A fifth node, providing the common mode voltage; a third resistor coupled between the third node and the fifth node; and The fourth resistor is coupled between the fourth node and the fifth node.

9. An electronic device, characterized in that: The electronic device comprises: Continuous Time Linear Equalizer (CTLE), including: a first inverter having an input connected to a first node; a second inverter having an input terminal connected to a second node, the input terminal of the second inverter being configured to receive a low-frequency component of an input signal and a high-frequency component of the input signal via the second node; a capacitor connected to the first node and the second node, wherein the capacitor is configured to block the low-frequency component to the first node and pass the high-frequency component to the first node; a first resistor coupled between a common mode voltage and the first node; a third inverter; a third node, the third node including the output terminal of the first inverter, the output terminal of the second inverter, and the output terminal of the third inverter, the third node providing an output signal; and The second resistor is coupled between the input terminal of the third inverter and the third node.

10. The electronic device according to claim 9, characterized in that The electronic device further comprises: The common mode voltage generator is coupled to the first resistor to provide the common mode voltage.

11. The electronic device according to claim 10, wherein: The common-mode voltage generator comprises: The fourth inverter has an input terminal and an output terminal, wherein the input terminal and the output terminal of the fourth inverter are coupled and provide a common mode voltage.

12. The electronic device according to claim 11, wherein: The fourth inverter is a replica of each of the first inverter, the second inverter, and the third inverter.

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