FPGA-based chip core verification device and method

Abstract

The application provides a kind of FPGA-based chip core verification device and method, by connecting a chip core verification device consisting of register and selector outside IP unit, when carrying out FPGA verification, the intermediate data to be verified that need to be read is cached to the register unit of chip core verification device, and the register unit 300 is connected to the system bus, so that the processing module reads the intermediate data to be verified of register unit through the system bus, so that IP design is more quickly and clearly positioned error after problem occurs in FPGA verification stage, by reading the intermediate data to be verified in IP that can affect function, make verification more reliable.In addition, in circuit implementation, by increasing selection unit and enable signal to select the line network or register that needs to be read, waste of address space is avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of programmable array logic, in particular to a chip core verification device and method based on FPGA. BACKGROUND

[0002] After the IP (Intelligent Property) core design of a chip, FPGA (Field Programmable Gate Array, programmable array logic) verification is needed for the IP. In the FPGA verification process, the same method as simulation cannot be used to see the values of all signals, and only the values of the registers hung on the bus can be used to determine whether errors occur in the verification process of the IP. When the FPGA chip is programmed by Keil engineering, the printed registers can only be used to determine whether errors occur.

[0003] Therefore, there is a lack of effective verification method for IP in the prior art. SUMMARY

[0004] Therefore, it is necessary to provide a chip core verification device and method based on FPGA in view of the above technical problems.

[0005] A chip core verification device based on FPGA, comprising: a logic unit, a selection unit and at least one register unit.

[0006] The first input end of the logic unit is connected with the clock pulse signal end, the second input end of the logic unit is connected with the enable end, and the output end of the logic unit is connected with each register unit; the input end of the selection unit is connected with the IP unit, and the output end of the selection unit is connected with the input end of each register unit; and the output end of the register unit is connected with the processing module through a bus interface.

[0007] The selection unit is used to receive intermediate data to be verified of the IP unit and send the intermediate data to be verified to the register unit, the logic unit is used to receive signals of the clock pulse signal end and the clock pulse signal end, control the register unit to work, the register unit is used to store the intermediate data to be verified, the processing module is used to read the intermediate data to be verified stored by the register unit, verify the intermediate data to be verified, determine error data based on the verification result of the intermediate data to be verified, and modify the intermediate data to be verified of the IP unit based on the error data.

[0008] In one of the embodiments, the selection unit comprises at least one first selector and at least two second selectors, a first input of the first selector is connected to the first channel of the IP unit, a second input of the first selector is connected to the second channel of the IP unit, a first output of the first selector is connected to a first input and a second input of each of the second selectors, a second output of the first selector and an output of each of the second selectors are connected to an input of the register unit.

[0009] In one of the embodiments, the register unit comprises at least two first registers and at least one second register, an output of the AND logic unit is connected to a first input of each of the first registers and a first input of the second register, an output of each of the second selectors is connected to a second input of each of the first registers, an output of each of the first registers is connected to the processing module through a bus interface; a second output of the first selector is connected to a second input of the second register, an output of the second register is connected to the processing module through a bus interface.

[0010] In one of the embodiments, the first register is a read-write register.

[0011] In one of the embodiments, the second register is a read-write register.

[0012] In one of the embodiments, the AND logic unit comprises an AND logic gate.

[0013] In one of the embodiments, the intermediate data for verification comprises a wire net value and a value of an intermediate register of the FPGA.

[0014] A chip core verification method based on FPGA, comprising:

[0015] receiving intermediate data for verification of an IP unit by a selection unit;

[0016] storing the intermediate data for verification by a register unit;

[0017] verifying the intermediate data for verification by a processing module, determining error data based on a verification result of the intermediate data for verification, and modifying the intermediate data for verification of the IP unit based on the error data.

[0018] In one embodiment, the selection unit comprises at least one first selector and at least two second selectors, a first input of the first selector is connected to the first channel of the IP unit, a second input of the first selector is connected to the second channel of the IP unit, a first output of the first selector is connected to a first input and a second input of each of the second selectors, a second output of the first selector and an output of each of the second selectors are connected to an input of the register unit.

[0019] In one embodiment, the register unit comprises at least two first registers and at least one second register, an output of each of the second selectors is connected to a second input of each of the first registers, an output of each of the first registers is connected to the processing module through a bus interface; the second output of the first selector is connected to a second input of the second register, an output of the second register is connected to the processing module through a bus interface.

[0020] The above-mentioned FPGA-based chip core verification device and method, a chip core verification device composed of registers and selectors is connected outside the IP unit, when performing FPGA verification, the intermediate data to be verified which needs to be read is cached into the register unit of the chip core verification device, and the register unit is connected to the system bus, so that the processing module reads the intermediate data to be verified of the register unit through the system bus, so that the IP design can be more quickly and clearly positioned to the error after the problem in the FPGA verification stage, and the verification is more reliable through reading of the intermediate data to be verified which may affect the function in the IP. In addition, in the circuit implementation, the selection unit and the enable signal are added to select the line network or the register which needs to be read, so as to avoid waste of address space. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 The logic connection diagram of the FPGA-based chip core verification device in one embodiment;

[0022] Figure 2 The flowchart of the FPGA-based chip core verification method in one embodiment;

[0023] Figure 3 The flowchart of the FPGA-based chip core verification method in another embodiment. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical scheme and advantages of the present application clearer, the present application is further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0025] Example 1

[0026] In this embodiment, as Figure 1 As shown, an FPGA-based chip core verification device is provided, comprising: an AND logic unit 100, a selection unit 200, and at least one register unit 300; a first input terminal of the AND logic unit 100 is connected to a clock pulse signal terminal, a second input terminal of the AND logic unit 100 is connected to an enable terminal, and an output terminal of the AND logic unit 100 is connected to each of the register units 300; an input terminal of the selection unit 200 is connected to an IP unit, and an output terminal of the selection unit 200 is connected to the input terminal of each of the register units 300; an output terminal of the register unit 300 is connected to a processing module via a bus interface 410.

[0027] The selection unit 200 is used to receive the intermediate data to be verified from the IP unit and send the intermediate data to be verified to the register unit 300. The AND logic unit 100 is used to receive the signal from the clock pulse signal terminal and the signal from the clock pulse signal terminal, and control the register unit 300 to work. The register unit 300 is used to store the intermediate data to be verified. The processing module is used to read the intermediate data to be verified stored in the register unit 300, verify the intermediate data to be verified, determine the erroneous data based on the verification result of the intermediate data to be verified, and modify the intermediate data to be verified from the IP unit based on the erroneous data.

[0028] In this embodiment, as Figure 1 As shown, the AMBA Interface is a bus interface that supports the AMBA bus protocol. AMBA is an on-chip bus developed and launched by ARM (Advanced RISC Machines), and supports protocols including AHB and APB. This bus interface is a system bus used to connect processing modules.

[0029] In this embodiment, the processing module is a CPU (central processing unit), which is used to verify the intermediate data to be verified. In this embodiment, by setting the selection unit 200, the IP unit and the data of the IP unit can be selected. The selection unit 200 is used to select the IP unit and the data of the IP unit that need to be verified. The selected data is the intermediate data to be verified.

[0030] In this embodiment, the selection unit 200 is connected to the IP unit, which is an IP core. The selection unit 200 is used to obtain the intermediate data to be verified from the IP unit. The intermediate data to be verified includes net values ​​and the values ​​of intermediate registers of the FPGA.

[0031] The first input end of the logic unit 100 is connected with a clock pulse signal end for receiving a clock pulse signal CLK, and the second input end of the logic unit 100 is connected with an enable end for receiving an enable signal Enable. When the clock pulse signal CLK and the enable signal Enable are both high, the output end of the logic unit 100 outputs a signal, so that the register unit 300 works and buffers the intermediate data to be verified.

[0032] In the embodiment, the data in the IP unit is selected by the logic unit 100 receiving the enable signal and the selection unit 200 selecting the data of the IP unit, so that the intermediate data to be verified, i.e. the line network value and the value of the intermediate register of the FPGA, can be buffered by the register unit 300 and then verified by the processing module.

[0033] In the above embodiment, a chip core verification device composed of a register and a selector is connected outside the IP unit. When the FPGA is verified, the intermediate data to be verified to be read is buffered in the register unit 300 of the chip core verification device, and the register unit 300 is connected to the system bus, so that the processing module reads the intermediate data to be verified of the register unit 300 through the system bus, so that the IP design can be more quickly and clearly positioned to find errors after the FPGA verification stage. By reading the intermediate data to be verified in the IP which may affect the function, the verification is more reliable. In addition, in the circuit implementation, the selection unit 200 and the enable signal are added to select the line network or the register to be read, so as to avoid the waste of address space.

[0034] In one embodiment, the selection unit 200 includes at least one first selector 210 and at least two second selectors 220. The first input end of the first selector 210 is used to connect the first channel of the IP unit, the second input end of the first selector 210 is used to connect the second channel of the IP unit, the first output end of the first selector 210 is connected with the first input end and the second input end of each second selector 220, and the second output end of the first selector 210 and the output end of the second selector 220 are connected with the input end of the register unit 300.

[0035] In one embodiment, the register unit 300 comprises at least two first registers 310 and at least one second register 320, the output of the AND logic unit 100 is connected to the first input of each of the first registers 310 and the first input of the second register 320, the output of each of the second selectors 220 is connected to the second input of each of the first registers 310, the output of each of the first registers 310 is connected to the processing module through the bus interface 410; the second output of the first selector 210 is connected to the second input of the second register 320, and the output of the second register 320 is connected to the processing module through the bus interface 410.

[0036] In one embodiment, the first register 310 is a read-write register. In one embodiment, the second register 320 is a read-write register. In this embodiment, both the first register 310 and the second register 320 are read-write registers, which can be read and written by the processing module, so that the verification device can monitor the value of the intermediate variable of the IP in the working mode without affecting the actual production.

[0037] In one embodiment, the AND logic unit 100 comprises an AND logic gate 110. The first input of the AND logic gate 110 is connected to the clock signal end, the second input of the AND logic gate 110 is connected to the enable end, and the output of the AND logic gate 110 is connected to the first input of each of the first registers 310 and the first input of the second register 320.

[0038] In this embodiment, when the AND logic gate 110 receives the enable signal Enable, the first registers 310 and the second register 320 are enabled, and the selectors receive the intermediate data to be verified of the IP unit and transmit it to the first registers 310 and the second register 320, so that the first registers 310 and the second register 320 store the intermediate data to be verified.

[0039] Embodiment two

[0040] In this embodiment, as shown in Figure 2 a chip core verification method based on FPGA is provided, comprising:

[0041] In step 510, the intermediate data to be verified of the IP unit is received by the selection unit.

[0042] In step 520, the intermediate data to be verified is stored by the register unit.

[0043] In step 530, the processing module verifies the intermediate data to be verified, determines error data based on the verification result of the intermediate data to be verified, and modifies the intermediate data to be verified of the IP unit based on the error data.

[0044] In this embodiment, the selection unit selects data to be read from the IP unit as the intermediate data to be verified, sends the intermediate data to be verified to the register unit for storage, and enables the processing module to read the intermediate data to be verified of the register unit through the system bus, so that the IP design can be quickly and clearly positioned to the error after the problem in the FPGA verification stage, and the verification is more reliable through the reading of the intermediate data to be verified in the IP which may affect the function.

[0045] In one embodiment, the selection unit includes at least one first selector and at least two second selectors, a first input end of the first selector is connected to a first channel of the IP unit, a second input end of the first selector is connected to a second channel of the IP unit, a first output end of the first selector is connected to a first input end and a second input end of each of the second selectors, a second output end of the first selector and an output end of the second selector are connected to an input end of the register unit.

[0046] In one embodiment, the register unit includes at least two first registers and at least one second register, an output end of each of the second selectors is connected to a second input end of each of the first registers, an output end of each of the first registers is connected to the processing module through a bus interface; the second output end of the first selector is connected to a second input end of the second register, and an output end of the second register is connected to the processing module through a bus interface.

[0047] Embodiment three

[0048] As shown in Figure 3 , it is a chip core verification method based on FPGA in one embodiment, please combine Figure 1 , the chip core verification device based on FPGA is used for buffering the values of registers and line networks in the IP which cannot be directly read through the bus.

[0049] First, a macro definition of a digital circuit device is made, in which various IP units to be verified are connected, the intermediate registers and wire nets in the IP units that will affect the function or need to be read are connected to the registers of the verification device, and addresses are allocated and hung in the system bus, i.e., the selector is connected to the IP units to be verified, so that the selector can send data to the registers, and the registers are connected to the system bus AMBA Interface. In the process of designing various IP units, it is determined by the macro definition whether the values of the intermediate registers and wire nets are output. When the macro definition is opened, the wire nets and intermediate registers in the IP units are output as output signals to the verification device. The selector of the verification device is controlled by configuring the registers, so that the required IP units and signals can be selected by controlling the registers during verification, and the values of the signals are stored in the registers. The configuration registers of the device are readable and writable for the CPU, and the registers that cache the values of the wire nets and intermediate registers of the IP units to be verified are read-only for the CPU, because the verification device only helps us monitor the values of the intermediate variables of the IP units in the working mode, and cannot actually affect the actual values.

[0050] Before the FPGA verification is performed, the macro definition is opened, the verification device circuit is effectively burned into the FPGA, and the IP units of the chip are verified. If an error occurs during verification, the control registers of the verification device are configured, so that the values of the wire nets and intermediate registers in the IP units to be verified can be cached in the registers of the verification device, and the software prints the values read from the registers. The printed values can be used to determine what errors occur in the process of implementing the function of the IP units, and the errors are modified. After the modification is completed, the FPGA verification is repeated. After the FPGA verification is completed, the macro definition of the verification device needs to be closed. The device has no practical significance, and will adversely affect the area, power consumption, etc. of the chip during synthesis.

[0051] In addition, the address space allocated by each IP unit that is not used or reserved can also be used to implement the caching of intermediate values, and the values of the wire nets and intermediate registers in the IP units are transmitted to the unused registers in the IP address space, and an enable signal for reading the registers is added to ensure that the CPU can read the registers.

[0052] In the above embodiment, the IP units are designed to be more quickly and clearly positioned after problems occur during the FPGA verification phase, and the values of the wire nets and registers that are not allocated addresses in the IP units that can affect the function are read, so that the verification is more reliable. In addition, the selector and the enable signal are added in the circuit implementation to select the wire nets or registers to be read, so as to avoid waste of address space.

[0053] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when the computer program is executed, the processes of the above-mentioned embodiments of the methods can be included. Any reference to memory, storage, databases, or other media in the embodiments provided by the present application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0054] The technical features of the above embodiments can be combined in any way. In order to make the description simple, not all possible combinations of the technical features in the above embodiments are described, but as long as the combinations of the technical features do not exist, they should be considered as the scope of the present application.

[0055] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, some modifications and improvements can be made, which are all within the scope of the present application. Therefore, the scope of the patent of the present application should be subject to the appended claims.

Claims

1. A chip core verification device based on FPGA, characterized in that, include: It includes a logic unit, a selection unit, and at least one register unit; The first input terminal of the AND logic unit is connected to the clock pulse signal terminal, the second input terminal of the AND logic unit is connected to the enable terminal, and the output terminal of the AND logic unit is connected to each of the register units; the input terminal of the selection unit is connected to the IP unit, and the output terminal of the selection unit is connected to the input terminal of each of the register units; the output terminal of the register unit is connected to the processing module through the bus interface. The selection unit is used to receive the intermediate data to be verified from the IP unit and send the intermediate data to be verified to the register unit. The intermediate data to be verified includes net values ​​and intermediate register values ​​of the FPGA. The AND logic unit is used to receive the clock pulse signal and the enable signal to control the operation of the register unit. The register unit is used to store the intermediate data to be verified. The processing module is used to read the intermediate data to be verified stored in the register unit, verify the intermediate data to be verified, determine erroneous data based on the verification result of the intermediate data to be verified, and modify the intermediate data to be verified of the IP unit based on the erroneous data. The selection unit includes at least one first selector and at least two second selectors. The first input terminal of the first selector is used to connect to the first channel of the IP unit, the second input terminal of the first selector is used to connect to the second channel of the IP unit, the first output terminal of the first selector is connected to the first input terminal and the second input terminal of each of the second selectors, and the second output terminal of the first selector and the output terminal of the second selectors are connected to the input terminal of the register unit.

2. The apparatus according to claim 1, characterized in that, The register unit includes at least two first registers and at least one second register. The output of the AND logic unit is connected to the first input of each of the first registers and the first input of each of the second registers. The output of each of the second selectors is connected to the second input of each of the first registers. The output of each of the first registers is used to connect to the processing module through a bus interface. The second output of the first selector is connected to the second input of the second register. The output of the second register is used to connect to the processing module through a bus interface.

3. The apparatus according to claim 2, characterized in that, The first register is a read-write register.

4. The apparatus according to claim 2, characterized in that, The second register is a read-write register.

5. The apparatus according to claim 1, characterized in that, The AND logic unit includes AND logic gates.

6. The apparatus according to claim 1, characterized in that, The verification intermediate data includes net values ​​and the values ​​of intermediate registers in the FPGA.

7. A chip core verification method based on FPGA, applied to the chip core verification apparatus based on FPGA as described in any one of claims 1-6, characterized in that, include: The intermediate data to be verified from the IP unit is received by selecting the unit; The intermediate data to be verified is stored in the register unit; The processing module verifies the intermediate data to be verified, identifies erroneous data based on the verification results, and modifies the intermediate data to be verified for the IP unit based on the erroneous data. The input terminal of the selection unit is used to connect to the IP unit, and the output terminal of the selection unit is connected to the input terminal of each of the register units; the output terminal of the register unit is used to connect to the processing module through a bus interface.

8. The method according to claim 7, characterized in that, The selection unit includes at least one first selector and at least two second selectors. The first input terminal of the first selector is used to connect to the first channel of the IP unit, the second input terminal of the first selector is used to connect to the second channel of the IP unit, the first output terminal of the first selector is connected to the first input terminal and the second input terminal of each of the second selectors, and the second output terminal of the first selector and the output terminal of the second selectors are connected to the input terminal of the register unit.

9. The method according to claim 8, characterized in that, The register unit includes at least two first registers and at least one second register. The output of each second selector is connected to the second input of each first register. The output of each first register is used to connect to the processing module through a bus interface. The second output of the first selector is connected to the second input of the second register. The output of the second register is used to connect to the processing module through a bus interface.

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