Flash memory controller and power management methods

Abstract

This application discloses a flash memory controller and a power management method. The flash memory controller has a low-power mode and a normal operating mode. The power management method includes: when entering the low-power mode, storing runtime data in a storage block of the flash memory, and storing the starting address of the runtime data in the storage block as a parameter value in a register of a power management unit; and when restoring to the normal operating mode, obtaining the starting address of the runtime data in the storage block according to the parameter value stored in the register of the power management unit, and restoring the runtime data from the storage block. This power management method utilizes the continuous power-on characteristic of the power management unit to store the starting address of the runtime data in the storage block, realizing rapid recovery of runtime data, which not only saves the power consumption of the read operation in the data lookup process, but also improves the stability of the flash memory and extends its service life.

Description

Technical Field

[0001] This invention relates to the field of data storage technology, and in particular to a flash memory controller and power management method. Background Technology

[0002] Solid-state drives (SSDs) are hard drives made using solid-state electronic storage chips, primarily composed of a controller, storage media, and cache chips. Currently, the most common SSDs use flash memory as the storage medium, such as non-volatile NAND flash memory.

[0003] Solid-state drives (SSDs) offer advantages such as small size and high speed, but also disadvantages including high heat generation and susceptibility to overheating and performance degradation. The flash memory controller in an SSD is the component that generates the most heat. Therefore, the flash memory controller includes a power management unit (Power Management Unit) to enter a low-power mode when the system is idle. In low-power mode, the Power Management Unit reduces the clock frequency of internal modules or shuts down some internal modules to reduce power consumption. When a new read / write request is received, the flash memory controller returns to normal power mode. The active power management function of the flash memory controller effectively reduces idle temperature, allowing for a larger temperature rise margin during full-speed operation, thereby reducing the occurrence of overheating and performance degradation.

[0004] When transitioning from normal operating mode to low-power mode, the flash controller stores runtime data in the flash memory's storage blocks, and then the power management unit (Power Management Unit) shuts down the flash controller's processor. When returning from low-power mode to normal operating mode, the Power Management Unit (Power Management Unit) enables the flash controller's processor, and the flash controller restores the runtime data from the flash memory's storage blocks.

[0005] However, during the recovery of runtime data, the flash controller must locate the runtime data within the flash memory. This search process requires multiple read operations. Due to the time-consuming nature of these read operations, the flash controller struggles to quickly return to normal operating mode, resulting in additional power consumption and reduced stability and lifespan of the flash memory. Summary of the Invention

[0006] In view of the above problems, the purpose of the present invention is to provide a flash memory controller and a power management method, wherein the starting address of runtime data in the storage block is obtained according to the parameter value stored in the register of the power management unit, so as to realize the fast recovery of runtime data.

[0007] According to one aspect of the present invention, a power management method for a flash memory controller is provided, the flash memory controller having a low-power mode and a normal operating mode, the power management method comprising:

[0008] When entering the low-power mode, runtime data is stored in a memory block of flash memory, and the starting address of the runtime data in the memory block is stored as a parameter value in a register of the power management unit; and

[0009] When restoring to the normal operating mode, the starting address of the runtime data in the storage block is obtained according to the parameter value stored in the register of the power management unit, and the runtime data is restored from the storage block.

[0010] Preferably, the step of obtaining the starting address of the runtime data in the storage block based on the parameter value stored in the register of the power management unit includes:

[0011] Read the parameter values ​​stored in the registers of the power management unit;

[0012] The prior state of the flash memory controller is determined based on the parameter values; and

[0013] When the prior state is the low-power mode, the parameter value is used as the starting address of the runtime data in the storage block.

[0014] Preferably, the flash memory controller further has a power-off state, in which the recovery of runtime data from the storage block is abandoned when the prior state is the power-off state.

[0015] Preferably, the valid and invalid values ​​of the parameter value indicate the prior state as the low-power mode and the power-off state, respectively.

[0016] Preferably, the parameter value is valid when it is greater than 0, and invalid when it is equal to 0.

[0017] Preferably, in the normal operating mode of the flash memory controller, the processor detects whether the system is in an idle state, and when the system is in an idle state or the processor detects that the host actively requests to enter a low-power mode, it notifies the power management unit to switch the flash memory controller from the normal operating mode to the low-power mode.

[0018] Preferably, in the low-power mode of the flash memory controller, the processor detects the host's access request to the flash memory controller, and when the access request is detected or the processor detects that the host actively requests to exit the low-power mode, it notifies the power management unit to switch the flash memory controller from the low-power mode to the normal operating mode.

[0019] Preferably, the step of recovering the runtime data from the storage block includes:

[0020] Using the starting address of the runtime data in the storage block as a page pointer, obtain the starting page of the runtime data in the storage block; and

[0021] The runtime data is obtained by reading the page data of the corresponding storage area of ​​the storage block according to the starting page, and the runtime data is restored to the flash controller.

[0022] Preferably, the register of the power management unit also stores the amount of runtime data, and the corresponding storage area of ​​the storage block is a storage area that corresponds to the number of pages starting from the start page and corresponding to the amount of data.

[0023] Preferably, the register of the power management unit also stores the end address of the runtime data in the storage block, the end address indicating the end page of the runtime data in the storage block, and the corresponding storage area of ​​the storage block is the storage area from the start page to the end page.

[0024] Preferably, the register of the power management unit also stores the starting address of the runtime data in the cache unit, and the corresponding cache area of ​​the cache unit is the cache area corresponding to the amount of data starting from the starting address of the cache unit.

[0025] Preferably, the register of the power management unit also stores the starting address of the runtime data in multiple cache areas in the cache unit and the amount of data in the multiple cache areas. The multiple cache areas are not contiguous in the cache unit. Restoring the runtime data to the flash controller includes restoring the runtime data to the multiple cache areas scattered in the cache unit.

[0026] According to another aspect of the present invention, a flash memory controller is provided, the flash memory controller having a low-power mode and a normal operating mode, including:

[0027] processor;

[0028] A cache unit, connected to the processor, is used to load applications in firmware form and to store system data and business data;

[0029] A host interface, through which the processor connects to an external host to receive data access requests;

[0030] A memory interface, via which the processor connects to an external flash memory to perform data access operations on the flash memory; and

[0031] A power management unit is used to turn on or off the power supply to at least one of the processor, the cache unit, and the memory interface.

[0032] The power management unit includes a register, which stores power consumption mode parameters and the starting address of runtime data in a memory block.

[0033] When entering the low-power mode, the processor stores runtime data in the flash memory block and stores the starting address of the runtime data in the memory block as a parameter value in the power management unit register.

[0034] When returning to the normal operating mode, the processor obtains the starting address of the runtime data in the storage block based on the parameter value stored in the register of the power management unit, and restores the runtime data from the storage block.

[0035] According to an embodiment of the present invention, a power management method for a flash memory controller includes the following steps: When transitioning from a normal operating mode to a low-power mode, the flash memory controller stores runtime data in a storage block of the flash memory and stores the starting address of the runtime data in the storage block as a parameter value in a register of a power management unit. Then, the power management unit shuts down the processor of the flash memory controller. When recovering from the low-power mode to the normal operating mode, the power management unit enables the processor of the flash memory controller. The flash memory controller obtains the starting address of the runtime data in the storage block based on the parameter value stored in the register of the power management unit and recovers the runtime data from the storage block of the flash memory. Since the power management unit remains powered on after the system power-on of the flash memory controller, the register of the power management unit can always retain data. This power management method allows the starting address of the runtime data in the storage block to be obtained simply by reading the register of the power management unit when recovering to the normal power mode, eliminating the need to search for the storage location of the runtime data in the flash memory. Therefore, it saves the time consumed by the read operation during the runtime data recovery process, enabling the flash memory controller to quickly recover to the normal operating mode. This not only saves the power consumption of the read operation during the data search process but also improves the stability and extends the service life of the flash memory. Attached Figure Description

[0036] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings.

[0037] Figure 1 A schematic block diagram of a solid-state drive is shown.

[0038] Figure 2 A flowchart illustrating the power management method for solid-state drives (SSDs) is provided.

[0039] Figure 3 A flowchart illustrating runtime data recovery in a power management method for solid-state drives according to the prior art is shown.

[0040] Figure 4 Show Figure 3 The diagram shows the data storage structure for runtime data in the power management method.

[0041] Figure 5 A flowchart illustrating a power management method for a solid-state drive according to an embodiment of the present invention is shown. Detailed Implementation

[0042] The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.

[0043] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0044] Unless the context explicitly requires it, the terms "comprising," "including," and similar terms throughout the specification and claims should be interpreted as encompassing rather than exclusive or exhaustive; that is, meaning "including but not limited to." In the description of this invention, it should be understood that terms such as "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0045] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0046] Figure 1A schematic block diagram of a solid-state drive (SSD) is shown. An exemplary computer system includes a host computer and an SSD, wherein the SSD 100 includes a flash memory controller 110 and a flash memory 120.

[0047] Computer system 100 includes a host computer and a solid-state drive (SSD). The SSD includes a flash memory controller 110 and a flash memory storage device 120. The flash memory controller 110 is connected to the host computer and is used to exchange read and write data with the host computer. The flash memory controller 110 is also connected to the flash memory storage device 120 and is used to perform read and write operations on the flash memory storage device 120.

[0048] Flash memory 120 is, for example, a flash chip array. To improve data read and write performance, the memory interface 113 of flash controller 110 can perform read and write operations on the flash chips of flash memory 120 via multiple channels (e.g., CH0 and CH2), with each channel connected to a group of flash chips.

[0049] The flash memory controller 110 includes a processor 111, a host interface 112, a memory interface 113, a cache unit 114, a power management unit 115, an ECC engine 116, and a clock circuit 117. The host interface 112 of the flash memory controller 110 is connected to a host computer for transmitting data and read / write commands. The processor 111 is connected to the host interface 112, the memory interface 113, and the cache unit 114. The processor 111 is used to parse read / write commands and execute read / write operations; detect access request information from the host interface 112; obtain system idle state information; and control the power consumption mode of the power management unit 115 based on the access request information from the host interface 112 and the system idle state information. The flash memory controller 110 accesses data from the flash memory via the memory interface 113. Preferably, the ECC engine 116 is used to verify data during read / write operations to ensure the reliability of data storage.

[0050] Cache unit 114, for example, SRAM and / or DRAM, is used to store the mapping table. Processor 111 also includes a core software layer for implementing memory control, namely the FTL (flash translation layer). The FTL consists of several programs, which processor 111 executes to translate read and write instructions upon receipt, thereby completing access to the flash memory 120. Thus, the host's file system and operating system can access the storage medium as if it were their own memory. The FTL also features, for example, support for bad block management, wear leveling, garbage collection, power-off recovery, and write balancing techniques.

[0051] The cache unit 114 can be an internal module integrated into the same control chip as the processor 111, or it can be a separate memory chip independent of the control chip. Preferably, the cache unit 114 includes both SRAM and DRAM, where the SRAM is an internal module within the control chip, and the DRAM is a separate memory chip connected to the control chip. Comparatively, SRAM has a speed advantage as a cache, but it is more expensive, while DRAM has cost and capacity advantages as a cache. Therefore, the advantages of both can be combined to support the speed and capacity requirements of the flash memory controller 110 respectively. For example, the first-level mapping table and the second-level mapping table can be stored in SRAM and DRAM respectively, thereby improving the efficiency of address management.

[0052] The power management unit 115 is connected to the processor 111 and the host interface 112, and is controlled by the processor 111 to set the power consumption mode of the flash controller 110, such as a normal operation mode and one of several low power modes at different levels.

[0053] Power management unit 115 is connected to clock circuit 117 and is used to control the system clock frequency. Therefore, in a specific low-power mode (e.g., the lowest level of low-power mode), power management unit 115 can limit the speed of memory interface 113 by reducing the system clock frequency. Power management unit 115 includes multiple switches connected to the power supply terminals of multiple internal modules of flash memory controller 110 for turning the power supply to the internal modules on / off. Therefore, in a specific low-power mode (e.g., the highest level of low-power mode), power management unit 115 can reduce power consumption by turning off the power supply to at least some internal modules. Power management unit 115 controls the clock frequency and / or power supply of at least some internal modules of flash memory controller 110 according to the power consumption mode to reduce the power consumption of flash memory controller and improve temperature stability.

[0054] Furthermore, the power management unit 115 also includes a register for storing power consumption mode parameters. For example, in a specific low-power mode, the power supply to the processor 111 of the flash memory controller 110 is turned off. At this time, the power management unit 115 cannot obtain the system's idle state information from the processor 111. The power management unit 115 is powered on in any power consumption mode of the flash memory controller 110. Therefore, the register of the power management unit 115 can continuously store the power consumption mode parameter values, and the power management unit 115 maintains the specific low-power mode according to the power consumption mode parameters stored in the register. Therefore, by using the register, the power management unit 115 can turn off the power supply to the processor 111 in a specific low-power mode, thus turning off the power supply to as many internal modules as possible, which is beneficial for minimizing the power consumption of the flash memory controller 110.

[0055] Figure 2 A flowchart illustrating a power management method for solid-state drives (SSDs) is provided. For example, using... Figure 1 The power management unit 115 in the flash memory controller 110 shown executes this power management method.

[0056] In step S01, the flash memory controller 110 is in normal operating mode.

[0057] In step S02, the processor 111 detects that the host is about to enter a low-power mode or determines that the system is in an idle state.

[0058] If the system is not in an idle state, return to step S01 and maintain normal operating mode. If the system is in an idle state, continue to step S03 to notify the power management module 115 to enter low-power mode. In addition, the processor 111 will also execute the above step S03 when it detects that the host actively requests to enter low-power mode.

[0059] In an optional embodiment, the processor 111 detects whether the system is in an idle state. For example, if the system idle time is detected to be greater than a reference value, the processor notifies the power management module 115 to enter a low-power mode. This reference value is, for example, 10 seconds.

[0060] In step S03, the processor 111 notifies the power management module to enter low-power mode.

[0061] Preferably, when the system idle time exceeds a first reference value, the power management module 115 is notified to enter a first low-power mode.

[0062] In step S04, the power management module shuts off power to some modules in the memory controller.

[0063] The power management unit 115 adjusts the system clock frequency via the clock circuit 117, thereby limiting the speed of the memory interface 113 by reducing the system clock frequency and shutting off the power supply to at least some internal modules of the flash controller 110, such as the processor 111 and the memory interface 113, thus controlling the flash controller 110 to enter a low-power mode. At this time, the processor 111 of the flash controller 110 remains powered on.

[0064] In the embodiments of this application, the low-power mode can be divided into multiple levels. Before entering the first low-power mode, a preliminary determination can be made by using a system idle time greater than a second reference value as a reference condition. This second reference value is, for example, 0.5s. If the condition is met, the power management module 115 is controlled to enter the second low-power mode. The power management unit 115 adjusts only the system clock frequency via the clock circuit 117, and limits the speed of the memory interface 113 by reducing the system clock frequency to meet the requirement of slightly reducing power consumption. At this time, the host interface 112 of the flash memory controller 110 remains powered on.

[0065] In the first power consumption mode, the power management unit 115 shuts down the power supply to at least some internal modules of the flash controller 110, such as the processor 111 and the memory interface 113, to further reduce power consumption. At this time, the host interface 112 of the flash controller 110 remains powered on.

[0066] In step S05, the processor 111 detects that the host is about to exit low-power mode or detects a host access request.

[0067] If a host access request is detected, steps S06 and S07 are executed. Additionally, if the processor 111 detects that the host actively requests to exit low-power mode, steps S06 and S07 are also executed, exiting low-power mode and resuming normal operation to respond to read and write commands. If no host access request is detected, the process returns to step S04, and the power management unit 115 maintains low-power mode.

[0068] In step S06, the processor 111 notifies the power management module to exit the low-power mode.

[0069] In step S07, the power management module powers on some modules in the memory controller.

[0070] The power management unit 115 adjusts the system clock frequency via the clock circuit 117 to restore the system clock frequency's speed limit on the memory interface 113 and to enable power supply to at least some internal modules of the flash controller 110, such as the processor 111 and the memory interface 113, thereby controlling the flash controller 110 to exit the low-power mode, i.e., return to step S01, and the flash controller is in normal operating mode.

[0071] In the power management method described above, the processor 111 controls the power management unit 115 to operate in a power mode based on access request information and idle state information. For example, this might be a normal operating mode or one of different levels of a first low-power mode and a second low-power mode. The normal operating mode of the flash memory controller 110 is full-speed mode, the first low-power mode is sleep mode, and the second low-power mode is speed-limited mode. When the system idle time of the flash memory controller 110 exceeds a reference value, the processor 111 controls the power management unit 115 to sequentially enter the first low-power mode and the second low-power mode based on the length of the system idle time.

[0072] In the first low-power mode, the power management unit 115 shuts down at least some internal modules in the flash memory controller 110, achieving a higher level of power reduction compared to the second low-power mode. However, the first low-power mode described above involves not only power supply control of internal modules but also the requirement to save and restore runtime data. The low-power modes described below refer to the first low-power mode, which requires saving and restoring runtime data.

[0073] The runtime data of the flash controller 110 is system data or business data generated during the program execution of the processor 111. For example, the configuration data generated by the flash controller 110 during the power-on initialization process is usually the data that the solid-state drive has in the cache unit 114 when it is in normal working mode.

[0074] When entering low-power mode, processor 111 executes a boot program loaded in firmware form, saves runtime data in the storage block of flash memory 120, and then power management unit 115 shuts down the power supply to processor 111. When returning to normal operating mode, power management unit 115 turns on the power supply to processor 111, processor 111 loads firmware into cache unit 114, and executes a recovery program loaded in firmware form, reading runtime data from the storage block of flash memory 120.

[0075] Since the processor 111 is powered off in low-power mode, runtime data is lost. Saving runtime data when entering low-power mode and restoring runtime data when returning to normal operating mode can significantly reduce the initialization time of the flash controller 110 to restore normal operating state.

[0076] Figure 3 A flowchart illustrating runtime data recovery in a power management method for solid-state drives according to existing technology is shown. For example, using... Figure 1 The power management unit 115 in the flash memory controller 110 shown performs runtime data recovery of the power management method.

[0077] In the power management method described above, when entering a low-power mode, runtime data is stored in a memory block of the flash memory 120. This runtime data is continuously maintained after the data page of the stored data in the memory block. See also... Figure 4 Within the storage block, runtime data is stored in the storage area between the start page and the head page.

[0078] When returning to normal operating mode, the processor 111 restores power, executes a recovery program loaded in firmware form, and reads runtime data from the storage block of the flash memory 120.

[0079] In steps S11 and S12, the data pages of the storage block are traversed sequentially until a page containing empty data is read. This traversal step obtains a page pointer, which indicates the last position of the data page storing the data.

[0080] In step S13, the first empty page is used as the header page. The header page is the first empty page after the data page that stores the data.

[0081] In step S14, the previous data page of the header page is read, and the validity of the data is determined based on the data markers of the data page.

[0082] If the data from the previous data page is valid, proceed to step S15 to obtain runtime data. If the data from the previous data page is invalid, proceed to step S17 and abandon the data recovery process for runtime data.

[0083] In step S15, the starting page of the runtime data is obtained.

[0084] For example, processor 111 calculates the page size of the runtime data based on the amount of runtime data, and subtracts the page size of the storage area from the page pointer of the head page to obtain the starting page of the runtime data. Therefore, the runtime data is stored in the storage area between the start page and the head page.

[0085] In step S16, data recovery is performed.

[0086] For example, processor 111 reads runtime data from the storage area between the start page and the head page of the storage block, writes the runtime data into cache unit 114, thereby restoring the runtime data.

[0087] The runtime data recovery method described above in the existing power management method requires traversing the data pages in the flash memory's storage block to locate the runtime data. This search process requires multiple read operations. Due to the time-consuming read operations, the flash controller struggles to quickly return to normal operating mode, resulting in additional power consumption and reduced stability and lifespan of the flash memory.

[0088] Figure 5 A flowchart illustrating a power management method for a solid-state drive according to an embodiment of the present invention is shown. For example, using... Figure 1 The power management unit 115 in the flash memory controller 110 shown executes this power management method.

[0089] In step S21, the flash memory controller 110 enters a low-power mode.

[0090] In this step, the processor 111 detects whether the system is in an idle state. For example, if the system idle time is detected to be greater than a reference value, the processor notifies the power management module 115 to enter a low-power mode. The power management module 115 then shuts off power to at least some internal modules of the flash memory controller 110, thereby controlling the flash memory controller 110 to enter a low-power mode. The reference value is, for example, 10 seconds.

[0091] In step S22, the processor 111 executes the boot program loaded in firmware form and saves runtime data in the storage block of the flash memory 120.

[0092] This runtime data is continuously stored after the data pages of the storage block. See also Figure 4 Within the storage block, runtime data is stored in the storage area between the start page and the head page.

[0093] In step S23, the processor 111 stores the starting address of the runtime data in the memory block as a parameter value in the register of the power manager 115. This starting address of the runtime data in the memory block may, for example, indicate the flash memory address of the starting page. Preferably, the register of the power manager 115 is used not only to store the starting address of the runtime data in the memory block, but also to store the amount of runtime data, or the ending address of the runtime data in the memory block.

[0094] In step S24, the power management unit 115 shuts off the power supply to the processor 111. Preferably, the power management unit 115 also shuts off the power supply to the memory interface 113 to further reduce power consumption.

[0095] At this time, the host interface 112 and power management unit 115 of the flash memory controller 110 remain powered on.

[0096] In step S25, the power management unit 115 detects the access request information of the host interface 112.

[0097] If a host access request is detected, proceed to steps S26 to S29 to restore normal operating mode and respond to read / write commands. If no host access request is detected, return to step S24 to maintain low-power mode.

[0098] In step S26, the power management unit 115 enables power supply to the processor 111 and the memory interface 113.

[0099] In step S27, the processor 111 reads the register of the power management unit 115 to obtain the parameter value stored therein, which serves as the starting address of the runtime data in the storage block.

[0100] In step S28, the processor 111 reads the runtime data from the storage block of the flash memory 120 according to the starting address of the runtime data in the storage block, and writes the runtime data into the cache unit 114, thereby restoring the runtime data.

[0101] For example, the processor 111 uses the page pointer of the starting page of the runtime data to read the page data of the corresponding memory area of ​​the memory block according to the amount of runtime data.

[0102] If the registers of the power management unit 115 still store the amount of runtime data, then the corresponding storage area of ​​the storage block is the storage area for the number of pages corresponding to the amount of data, starting from the start page. If the registers of the power management unit 115 also store the end address of the runtime data in the storage block, where the end address indicates the end page of the runtime data in the storage block, and the end page in the storage block corresponds to the head page of the data pages stored above, then the corresponding storage area of ​​the storage block is the storage area from the start page to the end page.

[0103] In an optional embodiment, the register of the power management unit 115 also stores the starting address of the runtime data in the cache unit 114 and the amount of runtime data. The corresponding cache area of ​​the cache unit is the cache area corresponding to the amount of data starting from the starting address of the cache unit. Preferably, the register of the power management unit 115 stores the starting addresses of multiple cache areas of runtime data in the cache unit 114 and the amount of data in each cache area, wherein the cache areas are not contiguous in the cache unit 114. Based on the starting addresses of multiple cache areas and the amount of data in each cache area, the runtime data existing between the start page and the header page in the flash memory block can be restored to its original location scattered in each cache area of ​​the cache unit 114. Assume that in step S22, the runtime data in the first cache area, the second cache area, and the third cache area are saved between the start page (denoted as fas_s) and the header page in the flash memory block. The first, second, and third caches are distributed across cache unit 114, meaning their address ranges are not contiguous. The starting address of the first cache can be denoted as S1, and the amount of data in the first cache can be denoted as len1. The starting address of the second cache can be denoted as S2, and the amount of data in the second cache can be denoted as len2. The starting address of the third cache can be denoted as S3, and the amount of data in the second cache can be denoted as len3. In step S23, the register of power management unit 115 stores fas_s, and can also store S1, len1, S2, len2, S3, and len3. In step S27, after obtaining fas_s, S1, len1, S2, len2, S3, and len3, in step S28, the runtime data stored starting from fas_s can be quickly and accurately restored to the first cache indicated by S1 and len1, the second cache indicated by S2 and len2, and the third cache indicated by S3 and len3.

[0104] In the power management method described above, when transitioning from normal operating mode to low-power mode, the flash memory controller 110 stores runtime data in the storage block of the flash memory 120 and stores the starting address of the runtime data in the storage block as a parameter value in the register of the power management unit 115. Then, the power management unit 115 shuts down the processor 111 of the flash memory controller 110. When recovering from low-power mode to normal operating mode, the power management unit 115 enables the processor 111 of the flash memory controller 110. The flash memory controller 110 obtains the starting address of the runtime data in the storage block according to the parameter value stored in the register of the power management unit 115 and restores the runtime data from the storage block of the flash memory 120. Since the power management unit 115 remains powered on after the system of the flash memory controller 110 is powered on, the register of the power management unit 115 can always retain data. When the power management method restores to the normal power consumption mode, it can obtain the starting address of the runtime data in the storage block by reading the register of the power management unit 115, without having to search for the storage location of the runtime data in the flash memory 120. Therefore, it can save the time spent on the read operation of restoring the runtime data search process, so that the flash controller 110 can quickly restore to the normal working mode. This not only saves the power consumption of the read operation of the data search process, but also improves the stability of the flash memory 120 and extends its service life.

[0105] In the above embodiments, the process of the flash memory controller 110 entering a low-power mode from a normal operating mode and returning to a normal operating mode from a low-power mode is described. However, the flash memory controller 110 may need to return to a normal operating mode due to various events. For example, the prior state of the flash memory controller 110 may be either a low-power state or a power-off state. If the prior state is the low-power state described above, the runtime data recovery process in steps S27 and S28 is executed. If the prior state is a power-off state, the recovery of the runtime data from the memory block is abandoned. Regardless of whether it is a low-power state or a power-off state, the recovery process of the flash memory controller 110 includes actions such as powering on the processor 111, reloading the firmware, and initializing internal modules and applications.

[0106] In a further improved embodiment, the parameter values ​​stored in the registers of the power management unit 115 serve to indicate both the prior state and the starting address of the runtime data in the memory block. Valid and invalid parameter values ​​indicate the prior state as low-power mode and power-off state, respectively. For example, a parameter value greater than 0 is a valid value, and a parameter value equal to 0 is an invalid value.

[0107] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A power management method for a flash controller having a low power consumption mode and a normal operation mode, the power management method comprising: saving runtime data in a storage block of a flash memory when entering the low power consumption mode, and saving a start address of the runtime data in the storage block as a parameter value in a register of a power management unit; and obtaining the start address of the runtime data in the storage block according to the parameter value saved in the register of the power management unit when resuming to the normal operation mode, and resuming the runtime data from the storage block, wherein the step of resuming the runtime data from the storage block comprises: obtaining a start page of the runtime data in the storage block as a page pointer with the start address of the runtime data in the storage block; and reading page data of a corresponding storage area of the storage block according to the start page to obtain the runtime data, and resuming the runtime data to the flash controller.

2. The power management method of claim 1, wherein, The step of obtaining the start address of the runtime data in the storage block according to the parameter value saved in the register of the power management unit comprises: reading the parameter value saved in the register of the power management unit; judging a previous state of the flash controller according to the parameter value; and in a case that the previous state is the low power consumption mode, taking the parameter value as the start address of the runtime data in the storage block.

3. The power management method of claim 2, wherein, The flash controller further has a power-off state, in a case that the previous state is the power-off state, giving up resuming the runtime data from the storage block.

4. The power management method of claim 3, wherein, Valid and invalid values of the parameter value respectively indicate the previous state as the low power consumption mode and the power-off state.

5. The power management method of claim 4, wherein, The parameter value is valid when greater than 0, and the parameter value is invalid when equal to 0.

6. The power management method of claim 1, wherein, In the normal operation mode of the flash controller, a processor in the flash controller detects whether a system is in an idle state, and notifies the power management unit to switch the flash controller from the normal operation mode to the low power consumption mode when the system is in the idle state or the processor detects that a host actively requires entering the low power consumption mode.

7. The power management method of claim 1, wherein, In the low power consumption mode of the flash controller, a processor in the flash controller detects an access request of a host to the flash controller, and notifies the power management unit to switch the flash controller from the low power consumption mode to the normal operation mode when the access request is detected or the processor detects that the host actively requires exiting the low power consumption mode.

8. The power management method of claim 1, wherein, The register of the power management unit further saves a data amount of the runtime data, and the corresponding storage area of the storage block is a storage area of a page number corresponding to the data amount from the start page.

9. The power management method of claim 7, wherein, The register of the power management unit further saves an end address of the runtime data in the storage block, the end address indicates an end page of the runtime data in the storage block, and the corresponding storage area of the storage block is a storage area from the start page to the end page.

10. The power management method of claim 8, wherein, The register of the power management unit also stores the start address of the runtime data in the cache unit, and the corresponding cache area of the cache unit is the cache area corresponding to the data amount starting from the start address of the cache unit.

11. The power management method of claim 7, wherein, The register of the power management unit also stores the start addresses of the runtime data in a plurality of cache areas in the cache unit and the data amounts of the plurality of cache areas, and the plurality of cache areas are discontinuous in the cache unit. The restoring the runtime data to the flash controller comprises: restoring the runtime data to the plurality of cache areas dispersed in the cache unit.

12. A flash controller having a low power consumption mode and a normal working mode, comprising: a processor; a cache unit connected to the processor, used to load an application program in the form of firmware and store system data and service data; a host interface, via which the processor is connected to an external host to receive a data access request; a memory interface, via which the processor is connected to an external flash memory to perform a data access operation on the flash memory; and a power management unit used to turn on or off the power supply of at least one of the processor, the cache unit and the memory interface, wherein the power management unit comprises a register used to store a power consumption mode parameter and a start address of runtime data in a storage block, when entering the low power consumption mode, the processor stores runtime data in a storage block of the flash memory, and stores the start address of the runtime data in the storage block as a parameter value in the register of the power management unit, and when restoring to the normal working mode, the processor obtains the start address of the runtime data in the storage block according to the parameter value stored in the register of the power management unit, takes the start address of the runtime data in the storage block as a page pointer, obtains a start page of the runtime data in the storage block, and reads page data of a corresponding storage area of the storage block according to the start page to obtain the runtime data, and restores the runtime data to the flash controller.

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