A GPU hardware acceleration unit full-pipeline design method

Abstract

The application provides a GPU hardware acceleration unit full-pipeline design method, solves the problem that a conventional single draw configuration broadcast issuing mode is easy to cause unit space and low rendering efficiency, and mainly comprises the following technical scheme: S1, configuration information and data information in each draw are uniformly formatted and end marks are respectively agreed, and then the information is uniformly stored in a memory; S2, a configuration flow channel and a data flow channel are designed in the memory, a common channel, a local channel and a judgment module are designed for each hardware acceleration unit; S3, the transmission configuration of all draws in the hardware acceleration unit is repeated until the rendering of a frame of image is completed, the previous single draw configuration broadcast issuing mode is changed into a pipeline issuing mode, so that the whole pipeline unit can work simultaneously with different configurations, and the image rendering efficiency is greatly improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of hardware acceleration circuit in graphics processor, and particularly relates to a GPU hardware acceleration unit full-pipeline design method. BACKGROUND

[0002] In a general-purpose graphics processor, an image usually needs to pass through units such as vertex shading, primitive assembly, pre-clipping, clipping, back face culling, viewport transformation, rasterization, fragment shading, and pixel generation, and finally generates an image that we want to draw. Except that vertex shading and fragment shading are implemented by using a shading processor, other functions are more implemented by using hardware acceleration. The specific module function description is as follows:

[0003] Primitive assembly (PA): the primitive assembly unit assembles vertex information from the vertex shader according to the primitive type and the assembly mode to form point, line, and triangle basic primitives;

[0004] Pre-clipping (PCULL): the pre-clipping unit removes triangle primitives that are not visible in the field of view, thereby reducing the calculation amount of the subsequent pipeline;

[0005] Clipping (CLIP): divided into a plane clipping unit and a three-dimensional clipping unit. The plane clipping unit clips 3D primitives to be drawn using a user-defined clipping plane, discards the clipped primitives, and forms new 3D primitives. The three-dimensional clipping unit uses six faces of a view volume defined in the projection transformation to clip 3D primitives, discards the clipped primitives, and forms new 3D primitives;

[0006] Back face culling (CULLFACE): the back face culling unit can remove the front or back of a triangle primitive according to the user's configuration, thereby reducing the calculation amount of the subsequent pipeline;

[0007] Viewport transformation (VPT): after the 3D primitives of the viewport transformation unit are transformed, they will be displayed in the user-defined viewport;

[0008] Rasterization (RASTER): the rasterization unit completes the rasterization of any size point, any width straight line, and any triangle. It supports point drawing mode of straight lines and triangles, and realizes anti-aliasing of points, lines, and triangles;

[0009] Usually, a complex image of a frame is composed of hundreds or thousands of triangles. The vertices of the triangles can have different lighting, material, or fog properties, can use different assembly modes, and can use different viewport transformations. Therefore, different configurations are needed to achieve this. Therefore, we usually need to use different draws to implement the drawing work of a frame of image.

[0010] If one frame of image needs to be realized by one or more draws, it is necessary to realize by combining different configuration information and corresponding vertex data.

[0011] Common processing mode: when there are multiple draws, the configuration information of the first draw is configured into all units, and then all units are triggered to color from vertex 0 to PAR (PA->PCULL->…->RASTER) to fragment, and finally generate pixels, and then the configuration information and vertex data of the second draw are issued to generate the second batch of pixels, until all draws of this frame of image are completed.

[0012] Such an implementation mode is very efficient in image rendering when the number of draws is small and the vertex or pixel data of a single draw is large, but once the number of draws is large and the vertex or pixel data of each draw is small, the efficiency of image rendering will be exponentially reduced, because the configuration information of the next draw cannot be issued before the current draw is completed, resulting in that the front pipeline unit is in an idle state when the previous draw reaches the rear unit of the entire pipeline, greatly reducing the utilization rate of the pipeline. SUMMARY

[0013] The technical problem to be solved by the present application is to overcome the defects existing in the prior art, and the present application provides a GPU hardware acceleration unit full pipeline design method.

[0014] To solve the above technical problems, the technical scheme adopted by the present application is: a GPU hardware acceleration unit full pipeline design method, comprising a plurality of image rendering draws and a plurality of hardware acceleration units, each of the draws comprising corresponding configuration information and data information, the plurality of hardware acceleration units being arranged in image rendering order, and the specific steps being as follows:

[0015] S1, format unification and end flag setting are performed on the configuration information and data information in each draw, and then the information is stored in the memory;

[0016] S2, a configuration pipeline and a data pipeline are designed in the memory, and a normal channel, a local channel and a judgment module are designed for each hardware acceleration unit,

[0017] The configuration pipeline reads the configuration information from the memory and transmits it in the normal channel of each hardware acceleration unit in turn, and the judgment module determines whether to write into the local channel or send down according to whether the configuration information belongs to the current hardware acceleration unit,

[0018] The data stream pipeline reads data information from the memory and sequentially transmits in the hardware acceleration unit, each hardware acceleration unit processes the graphics primitive according to the configuration information in the local channel, and the state machine in the hardware acceleration unit manages whether to start processing the graphics primitive and whether to send the processed graphics primitive to the next hardware acceleration unit.

[0019] S3, repeating the transmission configuration of all draw in the hardware acceleration unit until the rendering of a frame image is completed.

[0020] Further, the end flag of the configuration information in each draw is written into the local channel of all hardware acceleration units.

[0021] Further, the state of the state machine includes IDLE, CFG and DATA.

[0022] When the state machine is reset, the IDLE state is corresponding,

[0023] When the state machine is reset, the IDLE state is corresponding,

[0024] When the state machine is reset, the IDLE state is corresponding,

[0025] Further, after the data information in each draw is processed, the state machine enters the CFG state again, waits for the next draw data information, and repeats until the rendering of a frame image is completed.

[0026] Further, after the data information in each draw is processed, the state machine enters the CFG state again, waits for the next draw data information, and repeats until the rendering of a frame image is completed.

[0027] Further, the data information is calculated according to the configuration information.

[0028] Compared with the prior art, the beneficial effects of the present application include: changing the previous single draw configuration broadcast delivery mode to the pipeline delivery mode, adding a configuration end flag between draw and draw configuration, when each unit receives the end flag, it means that the configuration of the current draw has been completed, then actively read the data to be processed, so that the entire pipeline unit can work with different configurations of draw, greatly improving the efficiency of image rendering. BRIEF DESCRIPTION OF DRAWINGS

[0029] The disclosure of the present application will be described with reference to the accompanying drawings. It is to be noted that the drawings are only intended to illustrate the present application and are not intended to limit the scope of protection of the present application. In the drawings, the same reference numerals are used to refer to the same components. Among them:

[0030] Figure 1 A flowchart of step S1 according to an embodiment of the present application is schematically shown;

[0031] Figure 2 A flowchart of step S2 according to an embodiment of the present application is schematically shown;

[0032] Figure 3 A state machine state flowchart according to an embodiment of the present application is schematically shown. DETAILED DESCRIPTION

[0033] It is easy to understand that, according to the technical solution of the present application, a person skilled in the art can propose a plurality of structures and implementation manners which can be replaced with each other without changing the essential spirit of the present application. Therefore, the following detailed description and the drawings are only exemplary illustrations of the technical solution of the present application, and should not be regarded as the whole or as a limitation or restriction on the technical solution of the present application.

[0034] According to an embodiment of the present application, the GPU hardware acceleration unit full pipeline design method is combined with Figure 1 and shown.

[0035] A GPU hardware acceleration unit full pipeline design method, including a plurality of image rendering draws and a plurality of hardware acceleration units, each draw including corresponding configuration information and data information, the plurality of hardware acceleration units arranged in image rendering order, the specific steps being as follows:

[0036] S1, format the configuration information and data information in each draw and respectively assign an end flag, and then store the information in the memory;

[0037] S2, design a configuration flow channel and a data flow channel in the memory, and design a normal channel, a local channel and a judgment module for each hardware acceleration unit,

[0038] The configuration flow channel reads the configuration information from the memory and sequentially transmits it in the normal channel of each hardware acceleration unit. When transmitting, the judgment module determines whether to write to the local channel or send it down according to whether the configuration information belongs to the current hardware acceleration unit,

[0039] The data flow channel reads the data information from the memory and sequentially transmits it in the hardware acceleration unit. Each hardware acceleration unit processes the primitives according to the configuration information in its local channel. When processing the data information, the hardware acceleration unit internal state machine manages whether to start processing the primitives and whether to send the processed primitives down.

[0040] To achieve a fully pipelined hardware acceleration module design in this project:

[0041] First, hardware and software cooperation is required. The software needs to unify the configuration and data information of multiple draws within a single image frame according to the same format. The configuration and data information of each individual draw are one-to-one, such as... Figure 1 As shown, between draws, a configuration end flag cfg_fence needs to be agreed upon for configuration information, and a data end flag data_fence needs to be agreed upon for data information.

[0042] Then, two independent spaces are allocated in the DDR memory to store the configuration and data information. At the same time, two independent pipelines are designed, namely the configuration pipeline and the data pipeline, which are both independent and mutually influential.

[0043] like Figure 2 As shown, in this embodiment, the hardware acceleration unit specifically takes primitive assembly (PA), pre-clipping (PCULL), clipping (CLIP), backface blanking (CULLFACE), viewport transformation (VPT), ​​and rasterization (RASTER) as examples.

[0044] After the pipeline is started, the configuration pipeline actively reads the configuration information from DDR and sends it to the PA module when PA cfg_rdy is valid. At the same time, the data pipeline actively reads the data information from DDR and sends it to the PA module when PA data_rdy is valid. The two affect each other because the data information of each draw is calculated based on the configuration of its corresponding draw.

[0045] The detailed configuration pipeline works as follows: when the configuration pipeline reads configuration information from the DDR, it will send the read configuration information to the PA when the PA's cfg_rdy is valid. The configuration channel of the PA module has two configuration fifos, common fifo (ordinary channel) and local fifo (local channel), and an arbiter (judgment module). The hardware acceleration unit PA writes the received configuration information into the common fifo first, so as long as the common fifo is not full, the cfg_rdy is always valid, and the preceding configuration channel can continuously write configuration information to the PA common fifo. At the same time, as long as there is configuration information in the PA common fifo, the arbiter reads the configuration information from the common fifo and judges whether the configuration information belongs to the PA unit. If it is the configuration information of the PA unit, it is written into the PA local fifo. If it does not belong to the PA unit, the configuration information is sent to the next hardware acceleration unit PCULL. It needs to be noted that the end flag cfg_fence is written into the local fifo and also sent to the next unit, so as to ensure that the cfg_fence of each draw can be written into the configuration local fifo of all units. Such back pressure design can ensure that the configuration information can be continuously sent to each unit, and also ensure that the configuration information is not lost. At the same time, the judgment module judges whether the configuration information is for the current hardware acceleration unit. Only the configuration information of the non-current unit is sent to the next unit, so as to reduce unnecessary transmission of configuration information.

[0046] The detailed data channel works as follows: when the data pipeline reads data information from the DDR, it will transmit vertex data information to the PA module, provided that the PA unit's data_rdy is valid. The specific data_rdy is managed and implemented by the internal configuration data interaction state machine of each unit. After receiving the vertex data information, the PA unit will implement point, line or triangle primitive assembly according to the configuration information in the PA local channel, and send the assembled primitives to the subsequent units such as pre-clipping.

[0047] As Figure 3As shown, the data_rdy of each unit is realized by a data interaction state machine configured in the respective unit, each state machine has three states, namely IDLE, CFG and DATA state, under the reset (0 reset is valid), the state machine is in IDLE state, once out of reset, then the state machine will enter the CFG state, begin to read the configuration information from the local fifo of the respective unit, until the cfg_fence signal is read, indicating that the current draw configuration information has been received, then the state machine enters the DATA state, begins to feed back the data_rdy signal to the front unit, waits for the data_vld valid data of the front unit to come, then processes the data according to the specific configuration information of the unit, finally under the condition that the data_rdy of the next unit is valid, the processed data is issued, forming a one-level-by-one-level back pressure effect, until all the data to be processed of the current draw is processed, that is, the data_fence of the previous unit is received, then the state machine enters the CFG state again, waits for the configuration information of the next draw, so on and so forth until the rendering work of a frame of image is completed.

[0048] In addition, not every draw generated configuration information will contain all units, generally, in the first draw, all units will be configured and updated, and in the subsequent draw, only some unit configuration information may be needed, then the other units need to keep the previous configuration state, that is, the configuration information remains unchanged, at this time, there will be a continuous cfg_fence in these units, that is, after the configuration information of the last draw is ended, the DATA state is entered to receive and process data, and then the current draw is processed, and then the CFG state is entered again, at this time, the local fifo is read, and the cfg_fence is directly read, indicating that the configuration information of the current draw does not need to be modified, then the state machine can directly enter the DATA state again, so the processing is efficient and safe.

[0049] The technical scope of the present application is not limited to the above description, and those skilled in the art can make various modifications and modifications to the above embodiments without departing from the technical idea of the present application, and these modifications and modifications should be within the protection scope of the present application.

Claims

1. A GPU hardware acceleration unit full-pipelining design method, comprising a plurality of draw for image rendering and a plurality of hardware acceleration units, each of the draw comprising corresponding configuration information and data information, and the plurality of hardware acceleration units arranged in an image rendering order, characterized in that The specific steps are as follows: S1, format unification and end mark of configuration information and data information in each draw are agreed, and then the information is stored in the memory; S2, a configuration pipeline and a data pipeline are designed in the memory, a common channel, a local channel and a judging module are designed for each hardware acceleration unit, the configuration pipeline reads the configuration information from the memory and transmits the information in the common channel of each hardware acceleration unit in turn, the judging module determines whether the configuration information belongs to the current hardware acceleration unit, if yes, the information is written into the local channel, otherwise, the information is sent to the next unit, the data pipeline reads the data information from the memory and transmits the information in the hardware acceleration unit in turn, each hardware acceleration unit processes the graphics primitive according to the configuration information in the local channel, and the state machine in the hardware acceleration unit manages whether to start processing the graphics primitive and whether to send the processed graphics primitive to the next unit; Each state machine has three states, namely IDLE, CFG and DATA states, in the reset state, the state machine is in the IDLE state, once the reset is removed, the state machine enters the CFG state, starts to read the configuration information from the local fifo of the respective unit, until the cfg_fence signal is read, indicating that the configuration information of the current draw has been received, then the state machine enters the DATA state, starts to feed back the data_rdy signal to the previous unit, waits for the data_vld valid data of the previous unit, then processes the data according to the specific configuration information of the unit, finally, under the condition that the data_rdy of the next unit is valid, the processed data is sent to the next unit, forming a one-level-one-level back pressure effect, until all the data to be processed of the current draw is processed, that is, the data_fence of the previous unit is received, then the state machine enters the CFG state again, waits for the configuration information of the next draw, and the process is repeated until the rendering of a frame of image is completed; S3, repeat the transmission of the configuration in the hardware acceleration unit of all draws, until the rendering of a frame of image is completed. The end mark of the configuration information in each draw is written into the local channel of all hardware acceleration units. The state machine state includes IDLE, CFG and DATA, When the state machine is in the reset state, it corresponds to the IDLE state, 2. The GPU hardware acceleration unit full-pipelined design method of claim 1, wherein: When the state machine is removed from the reset, it corresponds to the CFG state, the current hardware acceleration unit starts to read the configuration information from the local channel, 3. The GPU hardware acceleration unit full-pipelined design method of claim 1, wherein: When the data pipeline reads the end mark in the configuration information, it corresponds to the DATA state, starts to feed back the data_rdy signal to the previous hardware acceleration unit, and determines whether to send the processed data according to whether the state machine of the next hardware acceleration unit is in the DATA state, if yes, sends the data, if not, does not send the data, when the state machine of the next hardware acceleration unit is in the DATA state, the previous hardware acceleration unit sends the data information according to the data_rdy signal. ​ ​ ​ ​ 4. The GPU hardware acceleration unit full-pipelined design method of claim 3, wherein: Each of the draw data information processing is the end flag, the state machine enters CFG state again, waits for the next draw data information, repeats until the rendering of a frame image is finished.

5. The GPU hardware acceleration unit full-pipelined design method of claim 3, wherein: The hardware acceleration unit is the end flag after the first draw configuration information transmission is finished, if the configuration information remains unchanged, the internal state machine directly corresponds to the DATA state at this time.

6. The GPU hardware acceleration unit full-pipelined design method of claim 1, wherein: The data information is calculated according to the configuration information.

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