Systems and methods including PIPE5 to PIPE4 converters

Abstract

Embodiments of the present invention provide a PIPE5 to PIPE4 converter that provides compatibility between a PIPE5 controller and a PIPE4 device. The converter includes a first interface connected to a PIPE5 controller including a MAC register via a message bus interface, a second interface connected to a PIPE4 device via a PCIe link, and a PHY register. When a first message bus interface signal is received from the PIPE5 controller, the first interface locates the target PHY register based on the first message bus interface signal, and the second interface generates a first link interface signal associated with the target PHY register and outputs the first link interface signal to the PIPE4 device.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a high-speed serial computer expansion bus standard in a computing system. Background Technology

[0002] The computing environment paradigm has shifted to ubiquitous computing systems that can be used anytime, anywhere. Consequently, the use of portable electronic devices such as mobile phones, digital cameras, and laptops has increased rapidly. These portable electronic devices typically use memory systems with memory devices (i.e., data storage devices). Data storage devices serve as either the main memory or secondary memory devices in portable electronic devices.

[0003] Because memory systems using memory devices have no moving parts, they offer excellent stability, durability, high data access speeds, and low power consumption. Examples of memory systems with these advantages include Universal Serial Bus (USB) memory devices, memory cards with various interfaces such as Universal Flash Memory (UFS), and Solid State Drives (SSDs). Memory systems can perform operations in response to commands (or requests) from a host device. Memory systems can be connected to host devices via one or more different interface protocols such as Universal Serial Bus (USB), Multimedia Card (MMC), and / or High-Speed ​​Peripheral Component Interconnect (PCI-e or PCIe).

[0004] PCIe is a high-speed serial computer expansion bus standard widely used in many computing and communication systems. Due to its dedicated point-to-point topology, PCIe provides high-speed data transfer and low latency. To accelerate the verification and device development time of PCIe-based subsystems, Intel defined the PHY interface (PIPE) for the High Speed ​​PCI architecture. Over time, PIPE has evolved from PIPE1 to PIPE6. PIPE specifications from PIPE1 to PIPE4 are backward compatible. However, PIPE4 is incompatible with PIPE5 / PIPE6. In this context, embodiments of the present invention emerged. Summary of the Invention

[0005] The present invention includes systems and methods for providing compatibility between PIPE5 controllers and PIPE4 devices.

[0006] On one hand, a system includes: a physical interface of a high-speed PCI (PCIe) PIPE5 controller, including multiple media access control (MAC) registers; a PIPE4 device; and a converter including a first interface connected to the PIPE5 controller via a message bus interface, a second interface connected to the PIPE4 device via a PCIe link, and multiple physical (PHY) registers. When a first message bus interface signal is received from the PIPE5 controller, the first interface locates a target PHY register among the multiple PHY registers based on the first message bus interface signal, and the second interface generates a first link interface signal associated with the target PHY register and outputs the first link interface signal to the PIPE4 device. When a second link interface signal is received from the PIPE4 device, the first interface locates a target MAC register among the multiple MAC registers based on the second link interface signal, and outputs a second message bus interface signal based on the second link interface signal to write to the target MAC register.

[0007] On the other hand, a method for connecting a high-speed PCI (PCIe) PIPE5 controller and a PIPE4 device includes: providing a converter, the converter including a first interface connected to a PIPE5 controller including multiple Media Access Control (MAC) registers via a message bus interface, a second interface connected to the PIPE4 device via a PCIe link, and multiple physical (PHY) registers; performing a first operation when a first message bus interface signal is received from the PIPE5 controller; and performing a second operation when a second link interface signal is received from the PIPE4 device. The first operation includes: locating a target PHY register among the multiple PHY registers based on the first message bus interface signal via the first interface; and generating a first link interface signal associated with the target PHY register and outputting the first link interface signal to the PIPE4 device via the second interface. The second operation includes: locating a target MAC register among the multiple MAC registers based on the second link interface signal via the first interface; and outputting a second message bus interface signal based on the second link interface signal via the first interface to write to the target MAC register.

[0008] Additional aspects of the invention will become apparent from the following description. Attached Figure Description

[0009] Figure 1 This is a block diagram illustrating a data processing system according to an embodiment of the present invention.

[0010] Figure 2 This is a block diagram illustrating a memory system according to an embodiment of the present invention.

[0011] Figure 3 This is a diagram illustrating a data processing system comprising two PCIe devices according to an embodiment of the present invention.

[0012] Figure 4 This is a diagram illustrating the PHY requirements for different interfaces and architectures.

[0013] Figure 5A and Figure 5B This is a diagram illustrating the incompatibility between PIPE4 and PIPE5.

[0014] Figure 6 This is a diagram illustrating a data processing system including a PIPE5 to PIPE4 converter according to an embodiment of the present invention.

[0015] Figure 7 This is a diagram illustrating the connection between the PIPE5 controller and the PIPE5 to PIPE4 converter according to an embodiment of the present invention.

[0016] Figures 8 to 11 This is a diagram illustrating the message bus interface signals according to an embodiment of the present invention.

[0017] Figure 12A and Figure 12B This is a diagram illustrating the PHY register and the target PHY register according to an embodiment of the present invention.

[0018] Figure 13A and Figure 13B This is a diagram illustrating the MAC register and the target MAC register according to an embodiment of the present invention.

[0019] Figure 14A and Figure 14B This is a diagram illustrating an example of a signal converted by a PIPE5 to PIPE4 converter 630 according to an embodiment of the present invention. Detailed Implementation

[0020] Various embodiments of the invention are described in more detail below with reference to the accompanying drawings. However, the invention may be implemented in different forms and therefore should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to convey the scope of the invention fully and completely to those skilled in the art. Furthermore, references to “embodiment,” “another embodiment,” etc., herein are not necessarily directed to only one embodiment, and different references to any such phrases are not necessarily directed to the same embodiment. Throughout this disclosure, the same reference numerals refer to the same parts in the drawings and embodiments of the invention.

[0021] This invention can be implemented in many ways, including: processes; devices; systems; computer program products implemented on computer-readable storage media; and / or processors, such as processors adapted to execute instructions stored in and / or provided by memory linked to the processor. In this specification, these embodiments or any other forms in which the invention may take may be referred to as technical solutions. Generally, the order of operation of the disclosed processes can be varied within the scope of this invention. Unless otherwise stated, components described as suitable for performing a task, such as processors or memory, may be implemented as general components temporarily configured to perform that task at a given time or manufactured as specific components to perform that task. As used herein, the term "processor," etc., refers to one or more means, circuits, and / or processing cores suitable for processing data such as computer program instructions.

[0022] The methods, processes, and / or operations described herein can be executed by code or instructions to be run by a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device can be those described herein or any other element besides those described herein. Because the algorithms underlying the methods (or the operation of the computer, processor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operations of the method embodiments can convert a computer, processor, controller, or other signal processing device into a dedicated processor for executing the methods herein.

[0023] When implemented at least in software, controllers, processors, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, and other signal generation and signal processing features may include, for example, memory or other storage devices for storing code or instructions to be executed by, for example, a computer, processor, microprocessor, controller, or other signal processing device.

[0024] The following provides a detailed description of embodiments of the invention, along with accompanying drawings illustrating aspects of the invention. The invention is described in conjunction with these embodiments, but is not limited to any particular embodiment. The scope of the invention is defined only by the claims. The invention encompasses many alternatives, modifications, and equivalents within the scope of the claims. Numerous specific details are set forth in the following description to provide a thorough understanding of the invention. These details are provided for illustrative purposes; the invention may be practiced without some or all of these specific details. For clarity, technical materials known in the art related to the invention have not been described in detail so as not to unnecessarily obscure the invention.

[0025] Figure 1This is a block diagram illustrating a data processing system 2 according to an embodiment of the present invention.

[0026] Reference Figure 1 The data processing system 2 may include a host device 5 and a memory system 10. The memory system 10 may receive requests from the host device 5 and operate in response to the received requests. For example, the memory system 10 may store data to be accessed by the host device 5.

[0027] The host device 5 can be implemented using any of a variety of electronic devices. In various embodiments, the host device 5 may include electronic devices such as: a desktop computer, a workstation, a 3D television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, and / or a digital video recorder and a digital video player. In various embodiments, the host device 5 may include portable electronic devices such as: a mobile phone, a smartphone, an e-book reader, an MP3 player, a portable multimedia player (PMP), and / or a portable game console.

[0028] The memory system 10 can be implemented using any of a variety of storage devices such as solid-state drives (SSDs) and memory cards. In various embodiments, the memory system 10 can be configured as a component of a variety of electronic devices such as: computers, ultra-mobile personal computers (PCs) (UMPCs), workstations, netbook computers, personal digital assistants (PDAs), portable computers, network tablet PCs, wireless phones, mobile phones, smartphones, e-book readers, portable multimedia players (PMPs), portable gaming devices, navigation devices, black boxes, digital cameras, digital multimedia broadcasting (DMB) players, 3D televisions, smart televisions, digital audio recorders, digital audio players, digital picture recorders, digital picture players, digital video recorders, digital video players, data center storage devices, devices capable of receiving and transmitting information in a wireless environment, radio frequency identification (RFID) devices, and a variety of electronic devices for home networks, a variety of electronic devices for computer networks, a variety of electronic devices for telematics networks, or a variety of components for computing systems.

[0029] The memory system 10 may include a memory controller 100 and a semiconductor memory device 200. The memory controller 100 can control all operations of the semiconductor memory device 200.

[0030] The semiconductor memory device 200 can perform one or more erase, program, and read operations under the control of the memory controller 100. The semiconductor memory device 200 can receive commands (CMD), addresses (ADDR), and data (DATA) via input / output lines. The semiconductor memory device 200 can receive power (PWR) via power lines and control signals (CTRL) via control lines. Depending on the design and configuration of the memory system 10, the control signal CTRL may include command latch enable signals, address latch enable signals, chip enable signals, write enable signals, read enable signals, and other operation signals.

[0031] The memory controller 100 and the semiconductor memory device 200 can be integrated into a single semiconductor device such as a solid-state drive (SSD). The SSD may include a storage device for storing data therein. When the memory system 10 is used in an SSD, a host device (e.g., ...) is connected to the memory system 10. Figure 1 The operating speed of the host device 5) can be significantly improved.

[0032] The memory controller 100 and the semiconductor memory device 200 can be integrated into a single semiconductor device, such as a memory card. For example, the memory controller 100 and the semiconductor memory device 200 can be integrated to configure PC cards, compact flash memory (CF) cards, smart media (SM) cards, memory sticks, multimedia cards (MMC), reduced-size multimedia cards (RS-MMC), miniature versions of MMC (micro MMC), secure digital cards (SD cards), mini secure digital cards (mini SD cards), micro secure digital cards (micro SD cards), high-capacity secure digital cards (SDHC), and / or universal flash memory (UFS).

[0033] Figure 2 This is a block diagram illustrating a memory system according to an embodiment of the present invention. For example, Figure 2 The memory system can be described Figure 1 The memory system 10 shown.

[0034] Reference Figure 2 The memory system 10 may include a memory controller 100 and a semiconductor memory device 200. The memory system 10 can respond to input from a host device (e.g., Figure 1 The host device 5) operates upon request and, in particular, stores data to be accessed by the host device.

[0035] The semiconductor memory device 200 can store data to be accessed by a host device.

[0036] The semiconductor memory device 200 can be implemented using volatile memory devices such as dynamic random access memory (DRAM) and / or static random access memory (SRAM) or non-volatile memory devices such as read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), ferroelectric random access memory (FRAM), phase change RAM (PRAM), magnetoresistive RAM (MRAM) and / or resistive RAM (RRAM).

[0037] The memory controller 100 can control the storage of data in the semiconductor memory device 200. For example, the memory controller 100 can control the semiconductor memory device 200 in response to a request from a host device. The memory controller 100 can provide data read from the semiconductor memory device 200 to the host device, and can store data provided from the host device into the semiconductor memory device 200.

[0038] The memory controller 100 may include a storage device 110, a control component 120, an error correction code (ECC) component 130, a host interface (I / F) 140, and a memory interface (I / F) 150 connected via a bus 160. The control component 120 may be implemented as a processor such as a central processing unit (CPU).

[0039] Storage device 110 can be used as working memory for memory system 10 and memory controller 100, and stores data for driving memory system 10 and memory controller 100. When memory controller 100 controls the operation of semiconductor memory device 200, storage device 110 can store data used by memory controller 100 and semiconductor memory device 200 for operations such as read operations, write operations, programming operations and erase operations.

[0040] Storage device 110 can be implemented using volatile memory such as static random access memory (SRAM) or dynamic random access memory (DRAM). As described above, storage device 110 can store data used by the host device in semiconductor memory device 200 for read and write operations. To store data, storage device 110 may include program memory, data memory, write buffer, read buffer, mapping buffer, etc.

[0041] Control component 120 can control the general operation of memory system 10 in response to corresponding requests from host device, and particularly for write and read operations of semiconductor memory device 200. Control component 120 can drive firmware called a flash translation layer (FTL) to control the general operation of memory system 10. For example, FTL can perform operations such as logical-to-physical (L2P) mapping, wear leveling, garbage collection, and / or bad block handling. L2P mapping is referred to as logical block addressing (LBA).

[0042] During a read operation, the ECC component 130 can detect and correct errors in the data read from the semiconductor memory device 200. When the number of error bits is greater than or equal to the threshold number of correctable error bits, the ECC component 130 may not correct the error bits, but instead output an error correction failure signal indicating that the correction of the error bits has failed.

[0043] In various embodiments, ECC component 130 may perform error correction operations based on coding modulation such as low-density parity-check (LDPC) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, turbo codes, turbo product codes (TPC), Reed-Solomon (RS) codes, convolutional codes, recursive systematic codes (RSC), trellis-coded modulation (TCM), or block-coded modulation (BCM). However, error correction is not limited to these techniques. Therefore, ECC component 130 may include any and all circuitry, systems, or devices suitable for error correction operations.

[0044] The host interface 140 can communicate with the host device through one or more of the following communication standards or interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), High-Speed ​​Peripheral Component Interconnect (PCI-e or PCIe), Small Computer System Interface (SCSI), Serial SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Enhanced Small Disk Interface (ESDI), and / or Electronic Integrated Drive (IDE).

[0045] Memory interface 150 provides an interface between memory controller 100 and semiconductor memory device 200, allowing memory controller 100 to control semiconductor memory device 200 in response to requests from host device. Memory interface 150 can generate control signals for semiconductor memory device 200 and process data under the control of control component 120. When semiconductor memory device 200 is flash memory such as NAND flash memory, memory interface 150 can generate control signals for memory and process data under the control of control component 120.

[0046] Semiconductor memory device 200 may include a memory cell array 210, control circuitry 220, voltage generation circuitry 230, row decoder 240, page buffer array 250 (which may be an array of page buffers), column decoder 260, and input / output (I / O) circuitry 270. The memory cell array 210 may include multiple memory blocks 211 capable of storing data. The voltage generation circuitry 230, row decoder 240, page buffer array 250, column decoder 260, and I / O circuitry 270 may form peripheral circuitry for the memory cell array 210. The peripheral circuitry may perform programming, reading, or erasing operations on the memory cell array 210. The control circuitry 220 may control the peripheral circuitry.

[0047] The voltage generation circuit 230 can generate operating voltages of various levels. For example, in an erase operation, the voltage generation circuit 230 can generate operating voltages of various levels, such as erase voltage and pass voltage.

[0048] The line decoder 240 can communicate electrically with the voltage generation circuit 230 and a plurality of memory blocks 211. The line decoder 240 can select at least one memory block among the plurality of memory blocks 211 in response to a line address generated by the control circuit 220, and transmit the operating voltage supplied from the voltage generation circuit 230 to the selected memory block.

[0049] Page buffer array 250 can be connected to memory cell array 210 via bit lines. Page buffer array 250 can precharge bit lines BL with a positive voltage in response to page buffer control signals generated by control circuit 220, and transfer data to and from selected memory blocks or temporarily store transferred data during programming and read operations.

[0050] The column decoder 260 can transmit data to and receive data from the page buffer array 250, and can also transmit data to and receive data from the input / output circuit 270.

[0051] The input / output circuit 270 can transmit data from external devices (e.g., ...) via various lines. Figure 1 The memory controller 100 receives commands and addresses and transmits them to the control circuit 220, which transmits data from external devices to the column decoder 260, or outputs data from the column decoder 260 to external devices.

[0052] The control circuit 220 can control the peripheral circuits in response to commands and addresses.

[0053] Figure 3 This is a diagram illustrating a data processing system 300 comprising two high-speed peripheral component interconnect (PCI-e or PCIe) devices according to an embodiment of the present invention.

[0054] Reference Figure 3 The data processing system (or computing system) 300 may include two PCIe devices 310 and 320. PCIe devices 310 and 320 can be interconnected via a PCIe link. By way of example and without limitation, PCIe device 310 may be a host device 5, and PCIe device 320 may be a storage device (or memory system) 10, such as... Figure 1 and Figure 2 As shown. In some embodiments, the PCIe device 320 may be a NAND controller system-on-a-chip (SoC) implemented using a PCIe controller 322 and a PCIe PHY interface 324. The PCIe controller 322 and the PCIe physical layer (PHY) interface 324 may be connected via a PIPE (PHY interface for high-speed PCI) interface (link). This embodiment is described in U.S. Patent Application No. 10,817,443 entitled "Configurable Interface Card," which is incorporated herein by reference in its entirety.

[0055] PCIe is a multi-layer serial bus protocol that implements a dual-simplex link. Due to its dedicated point-to-point topology, PCIe provides high-speed data transfer and low latency. There exists a PIPE (PHY Interface for High-Speed ​​PCI) specification that defines the PHY's internal interface to the PCIe controller. PIPE is a standard interface defined between a sublayer of the Physical (PHY) layer (i.e., the Physical Coding Sublayer (PCS)) and the Media Access Control (MAC) layer. The PHY layer can include a PCS layer connected to the MAC layer via the PIPE interface, and a Physical Media Attachment (PMA) layer connected to the PCS layer. This PIPE specification allows for flexible combinations between PHY IP vendors and PCIe controller IP vendors without requiring two IPs from the same vendor.

[0056] PCIe has evolved and is entering the 5th generation (Gen5) / 6th generation (Gen6) stage. PCIe Gen5 uses PIPE5.1, while PCIe Gen6 uses PIPE6. As PCIe iterated from Gen1 to Gen4, the PIPE specification iterated from PIPE1 to PIPE4. (See reference...) Figure 4 The specification table shown, “PHY interface for high-speed PCI, SATA, USB 3.1, DisplayPort and USB4 architecture version 6.0” (hereinafter referred to as the “PIPE specification”), shows that the PIPE specifications from PIPE1 to PIPE4 are backward compatible, while PIPE4 and PIPE5 / PIPE6 are not compatible.

[0057] Reference Figure 4 For PCIe 5 / PCIe 6, a "legacy pin interface" is not allowed. However, PCIe 4.0 and earlier versions require it. This incompatibility can cause problems with the emulation and / or verification of PCIe controllers and SoCs that include PCIe controllers. Figure 5A In the example shown, if the PCIe controller, PCIe PHY interface, and simulation / verification device are all PIPE5 versions, then PCIe Gen5 testing will be performed. In many cases, a lower-speed test environment is required (e.g., FPGA / simulation / emulation). Lower speed corresponds to Gen4 and Gen3, which require PIPE4 (e.g., up to 16 gigabits per second (GT / s)). Therefore, if the PCIe controller is PIPE5 and the simulation / verification device is PIPE4, then PCIe Gen4 or Gen3 testing will not be performed. That is, PIPE4 is not implemented with a PIPE5 controller. Therefore, it is desirable to provide a scheme to provide compatibility between test devices (i.e., simulation / verification) with different versions of PCIe controllers. In some embodiments, such as Figure 5B As shown, the PIPE5 PCIe controller is compatible with PIPE4 devices via a PIPE5 to PIPE4 converter, enabling the performance of PCIe Gen4 or Gen3 tests. Figure 5B The diagram illustrates the use of a PIPE5 to PIPE4 converter without a PCIe PHY interface when the PCIe controller and test apparatus have different versions. Further, it illustrates the use of a PCIe PHY interface without a PIPE5 to PIPE4 converter when the PCIe controller and test apparatus have the same version.

[0058] Figure 6 This is a diagram illustrating a data processing system 600 including a PIPE5 to PIPE4 converter 630 according to an embodiment of the present invention.

[0059] Reference Figure 6 The data processing system 600 may include a PIPE5 controller 610, a PIPE4 device 620, and a PIPE5-to-PIPE4 converter 630. The PIPE5 controller 610 represents a PCIe controller according to PIPE specification version 5 (i.e., PIPE5), supporting a first link speed (e.g., 32 GT / s). The PIPE4 device 620 may include a test apparatus for simulation and verification according to PIPE specification version 4 (i.e., PIPE4), supporting a second link speed lower than the first link speed (e.g., up to 16 GT / s). In some embodiments, the PIPE4 device 620 may be a verification IP (VIP), an FPGA, or a simulation apparatus. A message bus interface 640 may be connected to the interface between the PIPE5 controller 610 and the PIPE5-to-PIPE4 converter 630. A PIPE link 650 may be connected to the interface between the PIPE4 device 620 and the PIPE5-to-PIPE4 converter 630. The message bus interface (i.e., the PIPE5 interface) 640 may conform to and comply with the PIPE5 specification. The PICe link (i.e., PIPE4 interface) 650 can follow and conform to the PIPE4 specification.

[0060] The PIPE5 to PIPE4 converter 630 may include a low-pin counting interface 632 as a first interface and a high-pin counting interface 634 as a second interface. The low-pin counting interface 632 conforms to the PIPE5 specification. The high-pin counting interface 634 conforms to the PIPE4 specification. The low-pin counting interface 632 can implement a low-pin counting state machine. The high-pin counting interface 634 can generate high-pin counting signals. The low-pin counting interface 632 can be connected to the PIPE5 controller 610 via a message bus interface 640. The high-pin counting interface 634 can be connected to the PIPE4 device 620 via a PCIe link 650.

[0061] The low-pin count interface 632 can transmit all relevant information via the message bus interface 640. Therefore, the low-pin count state machine can implement the message bus.

[0062] The PIPE5 to PIPE4 converter 630 can use address space to enable, for example Figure 7The message bus interface 640 between the MAC layer 710 and the PHY layer 720 is shown. These address spaces (e.g., 12-bit address spaces) can be used to host registers associated with specific PIPE operations. In some embodiments, the MAC layer 710 and the PHY layer 720 may each include address spaces, namely multiple MAC registers and multiple PHY registers. Each address space can be divided into four main regions: a receiver address region (RX), a transmitter address region (TX), a common address region (CMN), and a vendor-specific address region. The MAC layer 710 and the PHY layer 720 can access specific locations in the registers to initiate operations, participate in handshakes, or indicate status. The MAC layer 710 can initiate a request on the message bus interface 640 to access registers hosted in the PHY address space (i.e., PHY registers). The PHY layer 720 can initiate a request on the message bus interface 640 to access registers hosted in the MAC address space (i.e., MAC registers).

[0063] The low-pin-count interface 632 can transmit message bus interface signals between the PIPE5 controller 610 and the PIPE5 to PIPE4 converter 630. In some embodiments, such as Figure 8 As shown, the message bus interface signals can include signals (i.e., commands, addresses, and data), such as M2P_MessageBus[7:0] as input to the PIPE5 controller 610 and P2M_MessageBus[7:0] as output to the PIPE5 controller 610. Figure 9 The message bus commands are shown (e.g., write_uncommitted, write_committed, read, read completion, write_ack). The timing of each message bus transaction is as follows: Figures 10A to 10D As shown. Figure 10A The command-only message bus transaction timing (NOP, write_ack) is shown. Figure 10B The message bus transaction timing (Read) for {command + address} is shown. Figure 10B The message bus transaction timing (Read completion) for {command + data} is shown. Figure 10D The message bus transaction timing (Write_uncommitted, Write_committed) for {command + address + data} is shown. Figure 10B In the context of a read operation, commands [3:0] and Addr [11:8] are transmitted at (t), and Addr [7:0] is transmitted at (t+1). Figure 10DIn the context of a write operation, commands [3:0] and Addr [11:8] are transmitted at (t), Addr [7:0] is transmitted at (t+1), and Data [7:0] is transmitted at (t+2). The message bus transaction framework is as follows: Figure 11 As shown. Figure 11 As shown, the write operation requires 3 cycles (i.e., {cmd[3:0]+addr[11:8]}, addr[7:0], and data[7:0]).

[0064] Figure 7 This is a diagram illustrating the connection between the PIPE5 controller 610 and the PIPE5 to PIPE4 converter 630 according to an embodiment of the present invention.

[0065] Reference Figure 7 A PIPE5 to PIPE4 converter (hereinafter referred to as converter) 630 can be connected to a PIPE5 controller 610 via a message bus interface 640. The message bus interface 640 can define the PIPE5 interface and the functional division between the MAC layer 710 of the PIPE5 controller 610 and the PHY layer 720 of the converter 630. The PHY layer 720 may include a Physical Coding Sublayer (PCS) connected to the message bus interface 640 and a Physical Media Attachment (PMA) layer connected to the PCS layer. In some embodiments, commands, data (e.g., TxData, TxDataK, RxData, RxDataK), and signals (e.g., Status, PCLK) can be transmitted between the MAC layer 710 and the PHY layer 720. As described above, the MAC layer 710 and the PHY layer 720 may each include an address space, i.e., multiple MAC registers and multiple PHY registers.

[0066] The implementation schemes for the PHY register and MAC register are respectively in Figure 12A and Figure 13A As shown in the image. Figure 12A As shown, there are multiple PHY registers, including receiver areas (RX1, RX2), transmitter areas (TX1, TX2), and common areas (CMN1, CMN2), and each register corresponds to a specific byte address (i.e., 12'h0-12'hA00). For example, address "12'h6" (i.e., 6h) corresponds to register PHY Rx Control 3. Register PHY Rx Control 3 can be used to control, for example... Figure 12B The receiver function is shown. (As shown in the image.) Figure 13AAs shown, there are multiple MAC registers, including receiver areas (RX1, RX2) and transmitter areas (TX1, TX2), and each register corresponds to a value at a specific byte address (i.e., 12'h0-12'h7FF). For example, address "12'hB" (i.e., Bh) corresponds to MAC register RxLink Evaluation Status 1. MAC register RxLink Evaluation Status 1 can be used to control... Figure 12B The receiver function is shown. It can be accessed via... Figure 8 and Figure 9 Signal-driven read and write commands are used to access these registers.

[0067] When a first message bus interface signal is received from the PIPE5 controller 610 via message bus interface 640, the low pin count interface 632 can locate the target PHY register in the PHY register based on the first message bus interface signal, which includes commands, addresses, and / or data. In some embodiments, the converter 630 may include a decoder for decoding the address in the first message bus interface signal to locate the target PHY register and determine its contents. The high pin count interface 634 can then generate a first link interface signal associated with the target PHY register and output the first link interface signal to the PIPE4 device 620 via PCIe link 650. In some embodiments, the first link interface signal may include at least one signal indicated by the contents of the target PHY register.

[0068] Therefore, the low pin count interface 632 utilizes the message bus interface 640 to write to and read from the register space. When the MAC layer 710 of the PIPE5 controller 610 issues a message bus write to a specific PHY register space, the converter 630 decodes the contents of the PHY register space and drives (generates) the appropriate PIPE4 signal to output to the PIPE4 device 620 via the PCIe link 650.

[0069] For example, when the PIPE5 controller 610 sends... Figure 12A When the PHY RX Control 3 register sends a message to the bus for writing, the converter 630 occupies the following space: Figure 12BThe data bits [2], [1], and [0] in the PHY RX Control 3 register shown are used to generate appropriate PCIe link interface signals. These bits correspond to the PCIe link interface signals InvalidRequest, RxEqInProgress, and RxEqEval associated with PICe link 650 (i.e., PIPE4 interface) 650. InvalidRequest indicates a signal used to indicate that the link evaluation feedback request is out of range for the link partner TX equalization (EQ) setting. RxEqInProgress indicates a signal used by the MAC to indicate when the link equalization evaluation is performed. RxEqEval indicates a signal used to indicate that the PHY has started evaluating the remote transmitter TX EQ setting. The converter 630 can then send the PCIe link interface signals, namely InvalidRequest, RxEqInProgress, and RxEqEval, to the PIPE4 device 620 via PICe link 650. At the same time, the converter 630 can send a message bus response back to the PIPE5 controller 610.

[0070] When the second link interface signal is received from the PIPE4 device 620 via the second interface 634, the first interface 632 can locate the target MAC register in the MAC register based on the address in the second link interface signal. Further, the first interface 632 can output a second message bus interface signal to the PIPE5 controller 610 via the message bus interface 640. The second message bus interface signal can be a request to write data from the second link interface signal into the target MAC register corresponding to the second link interface signal.

[0071] Therefore, when the PIPE4 device 620 transmits the link interface signal, the converter 630 can decode the address and data of the target MAC register based on the link interface signal. Furthermore, the converter 630 can generate a message bus request to the PCIe5 controller 610 using a configuration scheme (i.e., the PIPE5 low pin count communication scheme).

[0072] For example, when the PIPE4 device 620 transmits a link interface signal (e.g., LinkEvaluationFeedbackDirectionChange[5:0]), such as Figure 13B As shown, converter 630 decodes the link interface signal and locates the target MAC register (i.e., RX1:RX LinkEvaluation Status1 with address Bh) in MAC register 710 based on the link interface signal. Converter 630 drives message bus interface 640 to send a write to the target MAC register with address Bh.

[0073] Figure 14A and Figure 14B This is a diagram illustrating an example of a signal to be converted by a PIPE5 to PIPE4 converter 630 according to an embodiment of the present invention.

[0074] Figure 14A The input signals of the PIPE5 controller 610 are shown, namely the signals transmitted from the PHY layer 720 of the PIPE5-to-PIPE4 converter 630 to the MAC layer 710 of the PIPE5 controller 610. For example, Figure 14A The signal “pipe_linkeval_dirchng” in the code corresponds to, for example, Figure 13A and Figure 13B The MAC register RX Link Evaluation Status 1 shows {LinkEvaluationFeedbackDirectionChange}.

[0075] Figure 14B The output signal of the PIPE5 controller 610 is shown, that is, the signal transmitted from the MAC layer 710 of the PIPE5 controller 610 to the PHY layer 720 of the PIPE5 to PIPE4 converter 630. For example, Figure 14B The signals “pipe_invalidrequest”, “pipe_rxeqinprogress”, and “pipe_rxeqeval” correspond to, for example, the following: Figure 12A and Figure 12B The PHY register shown is PHY RX Control 3, containing {InvalidRequest, RxEqInProgress, RxEqEval}.

[0076] As described above, embodiments of the present invention provide a solution for providing compatibility between a PIPE5 controller and a PIPE4 device. Specifically, embodiments provide a system and method including a PIPE5-to-PIPE4 converter. These embodiments enable a PIPE5 controller (i.e., Gen5) to be validated using low-speed FPGAs, analog and VIP emulation devices (i.e., PIPE4 devices).

[0077] Furthermore, embodiments of the invention have been described in the accompanying drawings and specification. While specific terminology has been used herein, these are merely for describing embodiments of the invention. Therefore, this disclosure is not limited to the above-described embodiments, and many variations can exist within the spirit and scope of this disclosure. Embodiments can be combined to form additional embodiments.

[0078] While the foregoing embodiments have been shown and described in considerable detail for clarity and understanding, the invention is not limited to the details provided. As will be understood by those skilled in the art based on the foregoing disclosure, many alternatives exist for implementing the invention. Therefore, the disclosed embodiments are illustrative and not restrictive. The invention is intended to cover all modifications falling within the scope of the appended claims.

Claims

1. A data processing system comprising: a physical interface of a high-speed PCI PIPE 5 controller, i.e., a physical interface of a PCIe PIPE 5 controller, including a plurality of media access control registers, i.e., a plurality of MAC registers; a PIPE 4 device; and a translator including a first interface coupled to the PIPE 5 controller through a message bus interface, a second interface coupled to the PIPE 4 device through a PCIe link, and a plurality of physical registers, i.e., a plurality of PHY registers, wherein, when a first message bus interface signal is received from the PIPE 5 controller, the first interface finds a target PHY register among the plurality of PHY registers based on the first message bus interface signal, and the second interface generates and outputs a first link interface signal associated with the target PHY register to the PIPE 4 device, and wherein, when a second link interface signal is received from the PIPE 4 device, the first interface finds a target MAC register among the plurality of MAC registers based on the second link interface signal, and outputs a second message bus interface signal based on the second link interface signal to write to the target MAC register.

2. The system of claim 1, wherein the first message bus interface signal includes an address of the target PHY register, and the second message bus interface signal includes an address of the target MAC register.

3. The system of claim 1, wherein the first link interface signal includes at least one signal indicated by contents of the target PHY register.

4. The system of claim 1, wherein the first interface transmits a message bus response to the PIPE 5 controller in response to the first message bus interface signal.

5. The system of claim 1, wherein the second link interface signal includes data to be written to the target MAC register, and the second message bus interface signal includes data and an address of the target MAC register.

6. The system of claim 1, wherein the first interface complies with PIPE Specification version 5.0, and the second interface complies with PIPE Specification version 4.

0.

7. The system of claim 1, wherein the PIPE 4 device includes a test device for simulation and validation.

8. A method of coupling a high-speed PCI PIPE 5 controller with a PIPE 4 device, i.e., a method of coupling a PCIe PIPE 5 controller with a PIPE 4 device, the method comprising: providing a translator including a first interface coupled to the PIPE 5 controller through a message bus interface, a second interface coupled to the PIPE 4 device through a PCIe link, and a plurality of physical registers, i.e., a plurality of PHY registers, the PIPE 5 controller including a plurality of media access control registers, i.e., a plurality of MAC registers; when a first message bus interface signal is received from the PIPE 5 controller, performing a first operation; and when receiving a second link interface signal from the PIPE4 device, performing a second operation, wherein the first operation comprises: finding, by the first interface, a target PHY register among the plurality of PHY registers based on the first message bus interface signal; and generating, by the second interface, a first link interface signal associated with the target PHY register and outputting the first link interface signal to the PIPE4 device, and wherein the second operation comprises: finding, by the first interface, a target MAC register among the plurality of MAC registers based on the second link interface signal; and outputting, by the first interface, a second message bus interface signal based on the second link interface signal to write to the target MAC register.

9. The method of claim 8, wherein the first message bus interface signal comprises an address of the target PHY register and the second message bus interface signal comprises an address of the target MAC register.

10. The method of claim 8, wherein the first link interface signal comprises at least one signal indicated by contents of the target PHY register.

11. The method of claim 8, further comprising: transmitting, by the first interface, a message bus response to the PIPE5 controller in response to the first message bus interface signal.

12. The method of claim 8, wherein the second link interface signal comprises data to be written to the target MAC register and the second message bus interface signal comprises data and an address of the target MAC register.

13. The method of claim 8, wherein the first interface complies with PIPE Specification version 5.0 and the second interface complies with PIPE Specification version 4.

0.

14. The method of claim 8, wherein the PIPE4 device comprises a test device for simulation and validation.

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