A multi-core SOC synchronization system

Abstract

This invention relates to a multi-core SOC synchronization system, comprising multiple CPUs, each CPU having at least one synchronization interface module. The synchronization interface module includes a synchronization input interface `sync_i`, a synchronization output interface `sync_o`, a synchronization clear input interface `clr_sync_o`, and a synchronization clear output interface `clr_sync_i`. Two CPUs requiring synchronization are connected and synchronized through the synchronization interface module. This invention is highly efficient for multiple synchronizations between dual-core CPUs, offering high flexibility and stability. It can also be efficiently extended to multiple synchronizations between multiple core CPUs, facilitating applications in multi-core products across different platforms. It is compatible with various products, highly modular, and reusable, reducing redundant development and improving development efficiency.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and more specifically to a multi-core SOC synchronization system. Background Technology

[0002] With technological advancements, multi-core SoCs are becoming increasingly widespread. Some dedicated chips require multiple cores to rely on the same hardware peripheral or configuration parameters during initialization, resulting in complex timing requirements and necessitating multiple synchronizations. For market applications of multi-core systems, some initializations related to the duration of hardware peripheral changes require multiple synchronizations. However, existing polling methods can only be used for single-time synchronization and cannot handle multiple synchronizations, failing to meet the requirements for complex hardware peripheral initializations. Furthermore, the CPU frequencies of each core may differ; using existing polling methods for multiple synchronizations could lead to system crashes due to frequency asynchrony. Summary of the Invention

[0003] To address the problems existing in the prior art, the purpose of this invention is to provide a multi-core SOC synchronization system that can achieve multiple synchronizations between different CPUs.

[0004] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0005] A multi-core SOC synchronization system includes multiple CPUs, each CPU having at least one synchronization interface module, wherein the synchronization interface module has a synchronization input interface sync_i, a synchronization output interface sync_o, a synchronization clear input interface clr_sync_o, and a synchronization clear output interface clr_sync_i.

[0006] When multiple CPUs are synchronized, each CPU performs at least one synchronization process; the synchronization process refers to synchronization between two CPUs.

[0007] During synchronization, two CPUs that need to be synchronized are connected through a synchronization interface module. The two CPUs are defined as the first CPU and the second CPU. The synchronization interface module of the first CPU is defined as the first synchronization interface module, and the synchronization interface module of the second CPU is defined as the second synchronization interface module.

[0008] The synchronization output interface sync_o of the first synchronization interface module is connected to the synchronization input interface sync_i of the second synchronization interface module, and the synchronization clear output interface clr_sync_i of the first synchronization interface module is connected to the synchronization clear input interface clr_sync_o of the second synchronization interface module; the synchronization output interface sync_o of the second synchronization interface module is connected to the synchronization input interface sync_i of the first synchronization interface module, and the synchronization clear output interface clr_sync_i of the second synchronization interface module is connected to the synchronization clear input interface clr_sync_o of the first synchronization interface module.

[0009] The synchronization process between the first CPU and the second CPU is as follows:

[0010] The first CPU sets the synchronization output interface sync_o of the first synchronization interface module to 1 and the synchronization input interface sync_i of the second synchronization interface module to 1. The second CPU then knows that the first CPU is ready. The first CPU then starts polling the synchronization input interface sync_i of the first synchronization interface module. If the synchronization input interface sync_i of the first synchronization interface module is not 1, it sleeps for time T and then enters the next polling. If the synchronization input interface sync_i of the first synchronization interface module is 1, the first CPU sets the synchronization clear output interface clr_sync_i of the first synchronization interface module to 1 and the synchronization clear input interface clr_sync_o of the second synchronization interface module to 1. This triggers the first CPU to set the synchronization output interface sync_o of the first synchronization interface module to 0, and also triggers the second CPU to set the synchronization output interface sync_o of the second synchronization interface module to 0. After sleeping for time T+delta, the synchronization process between the first CPU and the second CPU is completed.

[0011] The delta is set to 0.1T-0.3T.

[0012] By adopting the above solution, this invention can be efficiently used for multiple synchronizations between dual cores, offering high flexibility and stability. It can also be efficiently used to extend multiple synchronizations between multi-core systems, facilitating multi-core product applications on different platforms. Different products can share resources, exhibiting high modularity and strong reusability, reducing redundant development and improving development efficiency. Furthermore, this invention allows for flexible configuration of sleep time T and delta according to different product platforms, enabling timely release of hardware resources while ensuring system reliability, thereby improving system operating efficiency. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of the synchronization interface module;

[0014] Figure 2 A schematic diagram showing the connection of the synchronization interface module between two CPUs;

[0015] Figure 3 The flowchart shows the synchronization process between two CPUs;

[0016] Figure 4 This is a schematic diagram illustrating the synchronization between two CPUs;

[0017] Figure 5 This is a schematic diagram illustrating the synchronization between three CPUs. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments.

[0019] Example 1

[0020] This invention discloses a multi-core SOC synchronization system, which includes multiple CPUs, each CPU having at least one synchronization interface module.

[0021] like Figure 1 As shown, the synchronization interface module has a synchronization input interface sync_i, a synchronization output interface sync_o, a synchronization clear input interface clr_sync_o, and a synchronization clear output interface clr_sync_i.

[0022] like Figure 2 As shown, this embodiment requires synchronization between two CPUs. The two CPUs to be synchronized are defined as a first CPU and a second CPU. The synchronization interface module of the first CPU is defined as the first synchronization interface module, and the synchronization interface module of the second CPU is defined as the second synchronization interface module. The synchronization output interface `sync_o` of the first synchronization interface module is connected to the synchronization input interface `sync_i` of the second synchronization interface module, and the synchronization clear output interface `clr_sync_i` of the first synchronization interface module is connected to the synchronization clear input interface `clr_sync_o` of the second synchronization interface module; similarly, the synchronization output interface `sync_o` of the second synchronization interface module is connected to the synchronization input interface `sync_i` of the first synchronization interface module, and the synchronization clear output interface `clr_sync_i` of the second synchronization interface module is connected to the synchronization clear input interface `clr_sync_o` of the first synchronization interface module.

[0023] like Figure 3 and Figure 4 As shown, the synchronization process between the first CPU and the second CPU is as follows:

[0024] The first CPU sets the synchronization output interface sync_o of the first synchronization interface module to 1 and the synchronization input interface sync_i of the second synchronization interface module to 1. The second CPU then knows that the first CPU is ready. The first CPU then starts polling the synchronization input interface sync_i of the first synchronization interface module. If the synchronization input interface sync_i of the first synchronization interface module is not 1, it sleeps for time T and then enters the next polling. If the synchronization input interface sync_i of the first synchronization interface module is 1, the first CPU sets the synchronization clear output interface clr_sync_i of the first synchronization interface module to 1 and the synchronization clear input interface clr_sync_o of the second synchronization interface module to 1. This triggers the first CPU to set the synchronization output interface sync_o of the first synchronization interface module to 0, and also triggers the second CPU to set the synchronization output interface sync_o of the second synchronization interface module to 0. After sleeping for time T+delta, the synchronization between the first CPU and the second CPU is completed.

[0025] After the second CPU receives the peripheral parameters, it needs to synchronize with the first CPU again. Specifically, the second CPU sets the synchronization output interface sync_o of the second synchronization interface module to 1 and the synchronization input interface sync_i of the first synchronization interface module to 1, so the first CPU knows that the second CPU is ready. Then, the second CPU starts polling the synchronization input interface sync_i of the second synchronization interface module. If the synchronization input interface sync_i of the second synchronization interface module is not 1, it sleeps for T time and then enters the next polling. If the synchronization input interface sync_i of the second synchronization interface module is 1, the second CPU sets the synchronization clear output interface clr_sync_i of the second synchronization interface module to 1 and the synchronization clear input interface clr_sync_o of the first synchronization interface module to 1, triggering the first CPU to set the synchronization output interface sync_o of the first synchronization interface module to 0, and triggering the second CPU to set the synchronization output interface sync_o of the second synchronization interface module to 0. After sleeping for T+delta time, the synchronization between the first CPU and the second CPU is completed.

[0026] Once the first CPU and the second CPU have synchronized, they can each run their respective tasks.

[0027] Because the CPU clock speeds of different cores may be asynchronous and the sleep time T may have timing errors, the delta time cannot be set to 0. Otherwise, the device cannot be used for multiple synchronizations. In this embodiment, delta is set to 0.1T-0.3T.

[0028] This invention adds a delta sleep time, which can be used for multiple synchronizations by creating and using only one synchronization interface module. It can also effectively avoid timing errors and system crashes caused by differences or asynchrony of CPU main frequency during multiple synchronizations.

[0029] Example 2

[0030] like Figure 5 As shown, to achieve synchronization among three CPUs, each CPU must perform at least one synchronization process, meaning at least two synchronizations are required. Specifically, synchronization is performed based on the actual connection relationship. When the first CPU and the second CPU are connected, and the second CPU and the third CPU are connected, synchronization between the first CPU and the second CPU, as well as between the second CPU and the third CPU, can be performed. When the first CPU and the third CPU are connected, and the second CPU and the third CPU are connected, synchronization between the first CPU and the third CPU, as well as between the second CPU and the third CPU, can be performed. In this embodiment, the first CPU and the second CPU are connected, and the second CPU and the third CPU are connected. Specifically, the first CPU has a first synchronization interface module, the second CPU has a second synchronization interface module and a third synchronization interface module, and the third CPU has a fourth synchronization interface module. The first synchronization interface module is connected to the second synchronization interface module, and the third synchronization interface module is connected to the fourth synchronization interface module. The connection between the two synchronization interface modules is the same as in Embodiment 1, and will not be repeated here.

[0031] The synchronization between the three CPUs is as follows:

[0032] First synchronization: The first CPU sets the synchronization output interface sync_o of the first synchronization interface module to 1 and the synchronization input interface sync_i of the second synchronization interface module to 1. The second CPU then knows that the first CPU is ready. The first CPU then starts polling the synchronization input interface sync_i of the first synchronization interface module. If the synchronization input interface sync_i of the first synchronization interface module is not 1, it sleeps for time T and then enters the next polling. If the synchronization input interface sync_i of the first synchronization interface module is 1, the first CPU sets the synchronization clear output interface clr_sync_i of the first synchronization interface module to 1 and the synchronization clear input interface clr_sync_o of the second synchronization interface module to 1. This triggers the first CPU to set the synchronization output interface sync_o of the first synchronization interface module to 0, and also triggers the second CPU to set the synchronization output interface sync_o of the second synchronization interface module to 0. After sleeping for time T+delta, the first synchronization is completed.

[0033] Second synchronization: The third CPU sets the synchronization output interface sync_o of the fourth synchronization interface module to 1 and the synchronization input interface sync_i of the third synchronization interface module to 1. The second CPU then knows that the third CPU is ready. The third CPU then starts polling the synchronization input interface sync_i of the fourth synchronization interface module. If the synchronization input interface sync_i of the fourth synchronization interface module is not 1, it sleeps for time T and then enters the next polling. If the synchronization input interface sync_i of the fourth synchronization interface module is 1, the third CPU sets the synchronization clear output interface clr_sync_i of the fourth synchronization interface module to 1 and the synchronization clear input interface clr_sync_o of the third synchronization interface module to 1, triggering the second CPU to set the synchronization output interface sync_o of the third synchronization interface module to 0, and also triggering the third CPU to set the synchronization output interface sync_o of the fourth synchronization interface module to 0. After sleeping for time T+delta, the second synchronization is completed.

[0034] If the second CPU also acquires peripheral parameters during the second synchronization process, it may be necessary to synchronize the first CPU and the second CPU again, i.e., a third synchronization.

[0035] The third synchronization: The first CPU sets the synchronization output interface sync_o of the first synchronization interface module to 1 and the synchronization input interface sync_i of the second synchronization interface module to 1. The second CPU then knows that the first CPU is ready. The first CPU then starts polling the synchronization input interface sync_i of the first synchronization interface module. If the synchronization input interface sync_i of the first synchronization interface module is not 1, it sleeps for time T and then enters the next polling. If the synchronization input interface sync_i of the first synchronization interface module is 1, the first CPU sets the synchronization clear output interface clr_sync_i of the first synchronization interface module to 1 and the synchronization clear input interface clr_sync_o of the second synchronization interface module to 1. This triggers the first CPU to set the synchronization output interface sync_o of the first synchronization interface module to 0, and also triggers the second CPU to set the synchronization output interface sync_o of the second synchronization interface module to 0. After sleeping for time T+delta, the third synchronization is completed.

[0036] Once the first, second, and third CPUs are synchronized, they can each run their respective tasks.

[0037] In summary, this invention can be efficiently used for multiple synchronizations between dual-core processors, offering high flexibility and stability. It can also be efficiently extended to multiple synchronizations between multi-core processors, facilitating applications across multi-core products on different platforms. It is compatible with various products, highly modular, and reusable, reducing redundant development and improving development efficiency. Furthermore, this invention allows for flexible configuration of sleep time T and delta based on different product platforms, enabling timely release of hardware resources while ensuring system reliability and improving system operating efficiency.

[0038] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0039] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0040] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0041] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0042] It should be noted that any reference signs placed between parentheses in the claims should not be construed as limiting the claims. The word "comprising" does not exclude the presence of components or steps not listed in the claims. The word "a" or "an" preceding a component does not exclude the presence of a plurality of such components. The invention can be implemented by means of hardware comprising several different components and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

[0043] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0044] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

[0045] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms should not be construed as necessarily referring to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

Claims

1. A multi-core SOC synchronization system, characterized in that: The synchronization system comprises a plurality of CPUs, each CPU being provided with at least one synchronization interface module, the synchronization interface module being provided with a synchronization input interface sync_i, a synchronization output interface sync_o, a synchronization clear input interface clr_sync_o and a synchronization clear output interface clr_sync_i; When the plurality of CPUs are synchronized, each CPU performs at least one synchronization process; the synchronization process refers to synchronization between two CPUs; During the synchronization process, the two CPUs to be synchronized are connected through the synchronization interface modules, the two CPUs being defined as a first CPU and a second CPU, the synchronization interface module of the first CPU being defined as a first synchronization interface module, and the synchronization interface module of the second CPU being defined as a second synchronization interface module; The synchronization output interface sync_o of the first synchronization interface module is connected to the synchronization input interface sync_i of the second synchronization interface module, and the synchronization clear output interface clr_sync_i of the first synchronization interface module is connected to the synchronization clear input interface clr_sync_o of the second synchronization interface module; the synchronization output interface sync_o of the second synchronization interface module is connected to the synchronization input interface sync_i of the first synchronization interface module, and the synchronization clear output interface clr_sync_i of the second synchronization interface module is connected to the synchronization clear input interface clr_sync_o of the first synchronization interface module; The synchronization process of the first CPU and the second CPU is as follows: The first CPU sets the synchronization output interface sync_o of the first synchronization interface module to 1, and the synchronization input interface sync_i of the second synchronization interface module to 1, and the second CPU knows that the state of the first CPU is ready; then the first CPU starts polling the synchronization input interface sync_i of the first synchronization interface module, if the synchronization input interface sync_i of the first synchronization interface module is not 1, the first CPU sleeps for T time and then enters the next polling; if the synchronization input interface sync_i of the first synchronization interface module is 1, the first CPU sets the synchronization clear output interface clr_sync_i of the first synchronization interface module to 1, and the synchronization clear input interface clr_sync_o of the second synchronization interface module to 1, triggers the first CPU to set the synchronization output interface sync_o of the first synchronization interface module to 0, and triggers the second CPU to set the synchronization output interface sync_o of the second synchronization interface module to 0, and then the first CPU sleeps for T+delta time, and the synchronization between the first CPU and the second CPU is completed.

2. The multi-core SOC synchronization system of claim 1, wherein: The delta is set to 0.1T-0.3T.

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