A path analysis method in static timing analysis of integrated circuits

Abstract

The present invention discloses a path analysis method in static timing analysis of integrated circuits, including the steps of: initializing the circuit structure, calculating based on the grouped delay information enumerated by the depth of the clock tree, and generating and merging candidate paths; representing the integrated circuit as a rooted clock tree and a directed acyclic graph; where the nodes represent the pins of the circuit and the edges represent the connection relationships between the pins; each edge is marked with the minimum and maximum time delays of signal transmission; grouping the clock tree according to a specified depth, and calculating the grouped delay information of the nodes through a delay propagation algorithm based on grouping constraints; iteratively generating candidate timing violation paths for each depth of the clock tree and screening and merging them, taking the paths with the first k smallest slack values, and obtaining the results of the first k paths with the most serious timing violations. Through the present invention, common pessimistic path elimination can be supported, the generality and efficiency of the path analysis method can be improved, and a calculation acceleration effect of up to 100 times can be achieved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit design automation, relates to integrated circuit static timing analysis technology, and specifically relates to a path analysis method in integrated circuit static timing analysis. The algorithm and data structure of the path analysis step in the static timing analysis process of integrated circuit back-end design are designed to support common pessimistic path removal (CPPR), and improve the generality and efficiency of the path analysis method. Background Art

[0002] In the design of sequential logic chips, at each rising edge of the clock, the registers in the integrated circuit store the data at the input end. The output end of the register and the input end of the register in the next calculation step are connected by combinational logic. Depending on the specifications, the register has requirements for the data preparation time at the input end. Before the rising edge of the clock arrives, the data at the input end should remain stable for a period of time; after the rising edge of the clock arrives, the data at the input end should still remain unchanged for a period of time, that is, the combinational logic between the registers cannot be too fast or too slow. Violations of timing will cause the chip to work unstably or the calculation results to be incorrect. Therefore, in integrated circuit design automation, timing analysis of the circuit is crucial for ensuring the correctness of chip design and improving the working efficiency of the chip.

[0003] Static timing analysis is to perform timing analysis according to a simplified component and wiring delay model, avoiding detailed simulation of the circuit each time, so it can be completed in a relatively short time. Static timing analysis is mainly divided into two stages. The first stage is called graph analysis. In this stage, for each node in the circuit, the possible earliest and latest arrival times of the signal, as well as the earliest and latest time constraints of the signal, are calculated. The second stage is called path analysis. In this stage, based on the graph analysis, the top k paths with the most serious timing violations are calculated. Depending on different timing analysis requirements, k ranges from 100 to tens of thousands.

[0004] In path analysis, in order to find the paths where timing violations may occur, we make the worst-case assumption for each edge in the path. For example, in setup time detection, we assume that the path from the clock pin to the starting register takes the maximum delay, while the path from the clock pin to the ending register takes the minimum delay. However, there may be a common part between these two paths, and it is impossible for this common path to take the minimum delay and the maximum delay at the same time. The purpose of common path pessimistic elimination in path analysis is to remove the unreasonable assumptions in the timing violation calculation process, so that the analysis results can more accurately reflect the situation of the circuit.

[0005] Timing analysis is usually placed in the inner loop of design automation steps (such as placement and routing) as an optimization goal, and thus will be run a large number of times. For very large scale integrated circuits, the number of basic components is usually in the tens of millions, which makes the static timing analysis step take a large amount of time and become a bottleneck in the design automation steps. Among them, the path analysis stage especially takes a large amount of time. Therefore, how to accelerate the operation of this stage has become an urgent problem to be solved.

[0006] The existing traditional path analysis algorithms have the following deficiencies:

[0007] (1) The path analysis algorithms of some static timing analysis tools do not include support for pessimistic elimination of common paths. Therefore, the results obtained are less accurate and have less guiding significance for integrated circuit design optimization.

[0008] (2) For tools that support pessimistic elimination of common paths, most of them calculate by brute-force enumeration to traverse all start-end register pairs. This results in the path analysis stage being hundreds or thousands of times slower than the case without pessimistic elimination of common paths, making the cost of static timing analysis unacceptable.

[0009] (3) Some of the above software performs pruning optimization according to the operation characteristics of specific circuits to reduce the running time. However, this method is related to the specific circuit form and is not universal, and it is still very slow in large-scale path generation tasks.

[0010] In summary, the existing path analysis implementations that include pessimistic elimination of common paths are restricted by inefficient data structures and algorithms, require a long time for very large scale integrated circuits and a large number of path generation tasks, and there is no relatively general and efficient acceleration algorithm yet. Summary of the Invention

[0011] Aiming at the deficiencies of the above existing technologies, the present invention provides a path analysis method in static timing analysis of integrated circuits, designs the algorithms and data structures of the path analysis step in static timing analysis, and conducts targeted optimization of pessimistic elimination of common paths. Through the present invention, the path analysis step in static timing analysis of integrated circuits can support common pessimistic path elimination (CPPR), improve the generality and efficiency of the path analysis method, and can achieve a calculation acceleration effect of up to a hundred times.

[0012] The difficulty of the common path pessimism elimination problem lies in that the lengths of the common paths between different registers are different, and thus the amounts of pessimism to be eliminated are different. Therefore, the top k timing violation paths obtained without considering the pessimism amount may not be the top k timing violation paths after eliminating the pessimism amount. In order to obtain the true top k paths, the existing methods can only obtain their respective common paths and their pessimism amounts by enumerating all register pairs, perform path extraction separately and then merge the results to obtain a correct path analysis report. For modern large-scale integrated circuits, the number of registers is in the hundreds of thousands, which results in very low efficiency of the traditional methods. Instead of eliminating the pessimism amount by enumerating register pairs, the present invention classifies the combinations of registers by enumerating different depths of the clock tree starting from the clock tree. The depth of the clock tree is generally less than one hundred, which is two to three orders of magnitude less than the number of registers. By designing a processing algorithm for different clock tree depths and a corresponding efficient data structure, the present invention provides a new and efficient solution for the path analysis of common path pessimism elimination.

[0013] The technical solution of the present invention is as follows:

[0014] A path analysis method in static timing analysis of an integrated circuit, which supports common path pessimism elimination, including the steps of: initializing the circuit structure, calculating the grouped delay information based on the enumeration of the clock tree depth, and generating and merging candidate paths to obtain a path list with the common path pessimism amount eliminated. In the circuit structure initialization step, the clock net of the integrated circuit is represented as a rooted tree (referred to as the clock tree), and the rest of the integrated circuit except the clock net is represented as a directed acyclic graph. In the structure of the rooted tree and the directed acyclic graph, the nodes represent the pins and turning parts of the circuit, and the edges represent the connection relationships between the pins. In the step of calculating the delay information based on the enumeration of the clock tree depth, the parts at a specified depth of the clock tree are grouped, and a delay propagation algorithm based on grouping constraints is designed to complete the calculation of the grouped delay information. In the candidate path generation and merging step, based on the grouped delay information of the nodes, for each depth of the clock tree, k candidate timing violation paths are iteratively generated in the priority queue, the candidate paths from different depths are screened and merged, and the paths with the first k smallest slack values are taken to obtain the result of the path analysis, that is, the first k paths with the most serious timing violations. Specifically, it includes the following steps:

[0015] A. Initializing the circuit structure;

[0016] Divide the circuit structure diagram of the integrated circuit into two parts, namely the clock netlist of the integrated circuit and other combinational logics. Represent the clock netlist of the integrated circuit as a rooted tree, called the clock tree; where the root node of the tree represents the clock pin of the chip, the leaf nodes represent registers, and the edges of the tree are the connection relationships between the nodes; represent other combinational logics in the integrated circuit as a directed acyclic graph, where the nodes in the graph represent the pins of the circuit, and the directed edges represent the connection relationships between the pins; in the above directed acyclic graph and rooted tree, each edge is marked with the minimum and maximum propagation delays of the signal transmission.

[0017] B. Calculation of grouped delay information based on clock tree depth enumeration;

[0018] Perform the depth calculation and grouping of clock tree nodes. Calculate the depth of each clock tree node, where the depth of the root node of the clock tree is 0, and the depth of the remaining nodes is the depth of its parent node plus 1. For each depth d of the clock tree nodes, group the part of the clock tree below this depth d, that is, each group is a subtree containing nodes with a depth greater than or equal to d + 1. Define the number of each group as the number of the root node of its subtree, and define the group number of each node as the number of the group it belongs to.

[0019] Perform delay propagation based on grouping constraints, including setup propagation and hold propagation. For the rooted tree of the clock netlist and the directed acyclic graph of other combinational logics, set the actual delay of each edge;

[0020] For setup propagation, set the tree edges above the depth d of the clock tree to the minimum delay, and set the tree edges below the depth d to the maximum delay; for the directed acyclic graph composed of combinational logics other than the clock tree, set the directed edges to the maximum delay. For hold propagation, exchange the above maximum delay and minimum delay.

[0021] For establishing time propagation, define the extreme delay of each node in the directed acyclic graph as the maximum possible delay among all paths ending at this node, and the second extreme delay as the second largest possible delay excluding the above-mentioned delay, and ensure that the clock tree node corresponding to this delay belongs to a different group number from the clock tree node of the maximum possible delay source; for hold time propagation, define the extreme delay of a node as the minimum possible delay among all paths ending at this node, and the second extreme delay as the second smallest possible delay excluding the above-mentioned delay, and ensure that the clock tree node corresponding to this delay belongs to a different group number from the clock tree node of the minimum possible delay source. Calculate the cumulative delay from the root node of the clock tree to each node on the clock tree, i.e., the delay of the clock tree node. Using the delay of the clock tree node as the initial value, complete the delay update on the directed acyclic graph according to the topological order to obtain the grouped delay information of each pin in the circuit: including the extreme delay, the group number of the clock tree node to which the extreme delay belongs, as well as the second extreme delay and the group number of the corresponding clock tree node.

[0022] C. Generation and merging of candidate paths;

[0023] Perform path generation based on grouping constraints, where the paths include setup time violation paths and hold time violation paths, corresponding to the setup time propagation and hold time propagation in the calculation steps of grouped delay information enumerated based on the clock tree depth respectively, and perform calculations on the corresponding delay information, specifically including initial path calculation and path iterative generation.

[0024] For each depth d (the value of d ranges from 0 to the height of the clock tree, and the height of the clock tree usually does not exceed 100), calculate the initial path of each register. For setup time propagation, calculate the earliest time constraint value of the register, i.e., the sum of the minimum time delays on the path from the root node of the clock tree to this register; for hold time propagation, calculate the latest time constraint value of the register, i.e., the sum of the maximum time delays on the path from the root node of the clock tree to this register; traverse all registers, and calculate the path with the most serious timing violation ending at this register, i.e., the path with the smallest slack value, as the initial path of this register through the time constraint value and delay information.

[0025] Based on the initial paths of each register, perform iterative generation of paths. Put the initial paths of all registers into a priority queue. Take out the path with the smallest slack value from the priority queue, enumerate the incoming edges of each point on this path, expand new paths through the incoming edges, and add them to the priority queue; for the problem of generating k timing violation paths (k usually ranges from 1 to 10000, depending on the requirements of static timing analysis), repeat the above operations k times, and the k paths taken out are used as the results of path iterative generation, which are the candidate paths for depth d.

[0026] Perform the merging of candidate paths. Among the k candidate paths generated for each depth d in the above steps, take out the start and end registers of the paths and calculate the lowest common ancestor (LCA) in the clock tree. Retain the paths with the lowest common ancestor depth of d and discard the remaining paths. Sort all the obtained paths in ascending order of the slack value, and take the top k paths as the final timing violation paths.

[0027] The above are the three steps for path analysis in the present invention. Through the above three steps A, B, and C, a complete path analysis process can be completed, and the obtained result is the result of eliminating the pessimism of the common path.

[0028] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0029] The present invention only needs to enumerate the depth of the clock tree to complete the elimination of the pessimism of the common path, obtain the true timing violation situation of the path, and calculate the top k paths with the most serious timing violations, without the need to consider each register separately. The depth of the clock tree is usually within 100, while the number of registers is in the order of hundreds of thousands. Therefore, the present invention can reduce the number of circuit diagram traversals by two to three orders of magnitude, reduce the cost of static timing analysis, and further improve the performance of the timing-driven chip design automation algorithm. Description of the Drawings

[0030] Figure 1 is a flowchart of the path analysis method provided by the present invention.

[0031] Figure 2 is a flowchart of the depth-based grouped delay information calculation and candidate path generation steps in the present invention.

[0032] Figure 3 is a schematic structural diagram of the circuit structure initialization in the specific implementation process of the present invention.

[0033] Figure 4 is a schematic diagram of the depth-based grouped delay information calculation based on the clock tree depth enumeration in the specific implementation process of the present invention.

[0034] Figure 5 is a schematic diagram of the candidate path generation process in the specific implementation process of the present invention. Detailed Embodiment

[0035] The following further elaborates the present invention through embodiments in conjunction with the drawings, but does not limit the scope of the present invention in any way.

[0036] The present invention provides a path analysis algorithm that supports pessimistic elimination of common paths. The clock net in the input circuit information is represented as a rooted tree, and the remaining combinational logic is represented as a directed acyclic graph. The depth of each node in the rooted tree is calculated, the points below each depth are grouped, and a delay propagation algorithm based on grouping constraints is designed to obtain the delay information of each node in the directed acyclic graph, including two extreme values of the delay and the grouping number of the clock tree node to which it belongs; the initial path is calculated through the delay information of the registers, and a priority queue is used to iteratively generate candidate paths; the candidate paths are screened and merged to obtain the top k timing violation paths, which is the result of the path analysis. By using the method of the present invention, only the depth of the clock tree needs to be enumerated, and the registers do not need to be enumerated, which can reduce the number of times of traversing the circuit diagram in the path analysis process by two to three orders of magnitude, reduce the cost of static timing analysis, and thus improve the performance of the timing-driven chip design automation algorithm.

[0037] The steps for the present invention to handle the path analysis problem are as Figure 1 shown, Figure 1 The solid arrows in it indicate the processing sequence relationship of the method steps. The steps include circuit structure initialization, calculation of delay information, generation and merging of candidate paths. Among them, the calculation of delay information and the generation of candidate paths are performed independently once for each depth, and the process is as Figure 2 shown, including calculating the cumulative delay of the clock tree nodes, calculating the grouped delay information of the nodes in the directed acyclic graph, generating the initial path, and iteratively generating candidate paths.

[0038] A. Circuit structure initialization

[0039] The circuit structure diagram of the integrated circuit is divided into two parts, where the clock net is represented as a rooted tree, and the other combinational logic is represented as a directed acyclic graph. As Figure 3 , where part 1 represents the rooted tree of the clock net, and part 2 represents the directed acyclic graph of the remaining combinational logic. The nodes in the figure represent the pins of the circuit, and the directed edges represent the connection relationships between the pins; in the rooted tree, the root CK represents the clock pin of the circuit design, and the leaves of the rooted tree (i.e., a, b, c, d, e in the figure) are the clock pins of the registers, and the two are connected through the rooted tree of the clock net; the directed acyclic graph of the combinational logic starts from the clock pins of the registers (i.e., a, b, c, d, e in the figure) and terminates at the input pins of the registers (i.e., a', b', c', d', e' in the figure), and the two are connected through the directed acyclic graph.

[0040] B. Calculation of grouped delay information based on clock tree depth enumeration

[0041] Perform the depth calculation and grouping of the clock tree nodes. Calculate the depth of each clock tree node, where the root node of the clock tree (i.e., Figure 3The depth of the CK node is 0, and the depth of the remaining nodes is the depth of their parent node plus 1. For example, Figure 3 the depths of nodes a, b, c, d, and e in Figure 4 are all 2. For each depth d of the clock tree nodes, the part of the clock tree below depth d is grouped, that is, each group is a subtree containing nodes with a depth greater than or equal to d + 1. Define the number of each group as the number of its subtree root node, and the group number of each node is defined as the number of the group it belongs to. For example,

[0042] Perform delay propagation based on grouping constraints, including setup time propagation and hold time propagation. For the rooted tree of the clock net and the directed acyclic graph of other combinational logics, set the actual delay of each edge; for setup time propagation, set the tree edges above depth d of the clock tree to the minimum delay, and the tree edges below depth d to the maximum delay. For the directed acyclic graph composed of combinational logics other than the clock tree, set the directed edges to the maximum delay. For example, Figure 4 in Figure 4 , set d = 1, then the part above d (i.e., the part marked as the dotted line) is set to the minimum delay, and the remaining part (i.e., the part marked as the solid line) is set to the maximum delay. For hold time, exchange the above maximum delay and minimum delay. For setup time propagation, define the delay extreme value of each directed acyclic graph node as the maximum possible delay among all paths ending at this node, and the second delay extreme value as the second largest possible delay except the above delay, and satisfy that the clock tree node corresponding to this delay and the source of the maximum possible delay belong to different group numbers; for hold time propagation, modify the above definition accordingly to the minimum delay. For example, Figure 4 in Figure 4 , there are two paths to reach node X, which are marked as p1 and p2 in the figure respectively. The specific path of p1 is from the root node CK to e, and then from e to X. The specific path of p2 is from the root node CK to d, and then from d to X. Therefore, the group number of the source of p1 is e, and the group number of the source of p2 is d. Calculate the cumulative delay from the clock tree root node to each node on the clock tree, that is, the delay of the clock tree node. Take the delay of the clock tree leaf node as the initial value (i.e., Figure 4 nodes a, b, c, d, and e in Figure 4 ), and complete the delay update on the directed acyclic graph according to the topological order to obtain the grouped delay information of each pin (such as X) in the circuit: including the delay extreme value, the group number of the clock tree node to which the delay extreme value belongs, and the second delay extreme value and the group number of the corresponding clock tree node. Take Figure 4 node X as an example. Assume that we are performing setup time propagation, d = 1, and the delay of path p1 is less than the delay of path p2. Then the delay information of node X is {{p1, e}, {p2, d}}.

[0043] C. Generation and Merging of Candidate Paths

[0044] Generate paths based on grouping constraints, where the paths include setup time violation paths and hold time violation paths, corresponding to the setup time propagation and hold time propagation in the calculation steps of grouping delay information based on clock tree depth enumeration respectively, and calculate on the corresponding delay information, specifically including initial path calculation and path iterative generation.

[0045] For each depth d, calculate the initial path of each register. For setup time propagation, calculate the earliest time constraint value of the register, that is, the sum of the minimum delays on the path from the clock tree root node to this register. As shown in the right half of Figure 5 which is represented by a dotted line, representing the path from the register back to the clock pin of the circuit design calculated according to the earliest time, that is, the earliest time constraint value. At the same time, assume d = 1, then the part of the clock net rooted tree above d = 1 in the left half takes the earliest time constraint value (dotted line), and the part below d = 1 and the directed acyclic graph of the combinational logic take the latest time constraint value (solid line); for hold time propagation, calculate the latest time constraint value of the register, that is, the sum of the maximum delays on the path from the clock tree root node to this register.

[0046] Traverse all registers, and calculate the path with the most serious timing violation ending at this register, that is, the path with the smallest slack value, as the initial path of this register through the time constraint value and delay information. As shown in Figure 5 the input pin of register a in which is marked as a' in the figure. Assume that the delay information of a' includes two paths p1 and p3 in the figure, and the group number of p3 is a, which is the same as the group number to which a' belongs, so it cannot be considered. Therefore, the path with the most serious timing violation ending at a' is p1, which is the initial path of register a.

[0047] Based on the initial paths of each register, perform iterative generation of paths. Put the initial paths of all registers into the priority queue. Take out the path with the smallest slack value from the priority queue, enumerate the incoming edges of each point on this path, and expand new paths through the incoming edges and add them to the priority queue; as shown in Figure 5 for register a in which, its initial path is p1. Enumerate node X on p1, enumerate the incoming edge Y->X of X, and expand the path CK->d->Y->X (that is, the path shown in bold label) through this incoming edge, and add this path to the priority queue. Repeat the above operation k times, and the k paths taken out are used as the result of path iterative generation, that is, the candidate paths of depth d.

[0048] Perform the merging of candidate paths. Among the k candidate paths generated for each depth d in the above steps, take out the starting and ending registers of the paths and calculate the lowest common ancestor (LCA) on the clock tree. Retain the paths with the lowest common ancestor depth of d and discard the remaining paths. Sort all the obtained paths in ascending order of the slack value, and take the first k paths as the final timing violation paths.

[0049] It should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art can understand that various substitutions and modifications are possible without departing from the scope of the present invention and the appended claims.

Claims

1. A path analysis method in static timing analysis of an integrated circuit, comprising the steps: circuit structure initialization, calculation based on grouped delay information enumerated by clock tree depth, and generation and merging of candidate paths; In the circuit structure initialization step, the clock netlist of the integrated circuit is represented as a rooted tree, called the clock tree; The combinational logic part of the integrated circuit is represented as a directed acyclic graph; among them, the root node of the clock tree represents the clock pin of the chip, the leaf nodes represent registers, and the edges of the clock tree represent the connection relationships between the nodes; the nodes in the directed acyclic graph represent the pins of the circuit, and the directed edges in the graph represent the connection relationships between the pins; in the directed acyclic graph and the clock tree, each edge is marked with the minimum and maximum propagation delays of the signal; In the step of calculating delay information based on clock tree depth enumeration, the nodes below the specified depth of the clock tree are grouped, and by designing a delay propagation algorithm based on grouping constraints, the grouped delay information of the nodes is calculated; In the candidate path generation and merging step, based on the grouped delay information of the nodes, for each depth of the clock tree, k candidate timing violation paths are iteratively generated in the priority queue, the candidate paths from different depths are screened and merged, and the first k paths with the smallest slack value are taken to obtain the result of path analysis, that is, the first k paths representing the most serious timing violations; Through the above steps, path analysis in the static timing analysis of the integrated circuit is realized, and paths supporting common path pessimistic elimination are obtained.

2. The path analysis method in static timing analysis of an integrated circuit according to claim 1, wherein, In the circuit structure initialization step, the structure of the directed acyclic graph of the combinational logic of the integrated circuit specifically starts from the clock pin of the register and ends at the input pin of the register.

3. The path analysis method in static timing analysis of an integrated circuit according to claim 1, wherein, The step of calculating grouped delay information based on clock tree depth enumeration includes: calculating the depth of each clock tree node and grouping the clock tree by depth; among them: The depth of the root node of the clock tree is 0, and the depth of the remaining nodes is the depth of their parent node plus 1; Grouping the clock tree by depth, each group obtained is a subtree; grouping the clock tree by depth d, the obtained subtree contains nodes with a depth greater than or equal to d + 1; Define the number of each group as the number of the root node of its subtree; define the group number of each node as the number of the group it belongs to.

4. The path analysis method in static timing analysis of an integrated circuit according to claim 3, wherein, The value of d ranges from 0 to the height of the clock tree; the height of the clock tree does not exceed 100.

5. The path analysis method in static timing analysis of an integrated circuit according to claim 1, wherein, Design a delay propagation algorithm based on grouping constraints, including setup time propagation and hold time propagation; For the clock tree and the directed acyclic graph of the combinational logic, set the actual delay of each edge; For setup time propagation, set the tree edges above depth d of the clock tree to the minimum delay, and the tree edges below depth d to the maximum delay; for the directed acyclic graph of the combinational logic, set the directed edges in it to the maximum delay; for hold time propagation, exchange the above maximum delay and minimum delay; For establishing time propagation, define the extreme delay of each directed acyclic graph node as the maximum possible delay among all paths ending at this node, and the second extreme delay as the second largest possible delay excluding the above-mentioned delay, and ensure that the clock tree node corresponding to this delay and the clock tree node of the maximum possible delay source belong to different group numbers; for hold time propagation, define the extreme delay of a node as the minimum possible delay among all paths ending at this node, and the second extreme delay as the second smallest possible delay excluding the above-mentioned delay, and ensure that the clock tree node corresponding to this delay and the clock tree node of the minimum possible delay source belong to different group numbers; Then calculate the cumulative delay from the clock tree root node to each node on the clock tree, that is, the delay of the clock tree node; Using the delay of the clock tree node as the initial value, complete the delay update on the directed acyclic graph according to the topological order to obtain the grouped delay information of each pin in the circuit, including: the extreme delay, the group number of the clock tree node to which the extreme delay belongs, as well as the second extreme delay and the group number of the corresponding clock tree node.

6. The path analysis method in static timing analysis of an integrated circuit according to claim 5, wherein, The steps of candidate path generation and merging include performing path generation based on grouped constraints, where the paths include setup time violation paths and hold time violation paths, corresponding to the setup time propagation and hold time propagation in the grouped delay information calculation steps based on clock tree depth enumeration respectively, and performing calculations on the corresponding delay information.

7. The path analysis method in static timing analysis of an integrated circuit according to claim 6, wherein, Performing calculations on the corresponding delay information specifically includes initial path calculation and path iterative generation; For each depth d, calculate the initial path of each register: for setup time propagation, calculate the earliest time constraint value of the register, that is, the sum of the minimum time delays on the path from the clock tree root node to this register; for hold time propagation, calculate the latest time constraint value of the register, that is, the sum of the maximum time delays on the path from the clock tree root node to this register; traverse all registers, and calculate the path with the most serious timing violation ending at this register, that is, the path with the smallest slack value, as the initial path of this register through the time constraint value and delay information; Based on the initial paths of each register, perform path iterative generation; put the initial paths of all registers into a priority queue; take out the path with the smallest slack value from the priority queue, enumerate the incoming edges of each point on this path, extend new paths through the incoming edges, and add them to the priority queue; repeat the above operations k times, and the k paths taken out are used as the result of path iterative generation, that is, the candidate paths for depth d.

8. The path analysis method in static timing analysis of an integrated circuit according to claim 5, wherein, The steps of candidate path generation and merging include performing candidate path merging: Specifically, among the k candidate paths generated for each depth d, take out the starting and ending registers of the path, and calculate the lowest common ancestor LCA on the clock tree, retain the paths with the lowest common ancestor depth of d and discard the remaining paths; Sort all the obtained paths in ascending order of slack value, and take the first k paths as the final timing violation paths, that is, complete the complete path analysis process, and the obtained paths are the path results after eliminating the pessimism of common paths.

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