Semiconductor memory device

Abstract

A semiconductor memory device is provided. The semiconductor memory device includes a temperature sensor, a plurality of memory blocks, and a refresh controller. The temperature sensor detects a device temperature inside the semiconductor memory device to generate a corresponding temperature signal. Each of the memory blocks includes a memory cell array having a plurality of volatile memory cells and a plurality of word lines. The refresh controller monitors accesses to the plurality of word lines, detects accesses occurring a prescribed number of times within a prescribed period, and assigns a refresh operation corresponding to a refresh operation command as a first refresh operation or a second refresh operation.

Description

Technical Field

[0001] This invention relates to an electronic device, and more particularly to a refresh control method for a semiconductor memory device having memory cells that require refresh operations to maintain data, and a semiconductor memory device suitable for this method. Background Technology

[0002] As manufacturing processes have become increasingly sophisticated, row hammering has become a significant issue in Dynamic Random Access Memory (DRAM) semiconductor memory devices. The hammer threshold, defined as the number of times an error occurs due to word line activation / deactivation, has fallen below 100,000 times in the 20nm generation. Without countermeasures within the DRAM itself or on the memory system side, maintaining normal operation becomes difficult.

[0003] As a circuit countermeasure in DRAM, row hammer refresh (RHR), which involves capturing frequently accessed row addresses (hammer addresses) and appending refresh operations to adjacent row addresses at an appropriate frequency, is widely used. There are generally two methods for capturing hammer addresses: one focuses on increasing the number of occurrences (access count), and the other focuses on the naturally increasing frequency of occurrence (probability of occurrence).

[0004] However, in order to maintain the necessary data retention characteristics, the refresh cycle is shortened, and the effective refresh period is also shortened. It is easy to increase the effect of row interference refresh at the same time, but this means that the amount of data refreshed in one refresh operation (the number of memory units) and the number of word lines enabled are further increased, that is, the refresh current (idd5) will increase significantly.

[0005] As a countermeasure to mitigate this issue, temperature-compensated refresh (TCR) is known to be used in recent mobile DRAMs (e.g., LPDDR4). As temperature decreases, the significant cell leakage factor is greatly reduced, thus allowing for extended refresh cycles. Furthermore, the control unit on the DRAM control side extends the automatic refresh command transmission interval by, for example, two or four times. This reduces refresh current in practical applications.

[0006] However, at low temperatures, the rate at which automatic refresh commands are assigned to row interference refreshes increases, making it difficult to balance row interference refreshes with other regular refreshes (CBR (CAS before RAS) refreshes) and increasing the risk of data retention.

[0007] Since entering the 1αnm generation, due to the significant reduction in hammer threshold, most refresh operations at low temperatures must be allocated to row interference refresh. In the temperature-compensated refresh used in mobile DRAM, it will be difficult to simultaneously maintain the data retention capability and reduce refresh current of the product in the future. Summary of the Invention

[0008] The present invention provides a semiconductor memory device that can appropriately adjust the execution cycle of CBR refresh and row interference refresh across all temperature ranges to obtain necessary and sufficient data retention capability and reduce power consumption.

[0009] A semiconductor memory device includes a temperature sensor, multiple memory blocks, and a refresh controller. The temperature sensor detects the internal temperature of the semiconductor memory device to generate a corresponding temperature signal. Each memory block includes an array of memory cells with multiple volatile memory cells and multiple word lines. The refresh controller monitors access to the multiple word lines, detects accesses occurring a predetermined number of times within a specified period, and assigns refresh operations corresponding to refresh operation commands as either a first refresh operation or a second refresh operation.

[0010] In one embodiment of the present invention, the first refresh operation is thinned out and enabled based on device temperature information, and the second refresh operation is thinned out and enabled based on word line access information. When the first refresh operation and the second refresh operation are in the same loop, and two internal refreshes cannot be performed in the same loop, the refresh controller controls the execution of one refresh operation in the loop and transfers the unexecuted refresh operation to the next loop for execution.

[0011] Based on the above, the semiconductor memory device of the present invention can generate a signal (first refresh signal) for performing CBR refresh operation and a signal (second refresh signal) for performing row interference refresh operation based on the refresh action signal. Furthermore, in the present invention, the execution cycle of CBR refresh (first refresh) and row interference refresh (second refresh) can be appropriately diluted and adjusted, provided that necessary and sufficient refresh opportunities are provided across all temperature ranges. This ensures both data retention capability and power consumption reduction. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of a semiconductor memory device according to an embodiment of the present invention;

[0013] Figure 2 This is a schematic diagram of a memory block according to an embodiment of the present invention;

[0014] Figure 3 This is a circuit diagram of a refresh controller according to an embodiment of the present invention;

[0015] Figures 4A to 4C This is a waveform diagram of a refresh operation of a semiconductor memory device according to an embodiment of the present invention;

[0016] Figures 5A to 5C This is a waveform diagram of a refresh operation of a semiconductor memory device according to an embodiment of the present invention;

[0017] Figure 6 This is a circuit diagram of a refresh controller according to an embodiment of the present invention;

[0018] Figures 7A to 7C This is a waveform diagram of a refresh operation of a semiconductor memory device according to an embodiment of the present invention;

[0019] Figure 8 This is a circuit diagram of an RHR state control circuit according to an embodiment of the present invention;

[0020] Figure 9 This is a schematic diagram of a semiconductor memory device according to an embodiment of the present invention;

[0021] Figure 10 This is a schematic diagram of a memory block according to an embodiment of the present invention;

[0022] Figure 11A This is a schematic diagram of a CBR thinning circuit according to an embodiment of the present invention;

[0023] Figure 11B This is an example of the operating waveform of a CBR thinning circuit according to an embodiment of the present invention;

[0024] Figure 12A This is a schematic diagram of an RHRSLOT generation circuit according to an embodiment of the present invention;

[0025] Figure 12B This is an example of the operating waveform of the RHRSLOT generation circuit according to an embodiment of the present invention;

[0026] Figure 13A This is a schematic diagram of an RHR thinning circuit according to an embodiment of the present invention;

[0027] Figure 13B This is an example of the operating waveform of an RHR thinning circuit according to an embodiment of the present invention;

[0028] Figure 14 This is a schematic diagram of an RHR state control circuit according to an embodiment of the present invention;

[0029] Figure 15A This is a schematic diagram of an RHR thinning circuit according to an embodiment of the present invention;

[0030] Figure 15B This is an example of the operating waveform of an RHR thinning circuit according to an embodiment of the present invention;

[0031] Figure 16A This is a schematic diagram of an ACK clock generator according to an embodiment of the present invention;

[0032] Figure 16B This is an example of the operating waveform of an ACK clock generator according to an embodiment of the present invention. Detailed Implementation

[0033] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0034] Please refer to the following: Figure 1 , Figure 1 This is a schematic diagram of a semiconductor memory device 100 according to an embodiment of the present invention. The semiconductor memory device 100 includes a temperature sensor 110, a mode register and an OTP block 120, a refresh controller 130, memory blocks 140_1 to 140_N, and a command decoder 150. N is a positive integer greater than 1. In this embodiment, a structure is adopted in which a single refresh controller 130 controls the refresh operations of all memory blocks 140_1 to 140_N.

[0035] Temperature sensor 110 is, for example, any type of sensing component / circuit with temperature detection function. Temperature sensor 110 is used to detect the device temperature inside semiconductor memory device 110 to generate a corresponding temperature signal TS.

[0036] The mode register and OTP (One-Time Programmable memory) block 120 is, for example, a circuit composed of multiple anti-fuses and a register group called the mode register. The multiple anti-fuses store various operation setting information, such as the burst length (BL) and CAS latency (CL) related to read operation specifications, or the first refresh setting information TMRS and the second refresh setting information TMRHR related to the present invention. When the chip starts up, the various operation setting information pre-written to the anti-fuses is loaded into the mode register, and the setting information stored in each mode register is provided to the respective circuits in the chip. Furthermore, after the chip starts up, the operation setting information stored in the mode register can be reset via the MRS (Mode Register Set) command, based on the MRS signal generated from the command decoder 150 and the encoded information externally input from the address input buffer 161.

[0037] The refresh controller 130 receives first refresh setting information TMRS and second refresh setting information TMRHR from the mode register and OTP block 120, and receives a temperature signal TS from the temperature sensor 110 to determine the operating specifications related to refresh control. Furthermore, it can output a first refresh signal CBRSLOT and a second refresh signal RHRSLOT based on the refresh action signal RFIP. The refresh action signal RFIP is a pulse signal generated by the command decoder 150 when an external command signal COM indicates a refresh command. The refresh controller 130 can adjust the output interval of the first refresh signal CBRSLOT based on the first refresh setting information TMRS and the temperature signal TS, and adjust the output interval of the second refresh signal RHRSLOT based on the second refresh setting information TMRHR and the temperature signal TS. Furthermore, the refresh controller 130 can generate a CBR refresh address RFA based on the adjusted first refresh signal CBRSLOT and second refresh signal RHRSLOT. The first refresh setting information TMRS, for example, represents the level information of the CBR refresh skip rate. By combining it with the temperature information TS, it determines the activation rate of the first refresh signal CBRSLOT and achieves temperature compensation for the refresh cycle. The second refresh setting information TMRHR includes, for example, refresh interruption rate and setting information for row hammer refresh. The refresh interruption rate, for example, represents the proportion of time the logic level of the second refresh signal RHRSLOT changes corresponding to an interruption of the second clock RHRCLK. Memory blocks 140_1 to 140_N are coupled to refresh controller 130. Memory blocks 140_1 to 140_N can respond to the execution of a first refresh operation by the first refresh signal CBRSLOT, and can also respond to the execution of a second refresh operation by the second refresh signal RHRSLOT. The first refresh operation is, for example, a refresh operation for performing CBR (CAS before RAS) refresh, and the second refresh operation is, for example, a refresh operation for performing row hammer refresh (RHR). In this embodiment, the first refresh signal CBRSLOT can indicate the time period for performing CBR refresh, and the second refresh signal RHRSLOT can indicate the time period for performing row hammer refresh.

[0038] like Figure 1As shown, the semiconductor memory device 100 also includes an address multiplexer 152, a column address counter and latch 154, a memory storage address control logic 156, an address input buffer 161, an address decoder 162, a command input buffer 163, a clock input buffer 164, an internal clock generator 165, an internal power supply circuit 166, a DQ input / output buffer 167, an address terminal 171, a command terminal 172, a clock terminal 173, a data terminal 174, a data mask terminal 175, a power supply terminal 176, a power supply terminal 177, and a GIO and a GIO gate 180.

[0039] Address terminal 171 is the terminal for receiving the address signal ADD from an external source. The address signal ADD can be provided to the address decoder 162 via the address input buffer 161. After decoding, the address decoder 162 can provide the data address XADD to the address multiplexer 152, the column address YADD to the column address counter and latch 154, and the block address BA to the repository address control logic 156 based on the address signal ADD.

[0040] Command terminal 172 is a terminal for receiving the command signal COM from an external source. The command signal COM can be provided to the command decoder 150 via command input buffer 163. The command decoder 150 is a circuit that generates various internal commands by decoding the command signal COM. Internal commands include, for example, the active signal ACT, the precharge signal PREC, the read signal RD, the write signal WT, and the refresh action signal RFIP. The active signal ACT is a pulse signal (active command) enabled when the command signal COM indicates column access. When the active signal ACT is enabled, the row decoder for the specified memory block address is enabled. The precharge signal PREC is a pulse signal enabled when the command signal COM indicates precharge. When the precharge signal PREC is enabled, the row decoder for the specified memory block and the word line specified by the row address controlled by this row decoder are disabled. Furthermore, when the command signal COM indicates an automatic refresh command, the command decoder 150 can enable the refresh action signal RFIP.

[0041] Address multiplexer 152 is coupled to refresh controller 130, command decoder 150, and address decoder 162. Address multiplexer 152 receives the CBR refresh address RFA and data address XADD, and selects either the CBR refresh address RFA or the data address XADD as the first row address XADD1 for output based on the refresh action signal RFIP. For example, when the refresh action signal RFIP is disabled, indicating a normal read or write operation, address multiplexer 152 provides the data address XADD (external input address) as the first row address XADD1. When the refresh action signal RFIP is enabled, indicating a row interference operation or CBR refresh operation, address multiplexer 152 provides the data address XADD (external input address) as the first row address XADD1.

[0042] The column address counter and latch 154 provides column address YADD1 based on column address YADD. The repository address control logic 156 provides block selection signals BS_1 to BS_N based on block address BA.

[0043] Clock terminal 173 is used to input external clock signals CK and CKB. The external clock signals CK and CKB are complementary signals and are both provided to clock input buffer 164. Clock input buffer 164 generates an internal clock signal ICLK based on the external clock signals CK and CKB and controlled by the clock enable signal CKE from command input buffer 163, and provides the internal clock signal ICLK to command decoder 150 and internal clock generator 165. Internal clock generator 165 can generate an internal clock signal LCLK based on the internal clock signal ICLK to control the operating timing of DQ input / output buffer 167.

[0044] The GIO and GIO gate 180 are coupled to the DQ input / output buffer 167 and connected to memory blocks 140_1 to 140_N via multiple main input / output lines (MIO). The GIO and GIO gate 180 are used to read data from a specified memory block into the DQ input / output buffer 167 during a read operation and to write data from the DQ input / output buffer 167 into a specified memory block during a write operation.

[0045] Data terminal 174 is used to transmit input / output data DQ. Data shield terminal 175 is used to receive the data shield signal DM. When the data shield signal DM is enabled, the overwriting of the corresponding data is prohibited. Power supply terminal 176 receives the power supply voltages VDD and VSS and provides the power supply voltages VDD and VSS to the internal power supply circuit 166. The internal power supply circuit 166 generates various internal potentials VPP, VBB, VBLH, VOD, VINT, etc., based on the power supply voltages VDD and VSS.

[0046] Power supply terminal 177 is used to receive power supply voltages VDDQ and VSSQ, and to supply power supply voltages VDDQ and VSSQ to input / output circuit 167. Power supply voltages VDDQ and VSSQ are the same potentials as the power supply voltages VDD and VSS supplied to power supply terminal 176, respectively. However, dedicated power supply potentials VDDQ and VSSQ are used for input / output circuit 167 to prevent power supply noise generated by input / output circuit 167 from propagating to other circuit blocks.

[0047] Command decoder 150 is coupled to refresh controller 130. Upon receiving a command signal COM indicating a refresh command, command decoder 150 can begin generating refresh action signal RFIP. Command decoder 150 can also transmit mode signal MRS to mode register and OTP block 120 according to command signal COM. The mode register, OTP block 120, and command decoder 150 can all be implemented using logic circuits well-known to those skilled in the art in the field of integrated circuits.

[0048] The following example illustrates the detailed structure of the memory block in this embodiment. Figure 2 This is a schematic diagram of a memory block 140_i according to an embodiment of the present invention. Figure 2 As shown, memory block 140_i includes OR gate 210, AND gate 220, AND gate 230, Row Hammer Address (RHA) detection circuit 240, address multiplexer 250, row decoder and memory block control 260, column decoder 270, LIO gate control and DM control logic 272, sensor amplifier 274, word driver 280, and memory cell array 290. In this embodiment, i is a positive integer, and 1 ≤ i ≤ N.

[0049] The first input of OR gate 210 is coupled to the first refresh signal CBRSLOT, and the second input of OR gate 210 is coupled to the second refresh signal RHRSLOT. The first input of AND gate 220 receives the refresh action signal RFIP, and the second input of AND gate 220 is coupled to the output of OR gate 210. The output of AND gate 220 generates a valid refresh signal RFEXE. The valid refresh signal RFEXE indicates that an automatic refresh operation has actually been performed, which includes CBR refresh and line interference refresh.

[0050] The first input of AND gate 230 is coupled to the refresh action signal RFIP, and the second input of AND gate 230 is coupled to the second refresh signal RHRSLOT. The output of AND gate 230 generates an enabled (high logic level) row interference signal RHR when both the refresh action signal RFIP and the second refresh signal RHRSLOT are enabled (high logic level).

[0051] RHA detection circuit 240 is coupled to the output of AND gate 230. RHA detection circuit 240 analyzes the second row address XADD2 in response to the in-process signal ACT, the precharge signal PREC, and the row interference signal RHR to generate the row interference refresh address RHA. Specifically, RHA detection circuit 240 monitors memory cell access operations at the current second row address XADD2 and detects accesses occurring more than or equal to a predetermined number of times within a specified period. If the second row address XADD2 experiences more than or equal to the predetermined number of accesses, the address adjacent to the second row address XADD2 is calculated as the row interference refresh address RHA.

[0052] It should be noted that the number of accesses to the word line can be obtained by counting the number of times the active signal ACT is enabled. The row interference refresh address (RHA) is the address used for row interference refresh. In the RHA detection circuit 240, the calculation method of the row interference refresh address RHA can be implemented using the memory circuit architecture well known to those skilled in the art in the field of integrated circuits.

[0053] The first input of the address multiplexer 250 receives the first row address XADD1 from the address multiplexer 152, and the second input of the address multiplexer 250 receives the row interference refresh address RHA. Based on the row interference signal RHR, the first row address XADD1 or the row interference refresh address RHA is selected as the second row address XADD2 for output.

[0054] The row decoder and memory block control 260 is coupled to the RHA detection circuit 240 and the address multiplexer 250. The row decoder and memory block control 260 can be driven by the active signal ACT and the precharge signal PREC, and latches the second row address XADD2 as the block access address BADD for output based on the valid refresh signal RFEXE.

[0055] Please refer to Figure 2 When the row interference signal RHR is equal to a low logic level, it indicates that it is not a row interference refresh operation, and the address multiplexer 250 will provide information from... Figure 1 The first row address XADD1 of the address multiplexer 152 is used as the second row address XADD2. When the row interference signal RHR is at a high logic level, it indicates that a row interference refresh operation is in progress, and the address multiplexer 250 will use the row interference refresh address RHA as the second row address XADD2.

[0056] like Figure 2 In the circuit configuration shown, when the first refresh signal CBRSLOT and the second refresh signal RHRSLOT are output simultaneously, memory block 140_i can perform either the first refresh operation or the second refresh operation, and execute the unperformed operation in the next refresh cycle. For example, when the second refresh signal RHRSLOT is output, regardless of whether the first refresh signal CBRSLOT is also output simultaneously, the row interference signal RHR output via AND gate 230 will cause address multiplexer 250 to select the row interference refresh address RHA as the second row address XADD2 for output, in order to perform the second refresh operation. Furthermore, the unperformed first refresh operation is executed in the next refresh cycle.

[0057] The memory cell array 290 has multiple word lines WL and multiple bit lines BL, and has a configuration in which memory cells MC are located at the intersection of word lines WL and bit lines BL. Figure 2 The memory cell array 290 shows one of the structures consisting of word lines WL, bit lines BL, and memory cells MC. In this embodiment, the selection of word lines WL is implemented by the row decoder and memory block control 260, and the selection of bit lines BL is implemented by the column decoder 270.

[0058] The word driver 280 is used to drive a specified word line WL, and the sensing amplifier 274 reads data from a specified memory cell MC or writes data to a specified memory cell MC via the bit line BL.

[0059] The LIO gate control and DM control logic 272 is connected to the sensor amplifier 274 via the secondary input / output line LIO. The LIO gate control and DM control logic 272 can access a specified memory cell MC via the sensor amplifier 274 based on the decoding result of the column decoder 270. Specifically, the sensor amplifier 274 can receive stored data from the memory cell MC via the bit line BL, sense the stored data according to the sensing start signal SAEn to obtain read data, and transmit the read data to the main input / output line MIO. The sensor amplifier 274 can also receive write data on the main input / output line MIO, sense the write data according to the sensing start signal SAEn, and write the sensing result to the memory cell MC via the bit line BL. In this embodiment, the RHA detection circuit 240 can also analyze the spare row address XRED and calculate the row interference refresh address RHA.

[0060] The following is a detailed description of the structure of the refresh controller in this embodiment. Figure 3 This is a circuit diagram of a refresh controller 300 according to an embodiment of the present invention. Figure 3 As shown, the refresh controller 300 includes a CBR thinning circuit 310, an RHR state control circuit 320, and a CBR counter 330.

[0061] The CBR thinning circuit 310 can output a first refresh signal CBRSLOT based on the first clock CBRCLK, and adjust the output interval of the first refresh signal CBRSLOT according to the temperature signal TS2, the first refresh setting information TMRS and the CBR refresh address RFA.

[0062] The RHR state control circuit 320 is coupled to the CBR thinning circuit 310. The RHR state control circuit 320 can output a second refresh signal RHRSLOT based on the second clock RHRCLK, and adjust the output interval of the second refresh signal RHRSLOT according to the temperature signal TS2 and the second refresh setting information TMRHR.

[0063] The CBR counter 330 is, for example, any type of counting component / circuit with counting functionality. The CBR counter 330 is coupled to the CBR thinning circuit 310 and the RHR state control circuit 320. The CBR counter 330 counts the number of times the first refresh operation is performed based on the counting signal CBRCNT to generate the CBR refresh address RFA.

[0064] exist Figure 3In this circuit, the CBR thinning circuit 310, the RHR state control circuit 320, and the CBR counter 330 are connected via a buffer gate 340, an AND gate 350, a multiplexer 360, an inverter 370, and an AND gate 380, respectively. The flip-flop 390 is used to respond to the inverted first refresh signal CBRSLOT and provide a temperature signal TS2 based on the temperature signal TS.

[0065] like Figure 3 As shown, the input of buffer gate 340 is coupled to the refresh action signal RFIP, and the output of buffer gate 340 can generate the first clock CBRCLK. The first input of AND gate 350 is coupled to the output of buffer gate 340, the second input of AND gate 350 receives the first refresh signal CBRSLOT, and generates a counting signal CBRCNTP at the output of AND gate 350.

[0066] The first terminal of multiplexer 360 is coupled to the refresh action signal RFIP, and the second terminal of multiplexer 360 receives the counting signal CBRCNTP. Based on the mode switching signal SW, it selects either the refresh action signal RFIP or the counting signal CBRCNTP as the second clock RHRCLK for output. The input terminal of inverter 370 is coupled to the second refresh signal RHRSLOT. The first input terminal of AND gate 380 is coupled to the output terminal of inverter 370, and the second input terminal of AND gate 380 is coupled to the counting signal CBRCNTP. The output terminal of AND gate 380 outputs the counting signal CBRCNT to CBR counter 330. The following describes this invention... Figure 3 The operating principle of the refresh controller 300 shown will be further explained.

[0067] The refresh controller 300 can receive the refresh action signal RFIP provided by the command decoder 150 when the command signal COM indicating the refresh command is generated. The refresh action signal RFIP is passed through the buffer gate 340 as the first clock CBRCLK and provided to the CBR thinning circuit 310 and AND gate 350.

[0068] The CBR thinning circuit 310 can generate a first refresh signal CBRSLOT based on the first clock CBRCLK according to the temperature signal TS2 and the first refresh setting information TMRS.

[0069] AND gate 350 is used to control the first clock CBRCLK. When the first refresh signal CBRSLOT is 1 (high logic level), the first clock CBRCLK is output as the counting signal CBRCNTP and sent to AND gate 380. When the second refresh signal RHRSLOT is 0 (low logic level), the counting signal CBRCNT will be equal to the first clock CBRCLK and provided to the next stage CBR counter 330 as the basis for performing the counting action.

[0070] When the second refresh signal RHRSLOT is 1 (high logic level), the CBR refresh operation is disabled, and a line interference refresh operation is performed instead. Simultaneously, the counter signal CBRCNT remains at 0 (low logic level), and the CBR counter 330 stops counting, corresponding to the CBR refresh being disabled. In other words, the CBR counter 330 counts the number of CBR refreshes to generate the CBR refresh address RFA.

[0071] On the other hand, the refresh action signal RFIP and the counting signal CBRCNTP are provided to the multiplexer 360. The multiplexer 360 selects either the refresh action signal RFIP or the counting signal CBRCNTP as the second clock RHRCLK to drive the next-stage RHR state control circuit 320 based on the mode switching signal SW. The RHR state control circuit 320 is the circuit used to generate the second refresh signal RHRSLOT.

[0072] The RHR state control circuit 320 can generate a second refresh signal RHRSLOT based on the second clock RHRCLK according to the temperature signal TS2 and the second refresh setting information TMRHR.

[0073] It is worth mentioning that, although the purposes of CBR refresh and line interference refresh are different in this embodiment, the first refresh signal CBRSLOT used for CBR refresh and the second refresh signal RHRSLOT used for line interference refresh are both generated based on the refresh action signal RFIP. However, as Figure 3 As shown, the multiplexer 360 can select either the refresh action signal RFIP or the count signal CBRCNTP as the second clock RHRCLK based on the mode switching signal SW.

[0074] The mode switching signal SW can be provided, for example, by the command decoder 150. When the mode switching signal SW is at a low logic level (mode A), the multiplexer 360 outputs the counting signal CBRCNTP as the second clock RHRCLK. In mode A, due to the action of the AND gate 350, the second clock RHRCLK is also adjusted along with the temperature signal TS2 (corresponding to the adjustment of the first refresh signal CBRSLOT by the CBR thinning circuit 310 based on the temperature signal TS2).

[0075] Since the refresh skip rate of the CBR thinning circuit 310 increases as the temperature decreases, in order to prevent the second refresh signal RHRSLOT from being affected by temperature, the RHR state control circuit 320 should also adjust the refresh interrupt rate to a higher value according to the temperature signal TS2.

[0076] Figures 4A to 4CThis is a waveform diagram illustrating the refresh operation of a semiconductor memory device according to an embodiment of the present invention. Please also refer to... Figure 3 and Figures 4A to 4C The refresh operation is explained when the mode switching signal SW is at a low logic level (mode A).

[0077] Figure 4A This describes the signal waveform of the refresh interval tREFI in the first refresh operation (CBR refresh) when it is a multiple of 1x. The multiple of the refresh interval tREFI is determined by the CBR thinning circuit 310 based on the temperature signal TS2 and the first refresh setting information TMRS. Here, x can be any integer, for example, as long as the change in the CBR refresh address RFA can be observed.

[0078] exist Figure 4A In this case, the CBR thinning circuit 310 will not skip any of the first clock CBRCLK, and the refresh interval tREFI of the first refresh operation will be equal to the interval of the refresh action signal RFIP. Therefore, the waveform of the effective refresh signal RFEXE is equal to that of the refresh action signal RFIP.

[0079] When the refresh action signal RFIP pulse P40 occurs, the RHR state control circuit 320 generates the first second refresh signal RHRSLOT. Due to the action of inverter 370 and AND gate 380, the CBR counter 330 pauses counting, causing the CBR refresh address RFA to remain at X-7. Simultaneously, the memory block performs a second refresh operation. Subsequently, when the refresh action signal RFIP pulse P41 occurs, the RHR state control circuit 320 generates a second second refresh signal RHRSLOT.

[0080] Figure 4B This describes the signal waveform where the refresh interval tREFI of the first refresh operation (CBR refresh) is a multiple of 2x.

[0081] exist Figure 4B In this case, the CBR thinning circuit 310 can skip half of the first clock CBRCLK, and the refresh interval tREFI of the first refresh operation will be equal to twice the interval of the refresh action signal RFIP.

[0082] During the refresh action signal RFIP pulse P40, the first refresh signal CBRSLOT and the second refresh signal RHRSLOT conflict (occur simultaneously). When the conflict occurs, the refresh controller 300 does not extend or adjust the high logic level time of the first refresh signal CBRSLOT or the second refresh signal RHRSLOT. Therefore, the memory block will prioritize the second refresh operation and skip the first refresh operation. Due to the action of the inverter 370 and AND gate 380, the CBR counter 330 will pause counting at this time, causing the CBR refresh address RFA to remain at X-3. Subsequently, during the refresh action signal RFIP pulse P42, the first refresh signal CBRSLOT and the second refresh signal RHRSLOT conflict again, and the CBR counter 330 pauses counting again.

[0083] Figure 4C This describes the signal waveform where the refresh interval tREFI is a multiple of 4x during the first refresh operation (CBR refresh). Figure 4C In this case, the CBR thinning circuit 310 can skip three-quarters of the first clock CBRCLK, and the refresh interval tREFI of the first refresh operation will be equal to four times the interval of the refresh action signal RFIP.

[0084] During the refresh action signal RFIP pulse P40, the first refresh signal CBRSLOT and the first second refresh signal RHRSLOT conflict. When this conflict occurs, the refresh controller 300 does not extend or adjust the high logic level time of the first refresh signal CBRSLOT or the second refresh signal RHRSLOT. Therefore, the memory block will prioritize the second refresh operation and skip the first refresh operation. Due to the action of the inverter 370 and AND gate 380, the CBR counter 330 will pause counting at this time, causing the CBR refresh address RFA to remain at X-1. Subsequently, during the refresh action signal RFIP pulse P43, the first refresh signal CBRSLOT and the second second refresh signal RHRSLOT conflict again, and the CBR counter 330 will pause counting again.

[0085] Please return Figure 3 When the mode switching signal SW is at a high logic level (mode B), the multiplexer 360 will directly output the refresh action signal RFIP as the second clock RHRCLK.

[0086] Figures 5A to 5C This is a waveform diagram illustrating the refresh operation of a semiconductor memory device according to an embodiment of the present invention. Please also refer to... Figure 3 and Figures 5A to 5C The refresh operation is explained when the mode switching signal SW is at a high logic level (mode B).

[0087] Figure 5A This describes the signal waveform where the refresh interval tREFI, a multiple of 1x, is used in the first refresh operation (CBR refresh). Figure 5A In this case, the CBR thinning circuit 310 will not skip any of the first clock CBRCLK, and the refresh interval tREFI of the first refresh operation will be equal to the interval of the refresh action signal RFIP. Therefore, the waveform of the effective refresh signal RFEXE is equal to that of the refresh action signal RFIP.

[0088] When the refresh action signal RFIP pulse P50 occurs, the RHR state control circuit 320 generates the first second refresh signal RHRSLOT. Due to the action of inverter 370 and AND gate 380, the CBR counter 330 pauses counting, causing the CBR refresh address RFA to remain at X-7. Simultaneously, the memory block performs a second refresh operation. Subsequently, when the refresh action signal RFIP pulse P51 occurs, the RHR state control circuit 320 generates a second second refresh signal RHRSLOT.

[0089] Figure 5B This describes the signal waveform where the refresh interval tREFI is a multiple of 2x during the first refresh operation (CBR refresh). Figure 5B In this case, the CBR thinning circuit 310 can skip half of the first clock CBRCLK, and the refresh interval tREFI of the first refresh operation will be equal to twice the interval of the refresh action signal RFIP.

[0090] During the refresh action signal RFIP pulse P50, the first refresh signal CBRSLOT and the second refresh signal RHRSLOT will conflict. When the conflict occurs, the refresh controller 300 does not extend or adjust the time when the first refresh signal CBRSLOT or the second refresh signal RHRSLOT is at a high logic level. Therefore, the memory block will prioritize the second refresh operation and skip the first refresh operation. Due to the action of the inverter 370 and AND gate 380, the CBR counter 330 will pause counting at this time, causing the CBR refresh address RFA to remain at X-3.

[0091] and Figure 4B Unlike other cases, the second clock RHRCLK does not need to depend on the first refresh signal CBRSLOT. Therefore, when the refresh action signal RFIP pulse P51 occurs, the first refresh signal CBRSLOT and the second refresh signal RHRSLOT will not conflict.

[0092] Figure 5C This describes the signal waveform where the refresh interval tREFI is a multiple of 4x during the first refresh operation (CBR refresh). Figure 5CIn this case, the CBR thinning circuit 310 can skip three-quarters of the first clock CBRCLK, and the refresh interval tREFI of the first refresh operation will be equal to four times the interval of the refresh action signal RFIP.

[0093] During the refresh action signal RFIP pulse P50, the first refresh signal CBRSLOT and the second refresh signal RHRSLOT will conflict. For example... Figure 5C As shown, when a conflict occurs, the refresh controller 300 does not extend or adjust the time when the first refresh signal CBRSLOT or the second refresh signal RHRSLOT is at a high logic level. Therefore, the memory block will prioritize the second refresh operation and skip the first refresh operation. Due to the action of the inverter 370 and the AND gate 380, the CBR counter 330 will pause counting at this time, causing the CBR refresh address RFA to remain at X-1.

[0094] and Figure 4C Unlike other cases, the second clock RHRCLK does not need to depend on the first refresh signal CBRSLOT. Therefore, when the refresh action signal RFIP pulse P51 occurs, the first refresh signal CBRSLOT and the second refresh signal RHRSLOT will not conflict.

[0095] Please return Figure 3 ,exist Figure 3 In the embodiments described, proper control is not possible when both the first refresh signal CBRSLOT and the second refresh signal RHRSLOT are generated simultaneously. When the mode switching signal SW is low (mode A), the multiplexer 360 provides the counting signal CBRCNTP associated with the first clock CBRCLK to the RHR state control circuit 320 as the second clock RHRCLK. Therefore, the second refresh operation is limited to the opportunities previously available for the first refresh operation, making it impossible to achieve a high-frequency second refresh operation at low temperatures. When the mode switching signal SW is high (mode B), the contention problem is resolved by prioritizing the second refresh operation, but this reduces the opportunities for the first refresh operation, leading to data loss. The following... Figure 6 A circuit that improves upon the aforementioned shortcomings is shown.

[0096] Figure 6 This is a circuit diagram of a refresh controller 400 according to an embodiment of the present invention. The operation modes of the CBR thinning circuit 410, RHR state control circuit 420 and CBR counter 430 are the same as or similar to those of the aforementioned CBR thinning circuit 310, RHR state control circuit 320 and CBR counter 330, so their operation modes will not be described again here.

[0097] Unlike the previous embodiments, in this embodiment, the CBR thinning circuit 410, the RHR state control circuit 420, and the CBR counter 430 are connected via a buffer gate 440, an AND gate 450, an AND gate 460, and a NAND gate 470, respectively. The input of the buffer gate 440 is coupled to the refresh action signal RFIP, and the output of the buffer gate 440 generates a second clock RHRCLK.

[0098] AND gate 450's first input is coupled to the refresh action signal RFIP, and its output generates a first clock signal CBRCLK. AND gate 460's first input is coupled to the first clock signal CBRCLK, its second input is coupled to the first refresh signal CBRSLOT, and its output generates a counting signal CBRCNT. NAND gate 470's first input is coupled to the second refresh signal RHRSLOT, its second input is coupled to the first refresh signal CBRSLOT, and its output is coupled to the second input of AND gate 450. A flip-flop 480 reacts to the inverted first refresh signal CBRSLOT to provide a temperature signal TS2 based on the temperature signal TS.

[0099] in accordance with Figure 6 The circuit configuration shown not only ensures that the second refresh operation is not limited to the original opportunities of the first refresh operation, but also does not reduce the opportunities of the first refresh operation, thus improving the shortcomings of the above embodiments.

[0100] Figures 7A to 7C This is a waveform diagram illustrating the refresh operation of a semiconductor memory device according to an embodiment of the present invention. Please also refer to... Figure 6 and Figures 7A to 7C The refresh operation of this embodiment will be explained.

[0101] Figure 7A This describes the signal waveform where the refresh interval tREFI, a multiple of 1x, is used in the first refresh operation (CBR refresh). Figure 7A In this case, the CBR thinning circuit 410 will not skip any of the first clock CBRCLK, and the refresh interval tREFI of the first refresh operation will be equal to the interval of the refresh action signal RFIP. Therefore, the waveform of the effective refresh pulse RFEXE is equal to that of the refresh action signal RFIP.

[0102] When the refresh action signal RFIP pulse P70 occurs, the RHR state control circuit 420 generates the first second refresh signal RHRSLOT. Due to the actions of NAND gates 470, AND gates 450 and 460, the CBR counter 430 pauses counting, causing the CBR refresh address RFA to remain at X-7. Subsequently, when the refresh action signal RFIP pulse P71 occurs, the RHR state control circuit 420 generates a second second refresh signal RHRSLOT.

[0103] Figure 7B This describes the signal waveform where the refresh interval tREFI is a multiple of 2x during the first refresh operation (CBR refresh). Figure 7B In this case, the CBR thinning circuit 410 can skip half of the first clock CBRCLK, and the refresh interval tREFI of the first refresh operation will be equal to twice the interval of the refresh action signal RFIP.

[0104] exist Figure 7B During the refresh operation, when pulse P70 of the RFIP signal is applied, the first refresh signal CBRSLOT and the first second refresh signal RHRSLOT will conflict. Due to the actions of NAND gates 470, AND gates 450 and 460, the CBR counter 430 will pause counting, causing the CBR refresh address RFA to remain at X-3. Simultaneously, the memory block will perform a second refresh operation.

[0105] However, when a conflict occurs, the refresh controller 400 extends the time during which the first refresh signal CBRSLOT is high, allowing it to execute the first refresh operation at the time of the next refresh action signal RFIP. Therefore, the opportunity for the first refresh operation is not reduced.

[0106] Similarly, when the refresh action signal RFIP pulse P71 occurs, the refresh controller 400 also extends the time when the first refresh signal CBRSLOT is at a high logic level, so that it can perform the first refresh operation at the time of the next refresh action signal RFIP.

[0107] Figure 7C This describes the signal waveform where the refresh interval tREFI is a multiple of 4x during the first refresh operation (CBR refresh). Figure 7C In this case, the CBR thinning circuit 410 can skip three-quarters of the first clock CBRCLK, and the refresh interval tREFI of the first refresh operation will be equal to four times the interval of the refresh action signal RFIP.

[0108] During the refresh action signal RFIP pulse P70, the first refresh signal CBRSLOT and the first second refresh signal RHRSLOT will conflict. Due to the actions of NAND gates 470, AND gate 450, and AND gate 460, the CBR counter 430 will pause counting, causing the CBR refresh address RFA to remain at X-1. Simultaneously, the memory block will perform a second refresh operation.

[0109] However, when conflict arises, such as Figure 7C As shown, the refresh controller 400 extends the time during which the first refresh signal CBRSLOT is high, enabling it to execute the first refresh operation at the time of the next refresh action signal RFIP. Therefore, the opportunity for the first refresh operation is not reduced.

[0110] Similarly, when the refresh action signal RFIP pulse P71 occurs, the refresh controller 400 also extends the time when the first refresh signal CBRSLOT is at a high logic level, so that it can perform the first refresh operation at the time of the next refresh action signal RFIP.

[0111] It should be noted that, in one embodiment, the RHR state control circuit can also adjust the output interval of the second refresh signal RHRSLOT based on the number of word line accesses. For example, Figure 8 This is a circuit diagram of an RHR state control circuit 500 according to an embodiment of the present invention. The RHR thinning circuit 510 can generate a third clock RHRCLKD based on a second clock RHRCLK, a second refresh signal RHRSLOT, and the active signal ACT corresponding to each memory block 140_1 to 140_N. The RHR thinning circuit 510 can count the active signals ACT of each memory block 140_1 to 140_N to obtain the number of word line accesses.

[0112] The RHRSLOT generation circuit 520 is coupled to the RHR thinning circuit 510. The RHRSLOT generation circuit 520 can generate a second refresh signal RHRSLOT based on a third clock RHRCLKD, and adjust the output interval of the second refresh signal RHRSLOT according to the temperature signal TS2 and the second refresh setting information TMRHR.

[0113] It should be noted that, in one embodiment, a corresponding refresh controller can also be configured for each memory block. To enable those skilled in the art to better understand the present invention, another embodiment will be described in detail below.

[0114] Figure 9This is a schematic diagram of a semiconductor memory device 600 according to an embodiment of the present invention. The semiconductor memory device 600 includes a temperature sensor 610, a mode register and an OTP block 620, memory blocks 640_1 to 640_N, and a command decoder 650. In this embodiment, a structure is adopted in which each memory block 640_1 to 640_N has a refresh controller for control.

[0115] The operation modes of the temperature sensor 610, mode register and OTP block 620, column address counter and latch 654, storage address control logic 656, address input buffer 661, address decoder 662, command input buffer 663, clock input buffer 664, internal clock generator 665, internal power supply circuit 666, DQ input / output buffer 667, address terminal 671, command terminal 672, clock terminal 673, data terminal 674, data shield terminal 675, power supply terminal 676, power supply terminal 677, and GIO and GIO gate 680 are the same as or similar to the corresponding components in the aforementioned semiconductor memory device 100, so their operation modes will not be described in detail here.

[0116] Unlike the previous embodiments, when the command decoder 650 receives the command signal COM indicating a refresh command, it can start generating refresh action signals RFIP_1 to RFIP_N and provide them to memory blocks 640_1 to 640_N respectively.

[0117] The following example illustrates the detailed structure of the memory block in this embodiment. Figure 10 This is a schematic diagram of a memory block 640_i according to an embodiment of the present invention. Figure 10 As shown, memory block 640_i includes a refresh controller 710, an OR gate 720, an AND gate 722, an AND gate 730, an inverter 732, an AND gate 734, an RHA detection circuit 740, an address multiplexer 750, a row decoder and memory block control 760, a column decoder 770, an LIO gate control and DM control logic 772, a sensor amplifier 774, a word driver 780, and a memory cell array 790.

[0118] The refresh controller 710 can output a first refresh signal CBRSLOT and a second refresh signal RHRSLOT based on the refresh action signal RFIP_i. The refresh controller 710 can adjust the output interval of the first refresh signal CBRSLOT according to the first refresh setting information TMRS and the temperature signal TS, and adjust the output interval of the second refresh signal RHRSLOT according to the second refresh setting information TMRHR and the temperature signal TS. Furthermore, the refresh controller 710 can generate a CBR refresh address RFA based on the adjusted first refresh signal CBRSLOT and second refresh signal RHRSLOT.

[0119] The first input of OR gate 720 is coupled to the first refresh signal CBRSLOT, and the second input of OR gate 720 is coupled to the second refresh signal RHRSLOT. The first input of AND gate 722 is coupled to the refresh action signal RFIP_i, and the second input of AND gate 722 is coupled to the output of OR gate 720. The output of AND gate 722 generates a valid refresh signal RFEXE. The valid refresh signal RFEXE indicates that an automatic refresh operation has actually been performed, including CBR refresh and line interference refresh.

[0120] The first input of AND gate 730 is coupled to the refresh action signal RFIP_i, the second input of AND gate 730 is coupled to the second refresh signal RHRSLOT, and a line interference signal RHR is generated at the output of AND gate 730.

[0121] The input of inverter 732 is coupled to the second refresh signal RHRSLOT. The first input of AND gate 734 is coupled to the output of inverter 732. The second input of AND gate 734 is coupled to the second refresh signal CBRSLOT. The third input of AND gate 734 is coupled to the refresh action signal RFIP_i. The output of AND gate 734 generates the selection signal CBR.

[0122] RHA detection circuit 740 is coupled to the output of AND gate 730. RHA detection circuit 740 analyzes the second row address XADD2 in response to the in-process signal ACT, the precharge signal PREC, and the row interference signal RHR to generate the row interference refresh address RHA. Specifically, RHA detection circuit 740 monitors accesses to word lines WL within the memory cell array 790 based on the current second row address XADD2, and detects accesses occurring a predetermined number of times within a specified period to calculate the address adjacent to the address where the predetermined number of accesses occur, using this address as the row interference refresh address RHA.

[0123] The refresh controller 710 within memory block 640_i can output a first refresh signal CBRSLOT and a second refresh signal RHRSLOT based on the refresh action signal RFIP_i. The refresh controller 710 can adjust the output interval of the first refresh signal CBRSLOT according to the first refresh setting information TMRS and the temperature signal TS, and adjust the output interval of the second refresh signal RHRSLOT according to the second refresh setting information TMRHR and the temperature signal TS. Furthermore, the refresh controller 710 can generate a CBR refresh address RFA based on the adjusted first refresh signal CBRSLOT and second refresh signal RHRSLOT.

[0124] The first input of the address multiplexer 750 is coupled to the data address XADD from the address decoder 662. The second input of the address multiplexer 750 is coupled to the CBR refresh address RFA from the refresh controller 710. The third input of the address multiplexer 750 is coupled to the line interference refresh address RHA. The address multiplexer 750 selects the data address XADD, the CBR refresh address RFA, or the line interference refresh address RHA as the second line address XADD2 for output based on the selection signal CBR and the line interference signal RHR.

[0125] Reference Figure 10 When the selection signal CBR is low and the row interference signal RHR is low, it indicates a normal read or write operation. The address multiplexer 750 provides the data address XADD (external input address) as the block access address BADD. When the selection signal CBR is high and the row interference signal RHR is low, it indicates a CBR refresh operation. The address multiplexer 750 uses the CBR refresh address RFA calculated by the refresh controller 710 as the block access address BADD. When the selection signal CBR is low and the row interference signal RHR is high, it indicates a row interference refresh operation. The address multiplexer 750 uses the row interference refresh address RHA as the block access address BADD.

[0126] like Figure 10 The circuit configuration shown allows memory block 640_i to perform either a first refresh operation or a second refresh operation when both the first refresh signal CBRSLOT and the second refresh signal RHRSLOT are output simultaneously. Specifically, when the second refresh signal RHRSLOT is output, regardless of whether the first refresh signal CBRSLOT is output simultaneously, the configuration of AND gate 730, inverter 732, and AND gate 734 will cause address multiplexer 750 to select the row interference refresh address RHA as the second row address XADD2 for output, in order to perform the second refresh operation.

[0127] The operation methods of the row decoder and memory block control 760, column decoder 770, LIO gate control and DM control logic 772, sensor amplifier 774, word driver 780 and memory cell array 790 are the same as or similar to the corresponding components in the aforementioned semiconductor memory device 100, so their operation methods will not be described in detail here.

[0128] Although this embodiment employs a structure where each memory block 640_1 to 640_N has a refresh controller for control, the operation of the first refresh signal CBRSLOT and the second refresh signal RHRSLOT is not significantly different from the aforementioned embodiments. Therefore, those skilled in the art can also... Figure 3 , Figure 6 as well as Figure 8 The circuit configuration shown is applied to the semiconductor memory device 600.

[0129] Let's take another example to illustrate the internal structure of the CBR thinning circuit. Figure 11A This is a schematic diagram of a CBR thinning circuit 800 according to an embodiment of the present invention. Figure 11A As shown, the CBR thinning circuit 800 includes a period counter 810, a set signal generator 820, a reset signal generator 830, an inverter 840, a NAND gate 850, a flip-flop 860, and an inverter 870. The structure of the CBR thinning circuit 800 is applicable to... Figure 3 CBR thinning circuit 310 and Figure 6 The CBR thinning circuit 410.

[0130] A cycle counter 810 counts the first clock CBRCLK to generate a count value CNT1. The cycle counter 810 is also controlled by a reset signal RESET1 to restart counting. A setting signal generator 820 is coupled to the cycle counter 810. The setting signal generator 820 determines a setting value D1 based on a temperature signal TS2 and first refresh setting information TMRS. When the count value CNT1 changes from the setting value D1 to another value, the setting signal generator 820 generates a setting signal SET1. A reset signal generator 830 is coupled to the cycle counter 810. The reset signal generator 830 determines a setting value D2 based on a temperature signal TS2 and first refresh setting information TMRS. When the count value CNT1 changes from the setting value D2 to another value, the reset signal generator 830 generates a reset signal RESET2.

[0131] The input of inverter 840 is coupled to a reset signal RESET2. The first input of NAND gate 850 is coupled to the output of inverter 840, and the second input of NAND gate 850 is coupled to a start signal PWR, generating a reset signal RESET1 at the output of NAND gate 850. A flip-flop 860 is coupled to a setting signal generator 820 and NAND gate 850. The flip-flop 860 can change the logic level of its output based on the setting signal SET1 and the reset signal RESET1. Furthermore, the input of inverter 870 is coupled to the output of flip-flop 860, and the output of inverter 870 generates a first refresh signal CBRSLOT.

[0132] Figure 11B This is an example of the operating waveform of a CBR thinning circuit according to an embodiment of the present invention. Please also refer to... Figure 11A and Figure 11B The refresh operation of this embodiment will be explained.

[0133] like Figure 11B As shown, when the power is turned on (i.e., at time T1), the power supply voltage VDD rises. In response, signals related to power-on are activated. For example, when the power supply voltage VDD reaches a predetermined stable potential, the start signal PWR changes from 0 to 1 (active). Then, when the start signal PWR is activated, initial operation begins, and the reset signal RESET1 changes from 1 to 0. The reset signal RESET1 can be provided not only to the cycle counter 810 and the flip-flop 860, but also to other related circuits for reset operations. During the reset operation, in addition to setting the first refresh signal CBRSLOT to 1 (active), the CBR refresh address RFA of the CBR counter is also reset to zero (stop counting).

[0134] Next, after time point T1, the command decoder begins periodically providing the command signal COM, indicating a refresh command, according to its own settings, thus periodically generating the first clock CBRCLK. However, when the cycle counter 810 counts the first clock CBRCLK less than a threshold value (e.g., threshold x = 128), this circuit (CBR thinning circuit 800) will remain stopped according to the reset state. In other words, the refresh operation will not be performed for a period of time (initial operation). In this embodiment, the refresh operation can be used not only to retain data but also to reset various circuits.

[0135] When the first clock CBRCLK continues to be generated and the period counter 810 reaches the threshold value for the first clock CBRCLK (i.e., time point T2), the period counter 810 will be released from the stop state, and the generated count value CNT1 will begin to increment. In response, when the count value CNT1 increments from 0 (i.e., the set value D1) to 1, the setting signal generator 820 will generate a pulse for the setting signal SET1. The logic level at the output of the flip-flop 860 will become 1, and the first refresh signal CBRSLOT will be 0 (invalid). Thus, the first clock CBRCLK can be skipped and the first refresh signal CBRSLOT can be held at 0.

[0136] However, when the count value CNT1 reaches 3 (i.e., the set value D2) and needs to change (i.e., at time T3), the reset signal generator 830 generates a reset signal RESET2. Simultaneously, via the configuration of the inverter 840 and the NAND gate 850, a reset signal RESET1 is generated. The reset signal RESET1 resets the flip-flop 860. The logic level at the output of the flip-flop 860 becomes 0, and the first refresh signal CBRSLOT becomes 1 (valid). Simultaneously, before the count value CNT1 becomes 4, the period counter 810 is also reset by the reset signal RESET1, and the count value CNT1 is reset to 0. Thus, the refresh interval adjustment is paused without skipping the first clock CBRCLK at this time.

[0137] Similarly, as the first clock CBRCLK continues to be generated, the cycle counter 810 increments the count value CNT1 from 0 to 1. In response, the setting signal generator 820 generates a pulse for the setting signal SET1. The logic level at the output of the flip-flop 860 becomes 1, and the first refresh signal CBRSLOT is set to 0 (invalid). Thus, the refresh interval adjustment is restarted to skip the first clock CBRCLK and keep the first refresh signal CBRSLOT at 0.

[0138] The above operation can then be repeated. In this embodiment, the refresh cycle is extended by four times (refresh skip rate = 3 / 4).

[0139] Let's take another example to illustrate the internal structure of the RHRSLOT generation circuit. Figure 12A This is a schematic diagram of an RHRSLOT generation circuit 900 according to an embodiment of the present invention. The structure of the RHRSLOT generation circuit 900 is applicable to... Figure 8 The RHRSLOT generation circuit 520.

[0140] A cycle counter 910 counts against a third clock RHRCLKD to generate a count value CNT2. The cycle counter 910 is also controlled by a reset signal RESET3 to restart counting. A setting signal generator 920 is coupled to the cycle counter 910. The setting signal generator 920 determines a setting value D3 based on a temperature signal TS2 and second refresh setting information TMRHR. When the count value CNT2 changes from the setting value D3 to another value, the setting signal generator 920 generates a setting signal SET2. A reset signal generator 930 is coupled to the cycle counter 910. The reset signal generator 930 determines a setting value D4 based on a temperature signal TS2 and second refresh setting information TMRHR. When the count value CNT2 changes from the setting value D4 to another value, the reset signal generator 930 generates a reset signal RESET4.

[0141] The input of inverter 940 is coupled to a reset signal RESET4. The first input of NAND gate 950 is coupled to the output of inverter 940, and the second input of NAND gate 950 is coupled to a start signal PWR, generating a reset signal RESET3 at the output of NAND gate 950. A flip-flop 960 is coupled to a setting signal generator 920 and NAND gate 950. The flip-flop 960 can change the logic level of its output based on the setting signal SET2 and the reset signal RESET3. Furthermore, the input of buffer gate 970 is coupled to the output of flip-flop 960, and the output of buffer gate 970 generates a second refresh signal RHRSLOT.

[0142] Figure 12B This is an example of the operating waveform of the RHRSLOT generation circuit according to an embodiment of the present invention. Please also refer to... Figure 12A and Figure 12B The refresh operation of this embodiment will be explained.

[0143] like Figure 12B As shown, when the power supply is started (i.e., at time T4), the power supply voltage VDD rises. In response, signals related to power-on are activated. For example, when the power supply voltage VDD reaches a predetermined stable potential, the start signal PWR changes from 0 to 1 (active). Then, when the start signal PWR is activated, initial operation begins, and the reset signal RESET3 changes from 1 to 0, becoming a pulse signal for resetting. The reset signal RESET3 can be provided not only to the cycle counter 910 and the flip-flop 960, but also to other related circuits for resetting operations during startup.

[0144] Next, after time point T4, the control signal generator begins to periodically provide the command signal COM indicating the refresh command according to its own settings, and thus will start to periodically generate the third clock RHRCLKD.

[0145] When the initial action ends (i.e., time point T5), the count value CNT2 increases from fe (set value D3) to ff, and the setting signal generator 920 generates a pulse for the setting signal SET2. The logic level at the output of the flip-flop 960 will change to 1, and the second refresh signal RHRSLOT will be 1 (valid).

[0146] However, when the count value CNT1 reaches ff (set value D4) and needs to change, the reset signal generator 930 generates a reset signal RESET4. Accompanying this, a reset signal RESET3 is generated via the configuration of the inverter 940 and the NAND gate 950. The reset signal RESET3 resets the flip-flop 960. The logic level at the output of the flip-flop 960 becomes 0, and the second refresh signal RHRSLOT becomes 0 (invalid).

[0147] Similarly, as the third clock RHRCLKD continues to be generated, the cycle counter 910 increments the count value CNT2 from f to 10. In response, the setting signal generator 920 generates a pulse for the setting signal SET2. The logic level at the output of the flip-flop 960 becomes 1, and the second refresh signal RHRSLOT is set to 1 (valid). This interrupts the third clock RHRCLKD again, generating the second refresh signal RHRSLOT. The above operation can then be repeated.

[0148] Let's take another example to illustrate the internal structure of the RHR thinning circuit. Figure 13A This is a schematic diagram of an RHR thinning circuit 1000 according to an embodiment of the present invention. The structure of the RHR thinning circuit 1000 is applicable to... Figure 8 The RHR thinning circuit 510.

[0149] The input of delay circuit 1020 is coupled to the second clock RHRCLK. The input of inverter 1030 is coupled to the output of delay circuit 1020. The first input of NAND gate 1040 is coupled to the output of inverter 1030, and the second input of NAND gate 1040 is coupled to the enable signal PWR. The first control terminal of flip-flop 1050 is coupled to the active signal ACT, and the second control terminal of flip-flop 1050 is coupled to the output of NAND gate 1040. The output of flip-flop 1050 is used to provide the first enable signal AEn.

[0150] The input of inverter 1060 is coupled to the second refresh signal RHRSLOT. The input of delay circuit 1070 is coupled to the second refresh signal RHRSLOT. The first input of AND gate 1080 is coupled to the output of inverter 1060, and the second input of AND gate 1080 is coupled to the output of delay circuit 1070. The input of inverter 1090 is coupled to the enable signal PWR. The first control terminal of flip-flop 1100 is coupled to the output of AND gate 1080, and the second control terminal of flip-flop 1100 is coupled to the output of inverter 1090. The output of flip-flop 1100 is used to provide the second enable signal PEn.

[0151] The input of inverter 1110 is coupled to the output of flip-flop 1050 to receive the first enable signal AEn. The first input of NAND gate 1120 is coupled to the output of inverter 1110, and the second input of NAND gate 1120 is coupled to the output of flip-flop 1100 to receive the second enable signal PEn. The output of NAND gate 1120 is used to provide a third enable signal En. The first input of AND gate 1130 is coupled to the output of NAND gate 1120 to receive the third enable signal En, the second input of AND gate 1130 is coupled to the second clock RHRCLK, and the output of AND gate 1130 generates the third clock RHRCLKD. According to... Figure 13A The circuit configuration shown can realize the function of the RHR thinning circuit.

[0152] Figure 13B This is an example of the operating waveform of the RHR thinning circuit 1000 according to an embodiment of the present invention. Please also refer to... Figure 13A and Figure 13B The refresh operation of this embodiment will be explained.

[0153] like Figure 13B As shown, when the power is turned on (i.e., at time T6), the power supply voltage VDD rises. In response, signals related to power-on are activated. For example, when the power supply voltage VDD reaches a predetermined stable potential, the start signal PWR changes from 0 to 1 (activated). Then, when the start signal PWR is activated, the initial operation begins. During the initial operation, even if the active signal ACT is not activated, the third enable signal En is locked to 1, and the line interference refresh (RHR) thinning has not yet started.

[0154] Next, after time T7, the second refresh signal RHRSLOT begins to be generated. At time T8, the flip-flop 1100 pulls the second enable signal PEn high to 1. In response, the third enable signal En is no longer locked to 1 and begins to react to the first enable signal AEn. Thus, when the active signal ACT is deactivated, the generation of the third clock RHRCLKD also stops, thereby changing the RHR interrupt rate (in...). Figure 13BFor example, the RHR interruption rate was reduced from 1 / (16+1) to 1 / (18+1)).

[0155] It should be noted that, in one embodiment, the RHRSLOT generation circuit can also be used as the first stage in the RHR state control circuit. Figure 14 This is a schematic diagram of an RHR state control circuit 1200 according to an embodiment of the present invention. The RHRSLOT generation circuit 1210 generates a third refresh signal RHRSLOTPre based on a second clock RHRCLK, and adjusts the output interval of the third refresh signal RHRSLOTPre according to the temperature signal TS2 and the second refresh setting information TMRHR.

[0156] The RHR thinning circuit 1220 is coupled to the RHRSLOT generation circuit 1210. The RHR thinning circuit 1220 generates the second refresh signal RHRSLOT based on the third refresh signal RHRSLOTPre, the corresponding memory block active signal ACT, and the precharge signal PREC. It should be noted that the precharge signal PREC is, for example, a pulse signal generated when bit line precharge is to begin. The precharge signal PREC can be generated when the control signal generator receives a precharge command.

[0157] Let's take another example to illustrate the internal structure of the RHR thinning circuit. Figure 15A This is a schematic diagram of an RHR thinning circuit 1300 according to an embodiment of the present invention. The structure of the RHR thinning circuit 1300 is applicable to... Figure 14 The RHR thinning circuit 1220.

[0158] The ACK clock generator 1310 generates an execution signal ACK based on the in-operation signal ACT, the precharge signal PREC, the temperature signal TS2, and the start signal PWR. The WL active time counter 1320 is coupled to the ACK clock generator 1310. The WL active time counter 1320 counts the execution signal ACK to generate a first enable signal AEn, and is controlled to restart counting by the reset signal RESET5.

[0159] The input of inverter 1330 is coupled to the third refresh signal RHRSLOTPre. The input of delay circuit 1340 is coupled to the third refresh signal RHRSLOTPre. The first input of AND gate 1350 is coupled to the output of inverter 1330, the second input of AND gate 1350 is coupled to the output of delay circuit 1340, and the output of AND gate 1350 generates a reset signal RESET5.

[0160] The input terminal of inverter 1360 is coupled to the start signal PWR. The first control terminal of flip-flop 1370 is coupled to the reset signal RESET5, and the second control terminal of flip-flop 1370 is coupled to the output terminal of inverter 1360. The output terminal of flip-flop 1370 is used to provide the second enable signal PEn.

[0161] The input of inverter 1380 is coupled to the output of WL active time counter 1320 to receive the first enable signal AEn. The first input of NAND gate 1390 is coupled to the output of inverter 1380, and the second input of NAND gate 1390 is coupled to the output of flip-flop 1370 to receive the second enable signal PEn. The output of NAND gate 1390 is used to provide a third enable signal En. The first input of AND gate 1400 is coupled to the output of NAND gate 1390 to receive the third enable signal En, the second input of AND gate 1400 is coupled to the third refresh signal RHRSLOTPre, and the output of AND gate 1400 generates the second refresh signal RHRSLOT. Figure 15A The circuit configuration shown can realize the function of the RHR thinning circuit.

[0162] Figure 15B This is an example of the operating waveform of the RHR thinning circuit 1300 according to an embodiment of the present invention. Please also refer to... Figure 15A and Figure 15B The refresh operation of this embodiment will be explained.

[0163] like Figure 15B As shown, when the power is turned on (i.e., at time T9), the power supply voltage VDD rises. In response, signals related to power-on are activated. For example, when the power supply voltage VDD reaches a predetermined stable potential, the start signal PWR changes from 0 to 1 (activated). Then, when the start signal PWR is activated, the initial operation begins. During the initial operation, even if the active signal ACT is not activated, the third enable signal En is locked to 1, and the line interference refresh (RHR) thinning has not yet started.

[0164] Next, after time point T10, the third refresh signal RHRSLOTPre is received. At time point T11, the flip-flop 1370 pulls the second enable signal PEn high to 1. In response, the third enable signal En is no longer locked to 1 and begins to react to the first enable signal AEn. Thus, even if the third refresh signal RHRSLOTPre is received, the generation of the second refresh signal RHRSLOT will stop if the count of the execution signal ACK by the WL active time counter 1320 has not yet reached the set threshold.

[0165] Let's take another example to illustrate the internal structure of the ACK clock generator. Figure 16AThis is a schematic diagram of an ACK clock generator 1500 according to an embodiment of the present invention. The structure of the ACK clock generator 1500 is applicable to... Figure 15A The ACK clock generator 1310.

[0166] The input of inverter 1510 is coupled to the precharge signal PREC. The first input of NAND gate 1520 is coupled to the output of inverter 1510, and the second input of NAND gate 1520 is coupled to the enable signal PWR. The first control terminal of flip-flop 1530 is coupled to the action signal ACT, and the second control terminal of flip-flop 1530 is coupled to the output of NAND gate 1520. The output of flip-flop 1530 is used to provide the fourth enable signal EnP.

[0167] The input of inverter 1540 is coupled to the output of inverter 1530 to receive the fourth enable signal EnP. The first input of NAND gate 1550 is coupled to the output of inverter 1540, and the second input of NAND gate 1550 is coupled to the output of inverter 1552. The output of NAND gate 1550 is used to provide the fifth enable signal EnS. The input of oscillator 1560 is coupled to the output of NAND gate 1550 to receive the fifth enable signal EnS. The control terminal of oscillator 1560 is coupled to the temperature signal TS2 and the oscillation information TMRHOSC. The output of oscillator 1560 generates the oscillation signal OSC and is coupled to the input of inverter 1552 and the input of delay circuit 1562. The output of delay circuit 1562 is used to provide the oscillation signal OSCD.

[0168] The input of delay circuit 1570 is coupled to the output of delay circuit 1562 to receive the oscillation signal OSCD. The input of inverter 1580 is coupled to the output of delay circuit 1570. The first input of NAND gate 1590 is coupled to the oscillation signal OSCD, the second input of NAND gate 1590 is coupled to the output of inverter 1580, and the output of NAND gate 1590 can generate the execution signal ACKF.

[0169] The input of inverter 1600 is coupled to the action signal ACT. The first input of NAND gate 1610 is coupled to the output of inverter 1600, and the second input of NAND gate 1610 is coupled to the output of NAND gate 1590 to receive the execution signal ACKF. The output of NAND gate 1610 can generate the execution signal ACK.

[0170] Figure 16B This is an example of the operating waveform of the ACK clock generator 1500 according to an embodiment of the present invention. Please also refer to... Figure 16A and Figure 16B The operation of this embodiment will be described below.

[0171] like Figure 16BAs shown, when a command signal COM indicating activation is received at time point T12, and a command signal COM indicating a write operation is received at time point T13, the flip-flop 1530 can receive an active signal ACT. After as follows... Figure 16A The circuit configuration shown indicates that the oscillator 1560 generates an oscillation signal OSC, which causes the NAND gate 1610 to generate a corresponding execution signal ACK.

[0172] In contrast, such as Figure 16B As shown, when the command signal COM indicating automatic refresh is received at time point T14, the flip-flop 1530 will not receive the active signal ACT. Consequently, the oscillator 1560 will not generate the oscillation signal OSC, and the NAND gate 1610 will not generate the execution signal ACK.

[0173] In addition, such as Figure 16B As shown, when a command signal COM indicating activation is received at time point T15, and a command signal COM indicating a read operation is received at time point T16, the flip-flop 1530 can also receive the active signal ACT. After as follows... Figure 16A The circuit configuration shown indicates that the oscillator 1560 generates an oscillation signal OSC, which causes the NAND gate 1610 to generate a corresponding execution signal ACK.

[0174] In summary, the semiconductor memory device of the present invention can generate a signal (first refresh signal) for performing CBR refresh operation and a signal (second refresh signal) for performing row interference refresh operation based on the refresh action signal. Furthermore, in the present invention, the execution cycle of CBR refresh (first refresh) and row interference refresh (second refresh) can be appropriately diluted and adjusted, provided that necessary and sufficient refresh opportunities are provided across all temperature ranges. Therefore, both data retention capability and power consumption can be reduced.

[0175] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor memory device, comprising: include: A temperature sensor is used to detect the internal temperature of the semiconductor memory device in order to generate a corresponding temperature signal; Multiple memory blocks, each memory block including a memory cell array having multiple volatile memory cells and multiple word lines, the multiple word lines respectively connecting the multiple volatile memory cells; A refresh controller, coupled to the temperature sensor and the plurality of memory blocks, monitors access to the plurality of word lines, detects accesses that occur a specified number of times within a specified period, and assigns refresh operations corresponding to refresh operation commands as either a first refresh operation or a second refresh operation. as well as The mode register and OTP block are coupled to the refresh controller and generate first refresh setting information and second refresh setting information based on the mode signal. The refresh controller outputs a first refresh signal and a second refresh signal based on the refresh action signal, and adjusts the output interval of the first refresh signal according to the first refresh setting information and the temperature signal, and adjusts the output interval of the second refresh signal according to the second refresh setting information and the temperature signal. The plurality of memory blocks respond to the first refresh signal by performing the first refresh operation, and respond to the second refresh signal by performing the second refresh operation. The refresh controller generates a CBR refresh address based on the first refresh signal and the second refresh signal, and when the first refresh signal and the second refresh signal are output simultaneously, each of the plurality of memory blocks performs one of the first refresh operation and the second refresh operation.

2. The semiconductor memory device of claim 1, wherein the first refresh operation is thinned out and enabled based on information about the device temperature, and the second refresh operation is thinned out and enabled based on information about the access volume of the plurality of word lines, wherein when the first refresh operation and the second refresh operation are in the same loop, and two internal refreshes cannot be performed in the same loop, the refresh controller is configured to control the execution of one refresh operation in the loop and transfer any unexecuted refresh operations to the next loop for execution.

3. The semiconductor memory device according to claim 1, wherein the first refresh operation is a refresh operation for performing CBR refresh, and the second refresh operation is a refresh operation for performing row interference refresh.

4. The semiconductor memory device according to claim 1, further comprising: A first address multiplexer is coupled to the refresh controller and the plurality of memory blocks, receives the data address and the CBR refresh address, and selects the data address or the CBR refresh address as the first row address according to the refresh action signal.

5. The semiconductor memory device of claim 4, wherein each of the plurality of memory blocks comprises: An AND gate, whose first input is coupled to the refresh action signal, whose second input is coupled to the second refresh signal, and which generates a row interference signal at its output. The RHA detection circuit, coupled to the output of the AND gate, generates a row interference refresh address based on the active signal, the row interference signal, and the second row address. The second address multiplexer has a first input terminal coupled to the first row address and a second input terminal coupled to the row interference refresh address, and selects either the first row address or the row interference refresh address as the second row address for output based on the row interference signal. as well as The row decoder and memory block control are coupled to the RHA detection circuit and the second address multiplexer, and latch the second row address as the block access address for output based on the in operation signal.

6. The semiconductor memory device of claim 1, wherein the refresh controller comprises: The CBR thinning circuit outputs the first refresh signal based on a first clock, and adjusts the output interval of the first refresh signal according to the temperature signal, the first refresh setting information, and the CBR refresh address. The RHR state control circuit, coupled to the CBR thinning circuit, outputs the second refresh signal based on the second clock, and adjusts the output interval of the second refresh signal according to the temperature signal and the second refresh setting information. as well as A CBR counter, coupled to the CBR thinning circuit and the RHR state control circuit, counts the number of times the first refresh operation is executed based on a first counting signal to generate the CBR refresh address.

7. The semiconductor memory device of claim 6, wherein the refresh controller further comprises: A buffer gate, whose input is coupled to the refresh action signal, and whose output generates the first clock; A first AND gate has its first input terminal coupled to the output terminal of the buffer gate, its second input terminal coupled to the first refresh signal, and generates a second counting signal at its output terminal. A multiplexer, with its first terminal coupled to the refresh action signal and its second terminal coupled to the second counting signal, selects either the refresh action signal or the second counting signal as the second clock for output according to a mode switching signal; An inverter whose input is coupled to the second refresh signal; as well as The second AND gate has its first input terminal coupled to the output terminal of the inverter, its second input terminal coupled to the second counting signal, and its output terminal outputting the first counting signal to the CBR counter.

8. The semiconductor memory device of claim 6, wherein the refresh controller further comprises: A buffer gate, whose input is coupled to the refresh action signal, and whose output generates the second clock; A first AND gate, whose first input is coupled to the refresh action signal, and whose output generates the first clock; The second AND gate has its first input coupled to the first clock, its second input coupled to the first refresh signal, and generates the first counting signal at its output. as well as The NAND gate has its first input coupled to the second refresh signal, its second input coupled to the first refresh signal, and its output coupled to the second input of the first AND gate.

9. The semiconductor memory device of claim 6, wherein the RHR state control circuit comprises: The RHR thinning circuit generates a third clock based on the second clock, the second refresh signal, and the active signal. as well as The RHRSLOT generation circuit, coupled to the RHR thinning circuit, generates the second refresh signal based on the third clock, and adjusts the output interval of the second refresh signal according to the temperature signal and the second refresh setting information.

10. The semiconductor memory device of claim 6, wherein the CBR thinning circuit comprises: A cycle counter counts the first clock cycle to generate a count value and is controlled to restart counting by a first reset signal; A setting signal generator is coupled to the period counter, and determines a first setting value based on the temperature signal and the first refresh setting information. When the count value changes from the first setting value to another value, a setting signal is generated. A reset signal generator, coupled to the cycle counter, determines a second setting value based on the temperature signal and the first refresh setting information, and generates a second reset signal when the count value changes from the second setting value to another value; A first inverter, the input of which is coupled to the second reset signal; The first NAND gate has its first input terminal coupled to the output terminal of the first inverter, its second input terminal coupled to the start signal, and generates the first reset signal at its output terminal. A flip-flop, coupled to the set signal generator and the first NAND gate, changes the logic level of the output terminal according to the set signal and the first reset signal; as well as The second inverter has its input terminal coupled to the output terminal of the flip-flop, and its output terminal generates the first refresh signal.

11. The semiconductor memory device of claim 9, wherein the RHRSLOT generation circuit comprises: A cycle counter counts the third clock to generate a count value and is controlled by a first reset signal to start counting again. A setting signal generator is coupled to the period counter, and determines a first setting value based on the temperature signal and the second refresh setting information. When the count value changes from the first setting value to another value, a setting signal is generated. A reset signal generator, coupled to the cycle counter, determines a second set value based on the temperature signal and the second refresh setting information, and generates a second reset signal when the count value changes from the second set value to another value; A first inverter, the input of which is coupled to the second reset signal; The second NAND gate has its first input terminal coupled to the output terminal of the first inverter, its second input terminal coupled to the start signal, and generates the first reset signal at its output terminal. A flip-flop, coupled to the set signal generator and the second NAND gate, changes the logic level of the output terminal according to the set signal and the first reset signal; as well as The second buffer gate has its input terminal coupled to the output terminal of the flip-flop, and its output terminal generates the second refresh signal.

12. The semiconductor memory device of claim 9, wherein the RHR thinning circuit comprises: The first delay circuit has its input terminal coupled to the second clock; The first inverter has its input terminal coupled to the output terminal of the first delay circuit; The second NAND gate has its first input terminal coupled to the output terminal of the first inverter, and its second input terminal coupled to the start signal; A first flip-flop has a first control terminal coupled to the active signal and a second control terminal coupled to the output of the second NAND gate. The second inverter has its input terminal coupled to the second refresh signal; The second delay circuit has its input terminal coupled to the second refresh signal; The third AND gate has its first input terminal coupled to the output terminal of the second inverter, and its second input terminal coupled to the output terminal of the second delay circuit. The third inverter has its input terminal coupled to the start signal; The second inverter has its first control terminal coupled to the output terminal of the third AND gate, and its second control terminal coupled to the output terminal of the third inverter. The fourth inverter has its input terminal coupled to the output terminal of the first inverter; The third NAND gate has its first input terminal coupled to the output terminal of the fourth inverter, and its second input terminal coupled to the output terminal of the second inverter. as well as The fourth AND gate has its first input coupled to the output of the third NAND gate, its second input coupled to the second clock, and its output generating the third clock.

13. The semiconductor memory device according to claim 1, further comprising: The command decoder, coupled to the refresh controller, begins to generate a refresh action signal upon receiving the refresh operation command.

14. A semiconductor memory device, comprising: include: A temperature sensor is used to detect the internal temperature of the semiconductor memory device in order to generate a corresponding temperature signal; Multiple memory blocks are coupled to the temperature sensor. Each memory block includes a refresh controller, a memory cell array with multiple volatile memory cells, and multiple word lines, each word line connecting to one of the multiple volatile memory cells. The refresh controller monitors accesses to the corresponding plurality of word lines, detects accesses occurring a predetermined number of times within a specified period, and assigns refresh operations corresponding to refresh operation commands as either a first refresh operation or a second refresh operation. The semiconductor memory device further includes: The mode register and OTP block are coupled to the refresh controller and generate first refresh setting information and second refresh setting information based on the mode signal. Each refresh controller outputs a first refresh signal and a second refresh signal based on the refresh action signal. It also adjusts the output interval of the first refresh signal according to the first refresh setting information and the temperature signal, and adjusts the output interval of the second refresh signal according to the second refresh setting information and the temperature signal. Each memory block responds to the corresponding first refresh signal by performing a first refresh operation, and responds to the corresponding second refresh signal by performing a second refresh operation. Each refresh controller generates a CBR refresh address based on the corresponding first refresh signal and second refresh signal, and when the first refresh signal and the second refresh signal are output simultaneously, the corresponding memory block performs one of the first refresh operation and the second refresh operation.

15. The semiconductor memory device of claim 14, wherein each of the plurality of memory blocks comprises: A first AND gate has its first input coupled to the refresh action signal, its second input coupled to the second refresh signal, and generates a line interference signal at its output. The RHA detection circuit is coupled to the output of the first AND gate and generates a row interference refresh address based on the active signal, the row interference signal, and the row address. An inverter whose input is coupled to the second refresh signal; The second AND gate has its first input coupled to the refresh action signal, its second input coupled to the first refresh signal, and its third input coupled to the output of the inverter, and generates a selection signal at its output. An address multiplexer has a first input coupled to the CBR refresh address, a second input coupled to the data address, and a third input coupled to the row interference refresh address. It selects one of the CBR refresh address, the data address, and the row interference refresh address as the row address for output based on the row interference signal and the selection signal. as well as The flip-flop, coupled to the RHA detection circuit and the address multiplexer, latches the row address as the block access address based on the in operation signal and outputs it.

16. The semiconductor memory device of claim 14, wherein each refresh controller comprises: The CBR thinning circuit outputs the first refresh signal based on a first clock, and adjusts the output interval of the first refresh signal according to the temperature signal, the first refresh setting information, and the CBR refresh address. The RHR state control circuit, coupled to the CBR thinning circuit, outputs the second refresh signal based on the second clock, and adjusts the output interval of the second refresh signal according to the temperature signal and the second refresh setting information. as well as A CBR counter, coupled to the CBR thinning circuit and the RHR state control circuit, counts the number of times the first refresh operation is executed based on a first counting signal to generate the CBR refresh address.

17. The semiconductor memory device of claim 16, wherein the RHR state control circuit comprises: The RHRSLOT generation circuit generates a third refresh signal based on the second clock, and adjusts the output interval of the third refresh signal according to the temperature signal and the second refresh setting information. as well as The RHR thinning circuit, coupled to the RHRSLOT generation circuit, generates the second refresh signal based on the third refresh signal, the corresponding active signal, and the precharge signal.

18. The semiconductor memory device of claim 17, wherein the RHR thinning circuit comprises: An ACK clock generator generates an execution signal based on the in operation signal, the precharge signal, the temperature signal, and the start signal. The WL active time counter, coupled to the ACK clock generator, counts the execution signals to generate an execution enable signal, and is controlled by a reset signal to start counting again. A first inverter, the input of which is coupled to the third refresh signal; Delay circuit, the input of which is coupled to the third refresh signal; The third AND gate has its first input terminal coupled to the output terminal of the first inverter, its second input terminal coupled to the output terminal of the delay circuit, and its output terminal generates the reset signal. The second inverter has its input terminal coupled to the start signal; A flip-flop, wherein its first control terminal is coupled to the reset signal, and its second control terminal is coupled to the output terminal of the second inverter; A third inverter, the input of which is coupled to the execution enable signal; The second NAND gate has its first input terminal coupled to the output terminal of the third inverter, and its second input terminal coupled to the output terminal of the flip-flop. as well as The fourth AND gate has its first input coupled to the output of the second NAND gate, its second input coupled to the third refresh signal, and its output generating the second refresh signal.

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