Random value generator

Abstract

The present disclosure relates to random value generators. The present disclosure includes systems, devices, and methods related to generating random data values. For example, a first read operation can be performed on a memory cell programmed to a first state, where the first read operation is performed using a first read voltage that is within a predetermined threshold voltage distribution corresponding to the first state. A program signal can be applied to the memory cell in response to the first read operation resulting in a snapback event, where the program signal is configured to place the memory cell in a second state. A second read operation can be performed using a second read voltage that is between the predetermined threshold voltage distribution corresponding to the first state and a second threshold voltage distribution corresponding to the second state to determine whether the memory cell is in the first state or the second state.

Description

Technical Field

[0001] This disclosure generally relates to memory devices, and more specifically, to apparatus for using memory devices to generate random data values. Background Technology

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory may require power to maintain its data and includes Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), and Synchronous Dynamic Random Access Memory (SDRAM), among others. Non-volatile memory provides persistent data by retaining stored data when no power is supplied and can include NAND flash memory, NOR flash memory, Read-Only Memory (ROM), Electrically Erasable Programmable Memory (EEPROM), Erasable Programmable Memory (EPROM), and resistive variable memory, such as Phase-Change Random Access Memory (PCRAM) and 3D Crosspoint Memory (e.g., 3D XPoint). TM Resistive random access memory (RRAM), ferroelectric random access memory (FeRAM), magnetoresistive random access memory (MRAM), and programmable conductive memory, as well as other types of memory.

[0003] Memory devices can be used as volatile and non-volatile memory for a wide range of electronic applications requiring high memory density, high reliability, and low power consumption. Non-volatile memory can be used in, for example, personal computers, portable memory sticks, solid-state drives (SSDs), digital cameras, cellular phones, portable music players and movie players such as MP3 players, and other electronic devices.

[0004] Memory cells can be programmed to correspond to states corresponding to one or more data values ​​(e.g., logic "1" or "0"). In various examples, programming one or more memory cells to random data values ​​can be useful. For instance, various computer algorithms and / or applications utilize random data values ​​(e.g., data values ​​not determined by the programmer and / or not predictable based on the algorithm's own underlying parameters). Random data values ​​can be used in a variety of environments, such as in probabilistic models, sampling values ​​from probability densities, simulating stochastic processes (e.g., the behavior of materials or financial markets), performing Monte Carlo simulations to approximate incalculable values, or adding extra security to cryptography and encryption keys, as well as other applications. Summary of the Invention

[0005] One aspect of this application relates to a method for generating random data values, comprising: performing a first read operation on a plurality of memory cells programmed to correspond to a first state corresponding to a first data value, wherein the first read operation is performed using a first read voltage within a predetermined threshold voltage distribution corresponding to the first state; and performing a second read operation using a second read voltage between the predetermined threshold voltage distribution corresponding to the first state and a second threshold voltage distribution corresponding to a second state corresponding to a second data value, to determine whether each of the plurality of memory cells is in the first state or the second state, wherein the result of the second read operation corresponds to the random data value based on the threshold voltage of each of the plurality of memory cells during the first read operation.

[0006] Another aspect of this application relates to an apparatus for generating random data values, comprising: an array of memory cells, each of which is programmable to a first state corresponding to a first data value and a second state corresponding to a second data value; and a controller coupled to the array and configured to generate a random one of the first and second data values ​​by: applying a first read voltage to a memory cell programmed to the first state, wherein the memory cell programmed to the first state has a predetermined threshold voltage distribution associated with the first state, and wherein the first read voltage has a value selected to be within the predetermined threshold voltage distribution; applying a programming signal to the memory cell in response to a retracement event caused by the application of the first read voltage, wherein the programming signal is configured to place the memory cell in the second state corresponding to the second data value; and applying a second read voltage to the memory cell to determine whether the memory cell is in the first or second state, wherein the second read voltage is not within the predetermined threshold voltage distribution associated with the first state; wherein the generated random one of the first and second data values ​​is based on the threshold voltage of the memory cell after the first read voltage is applied to the memory cell.

[0007] Another aspect of this application relates to a system for generating random data values, comprising: an array of memory cells, each of which is programmable to a first state corresponding to a first data value and a second state corresponding to a second data value; and a controller coupled to the array and configured to generate a random one of the first data value and the second data value by: applying a first read voltage to a memory cell programmed to the first state, wherein the memory cell programmed to the first state has a predetermined threshold voltage distribution associated with the first state, and wherein the first read voltage has a value selected at the center of the predetermined threshold voltage distribution; and detecting an indication of the memory cell based on whether the application of the first read voltage is responsive to the application of the first read voltage. A sudden cyclic event of the threshold voltage of the memory cell relative to the value of the first read voltage determines whether to program the memory cell to the first state or to apply a programming signal to the memory cell, the programming signal being configured to place the memory cell in a second state corresponding to a second data value; and to apply a second read voltage to the memory cell to determine whether the memory cell is in the first state or the second state, wherein the second read voltage is not within the predetermined threshold voltage distribution associated with the first state, wherein the randomized one of the first data value and the second data value is determined based on the threshold voltage of the memory cell relative to the first read voltage as confirmed by applying the second read voltage. Attached Figure Description

[0008] Figure 1 This is a block diagram of a device, according to several examples of the present disclosure, in the form of a computing system comprising a memory device associated with generating random data values.

[0009] Figure 2 It is a graph illustrating the distribution of threshold voltages corresponding to the data states of memory cells operable to generate random data values, according to several examples of this disclosure.

[0010] Figure 3 This is a graph illustrating instances of sudden return events associated with the generation of random data values ​​that are consistent with several instances of this disclosure.

[0011] Figures 4A-4C This is a graph illustrating various instances of prefetch sequences of memory cells associated with generating random data values, consistent with several instances of this disclosure.

[0012] Figure 5 This is an illustration of an example of a memory array associated with generating random data values, consistent with several examples of this disclosure.

[0013] Figure 6This is a graph illustrating the distribution of threshold voltages associated with the generation of random data values, consistent with several examples of this disclosure. Detailed Implementation

[0014] Various embodiments of this disclosure provide the ability to generate random data values. For example, memory cells can be programmed randomly as logic "1" or logic "0", or a group of memory cells can be programmed such that each memory cell in the group stores a random logic "1" or "0". For example, random data values ​​can be generated and / or read from the cells(s) in response to a host request. Random data values ​​can be used for various purposes, such as those associated with performing various applications (e.g., cryptographic functions, key generation, encryption, shielding protocols, digital signatures, etc.). For such applications and other applications, random data values ​​may be the target and / or may be needed to generate random and / or unpredictable outputs.

[0015] As further described herein, several embodiments involve utilizing the threshold voltage (Vt) "bouncing" characteristic of a variable-resistance memory cell to generate random data values. For example, a three-dimensional crosspoint cell (e.g., 3D XPoint) TM Various resistive variable memory cells, including self-selective memory (SSM) cells, exhibit a fluctuating behavior with a normal (e.g., Gaussian) distribution, characterized by a Vt value. Because such memory cells exhibit bidirectional threshold-switching behavior, applying a read voltage (e.g., a threshold voltage Vdm) located at the center of the Vt distribution will produce or not produce a ripple event (e.g., a bidirectional threshold-switching event) depending on whether the fluctuating Vt of the cell is above or below Vdm during a read operation. As further described below, resistive variable memory cells can comprise various chalcogenide materials as well as other materials exhibiting bidirectional threshold-switching behavior. As used herein, an SSM cell refers to a resistive variable memory cell in which a single material (e.g., a chalcogenide) serves both as a switching element and a storage element of the memory cell.

[0016] As an example, consider a resistive variable memory cell programmable to either a low-resistance state (e.g., SET state) or a high-resistance state (e.g., RESET state). The programming state of the cell can be determined by applying a Vdm between the set and reset states to the cell. If the cell's Vt is lower than Vdm, the cell will experience a quickback event, indicating that the cell is in a set state (e.g., the cell stores logic 0). If the cell's Vt is higher than Vdm, the cell will not experience a quickback event, indicating that the cell is in a reset state (e.g., the cell stores logic 1).

[0017] Embodiments of this disclosure utilize the hopping Vt characteristic to program memory cells as random data values ​​(e.g., 1 or 0). The random data values ​​can then be read from the cells and used in association with the execution of an application, which may include providing (a number of) the generated random data values ​​to a requesting entity, such as a host (e.g., a host processor).

[0018] The various embodiments of this disclosure operate as true random number generators (TRNGs) rather than pseudo random number generators (PRNGs) that can provide repeating patterns based on a seed value. Therefore, for example, embodiments of this disclosure can be more efficient and / or provide greater integrity for security / encryption applications.

[0019] As used herein, “one,” “a,” or “several” can refer to one or more of something, and “multiple” can refer to two or more such things. For example, “one memory device” can refer to one or more memory devices, and “multiple memory devices” can refer to two or more memory devices. As used herein, “random” refers to the various degrees of unpredictability in the generation of random data, including but not limited to pseudo-randomness, randomness, apparent randomness, true randomness, etc.

[0020] The figures in this document follow a numbering convention, where the first few digits correspond to the figure number and the remaining digits identify the elements or components in the figure. Similar elements or components between different figures can be identified by using similar digits.

[0021] Figure 1 This is a block diagram of a device in the form of a computing system 100 including a memory device 128, according to embodiments of the present disclosure. As used herein, the memory device 128, controller 140, and memory 130 may also be individually considered as a "device". Regarding Figure 1 The described components, configuration, and / or operation of the described memory element may include information about Figure 2-6 Any other component, configuration and / or operation described therein and / or interchangeable with it.

[0022] In this example, system 100 includes a host 126 coupled to a memory device 128, which includes memory 130. Memory 130 may represent one or more memory arrays. Host 126 may be a host system, such as a personal laptop computer, desktop computer, digital camera, smartphone, or memory card reader, and various other types of host systems. Host 126 may include a system motherboard and / or backplane and may include several processing resources (e.g., one or more processors, microprocessors, or some other type of control circuitry). System 100 may include a separate integrated circuit, or both host 126 and memory device 128 may be on the same integrated circuit. For example, system 100 may be a server system and / or a high-performance computing (HPC) system and / or a portion thereof. Although Figure 1 The examples shown illustrate systems with a von Neumann architecture, but embodiments of this disclosure can be implemented in a non-von Neumann architecture that may not include one or more components typically associated with a von Neumann architecture (e.g., CPU, ALU, etc.). In an example where system 100 includes a solid-state drive, host 126 may be coupled to an external processor ( Figure 1 (Not shown in the figure) system controller. In some embodiments, host 126 may be one or more host processors, and memory device 128 may be a managed memory device having a controller 140 serving as an on-die controller.

[0023] For clarity, system 100 has been simplified to focus on features particularly relevant to this disclosure. For example, memory 130 is any type of memory, such as a DRAM array, a self-selecting memory (SSM) array, or a 3D crosspoint memory array (e.g., 3D XPoint). TM ), SRAM array, STT RAM array, PCRAM array, TRAM array, RRAM array, NAND flash memory array and / or NOR flash memory array.

[0024] Memory 130 may include multiple memory elements. The memory elements may be various types of variable resistive memory cells. Each memory element may include, for example, a storage element and a selection element (e.g., a switching element) arranged at an intersection between a pair of conductive lines (e.g., an access line, which may be referred to as a word line or select line, and a sense line, which may be referred to as a bit line, data line, or digital line). For example, the storage element and / or switching element may be formed of one or more chalcogenide materials. In an SSM cell, a single chalcogenide material may serve as both a storage element and a switching element. For example, each memory cell may include a chalcogenide material, which may be formed of various doped or undoped materials that may or may not be phase-change materials, and / or may or may not undergo a phase change during reading and / or writing to the memory cell. The chalcogenide material may be a material or alloy containing at least one of the elements S, Se, and Te. Chalcogenide materials may include alloys of S, Se, Te, Ge, As, Al, Sb, Au, indium (In), gallium (Ga), tin (Sn), bismuth (Bi), palladium (Pd), cobalt (Co), oxygen (O), silver (Ag), nickel (Ni), and platinum (Pt). Example chalcogenide materials and alloys may include, but are not limited to, Ge-Te, In-Se, Sb-Te, Ga-Sb, In-Sb, As-Te, Al-Te, Ge-Sb-Te, Te-Ge-A s, In-Sb-Te, Te-Sn-Se, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te, In-SbGe, Te-Ge-Sb-S, T e-Ge-Sn-O, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-SbTe-Pd, Ge-Sb-Te-Co, Sb-Te-B i-Se, Ag-In-Sb-Te, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, GeTe-Sn-Ni, Ge-Te-Sn-Pd or Ge-Te-Sn-Pt. Examples of chalcogenide materials may also include SAG-based glass non-phase change materials, such as SeAsGe. As used herein, hyphenated chemical composition symbols indicate the elements contained in a particular compound or alloy and are intended to represent all stoichiometry involving the indicated element. For example, Ge-Te may include GexTey, where x and y can be any positive integers.

[0025] Memory device 128 includes an address circuitry 142 for latching address signals provided on bus 135 (e.g., an I / O bus) via I / O circuitry 144. The address signals are received via address circuitry 142 and decoded by row decoder 146 and column decoder 137 to access memory 130. Address signals may also be provided to controller 140 (e.g., via address circuitry 142 and / or via control bus 131). Data can be read from memory 130 by sensing voltage and / or current changes on data lines using a sensing circuitry 144 (not shown). The sensing circuitry 144 can read and latch a page (e.g., a row) of data from memory 130. I / O circuitry 144 can be used for bidirectional data communication with host 126 via I / O bus 135. Write circuitry 148 is used to write data to memory 130.

[0026] The memory cells of memory 130 can be programmed to specific states (e.g., set or reset) corresponding to bit values ​​(e.g., 1 or 0). For example, a set state can be a relatively low resistance state, while a reset state can be a relatively high resistance state.

[0027] Such as association Figure 2 and 3 Further, the programming state of a memory cell can be determined by applying a boundary voltage (Vdm) across the memory cell, for example, between a pair of signal lines (e.g., bit line and word line) to which the memory cell is coupled. Vdm (e.g., read voltage) can be a voltage level between a set and a reset distribution to determine the state of the cell. If Vdm is greater than Vt of the memory cell, a rush current is generated (e.g., a rush current event is detected), indicating that the cell is in a set state; and if Vdm is less than Vt of the memory cell, no rush current is generated, indicating that the cell is in a reset state.

[0028] Controller 140 (e.g., a memory controller), which may be referred to as memory bank control logic and / or a sequencer, decodes signals provided from host 126 via control bus 131. These signals may include chip enable signals, write enable signals, and address latch signals for controlling operations performed on memory 130, including data read, data write, and data erase operations. In various embodiments, controller 140 is responsible for executing instructions from host 126 and sequencing accesses to array 130. Controller 140 may be a state machine, a sequencer, or some other type of control circuitry system.

[0029] Controller 140 can control the operation of memory cells (e.g., read, write, rewrite, refresh, discharge) through various components. In some cases, one or more of row decoder 146 and column decoder 137 may be co-located with controller 140. Controller 140 can generate row and column address signals to activate desired access lines and sense lines. Controller 140 can also generate and control various voltages or currents used during operation of the memory array. Generally, the amplitude, shape, polarity, and / or duration of the applied voltage or current discussed herein may be adjusted or modified and may differ for the various operations discussed when operating memory 130.

[0030] Controller 140 may be configured to perform additional functions as described herein. For example, the controller may be configured to generate random data values ​​based on the "bouncing" or shifting of memory cell Vt. For example, controller 140 may receive a request for random data values ​​from host 126. In response to a request for random data values ​​from the host, controller 140 may be configured to perform various operations described below to generate random data values ​​based on the "bouncing" or shifting of memory cell Vt.

[0031] For example, controller 140 may be configured to apply a first read voltage to a memory cell programmed into a first state, wherein the memory cell programmed into the first state has a predetermined threshold voltage distribution associated with the first state, and wherein the first read voltage has a value selected to be at the center of the predetermined threshold voltage distribution. Controller 140 may be configured to determine, based on whether a ripple event indicative of a threshold voltage relative to the first read voltage is detected in response to the application of the first read voltage, whether to program the memory cell into the first state or to apply a programming signal to the memory cell, the programming signal being configured to place the memory cell into a second state corresponding to a second data value. Controller 140 may be configured to apply a second read voltage to the memory cell to determine whether the memory cell is in the first or second state, wherein the second read voltage is not within the predetermined threshold voltage distribution associated with the first state, and wherein the randomized first and second data values ​​are determined based on the threshold voltage of the memory cell relative to the first read voltage, as confirmed by applying the second read voltage.

[0032] Once controller 140 has caused the generation of random data values, controller 140 can cause the random data values ​​to be transmitted back to host 126 to fulfill a previous request for random data values ​​from host 126. In some instances, controller 140 can be configured to cause the generation of multiple random data values. Controller 140 can be configured to transmit multiple random data values ​​back to host 126 individually, in batches, and / or all at once. Multiple random data values ​​can be generated from a single unit through multiple iterations, and / or multiple random data values ​​can be generated from corresponding different memory units. In some instances, for example regarding... Figure 5 and Figure 6 As described, multiple different memory units and / or portions of multiple different memory units can be grouped to generate multiple random data values.

[0033] Figure 2 These are diagrams illustrating threshold voltage distributions 254-1 and 254-2 corresponding to memory cells, such as those in memory 130 operable according to several embodiments of this disclosure, for example, memory cells with corresponding data states. Regarding... Figure 2 The described components, configuration, and / or operation of the described memory element may include information about Figure 1 and 3 -6 describes any other components, configurations, and / or operations and / or may be interchanged with them.

[0034] As an example, distribution 254-1 can be referred to as a set state, which may correspond to a low Vt state, and distribution 254-2 can be referred to as a reset state, which may correspond to a high Vt state (e.g., a state corresponding to a relatively high Vt level compared to the Vt level corresponding to the set state). That is, threshold voltage distribution 254-1 may correspond to the threshold voltage range of the set state, and threshold voltage distribution 254-2 may correspond to the threshold voltage range of the reset state of the memory cell. In this example, distribution 254-1 corresponds to logic "1", and distribution 254-2 corresponds to logic "0"; however, the embodiment is not limited to this assignment encoding. As illustrated, threshold voltage distributions 254-1 and 254-2 may have an approximately normal distribution (e.g., Gaussian); however, the embodiment is not limited to such distributions.

[0035] In some instances, threshold voltage distributions 254-1 and 254-2 can be determined experimentally. For example, memory cells can be tested to determine threshold voltage distributions 251-1 and 254-2 for each data state to be stored in the memory cell. That is, the voltage distribution for a specific state stored on a particular memory cell can be determined based on multiple programming and reading operations performed on the memory cell prior to its shipment or sale. In some instances, threshold voltage distributions 254-1 and 254-2 can be determined and / or specified by the manufacturer based on thousands of tests of the memory cell and / or understanding of the physical properties and / or electrical behavior of the memory cell. In this way, threshold voltage distributions 254-1 and 254-2 can be predetermined for each data state of a given memory cell or group of memory cells. That is, threshold voltage distributions 254-1 and 254-2 can be determined before the distribution, sale, or use of the memory cell. In some instances, threshold voltage distributions 254-1 and 254-2 can be predetermined before performing a series of operations described herein and associated with generating random data values ​​based on Vt fluctuations.

[0036] As used herein, Vt jump can refer to the fluctuation of Vt within its threshold voltage distribution curve under the same test parameters. For example, a memory cell may have a first Vt. That first Vt may be the Vt for the set state. At any given time, the first Vt may be located anywhere along the threshold voltage distribution 254-1 of the memory cell for the set state. Similarly, a memory cell may have a second Vt. The second Vt may be the Vt for the reset state. At any given time, the second Vt may be located anywhere along the threshold voltage distribution 254-2 of the memory cell for the reset state. The fluctuation of Vt within their respective threshold voltage distributions 254-1 and 254-2 may be referred to as Vt jump. The sources of Vt jump may include fluctuations from the physical properties of the memory cell, the environment, and / or other sources of variation. The Vt jump described herein is separate from and distinct from Vt drift (e.g., an increase in Vt level over time), which may be experienced by various resistive memory cells (e.g., chalcogenide-based memory cells).

[0037] As described above, the data state of a memory cell can be determined by applying Vdm across the memory cell. For example, Vdm 250 with a voltage level between threshold voltage distributions 254-1 and 254-2 can be applied. By applying Vdm 250 at this midpoint between voltage distributions 254-1 and 254-2, the presence of a backflow current will indicate that the memory cell being read has a Vt below Vdm 250 and is in a set state, regardless of where Vt of the set state is located along its corresponding threshold voltage distribution 254-1 or where Vt of the reset state is located along its corresponding threshold voltage distribution 254-2. On the other hand, the absence of a backflow current will indicate that the memory cell being read has a Vt above Vdm 250 and is in a reset state. Moreover, this holds true regardless of where Vt of each state is actually located at the time of read, because substantially the entire threshold voltage distribution 254-1 is below Vdm 250 and substantially the entire threshold voltage distribution 254-2 is below Vdm 250.

[0038] The fluctuations or jumps in the actual position of the data state Vt of a memory cell may have a normal distribution with respect to its corresponding threshold voltage distribution. For example, the described threshold voltage distribution 254-1 of the first state of the memory cell may correspond to and / or describe the Vt jumps of the first state of the memory cell, and the described threshold voltage distribution 254-2 of the second state of the memory cell may correspond to and / or describe the Vt jumps of the second state of the memory cell.

[0039] The threshold voltage distribution 254-1 of the first state of the memory cell may include a central Vt value 252. The central Vt value 252 may be a voltage value located at the center of the threshold voltage distribution 254-1. The central Vt value 250 may be a voltage value at the midpoint of the curve corresponding to the normal distribution of the threshold voltage distribution 254-1 for memory cells programmed into the first state. For example, the central Vt value 252 may be a voltage value located in the middle of the threshold voltage distribution 254-1 corresponding to Vt fluctuations. Therefore, the Vt of the memory cell programmed into the first state is higher than the central Vt value 252 50% of the time and lower than the central Vt value 252 50% of the time. Thus, applying a voltage with the central Vt value 252 across the memory cell programmed into the first state will cause a ripple event 50% of the time and will not cause a ripple event 50% of the time. Therefore, applying a voltage with a center Vt value of 252 to a memory cell programmed to the first state will result in a truly random occurrence of a cyclic event.

[0040] The threshold voltage distribution 254-2 of the second state of the memory cell may include a central Vt value 256. The central Vt value 256 may be a voltage value located at the center of the threshold voltage distribution 254-2. The central Vt value 256 may be a voltage value at the midpoint of the curve corresponding to the normal distribution of the threshold voltage distribution 254-2 for memory cells programmed into the second state. For example, the central Vt value 256 may be a voltage value located in the middle of the threshold voltage distribution 254-2 corresponding to Vt fluctuations. Therefore, the Vt of the memory cell programmed into the first state is higher than the central Vt value 252 50% of the time, and the Vt of the memory cell programmed into the first state is lower than the central Vt value 252 50% of the time. Therefore, applying a voltage with the central Vt value 252 across the memory cell programmed into the second state will cause a ripple event 50% of the time and will not cause a ripple event 50% of the time. Therefore, applying a voltage with a center Vt value of 256 to a memory cell programmed to the second state will result in a truly random occurrence of a cyclic event.

[0041] Figure 3 Graph 360 illustrates instances of cyclic events, which may or may not be exhibited by memory cells in response to an applied voltage level, according to several embodiments of this disclosure. Regarding... Figure 3 The described components, configuration, and / or operation of the described memory element may include information about Figure 1-2 The components, configurations and / or operations described in 4-6 and / or interchangeable with them.

[0042] In graph 360, the horizontal axis represents the applied voltage and the vertical axis represents the current level. The horizontal axis includes a first threshold voltage level (VT1) 362 and a second threshold voltage level (VT2) 364. VT1 may correspond to a threshold voltage associated with a first possible state of the memory cell, such as a set state. For example, VT1 may correspond to the voltage value that generates a ripple event in the memory cell when applied to a memory cell programmed to the first state.

[0043] VT2 may correspond to a threshold voltage associated with a second possible state of the memory cell, such as a reset state. For example, VT2 may correspond to the voltage value that causes a shunt event in the memory cell when applied to a memory cell programmed to the first state.

[0044] Additionally, the horizontal axis includes a voltage value 350 corresponding to a typical Vdm applied between VT1 and VT2. The Vdm voltage value 350 can be applied to determine the data state of the memory cell. The Vdm voltage value 350 can correspond to... Figure 2 The Vdm 250 described herein can be located at Figure 2The threshold voltage distribution described herein is between 254-1 and 254-2. By applying a Vdm voltage value of 350 at this midpoint between VT1 and VT2, the presence of a rush current will indicate that the memory cell being read has a Vt lower than the Vdm voltage value of 350 (e.g., VT1) and is in a set state. On the other hand, the absence of a rush current when the Vdm voltage value of 350 is applied will indicate that the memory cell being read has a Vt higher than the Vdm voltage value of 350 (e.g., VT2) and is in a reset state.

[0045] For example, if a Vdm voltage value 350 is applied to a memory cell when the memory cell is programmed to a first state, a rapid return event 366, described as a rapid jump to a higher current level, may occur because the VT1 voltage level is reached and / or exceeded. However, if a Vdm voltage value 350 is applied to a memory cell when the memory cell is programmed to a second state, a rapid return event 368, described as a rapid jump to a higher current level, may not occur because the VT2 voltage level is not reached and / or exceeded. That is, when a Vdm voltage value 350 is applied to a memory cell programmed to a second state with a second threshold (e.g., VT2), the current level within the memory cell (visible as the portion of 368 intersecting the dashed line of 350) still has a relatively flat / gradual slope and has not yet experienced a sudden jump in current level indicating a rapid return event.

[0046] Return to reference Figure 2 The discussion states that the actual voltage Vt of the data state of a memory cell fluctuates or jumps. Therefore, although Figure 3 The description refers to VT1 362 and VT2 364 at single voltage values, but in reality, the precise Vt of these two states may fluctuate. Therefore, applying a voltage precisely at the VT1 level to a memory cell programmed in the first state may or may not generate a ripple event based on whether the actual Vt of the first state happens to fluctuate below, at, or above VT1 at the time of application. Similarly, applying a voltage precisely at the VT2 level to a memory cell programmed in the second state may or may not generate a ripple event based on whether the actual Vt of the second state happens to fluctuate below, at, or above VT2 at the time of application.

[0047] The Vt fluctuation associated with each state may have a normal distribution (e.g., Gaussian). The precise distribution programmed for a specific memory cell or group of memory cells for a particular state can be predetermined and established before selecting the voltage value to be applied to the memory cell. Furthermore, returning to the reference... Figure 2 The center Vt value of the first state can be selected from the threshold voltage distribution at the midpoint (e.g., Figure 2The center Vt value 252), which results in the detection of a ripple event 366 50% of the time and the absence of a ripple event 366 50% of the time when the center Vt value of the first state is applied to a memory cell programmed as the first state. Similarly, the center Vt value of the second state can be selected from the threshold voltage distribution at the midpoint (e.g., Figure 2 The central Vt value 256) causes the sudden return event 368 to be detected 50% of the time and not detected 50% of the time when the central Vt value in the second state is applied to the memory cell programmed to the first state.

[0048] Figures 4A-4C This is a graph illustrating examples of prefetch sequences of memory cells associated with generating random data values, consistent with several instances of this disclosure. Regarding... Figures 4A-4C The described components, configuration, and / or operation of the described memory element may include information about Figure 1-3 The components, configurations and / or operations described in 5-6 and / or interchangeable with them. Figures 4A-4C Examples of various prefetch sequences that can be used to generate random data values ​​across various memory array architectures and initial memory cell states, consistent with several examples of this disclosure, may be described.

[0049] For example, Figure 4A This is a graph illustrating an example of a prefetch sequence 470 of a memory cell associated with generating random data values, consistent with several instances of this disclosure. For example, Figure 4A Explanation, for example, 3D XPoint TM An example of a prefetch sequence 470 for a memory cell in memory. For example, Figure 4A This describes an example of a prefetch sequence 470 for a memory cell initially programmed to be in a set state or a low Vt state.

[0050] The prefetch sequence 470 graph illustrates the increase in time on the horizontal axis and the increase in voltage on the vertical axis. The prefetch sequence 470 may correspond to a set of operations used to generate random data values. In some instances, this set of operations may be performed by and / or cause to be performed by, for example... Figure 1 The memory controller 140 depicted herein is used to execute the memory controller. In some instances, the prefetch sequence 470 may be executed by and / or caused by the controller in response to a response from the host, for example... Figure 1 The host 126 described herein executes a request for a random data value.

[0051] The prefetch sequence 470 may differ from a normal or conventional programming sequence. A normal or typical programming sequence may involve performing a prefetch of a memory cell by utilizing Vdm between threshold voltage distributions of possible states stored in the memory cell to determine whether the memory cell is programmed to a first state or a second state corresponding to storing a first data value or a second data value based on the detection of a retrace event. Subsequently, a normal or typical programming sequence may involve, for example, using a 3D XPoint... TM In some instances of memory cells in a memory, a programming pulse at a voltage level higher than the highest reset Vt distribution is applied to program the memory cell to, for example, a reset state, where the reset state is a high Vt state.

[0052] In contrast, the prefetch sequence 470 may include a prefetch operation 472. The prefetch operation 472 may correspond to applying a first voltage value across the memory cell. The memory cell can be programmed to a known data state (e.g., set, reset, 0, 1, high resistance, low resistance, etc.). This could mean that the memory cell has previously been read as storing a known data state during a previous read. It could also mean that the memory cell has been preprogrammed to a known state via a write pulse. For example, a memory cell undergoing prefetch sequence 470 may contain a 3D XPoint. TM Memory cells in memory that are pre-programmed into, for example, a set state or a low Vt state.

[0053] After a memory cell is programmed into a specific state, the corresponding threshold voltage may be somewhat unstable for a period of time after programming. Therefore, the examples considered herein may include time allocation to allow the threshold voltage of the memory cell to drift over a predefined period of time after programming, thereby allowing the threshold voltage distribution to drift and stabilize over time. For example, preprogramming a memory cell into a known state may include stabilizing the threshold voltage of the memory cell by pre-drifting the memory cell pre-programmed into the first state after pre-programming it into the first state and before performing the pre-fetch operation 472 described below.

[0054] The memory cell may have a threshold voltage distribution corresponding to each state. That is, the voltage Vt of the first data state in the memory cell storing the first data state may fluctuate or oscillate within a first voltage value range. The first voltage value range may have a normal distribution corresponding to the threshold voltage distribution of the first state in the memory cell. Furthermore, the voltage Vt of the second data state in the memory cell storing the second data state may fluctuate or oscillate within a second voltage value range. The second voltage value range may have a normal distribution corresponding to the threshold voltage distribution of the second state in the memory cell.

[0055] The threshold voltage distributions corresponding to a first data state in the memory cell and a second data state in the memory cell can be predetermined. For example, the threshold voltage distributions corresponding to the first data state and the second data state can be known and / or defined before the prefetch sequence 470. In some instances, the threshold voltage distributions corresponding to the first data state and the second data state can be determined and / or specified by the manufacturer experimentally before the prefetch sequence 470.

[0056] The prefetch operation 472 can be performed at a first read voltage. When the memory cell is programmed to a first state, the first read voltage can be selected as a first read voltage within a predetermined threshold voltage distribution corresponding to the first state. For example, the first prefetch operation 472 can be performed at a first read voltage corresponding to a 3D XPoint. TM The first read voltage is executed within a predetermined threshold voltage distribution of the set or low Vt data state of the memory cell in the memory.

[0057] The prefetch operation 472 can be performed by applying a first read voltage across the memory cell corresponding to the center of a predetermined threshold voltage distribution programmed to the memory cell and monitoring whether a rush event is detected in response.

[0058] For example, when a memory cell is known to be programmed in a first state, the prefetch operation 472 may involve applying a voltage having a value at the center and / or midpoint of a predetermined threshold voltage distribution corresponding to the first data state of the memory cell storing the first data state. In an example, the memory cell is programmed to be in a set state. The threshold voltage distribution of that particular memory cell storing that particular set state can be predetermined. The prefetch operation 472 may involve applying a voltage from the center or midpoint of the threshold voltage distribution of that particular memory cell storing that particular set state.

[0059] Similarly, when a memory cell is known to be programmed in a second state, the prefetch operation 472 may involve applying a voltage having a value at the center and / or midpoint of a predetermined threshold voltage distribution corresponding to the second data state stored in the memory cell. In an example, the memory cell may be programmed to a reset or high Vt data state. The threshold voltage distribution of the specific memory cell storing that particular reset state may be predetermined. The prefetch operation 472 may involve applying a voltage from the center or midpoint of the threshold voltage distribution of the specific memory cell storing that particular reset state.

[0060] That is, compared with the normal or conventional read operation of a memory cell that utilizes the threshold voltage distribution between possible states stored in the memory cell, an example consistent with this disclosure involves a prefetch operation 472 that utilizes a voltage selected as the center of a distribution of pre-characterized Vt fluctuations in a pre-determined state of data to be stored in the memory cell to perform a prefetch operation.

[0061] As described above, applying a voltage at the center of a pre-characterized distribution of Vt fluctuations, chosen to represent the data state to be stored in a predetermined memory cell, can have the effect of randomly triggering a ripple event. That is, since the actual Vt of the memory cell storing a specific state naturally fluctuates within the pre-characterized distribution, a voltage applied at the center of that distribution can have the effect of triggering a ripple event 50% of the time and not triggering one ripple event 50% of the time. Whether the actual Vt is at, above, or below the voltage at the center of that distribution when applied is a random event.

[0062] Therefore, the voltage applied at the center of the distribution to which the known memory cells are programmed can produce a truly random result for the prefetch operation 472. Unlike Vdm, which utilizes the threshold voltage distributions between possible states stored in the memory cells, the voltage applied at the center of the distribution to which the known memory cells are programmed will not provide sufficient information to distinguish the data states or data values ​​stored in the memory cells with any determinism. Instead, the voltage applied at the center of the distribution of known data states or data values ​​stored in the memory cells will produce a random result corresponding to whether the actual Vt at the time of the prefetch operation 472 is at or below the applied voltage (e.g., proven by detecting a ripple event) or above the applied voltage (e.g., proven by not detecting a ripple event).

[0063] The prefetch sequence 470 may include a programming operation 474. For example, programming operation 474 may include programming a memory cell to a data state different from the data state it stored during prefetch operation 472. For example, if the memory cell is programmed to a set state, then programming operation 474 may include reprogramming the memory cell to a reset state. The prefetch sequence is illustrated as solid line 476.

[0064] However, programming operation 474 can be an optional part of prefetch sequence 470. In some instances, programming operation 474 can be skipped and the memory cell can be left in the data state it was programmed to during prefetch operation 472. For example, if the memory cell is programmed to a set state, then in some examples, programming operation 474 can be skipped and the memory cell can be programmed to a set state. This prefetch sequence is illustrated as dashed line 478.

[0065] Additionally, programming operation 474 can be skipped because, in some instances, the sudden return event itself can place the memory cell in a different data state than the data state stored during prefetch operation 472. For example, as... Figure 4C As explained, programming operation 474 can be skipped because prefetch operation 472 causes a ripple event to occur in the memory cell initially programmed to reset to a high Vt data state. This ripple event can effectively program the memory cell to a low Vt data state at the voltage corresponding to the center of the distribution of the reset state. However, in any case where a ripple event programs the cell, programming operation 474 can be performed to optimize programming to a new data state and / or enhance the electrical uniformity of the Vt distribution among the memory cells with respect to their new data state.

[0066] Controller, for example Figure 1 The controller 140 described herein can be configured to determine whether to perform programming operation 474. For example, the controller can be configured to determine whether to program the memory cell to a first data state corresponding to a first data value or to apply a programming signal to the memory cell, the programming signal being configured to place the memory cell to a second data state corresponding to a second data value based on whether a jog event is detected in prefetch operation 472.

[0067] For example, a memory cell can be programmed to a set state. During a prefetch operation 472, a voltage can be applied across the memory cell. This voltage can be the voltage at the center or midpoint of a predetermined voltage threshold distribution of Vt in the set state of the memory cell. Applying a voltage at this level can generate a randomized ripple event based on whether the actual Vt of the memory cell's set state has jumped to, above, or below the applied voltage during the prefetch operation 472. For example, if a ripple event is detected, the controller can be configured to perform a programming operation 474 by causing a write pulse to be applied to the memory cell to write it from the set state to a reset state. If no ripple event is detected, the controller can be configured to abandon the programming operation 474 and leave the memory cell in the set state.

[0068] However, the examples are not limited to this. For example, consider other examples where detecting a sudden return event has the opposite effect to those described above regarding maintaining or changing the data state of memory cells.

[0069] After prefetch sequence 470, the controller may perform a second read operation. The second read may be performed after a delay following programming operation 474 to allow the threshold voltage distribution time to drift and stabilize after programming and before the second read. The second read operation may involve applying voltage across the memory cell while monitoring for lag events. For example, the second read operation may be performed to determine whether the memory cell is currently programmed to a first data state or a second data state after prefetch sequence 470. For example, the memory cell may be read using a voltage at a typical Vdm level selected between a predetermined threshold voltage distribution of Vt corresponding to the first data state (e.g., set state) and a predetermined threshold voltage distribution of Vt corresponding to the second data state (e.g., reset state) of the memory cell. Thus, reading the memory cell using this Vdm will allow confirmation of the data state of the memory cell after prefetch sequence 470.

[0070] For example, if a quiescent event is detected when a Vdm voltage is applied, this can instruct the memory cell to be programmed into a first data state with a voltage distribution lower than the threshold voltage applied. Alternatively, if no quiescent event is detected when a Vdm voltage is applied, this can instruct the memory cell to be programmed into a second data state with a voltage distribution higher than the threshold voltage applied. For example, detecting a quiescent event when a Vdm voltage is applied can instruct the memory cell to be in a set state. Conversely, not detecting a quiescent event when a Vdm voltage is applied can instruct the memory cell to be in a reset state.

[0071] As described above, the determination of whether to leave the memory cell in the state it was programmed to during the prefetch operation 472 or to a different state is based on whether a ripple event is detected when the voltage is at the center of a predetermined threshold voltage distribution corresponding to the known data state to which the memory cell was programmed. As described above, whether a ripple event will occur when a voltage is applied at the center of the predetermined threshold voltage distribution corresponding to the known data state to which the memory cell was programmed is random. Therefore, determining whether to leave the memory cell in the state it was programmed to during the prefetch operation 472 or to change the result of the second read operation of the memory cell will also be a random output. Thus, the result of the second read operation may correspond to a random data value (e.g., set, reset, 0, 1, low resistance, high resistance, etc.) associated with the state of the memory cell detected during the second read operation.

[0072] The controller can cause a random data value output from the second read operation and / or a data value determined based on the random data value output from the second read operation to be transmitted to the host. For example, the controller can transmit a random data value to the host to fulfill a request for a random data value from the host. The random data value can be used in encryption functions, key generation, encryption, shielding protocols, digital signatures, etc.

[0073] If the host requests more than one random data value, the controller can repeat the described operation to generate additional random data values. For example, the controller can program a memory cell into a first state. The controller can perform another pre-fetch operation on the memory cell using a read voltage within a predetermined threshold voltage distribution corresponding to the first state. For example, the read voltage could be the voltage at the center or midpoint of the predetermined threshold voltage distribution corresponding to the first state. The controller can determine whether to program the memory cell into the first state or the second state based on whether a ripple event is detected during the application of the read voltage. The controller can perform a subsequent read operation by applying a Vdm voltage between the threshold voltage distributions of the first and second states to confirm whether the memory cell is in the first or second state. The controller can then transmit the resulting random data value to the host. This process can be repeated for a single cell the same number of times as required to satisfy the request for the random data value.

[0074] Furthermore, this process can be performed on multiple memory units simultaneously to satisfy requests for random data values ​​more quickly.

[0075] Figure 4B This is a graph illustrating an example of a prefetch sequence 471 of a memory cell associated with generating random data values, consistent with several instances of this disclosure. For example, Figure 4B This illustrates an example of a prefetch sequence 471 for a memory cell of an SSM cell. Figure 4B This describes an example of a prefetch sequence 471 for a memory cell initially programmed to be in a set state or a low Vt state.

[0076] and Figure 4A Similar to the prefetch sequence 470, prefetch sequence 471 may include a prefetch operation 472. Prefetch operation 472 may correspond to applying a first voltage value across the memory cell. The memory cell can be programmed to a known data state (e.g., set, reset, 0, 1, high resistance, low resistance, etc.). This may mean that the memory cell has previously been read as storing a known data state during a previous read. It may also mean that the memory cell has been preprogrammed to a known state via a write pulse. For example, a memory cell undergoing prefetch sequence 471 may contain an SSM cell preprogrammed to, for example, a set state.

[0077] Such as about Figure 4A As described, preprogramming a memory cell to a known state may include stabilizing the threshold voltage of the memory cell by pre-drifting the memory cell preprogrammed to the first state before performing the prefetch operation 472.

[0078] The memory cell may have a threshold voltage distribution corresponding to each state. That is, the voltage Vt of the first data state in the memory cell storing the first data state may fluctuate or oscillate within a first voltage value range. The first voltage value range may have a normal distribution corresponding to the threshold voltage distribution of the first state in the memory cell. Furthermore, the voltage Vt of the second data state in the memory cell storing the second data state may fluctuate or oscillate within a second voltage value range. The second voltage value range may have a normal distribution corresponding to the threshold voltage distribution of the second state in the memory cell. In some instances, the polarities associated with each state may be opposite to each other.

[0079] The threshold voltage distributions corresponding to a first data state in the memory cell and a second data state in the memory cell can be predetermined. For example, the threshold voltage distributions corresponding to the first data state and the second data state can be known and / or defined before the prefetch sequence 471. In some instances, the threshold voltage distributions corresponding to the first data state and the second data state can be determined and / or specified by the manufacturer experimentally before the prefetch sequence 471.

[0080] The prefetch operation 472 can be performed at a first read voltage. When the memory cell is programmed to a first state, the first read voltage can be selected as a first read voltage within a predetermined threshold voltage distribution corresponding to the first state. For example, the first prefetch operation 472 can be performed at a first read voltage within a predetermined threshold voltage distribution corresponding to the set data state of the memory cell in the SSM device.

[0081] The prefetch operation 472 can be performed by applying a first read voltage across the memory cell corresponding to the center of a predetermined threshold voltage distribution programmed to the memory cell and monitoring whether a rush event is detected in response.

[0082] For example, when a memory cell is known to be programmed in a first state, the prefetch operation 472 may involve applying a voltage having a value at the center and / or midpoint of a predetermined threshold voltage distribution corresponding to the first data state stored in the memory cell. In an example, the memory cell is programmed to be in a set state. The threshold voltage distribution of that particular memory cell storing that particular set state can be predetermined. The prefetch operation 472 may involve applying a voltage from the center or midpoint of the threshold voltage distribution of that particular memory cell storing that particular set state.

[0083] Similarly, when a memory cell is known to be programmed to a second state, the prefetch operation 472 may involve applying a voltage having a value at the center and / or midpoint of a predetermined threshold voltage distribution corresponding to the second data state stored in the memory cell. In an example, the memory cell is programmed to a reset data state. The threshold voltage distribution of that particular memory cell storing that particular reset state can be predetermined. The prefetch operation 472 may involve applying a voltage from the center or midpoint of the threshold voltage distribution of that particular memory cell storing that particular reset state. In some instances of memory cells containing an SSM device, the polarity of the threshold voltage distribution and / or midpoint of the reset state may have the opposite polarity to that of the threshold voltage distribution and / or midpoint of the set state.

[0084] As described above, applying a voltage at the center of a pre-characterized distribution of Vt fluctuations, chosen to represent the data state to be stored in a predetermined memory cell, can have the effect of randomly triggering a ripple event. That is, since the actual Vt of the memory cell storing a specific state naturally fluctuates within the pre-characterized distribution, a voltage applied at the center of that distribution can have the effect of triggering a ripple event 50% of the time and not triggering one ripple event 50% of the time. Whether the actual Vt is at, above, or below the voltage at the center of that distribution when applied is a random event.

[0085] Therefore, the voltage applied at the center of the distribution to which the known memory cells are programmed can produce a truly random result for the prefetch operation 472. Unlike Vdm, which utilizes the threshold voltage distributions between possible states stored in the memory cells, the voltage applied at the center of the distribution to which the known memory cells are programmed will not provide sufficient information to distinguish the data states or data values ​​stored in the memory cells with any determinism. Instead, the voltage applied at the center of the distribution of known data states or data values ​​stored in the memory cells will produce a random result corresponding to whether the actual Vt at the time of the prefetch operation 472 is at or below the applied voltage (e.g., proven by detecting a ripple event) or above the applied voltage (e.g., proven by not detecting a ripple event).

[0086] The prefetch sequence 471 may include a programming operation 474. For example, programming operation 474 may include programming a memory cell to a data state different from the data state stored during prefetch operation 472. For example, if the memory cell is programmed to a set state, then programming operation 474 may include reprogramming the memory cell to a reset state. This prefetch sequence is illustrated as solid line 476. As illustrated, programming operation 474 may include applying a programming voltage to a memory cell having a polarity opposite to that of the voltage applied in prefetch operation 472.

[0087] Programming operation 474 may be an optional part of prefetch sequence 470. In some instances, programming operation 474 may be skipped and the memory cell may be left in the data state it was programmed to during prefetch operation 472. For example, if the memory cell is programmed to a set state, then in some instances, programming operation 474 may be skipped and the memory cell may be programmed to a set state. This prefetch sequence is illustrated as dashed line 478.

[0088] Controller, for example Figure 1 The controller 140 described herein can be configured to determine whether to perform programming operation 474. For example, the controller can be configured to determine whether to program the memory cell to a first data state corresponding to a first data value or to apply a programming signal to the memory cell, the programming signal being configured to place the memory cell to a second data state corresponding to a second data value based on whether a jog event is detected in prefetch operation 472.

[0089] For example, a memory cell can be programmed to a set state. In a prefetch operation 472, a voltage can be applied across the memory cell. This voltage can be the voltage at the center or midpoint of a predetermined voltage threshold distribution of Vt in the set state of the memory cell. Applying a voltage at this level can be based on whether the actual Vt of the memory cell's set state has jumped to, above, or below, the applied voltage during the prefetch operation 472 to generate a randomized ripple event. For example, if a ripple event is detected, the controller can be configured to perform a programming operation 474 by causing a write pulse to be applied to the memory cell to write the memory cell from the set state to a reset state. If no ripple event is detected, the controller can be configured to abandon the programming operation 474 and leave the memory cell in the set state. Consider other instances where detecting a ripple event has the opposite effect to those described above regarding maintaining or changing the data state of the memory cell.

[0090] Following prefetch sequence 471, the controller may perform a second read operation. The second read may be performed after a delay following programming operation 474 to allow the threshold voltage distribution time to drift and stabilize after programming and before the second read. The second read operation may involve applying voltage across the memory cell while monitoring for lag events. For example, the second read operation may be performed to determine whether the memory cell is currently programmed to a first data state or a second data state after prefetch sequence 471. For example, the memory cell may be read using a voltage at a typical Vdm level that can be used to distinguish between a predetermined threshold voltage distribution of Vt corresponding to the first data state (e.g., set state) and a predetermined threshold voltage distribution of Vt corresponding to the second data state (e.g., reset state) of the memory cell, and / or otherwise. Thus, using this Vdm to read the memory cell will allow confirmation of the data state of the memory cell after prefetch sequence 471.

[0091] For example, if a quiescent event is detected when a Vdm voltage is applied, this can instruct the memory cell to be programmed into a first data state with a voltage distribution lower than the threshold voltage applied. Alternatively, if no quiescent event is detected when a Vdm voltage is applied, this can instruct the memory cell to be programmed into a second data state with a voltage distribution higher than the threshold voltage applied. For example, detecting a quiescent event when a Vdm voltage is applied can instruct the memory cell to be in a set state. Conversely, not detecting a quiescent event when a Vdm voltage is applied can instruct the memory cell to be in a reset state.

[0092] As described above, the determination of whether to leave the memory cell in the state it was programmed to during the prefetch operation 472 or to a different state is based on whether a ripple event is detected when the voltage is at the center of a predetermined threshold voltage distribution corresponding to the known data state to which the memory cell was programmed. As described above, whether a ripple event will occur when a voltage is applied at the center of the predetermined threshold voltage distribution corresponding to the known data state to which the memory cell was programmed is random. Therefore, determining whether to leave the memory cell in the state it was programmed to during the prefetch operation 472 or to change the result of the second read operation of the memory cell will also be a random output. Therefore, the result of the second read operation may correspond to a random data value (e.g., set, reset, 0, 1, low resistance, high resistance, etc.) associated with the state of the memory cell detected during the second read operation. Figure 4A The method described herein is similar to the method used to output and / or utilize random data values.

[0093] Figure 4C This is a graph illustrating an example of a prefetch sequence 473 of a memory cell associated with generating random data values, consistent with several instances of this disclosure. For example, Figure 4CExplanation, for example, 3D XPoint TM An example of a prefetch sequence 473 for a memory cell of a memory cell and / or an SSM cell. Figure 4C This illustrates an example of a prefetch sequence 473 for a memory cell initially programmed to be in a reset or high Vt state.

[0094] The prefetch sequence 473 graph illustrates the increase in time on the horizontal axis and the increase in voltage on the vertical axis. The prefetch sequence 473 may correspond to a set of operations used to generate random data values. In some instances, this set of operations may be performed by and / or cause to be performed by, for example... Figure 1 The memory controller 140 depicted herein is used to execute this. In some instances, the prefetch sequence 473 may be executed by and / or caused by the controller in response to a response from the host, for example... Figure 1 The host 126 described herein executes a request for a random data value.

[0095] The prefetch sequence 473 may differ from a normal or conventional programming sequence. A normal or typical programming sequence may involve performing a prefetch of the memory cell by utilizing Vdm between threshold voltage distributions of possible states stored in the memory cell to determine whether the memory cell is programmed to a first state or a second state corresponding to storing a first data value or a second data value based on the detection of a retrace event. Subsequently, a normal or typical programming sequence may involve programming the memory cell to, for example, a reset state by applying a programming pulse at an appropriate level and / or polarity of voltage.

[0096] The prefetch sequence 473 may include a prefetch operation 472. The prefetch operation 472 may correspond to applying a first voltage value across the memory cell. The memory cell can be programmed to a known data state (e.g., set, reset, 0, 1, high resistance, low resistance, etc.). This could mean that the memory cell has previously been read as storing a known data state during a previous read. It could also mean that the memory cell has been preprogrammed to a known state via a write pulse. For example, a memory cell undergoing prefetch sequence 470 may contain a 3D XPoint. TM Memory cells in memory and / or SSM devices pre-programmed with states such as a reset state. In some instances, the reset state may be a Vt state higher than the set state. In some instances, the reset state may have the opposite polarity to the set state.

[0097] After a memory cell is programmed into a specific state, the corresponding threshold voltage may be somewhat unstable for a period of time after programming. Therefore, the examples considered herein may include time allocation to allow the threshold voltage of the memory cell to drift over a predefined time period after programming, thereby allowing the threshold voltage distribution to drift over time and stabilize. For example, preprogramming a memory cell into a known state may involve stabilizing the threshold voltage of the memory cell by pre-drifting the memory cell pre-programmed into the specific state after pre-programming it into that state and before performing the pre-fetch operation 472 described below.

[0098] The memory cell may have a threshold voltage distribution corresponding to each state. That is, the Vt of the reset data state in the memory cell storing the reset data state may fluctuate or oscillate within a first voltage value range. The first voltage value range may have a normal distribution corresponding to the threshold voltage distribution of the reset state in the memory cell. As mentioned, in some instances, the threshold voltage distribution of the reset state may have a negative polarity and / or a polarity opposite to that of the threshold voltage distribution of the set state. In some instances, the threshold voltage distribution of the reset state may be associated with a voltage higher than that of the threshold voltage distribution of the set state. Furthermore, the Vt of the set data state in the memory cell storing the set data state may fluctuate or oscillate within a second voltage value range. The second voltage value range may have a normal distribution corresponding to the threshold voltage distribution of the set state in the memory cell. Moreover, the threshold voltage distribution of each data state of the memory cell may be predetermined before the prefetch sequence 473.

[0099] The prefetch operation 472 can be performed at a reset read voltage. When a memory cell is programmed to a reset data state, the reset read voltage can be selected as a read voltage within a predetermined threshold voltage distribution corresponding to the reset state. For example, the first prefetch operation 472 can be performed at a read voltage corresponding to a 3D XPoint. TM The reset read voltage is executed within a predetermined threshold voltage distribution of the reset data state of the memory and / or memory cell in the SSM.

[0100] The prefetch operation 472 can be performed by applying a reset read voltage across the memory cells, corresponding to the center of a predetermined reset threshold voltage distribution programmed to the memory cells, and monitoring whether a sudden return event is detected in response.

[0101] For example, when a memory cell is known to be programmed to a reset state, the prefetch operation 472 may involve applying a voltage having a value at the center and / or midpoint of a predetermined threshold voltage distribution corresponding to the reset data state stored in the memory cell. In this example, the memory cell is programmed to a reset state. The threshold voltage distribution of that particular memory cell storing that particular reset state can be predetermined. The prefetch operation 472 may involve applying a voltage from the center or midpoint of the threshold voltage distribution of that particular memory cell storing that particular reset state.

[0102] That is, compared with the normal or conventional read operation of a memory cell that utilizes the threshold voltage distribution between possible states stored in the memory cell, an example consistent with this disclosure involves a pre-read operation 472, which utilizes a voltage selected to be at the center of a pre-characterized distribution of Vt fluctuations in a pre-determined data state to be stored in the memory cell to perform a pre-read operation.

[0103] As described above, applying a voltage at the center of a pre-characterized distribution of Vt fluctuations, chosen to represent the data state to be stored in a predetermined memory cell, can have the effect of randomly triggering a ripple event. That is, since the actual Vt of the memory cell storing a specific state naturally fluctuates within the pre-characterized distribution, a voltage applied at the center of that distribution can have the effect of triggering a ripple event 50% of the time and not triggering one ripple event 50% of the time. Whether the actual Vt is at, above, or below the voltage at the center of that distribution when applied is a random event.

[0104] Therefore, the voltage applied at the center of the distribution to which the known memory cells are programmed can produce a truly random result for the prefetch operation 472. Unlike Vdm, which utilizes the threshold voltage distributions between possible states stored in the memory cells, the voltage applied at the center of the distribution to which the known memory cells are programmed will not provide sufficient information to distinguish with any determinism the data state or data value stored in the memory cells. Instead, the voltage applied at the center of the distribution of known data states or data values ​​stored in the memory cells will produce a random result corresponding to whether the actual Vt at the time of the prefetch operation 472 is at or below the applied voltage (e.g., demonstrated by the detection of a ripple event) or above the applied voltage (e.g., demonstrated by the absence of a ripple event).

[0105] Although the preread sequence may optionally include information about Figures 4A-4BThe programming operations described are similar to those described above, but prefetch sequence 473 is described as not involving such a programming operation. For example, it should be understood that a programming operation with appropriate voltage level and / or polarity can be applied to a memory cell to refresh its reset state and / or change the programmed data state of the memory cell to a set state. However, in some instances, a backlash event itself can place a memory cell in a data state different from the data state it stored during prefetch operation 472. For example, the programming operation can be skipped because prefetch operation 472 causes a backlash event to occur in a memory cell initially programmed to a reset high Vt data state, which can actually be programmed to a set data state by the backlash event at a voltage corresponding to the center of the distribution of the reset data state. That is, a backlash event may cause a change in the physical / electrical properties of the memory cell so that the data state of the memory cell no longer corresponds to the reset state, but now corresponds to the set state. However, in any case involving a backlash event reprogramming the cell, a programming operation can be performed to optimize the programming to the new data state and / or enhance the electrical uniformity of the Vt distribution of the new data state among the memory cells.

[0106] Controller, for example Figure 1 The controller 140 described herein can be configured to determine whether to perform a programming operation. For example, the controller can be configured to determine whether to program a memory cell to a reset data state corresponding to a reset data value or to apply a programming signal to a memory cell configured to program and / or refresh the memory cell to a set data state corresponding to a set data value based on whether a jog event is detected in the prefetch operation 472.

[0107] For example, a memory cell can be programmed to a reset state. During a prefetch operation 472, a voltage can be applied across the memory cell. This voltage can be the voltage at the center or midpoint of a predetermined voltage threshold distribution of Vt in the reset state of the memory cell. Applying a voltage at this level can be based on whether the actual Vt of the memory cell's reset state has jumped to, above, or below, the applied voltage during the prefetch operation 472 to generate a randomized ripple event. For example, if a ripple event is detected, the controller can be configured to perform a programming operation by causing a write pulse to be applied to the memory cell to write the memory cell from the reset state to the set state. Alternatively, and as... Figure 4C As explained, a memory cell that experiences a ripple event may not require programming, as the ripple event itself may be sufficient to reprogram the memory cell from a reset state to a set state. If no ripple event is detected, the controller can be configured to abandon programming and leave the memory cell in a reset state.

[0108] Following prefetch sequence 473, the controller may perform a second read operation. The second read may be performed after a delay to allow the threshold voltage distribution time to drift and stabilize after programming and before the second read. The second read operation may involve applying voltage across the memory cell while monitoring for lag events. For example, the second read operation may be performed to determine whether the memory cell is currently programmed to a reset data state or a set data state after prefetch sequence 473. For example, the memory cell may be read using a voltage at a typical Vdm level selected between a predetermined threshold voltage distribution of Vt corresponding to the reset data state of the memory cell and a predetermined threshold voltage distribution of Vt corresponding to the reset data state of the memory cell. Thus, reading the memory cell using this Vdm will allow confirmation of the data state of the memory cell after prefetch sequence 473.

[0109] For example, if a ripple event is detected when the Vdm voltage is applied, this may indicate that the memory cell is programmed to a set data state. Alternatively, if no ripple event is detected when the Vdm voltage is applied, this may indicate that the memory cell is programmed to a reset data state. For example, detecting a ripple event when the Vdm voltage is applied may indicate that the memory cell is in a set state. Conversely, not detecting a ripple event when the Vdm voltage is applied may indicate that the memory cell is in a reset state.

[0110] As described above, whether a ripple event will occur when a voltage is applied at the center of a predetermined threshold voltage distribution corresponding to the data state to which a known memory cell is programmed is random. Therefore, determining whether to leave the memory cell in its programmed state during prefetch operation 472 or to change the result of the second read operation will also be a random output. Thus, the result of the second read operation may correspond to a random data value (e.g., set, reset, 0, 1, low resistance, high resistance, etc.) associated with the state of the memory cell detected during the second read operation. This can be related to... Figure 4A The method described herein is similar to the method used to output and / or utilize random data values.

[0111] Figure 5 This is an illustration of an example of a memory array 580 associated with generating random data values, consistent with several instances of this disclosure. Regarding Figure 5 The described components, configuration, and / or operation of the described memory element may include information about Figure 1 -The components, configurations and / or operations described in any of the others in -4 and 6 are interchangeable with them.

[0112] The memory array 580 may include multiple interconnected memory cells 582-1…582-N. The memory cells 582-1…582-N may be logically and / or physically organized into groups to generate random data values ​​in a manner consistent with several instances of this disclosure. For example, the memory cells 582-1…582-N may be grouped together into physical and / or logical groups 584-1, 584-2, 584-3, and 584-N.

[0113] Each group 584-1, 584-2, 584-3, and 584-N may contain multiple memory cells 582-1…582-N of the array. For example, the first group 584-1 may contain memory cells 582-1, 582-2, 582-5, and 582-6. The second group 584-2 may contain memory cells 582-3, 582-4, 582-7, and 582-8. The third group 584-3 may contain memory cells 582-9, 582-10, 582-13, and 582-14. The fourth group 584-N may contain memory cells 582-11, 582-12, 582-15, and 582-N.

[0114] Groups 584-1…584-N can operate as individual random data value generation components (e.g., zones) and / or as individual components of individual random data value generation components.

[0115] Memory cells 582-1…582-N can be grouped based on their respective predetermined threshold voltage distributions. For example, a controller, such as… Figure 1 The controller 140 can be configured to group memory cells into groups 584-1, 584-2, 584-3, and 584-N based on the similarity between their respective predetermined threshold voltage distributions. For example, memory cells 582-1, 582-2, 582-5, and 582-6 can be determined to have highly similar (e.g., within a threshold amount) and / or identical predetermined threshold voltage distributions corresponding to their data states. Therefore, memory cells 582-1, 582-2, 582-5, and 582-6 can be grouped into the same group (e.g., the first group 584-1).

[0116] Memory cells 582-3, 582-4, 582-7, and 582-8 can be determined to have highly similar (e.g., within a threshold amount) and / or identical predetermined threshold voltage distributions corresponding to their data states. These cells may have predetermined threshold voltage distributions that are sufficiently different (e.g., beyond a threshold amount) from those memory cells in the first group 584-1 corresponding to their data states. Therefore, memory cells 582-3, 582-4, 582-7, and 582-8 may be grouped into the same group (e.g., the second group 584-2).

[0117] Memory cells 582-9, 582-10, 582-13, and 582-14 can be determined to have highly similar (e.g., within a threshold amount) and / or identical predetermined threshold voltage distributions corresponding to their data states. These cells may have predetermined threshold voltage distributions that are sufficiently different (e.g., beyond a threshold amount) from those memory cells in the first group 584-1 and the second group 584-2 corresponding to their data states. Therefore, memory cells 582-9, 582-10, 582-13, and 582-14 may be grouped into the same group (e.g., the third group 584-3).

[0118] Memory cells 582-11, 582-12, 582-15, and 582-N can be determined to have highly similar (e.g., within a threshold amount) and / or identical predetermined threshold voltage distributions corresponding to their data states. These cells may have predetermined threshold voltage distributions corresponding to their data states that are sufficiently different (e.g., beyond a threshold amount) from those memory cells in the first group 584-1, the second group 584-2, and / or the third group 584-3. Therefore, memory cells 582-11, 582-12, 582-15, and 582-N may be grouped into the same group (e.g., the fourth group 584-N).

[0119] Therefore, the constituent memory cells 582-1…582-N of each group 584-1…584-N can share a common threshold voltage distribution corresponding to their data states. Thus, all memory cells within a specific group can be used to simultaneously generate multiple random data values. Specifically, all multiple memory cells within a specific group can be programmed into a specific state known prior to the prefetch sequence. Then, as part of the prefetch operation, the same voltage corresponding to the state to which the cells are programmed, passing through the center or midpoint of the shared threshold voltage distribution, can be applied to all multiple memory cells within the specific group. Those cells in the group that exhibit a lag event during the prefetch operation can be programmed into different states, while those cells that do not exhibit a lag event during the prefetch operation can be left in their same state. A Vdm can be applied between the threshold voltage distributions of the first and second states of the memory cells, and the resulting output can be used as multiple simultaneously generated random data values.

[0120] Each of the memory cell groups 584-1…584-N can utilize different threshold voltage distributions corresponding to the data states constituting their respective memory cells. That is, while memory cells within a particular group may have a common predetermined threshold voltage distribution corresponding to their data states, memory cells in another group may have different common predetermined threshold voltage distributions corresponding to their data states. Thus, different applied voltages can be used for each of the memory cell groups 584-1…584-N. As described above, the outputs of operations on these various groups according to embodiments consistent with this disclosure can be combined and output as random data values.

[0121] Figure 6 This is a diagram illustrating the threshold voltage distribution 690 of the data states of a group of memory cells that does not share a common predetermined threshold voltage distribution corresponding to their data states, consistent with several instances of this disclosure. Regarding... Figure 6 The described components, configuration, and / or operation of the described memory element may include information about Figure 1-5 Any other component, configuration and / or operation described therein and / or interchangeable with it.

[0122] As described above, for the purpose of generating random data values ​​consistent with several instances of this disclosure, memory cells in an array may be grouped based on a predetermined threshold voltage distribution having highly similar and / or identical data states corresponding to them. However, in some instances, memory cells that do not share a common predetermined threshold voltage distribution corresponding to their data states may be grouped together.

[0123] When memory cells with different centers having threshold voltage distribution values ​​are grouped together, the resulting threshold voltage distribution of group 690 may have a non-normal (non-Gaussian) distribution. For example, the group may contain two (or more) different memory cells. Each of the memory cells may have a corresponding threshold voltage distribution for a specific state.

[0124] For example, the first memory cell may have a first threshold voltage distribution 694 for a specific state. The first memory cell may have a first center or midpoint voltage amount 692 of the first threshold voltage distribution 694. That is, consistent with the above examples of this disclosure, the midpoint voltage amount 692 may correspond to a threshold or read voltage that, when applied to a first memory cell programmed to a specific state and having the first threshold voltage distribution 694, will produce a ripple event or a ripple event that is not approximately random.

[0125] The second memory cell may have a second threshold voltage distribution 698 for a specific state. The second memory cell may have a second center or midpoint voltage amount 696 of the second threshold voltage distribution 698. That is, consistent with the above examples of this disclosure, the midpoint voltage amount 696 may correspond to a threshold or read voltage that, when applied to a second memory cell programmed to a specific state and having the second threshold voltage distribution 698, will generate a ripple event or generate a ripple event that is not approximately random.

[0126] When grouped together, the resulting threshold voltage distribution of group 690 may have a non-normal (non-Gaussian) distribution. Furthermore, using one of the center or midpoint voltage values ​​(e.g., first center or midpoint voltage value 692, second center or midpoint voltage value 696, etc.) with the resulting threshold voltage distribution of group 690 can generate ripple events in a non-random manner. For example, if the first center or midpoint voltage value 692 is used in a prefetch operation of a memory cell in the first group, a skewness in the amount of detected ripple events may occur. For instance, a prefetch operation may generate a ripple event 30% of the time and may not generate a ripple event 70% of the time.

[0127] To address this skew, a bias can be applied to the group. For example, the voltage under which a prefetch operation is performed on the group can be biased (e.g., higher, lower, etc.) to achieve a voltage closer to the center or midpoint of the threshold voltage distribution of group 690. That is, a new voltage under which a prefetch operation is performed on the group can be selected to produce the most random result from the prefetch operation. In the example given above, the voltage applied during the prefetch operation can be shifted upward from the first center or midpoint voltage amount 692 of the first threshold voltage distribution 694 to a new voltage amount between the first center or midpoint voltage amount 692 of the first threshold voltage distribution 694 and the second center or midpoint voltage amount 696 of the second threshold voltage distribution 698.

[0128] Alternatively and / or additionally, a bias can be applied at the back end to adjust for non-random skew caused by different centers of the threshold voltage distribution values ​​within the group. For example, the data value of the second read output from the memory cell after the prefetch sequence can be changed to bias the output back to random. In the example given above, 20% of the output due to the inability to detect a sudden return event and leaving the memory cell in its prefetch data state can be changed to another data state value to restore a 50% to 50% distribution in the output.

[0129] The above-described biasing mechanism, along with other biasing mechanisms, is equally applicable when attempting to mix different groups of memory cells and / or their outputs together.

[0130] Although specific embodiments have been illustrated and described herein, those skilled in the art will understand that arrangements calculated to achieve the same results may replace the specific embodiments shown. This disclosure is intended to cover adaptations or variations of the various embodiments of this disclosure. It should be understood that the above description is illustrative rather than restrictive. After reviewing the above description, combinations of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art. The scope of the various embodiments of this disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of the various embodiments of this disclosure should be determined by reference to the appended claims and the full scope of their equivalents.

[0131] In the foregoing detailed embodiments, various features are grouped in a single embodiment for the purpose of simplifying this disclosure. This disclosure method should not be construed as reflecting an intention that the disclosed embodiments of this disclosure must use more features than are expressly stated in each claim. Rather, as reflected in the appended claims, the subject matter of the invention lies in fewer than all features of a single disclosed embodiment. Therefore, the appended claims are thus incorporated into the detailed embodiments, wherein each claim is considered an independent, separate embodiment.

Claims

1. A method for generating random data values, comprising: A first read operation is performed on a plurality of memory cells (582-1…582-N) programmed to a first state corresponding to a first data value, wherein the first read operation is performed using a first read voltage (252, 256) within a predetermined threshold voltage distribution (254-1, 254-2) corresponding to the first state; and A second read operation is performed using a second read voltage (250, 350) between the predetermined threshold voltage distribution corresponding to the first state and the second threshold voltage distribution corresponding to the second state and the second data value, to determine whether each of the plurality of memory cells is in the first state or the second state. The result of the second read operation corresponds to the random data value based on the threshold voltage of each of the plurality of memory cells during the first read operation.

2. The method according to claim 1, wherein the method further comprises: A programming signal is applied to the portions of the plurality of memory cells based on whether the first read operation causes a sudden return event (366, 368) at a first portion of the plurality of memory cells, wherein the programming signal is configured to place each of the first portions of the plurality of memory cells in the second state.

3. The method of claim 2, wherein the method further comprises, after performing the second read operation: The plurality of memory cells are programmed to the first state; A third read operation is performed on the plurality of memory cells using the read voltage within the predetermined threshold voltage distribution corresponding to the first state; In response to the third read operation on the memory cell causing a sudden return event (366, 368), a subsequent programming signal is applied to a second portion of the plurality of memory cells, wherein the subsequent programming signal is configured to place each of the second portions of the plurality of memory cells in a second state corresponding to the second data value; and The second read voltage is used to perform a fourth read operation to determine whether each of the plurality of memory cells is in the first state or the second state.

4. The method according to claim 2, wherein the method further comprises: The programming signal is avoided being applied to the memory cell in response to the first read operation not causing a sudden return event (366, 368).

5. The method according to any one of claims 1 to 4, wherein the method further comprises: The predetermined threshold voltage distribution corresponding to the first state is determined based on multiple programming and reading operations.

6. The method according to any one of claims 1 to 4, wherein the method further comprises: The voltage at the center of the predetermined threshold voltage distribution corresponding to the first state is selected as the first read voltage; and The threshold voltage of each of the plurality of memory cells programmed into the first state is stabilized by pre-drifting the plurality of memory cells after they have been pre-programmed into the first state and before the first read operation is performed.

7. An apparatus for generating random data values, comprising: An array (130, 580) of memory cells (582-1…582-N), each of which is programmable to a first state corresponding to a first data value and a second state corresponding to a second data value; and A controller (140), coupled to the array and configured to generate a random one of the first data value and the second data value, by: A first read voltage (252, 256) is applied to a memory cell programmed to the first state, wherein the memory cell programmed to the first state has a predetermined threshold voltage distribution (254-1, 254-2) associated with the first state, and wherein the first read voltage has a value selected to be within the predetermined threshold voltage distribution; In response to a sudden return event (366, 368) caused by the applied first read voltage, a programming signal is applied to the memory cell, wherein the programming signal is configured to place the memory cell in a second state corresponding to a second data value; and A second read voltage (250, 350) is applied to the memory cell to determine whether the memory cell is in the first state or the second state, wherein the second read voltage is not within the predetermined threshold voltage distribution associated with the first state; The randomized value generated from the first data value and the second data value is based on the threshold voltage of the memory cell after the first read voltage is applied to the memory cell.

8. The device of claim 7, wherein the value of the first read voltage is selected to be at the center of the predetermined threshold voltage distribution in the first state.

9. The device of claim 8, wherein the detection of the retracement event in response to the applied first read voltage serves as an indication of whether the threshold voltage of the memory cell programmed to the first state is higher or lower than the value of the first read voltage.

10. The device of claim 8, wherein the center of the predetermined threshold voltage distribution in the first state is the center of the threshold voltage distribution in the first state as biased to account for variations in the threshold voltage distribution across a portion of a plurality of cells in the memory cell array.

11. The device according to any one of claims 7 to 10, wherein the memory cell is a variable resistance memory cell.

12. The device according to any one of claims 7 to 10, wherein the memory unit comprises a chalcogenide material serving as a storage element of the memory unit.

13. The device according to any one of claims 7 to 10, wherein the first state is a set state and the second state is a reset state.

14. The device according to any one of claims 7 to 10, wherein the controller is further configured to provide the generated randomizer of the first data value and the second data value to the host (126).

15. The device according to any one of claims 7 to 10, wherein the controller is further configured to generate the random one of the first data value and the second data value in response to a request from the host (126).

16. A system for generating random data values, comprising: An array (130, 580) of memory cells (582-1…582-N), each of which is programmable to a first state corresponding to a first data value and a second state corresponding to a second data value; and A controller (140), coupled to the array and configured to generate a random one of the first data value and the second data value, by: A first read voltage (252, 256) is applied to a memory cell programmed to the first state, wherein the memory cell programmed to the first state has a predetermined threshold voltage distribution (254-1, 254-2) associated with the first state, and wherein the first read voltage has a value selected at the center of the predetermined threshold voltage distribution. Based on whether a retracement event (366, 368) indicating the value of a threshold voltage of the memory cell relative to the first read voltage is detected in response to the application of the first read voltage, it is determined whether to program the memory cell to the first state or to apply a programming signal to the memory cell, the programming signal being configured to place the memory cell in a second state corresponding to a second data value; and A second read voltage (250, 350) is applied to the memory cell to determine whether the memory cell is in the first state or the second state, wherein the second read voltage is not within the predetermined threshold voltage distribution associated with the first state. The randomized individual generated from the first data value and the second data value is determined based on the threshold voltage of the memory cell relative to the first read voltage, as confirmed by applying the second read voltage.

17. The system of claim 16, wherein the controller is configured to: The memory cell is grouped together with other memory cells in the memory cell array, the other memory cells having the same value at the center of the predetermined threshold voltage distribution of the memory cell programmed into the first state at the corresponding center of their respective predetermined threshold voltage distribution; The first data value and a random one of the second data values ​​are generated from each of the other memory cells of the array based on whether the application of the first read voltage to each of the other memory cells causes a corresponding sync event.

18. The system of claim 16, wherein the controller is configured to: Group the memory cells with other memory cells in the array that are programmed to the first state; The first data value and a random one of the second data values ​​are generated from each of the other memory cells in the array based on the following: Whether the application of the first read voltage to each of the other memory cells results in a corresponding retrace event; and A bias is applied to adjust the non-random skew caused by the different centers of the threshold voltage distribution values ​​in the memory cells and the other memory cells.

19. The system of claim 16, wherein the controller is configured to: The first part of the memory cell array is divided into a first group (584-1…584-N) based on the memory cell and a first plurality of other memory cells programmed to the first state having the same threshold voltage distribution value. The first part includes the memory cell and the first plurality of other memory cells. The second part of the memory cell array is divided into a second group (584-1…584-N) based on a second center that has the same threshold voltage distribution value for a second plurality of other memory cells programmed to the first state. The second part contains the second plurality of other memory cells. The first read voltage is used to generate a random one of the first data values ​​and the second data values ​​from each of the first plurality of other memory cells of the array based on whether the application of the first read voltage to each of the first plurality of other memory cells results in a corresponding retrace event; and A third read voltage is used to generate a first data value and a random one of the second data values ​​from each of the second plurality of other memory cells in the array based on whether the application of the third read voltage to each of the second plurality of other memory cells results in a corresponding retrace event. The third read voltage has the same second center value selected as the threshold voltage distribution value among the second plurality of other memory cells.

20. The system according to any one of claims 16 to 19, wherein the controller is configured to combine the generated random number of the first data value and the second data value into an encryption function.

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