Apparatus and method for programming and verifying data in a non-volatile memory device

Abstract

The present application relates to apparatuses and methods of programming and verifying data in a non-volatile memory device. The memory device includes a cell group including a plurality of non-volatile memory cells capable of storing data, and a control circuit configured to perform a plurality of programming cycles for storing the data, each programming cycle including a program voltage application operation and a verify operation. During a respective programming cycle, the control circuit performs the verify operation for an N target level, an N-1 target level lower than the N target level, and an N+1 target level higher than the N target level in response to the program voltage application operation for the N target level. When a number of non-volatile memory cells having a threshold voltage exceeding the N+1 target level satisfies a preset criterion, the control circuit skips a next verify operation for a target level lower than the N+1 target level in response to a next program voltage application operation for the N+1 target level.

Description

Technical Field

[0001] One or more embodiments described herein relate to memory systems, and more particularly to apparatus and methods for improving the speed of data input / output operations in non-volatile memory devices within memory systems. Background Technology

[0002] Recently, the paradigm of computing environments has shifted to ubiquitous computing, making computer systems accessible almost anytime, anywhere. As a result, the use of portable electronic devices (e.g., mobile phones, digital cameras, laptops, etc.) is rapidly increasing. Each such portable electronic device may use or include a memory system with at least one memory device. The memory system may be a data storage device. The data storage device may serve as the primary or secondary storage device of the portable electronic device.

[0003] Unlike hard drives, this type of data storage device uses non-volatile semiconductor memory, exhibiting greater stability and durability. It lacks mechanical drive components (e.g., robotic arms) and therefore offers high data access speeds and relatively low power consumption. Examples of data storage devices with these advantages include, but are not limited to, Universal Serial Bus (USB) memory devices, memory cards with various interfaces, solid-state drives (SSDs), and the like. Summary of the Invention

[0004] Embodiments of this disclosure may provide a data processing system and a method for operating the data processing system. The data processing system includes components and resources such as a memory system and a host, and is capable of dynamically allocating multiple data paths for data communication between components based on the usage of the components and resources.

[0005] Embodiments of this disclosure may provide apparatus and methods for improving the data input / output speed of memory devices included in a data processing system.

[0006] In one embodiment, a memory device may include: a cell group comprising a plurality of non-volatile memory cells capable of storing data; and control circuitry configured to execute a plurality of programming cycles for storing data, each programming cycle including a programming voltage application operation for the plurality of non-volatile memory cells and a verification operation corresponding to the programming voltage application operation. The control circuitry may be configured to, during a respective programming cycle, perform verification operations for a target level of N, a target level of N-1 below N, and a target level of N+1 above N, in response to a programming voltage application operation for a target level of N. When the number of non-volatile memory cells having a threshold voltage exceeding the target level of N+1 meets a preset criterion, the control circuitry is configured to skip the next verification operation for a target level below N+1 in response to a next programming voltage application operation for the target level of N+1.

[0007] The number of target levels corresponding to multiple programming loops is three times the number of bits of data to be stored in each of the multiple non-volatile memory cells.

[0008] The control circuit can be configured to perform a verification operation corresponding to the programming voltage application operation by applying a first voltage to the selected word line for a first verification operation for a target level of N+1 and applying a second voltage lower than the first voltage to the selected word line for a second verification operation for a target level of N-1 and a target level of N.

[0009] The control circuit can be configured to precharge bit lines connected to multiple non-volatile memory cells before the first and second verification operations.

[0010] The control circuit can be configured to perform a verification operation corresponding to a programming voltage application operation by applying a first voltage to the selected word line for a first verification operation for a target level of N+1 and a second verification operation for a target level of N-1 or N. The control circuit is configured to perform the first verification operation for a longer period than the second verification operation.

[0011] The control circuitry can be configured to precharge the bit lines connected to multiple non-volatile memory cells prior to the first verification operation.

[0012] The control circuit changes or adjusts preset standards based on the programming / erase cycles of multiple non-volatile memory cells.

[0013] In another embodiment, the memory system may include: a controller configured to determine a location for storing programming data and transmit programming commands along with the programming data; and a memory device coupled to the controller via a data path and configured to receive programming commands and programming data and output success or failure of a programming operation against the programming data. The memory device may include: at least one memory block comprising a plurality of non-volatile memory cells capable of storing programming data; and control circuitry configured to execute a plurality of programming cycles for storing programming data in at least some of the non-volatile memory cells coupled to a selected word line in the at least one memory block, each programming cycle including a programming voltage application operation and a verification operation corresponding to the programming voltage application operation. The control circuitry may be configured to perform verification operations for a target level of N, a target level of N-1 below the target level, and a target level of N+1 above the target level, in response to a programming voltage application operation for a target level of N, during the respective programming cycle. When the number of non-volatile memory cells having a threshold voltage exceeding the N+1 target level among at least some of the non-volatile memory cells meets a preset criterion, the control circuit is configured to skip the next verification operation for a target level below the N+1 target level in response to the application of the next programming voltage for the N+1 target level.

[0014] The memory device may include: a buffer configured to temporarily store programming data to be stored in the location; and a voltage supply circuit controlled by a control circuit to apply a first voltage to the selected word line and a second voltage having a different level from the first voltage to the unselected word line.

[0015] The number of target levels corresponding to multiple programming cycles is three times the number of bits of programming data to be stored in each of the multiple non-volatile memory cells.

[0016] The control circuit can be configured to perform a verification operation corresponding to the programming voltage application operation by applying a first voltage to the selected word line for a first verification operation for a target level of N+1 and applying a second voltage lower than the first voltage to the selected word line for a second verification operation for a target level of N-1 and a target level of N.

[0017] The control circuit can be configured to precharge bit lines connected to at least some non-volatile memory cells before the first verification operation and the second verification operation.

[0018] The control circuit can be configured to perform a verification operation corresponding to a programming voltage application operation by applying a first voltage to the selected word line for a first verification operation for a target level of N+1 and a second verification operation for a target level of N-1 or N. The control circuit is configured to perform the first verification operation for a longer period than the second verification operation.

[0019] The control circuitry can be configured to precharge bit lines connected to at least some non-volatile memory cells prior to the first verification operation.

[0020] The control circuit changes or adjusts preset standards based on the programming / erase cycles of multiple non-volatile memory cells.

[0021] In another embodiment, a method for operating a memory device may include: receiving programming data, information about the location for storing the programming data, and a programming command; selecting a word line corresponding to the information about the location; and performing a plurality of programming cycles for storing the programming data in at least a plurality of non-volatile memory cells coupled to the selected word line, each programming cycle including a programming voltage application operation for the plurality of non-volatile memory cells and a verification operation corresponding to the programming voltage application operation. Performing the plurality of programming cycles may include: during a respective programming cycle, performing verification operations for a target level of N, a target level of N-1 below the target level, and a target level of N+1 above the target level in response to a programming voltage application operation for a target level of N; determining whether the number of non-volatile memory cells having a threshold voltage exceeding the target level of N+1 among the at least a plurality of non-volatile memory cells meets a preset criterion; and based on the determination result, skipping the next verification operation for a target level below the target level in response to a next programming voltage application operation for the target level of N+1.

[0022] Performing a verification operation may include: for a first verification operation targeting an N+1 target level, applying a first voltage to the selected word line; and for a second verification operation targeting both an N-1 target level and an N target level, applying a second voltage lower than the first voltage to the selected word line.

[0023] Performing the verification operation may further include: pre-charging bit lines connected to at least some non-volatile memory cells before the first verification operation; and pre-charging bit lines connected to at least some non-volatile memory cells before the second verification operation.

[0024] Performing a verification operation may include applying a first voltage to word lines connected to at least some non-volatile memory cells for a first verification operation targeting an N+1 target level and a second verification operation targeting an N-1 target level or an N target level. The first verification operation may take longer than the second verification operation.

[0025] Performing the verification operation may further include pre-charging the bit lines connected to at least some non-volatile memory cells prior to the first verification operation.

[0026] In another embodiment, a method of operating a memory device may include: executing a plurality of programming cycles, each programming cycle including a first operation and a second operation according to an Incremental Step Pulse Programming (ISPP) scheme, wherein the first operation within the current programming cycle includes an operation of applying a programming voltage to a selected word line to give at least one memory cell connected to the selected word line a programming state of a current target level, and wherein the second operation within the current programming cycle includes an operation of verifying whether the memory cell connected to the selected word line has a programming state of the current target level and a higher target level when the at least one memory cell connected to the selected word line has been verified to have a programming state of the current target level in a previous programming cycle. Attached Figure Description

[0027] The description herein refers to the accompanying drawings, in which similar reference numerals refer to similar parts throughout the drawings.

[0028] Figure 1 A memory device according to an embodiment of the present disclosure is illustrated.

[0029] Figure 2 A data processing system according to an embodiment of the present disclosure is illustrated.

[0030] Figure 3 An incremental step pulse programming (ISPP) operation according to an embodiment of the present disclosure is illustrated.

[0031] Figure 4 A method for storing multiple bits of data in a non-volatile memory cell according to an embodiment of the present disclosure is illustrated.

[0032] Figure 5 The programming and verification operations of the ISPP operation according to embodiments of the present disclosure are illustrated.

[0033] Figure 6 The target level corresponding to a plurality of programming pulses according to an embodiment of the present disclosure is illustrated.

[0034] Figure 7 A first example of a method for operating a memory device according to an embodiment of the present disclosure is illustrated.

[0035] Figure 8 The variation of the threshold voltage distribution in a programming operation according to an embodiment of the present disclosure is illustrated.

[0036] Figure 9A and Figure 9B An improved programming operation and verification operation according to an embodiment of the present disclosure are illustrated.

[0037] Figure 10A second example of a method for operating a memory device according to an embodiment of the present disclosure is illustrated.

[0038] Figure 11 Verification operations according to embodiments of this disclosure are illustrated.

[0039] Figure 12 An example is given of the improved performance obtained by a method for operating a memory device according to an embodiment of the present disclosure. Detailed Implementation

[0040] Various embodiments of the present disclosure are described below with reference to the accompanying drawings. However, the elements and features of the present disclosure may be configured or arranged differently to form other embodiments, which may be variations of any of the disclosed embodiments.

[0041] In this disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in “one embodiment,” “example embodiment,” “implementation,” “another embodiment,” “some embodiments,” “various embodiments,” “other embodiments,” “alternative embodiments,” etc., are intended to indicate that any such feature is included in one or more embodiments of this disclosure, but may or may not necessarily be combined in the same embodiment.

[0042] In this disclosure, the terms “comprising,” “including,” “containing,” and “included in” are open-ended. As used in the appended claims, these terms specify the presence of the mentioned element and do not exclude the presence or addition of one or more other elements. The terms in the claims do not exclude the inclusion of additional components (e.g., interface units, circuitry, etc.).

[0043] In this disclosure, various units, circuits, or other components may be described or claimed as being "configured" to perform multiple tasks. In this context, "configured as" is used to imply a structure by indicating that a block / unit / circuit / component includes a structure (e.g., a circuit) that performs one or more tasks during operation. Thus, a block / unit / circuit / component can be referred to as being configured to perform a task even when the specified block / unit / circuit / component is not currently in operation (e.g., not opened or not activated). Blocks / units / circuits / components used with the language "configured as" include hardware—e.g., circuits, memory storing program instructions executable to perform operations, etc. Additionally, "configured as" may include general structures (e.g., general-purpose circuits) manipulated by software and / or firmware (e.g., an FPGA or a general-purpose processor executing software) to operate in a manner capable of performing the tasks in question. "Configured as" may also include adapting a manufacturing process (e.g., a semiconductor manufacturing facility) to manufacture means (e.g., integrated circuits) suitable for implementing or performing one or more tasks.

[0044] As used in this disclosure, the term "circuit" or "logic" means all of the following: (a) a purely hardware circuit implementation (such as an implementation in analog and / or digital circuits only), and (b) a combination of circuits and software (and / or firmware), such as (if applicable): (i) a combination of processors or (ii) portions of processors / software (including digital signal processors), software, and memory that work together to enable a device (such as a mobile phone or server) to perform various functions, and (c) circuits such as a microprocessor or a portion of a microprocessor that require software or firmware (even if the software or firmware is not physically present) to function. This definition of "circuit" or "logic" applies to all uses of the term in this application (including in any claim). As another example, as used in this application, the term "circuit" or "logic" also covers implementations of processors (or processors) only, or portions of processors and their accompanying software and / or firmware. The term "circuit" or "logic" also covers, for example, and if applicable to a particular claim element, an integrated circuit for a storage device.

[0045] As used herein, the terms “first,” “second,” “third,” etc., serve as labels for the nouns that follow them and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). The terms “first” and “second” do not necessarily imply that a first value must precede a second value. Furthermore, while these terms may be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element that would otherwise have the same or similar name. For example, a first circuit can be distinguished from a second circuit.

[0046] Furthermore, the term "based on" is used to describe factors influencing a determination. This term does not exclude additional factors that may influence the determination. That is, a determination may be based solely on those factors, or at least partially on those factors. Consider the phrase "A is determined based on B." While B is a factor influencing the determination of A in this case, such a phrase does not exclude the possibility that the determination of A is also based on C. In other cases, A may be determined solely on B.

[0047] Here, a data item, data entry, or data term can be a bit sequence. For example, a data item may include the contents of a file, a portion of a file, a page in memory, an object in object-oriented programming, a digital message, a digitally scanned image, a portion of a video or audio signal, metadata, or any other entity that can be represented by a bit sequence. According to one implementation, a data item may include discrete objects. According to another implementation, a data item may include information units within a transmission packet between two different components.

[0048] Embodiments of the present disclosure will now be described with reference to the accompanying drawings, wherein similar reference numerals denote similar elements.

[0049] Figure 1 A memory system 110 according to an embodiment of the present disclosure is illustrated. Specifically, Figure 1 A memory cell array circuit in a memory die included in a memory device according to an embodiment of the present disclosure is illustrated schematically.

[0050] Reference Figure 1 The memory die 200 may include a memory bank 330, which includes a plurality of non-volatile memory cells. The memory bank 330 may include a plurality of cell strings 340. Each cell string 340 includes a plurality of non-volatile memory cells connected to each of a plurality of bit lines BL0 to BLm-1. Each cell string 340 disposed in each column of the memory bank 330 may include at least one drain select transistor (DST) and at least one string select transistor (SST). A plurality of non-volatile memory cells or memory cell transistors MC0 to MCn-1 may be connected in series between the drain select transistor (DST) and the string select transistor (SST). For example, each of the non-volatile memory cells MC0 to MCn-1 may be configured to store a multi-level cell (MLC) with a data item having multiple bits per cell. Each cell string 340 may be individually electrically connected to a corresponding bit line BL0 to BLm-1.

[0051] Figure 1A memory bank 330 including NAND flash memory cells is shown as an example. However, the memory bank 330 included in the memory device 150 according to embodiments of the present disclosure is not limited to NAND flash memory. In another embodiment, the memory bank 330 may also be implemented as NOR flash memory, a hybrid flash memory combining or mixing at least two different types of memory cells, or a monolithic NAND flash memory with a controller embedded in a single memory chip. Additionally, the memory bank 330 according to embodiments of the present disclosure may include flash memory cells in which the charge storage layer includes a conductive floating gate, or charge-trapped flash memory (CTF) cells in which the charge storage layer is formed of an insulating film.

[0052] According to embodiments of this disclosure, Figure 1 The memory group 330 shown may include Figure 2 The illustrated memory device 150 includes at least one memory block 152, 154, 156. According to embodiments, the memory device 150 may have a two-dimensional (2D) structure or a three-dimensional (3D) structure. For example, each of the memory blocks 152, 154, 156 in the memory device 150 may be implemented as a 3D structure (or a vertical structure). Each of the memory blocks 152, 154, 156 may have a three-dimensional structure extending along a first direction to a third direction (e.g., the x-axis direction, the y-axis direction, and the z-axis direction).

[0053] The memory group 330, comprising multiple memory blocks 152, 154, and 156 constituting the memory device 150, can be connected to multiple bit lines BL, multiple string select lines SSL, multiple drain select lines DSL, multiple word lines WL, multiple dummy word lines DWL (not shown), and multiple common source lines CSL. The memory group 300 may include multiple NAND strings NS, each NAND string NS including multiple memory cells MC. In the memory group 330, each NAND string NS can be connected to each bit line BL. Additionally, the string select transistor SST of each NAND string NS can be connected to the common source line CSL, and the drain select transistor DST of each NAND string NS can be connected to the corresponding bit line BL. Here, the memory cells MC can be arranged between the string select transistor SST and the drain select transistor DST of each NAND string NS.

[0054] Reference Figure 1The voltage supply circuit 170 in the memory device 150 can supply word line voltages (e.g., object voltages such as programming voltage, read voltage, and pass voltage) via each word line according to the operating mode, or supply voltage to the block body (e.g., a well region) to which each memory block, including the memory cell MC, is formed. In this case, the voltage generation operation of the voltage supply circuit 170 can be performed under the control of a control circuit (not shown). Furthermore, the voltage supply circuit 170 can generate multiple variable read voltages to distinguish multiple data items from each other. In response to the control of the control circuit, one of the memory blocks (or sectors) of the memory cell array can be selected, and one of the word lines of the selected memory block can be selected. Word line voltages can be supplied separately to the selected word line and the unselected word line. The voltage supply circuit 170 may include a voltage generation circuit (see reference) for generating target voltages with various levels. Figures 4 to 8 The voltage supply circuit 170 may be coupled to a first pin or pad that receives a first power supply voltage VCC applied from an external source (e.g., an external device) and a second pin or pad that receives a second power supply voltage VPP applied from an external device. Here, the second power supply voltage VPP may have a voltage level that is twice or higher than the voltage level of the first power supply voltage VCC. For example, the first power supply voltage VCC may have a voltage level of 2.0V to 5.5V, while the second power supply voltage may have a voltage level of 9V to 13V. The voltage supply circuit 170 according to embodiments of this disclosure may include a voltage generation circuit for more quickly generating target voltages of various levels used in the memory bank 330. The voltage generation circuit may use the second power supply voltage VPP to generate a target voltage with a higher voltage level than the second power supply voltage VPP.

[0055] The read / write circuit 320, controlled by the control circuitry of the memory device 150, can operate as a sense amplifier or a write driver depending on the operating mode. For example, in verification and read operations, the read / write circuit 320 can operate as a sense amplifier for reading data items from the memory cell array. Furthermore, in programming operations, the read / write circuit 320 can operate as a write driver for controlling the potential of bit lines based on the data items to be stored in the memory cell array. During programming operations, the read / write circuit 320 can receive data items to be programmed into the cell array from page buffers (not shown). The read / write circuit 320 can drive bit lines based on the input data items. For this purpose, the read / write circuit 320 includes a plurality of page buffers (PB) 322, 324, 326, each page buffer corresponding to each column (or each bit line) or each column pair (or each bit line pair). According to embodiments, a plurality of latches (not shown) may be included in each of the page buffers 322, 324, 326.

[0056] Although not shown, page buffers 322, 324, and 326 can be connected to data input / output devices (e.g., serialization circuits or serializers) via multiple buses. When each of page buffers 322, 324, and 326 is connected to a data input / output device via a different bus, potential delays in data transmission from page buffers 322, 324, and 326 can be reduced. For example, each of page buffers 322, 324, and 326 can perform data transmission without waiting time.

[0057] According to embodiments of this disclosure, in the process of programming data items into a non-volatile memory device, the data input / output speed can be improved by reducing the number of verification operations performed in the non-volatile memory device.

[0058] Furthermore, the memory device according to the embodiments of this disclosure can reduce the operational burden for verification operations, the degree of wear and tear on non-volatile memory cells in the memory device, and the interference between adjacent non-volatile memory cells in the memory device, thereby improving the security of stored data items.

[0059] Figure 2 A data processing system 100 according to an embodiment of the present disclosure is illustrated.

[0060] Reference Figure 2 The data processing system 100 may include a host 102 that is coupled to or connected to a memory system such as a memory system 110. For example, the host 102 and the memory system 110 may be connected to each other via a data bus, host cable, etc., to perform data communication.

[0061] The memory system 110 may include a memory device 150 and a controller 130. The memory device 150 and the controller 130 in the memory system 110 may be considered as physically separate components or elements. The memory device 150 and the controller 130 may be connected via at least one data path. For example, the data path may include a channel and / or a path.

[0062] According to embodiments, the memory device 150 and the controller 130 may be functionally separated components or elements. Furthermore, according to embodiments, the memory device 150 and the controller 130 may be implemented using a single chip or multiple chips. The controller 130 may perform data input / output operations in response to requests input from external devices. For example, when the controller 130 performs a read operation in response to a read request input from an external device, data stored in a plurality of non-volatile memory cells included in the memory device 150 is transferred to the controller 130.

[0063] like Figure 2As shown, memory device 150 may include a plurality of memory blocks 152, 154, and 156. Memory blocks 152, 154, and 156 can be understood as a group of non-volatile memory cells whose data is removed together in a single erase operation. Although not shown, memory blocks 152, 154, and 156 may include pages as a group of non-volatile memory cells that store data together during a single programming operation or output data together during a single read operation. For example, a memory block may include multiple pages.

[0064] For example, memory device 150 may include multiple memory planes or multiple memory dies. According to an embodiment, a memory plane may be considered as a logical or physical partition including at least one memory block, drive circuitry capable of controlling an array including multiple non-volatile memory cells, and buffers that can temporarily store data input to or output from the non-volatile memory cells.

[0065] Additionally, according to an embodiment, a memory die may include at least one memory plane. A memory die can be understood as a collection of components implemented on a physically distinguishable substrate. Each memory die can be connected to the controller 130 via a data path. Each memory die may include an interface for exchanging data items and signals with the controller 130.

[0066] According to an embodiment, the memory device 150 may include at least one memory block 152, 154, 156, at least one memory plane, or at least one memory die. Figure 1 The internal structure of the memory device 150 shown may vary depending on the performance of the memory system 110. Embodiments of this disclosure are not limited to... Figure 2 The internal structure is shown.

[0067] Reference Figure 2 The memory device 150 may include a voltage supply circuit 170 capable of supplying at least some voltages to memory blocks 152, 154, and 156. The voltage supply circuit 170 may include a voltage generation circuit for generating target voltages used in memory blocks 152, 154, and 156, as described above. Figures 4 to 8The voltage supply circuit 170 can supply a read voltage Vrd, a programming voltage Vprog, a pass voltage Vpass, or an erase voltage Vers to the non-volatile memory cells included in the memory blocks. For example, during a read operation for reading data stored in the non-volatile memory cells included in memory blocks 152, 154, and 156, the voltage supply circuit 170 can supply the read voltage Vrd to the selected non-volatile memory cell. During a programming operation for storing data in the non-volatile memory cells included in memory blocks 152, 154, and 156, the voltage supply circuit 170 can supply the programming voltage Vprog to the selected non-volatile memory cell. Furthermore, during a read operation or programming operation performed on a selected non-volatile memory cell, the voltage supply circuit 170 can supply the pass voltage Vpass to the unselected non-volatile memory cell. During an erase operation to erase data stored in the non-volatile memory cells included in memory blocks 152, 154, and 156, voltage supply circuit 170 can supply an erase voltage Vers to the memory blocks.

[0068] Memory device 150 may store information about various voltages supplied to memory blocks 152, 154, and 156 based on which operation is performed. For example, when the non-volatile memory cells in memory blocks 152, 154, and 156 can store multiple bits of data, multiple levels of read voltage Vrd may be needed to identify or read multiple data items. Memory device 150 may include a table containing information corresponding to multiple levels of read voltage Vrd for each multiple data item. For example, the table may include bias values ​​stored in registers, each bias value corresponding to a specific level of read voltage Vrd. The number of bias values ​​for read voltage Vrd used for read operations may be limited to a preset range. Furthermore, the bias values ​​may be quantized.

[0069] The host 102 may include a portable electronic device (e.g., a mobile phone, MP3 player, laptop computer, etc.) or a non-portable electronic device (e.g., a desktop computer, game console, television, projector, etc.). According to an embodiment, the host 102 may include the central processing unit (CPU) included in both portable and non-portable electronic devices.

[0070] Host 102 may also include at least one operating system (OS) capable of controlling the functions and operations performed within host 102. The OS can provide interoperability between host 102, which is operationally coupled to memory system 110, and users who wish to store data in memory system 110. The OS can support functions and operations corresponding to user requests. By way of example, and not limitation, OS can be classified as general-purpose operating systems and mobile operating systems based on the mobility of host 102. General-purpose operating systems can be further categorized into personal operating systems and enterprise operating systems based on system requirements or user environment. Compared to personal operating systems, enterprise operating systems can be specifically designed to protect and support high-performance computing.

[0071] The mobile operating system can be adapted to support services or functions for mobility (e.g., power-saving features). Host 102 may include multiple operating systems. In response to a user's request, host 102 can execute multiple operating systems interlocked with memory system 110. Host 102 can send multiple commands corresponding to the user's request to memory system 110, thereby executing operations corresponding to the multiple commands within memory system 110.

[0072] The controller 130 in the memory system 110 can control the memory device 150 in response to requests or commands input from the host 102. For example, the controller 130 can perform a read operation to provide data read from the memory device 150 to the host 102 and can perform a write operation (or programming operation) to store data input from the host 102 in the memory device 150. In order to perform data input / output (I / O) operations, the controller 130 can control and manage internal operations such as reading data, programming data, erasing data, etc.

[0073] According to an implementation, the controller 130 may include a host interface 132, a processor 134, an error correction circuit (ECC) 138, a power management unit (PMU) 140, a memory interface 142, and a memory 144. For example... Figure 2 The components included in the controller 130 shown can vary depending on the structure, function, and operational performance of the memory system 110.

[0074] For example, depending on the host interface protocol, the memory system 110 can be implemented using any of a variety of storage devices that can be electrically connected to the host 102. Non-limiting examples of suitable storage devices include solid-state drives (SSDs), multimedia cards (MMCs), embedded MMCs (eMMCs), miniature MMCs (RS-MMCs), micro MMCs, secure digital cards (SDs), mini SDs, micro SDs, universal serial bus (USB) storage devices, universal flash memory (UFS) devices, compact flash memory (CF) cards, smart media (SM) cards, memory sticks, etc. Depending on the implementation of the memory system 110, components can be added to or omitted from the controller 130.

[0075] Both host 102 and memory system 110 may include a controller or interface for sending and receiving signals, data, etc., according to one or more predetermined protocols. For example, host interface 132 in memory system 110 may include devices capable of sending signals, data, etc. to host 102 or receiving signals, data, etc. from host 102.

[0076] The host interface 132 included in controller 130 can receive signals, commands (or requests), and / or data input from host 102. For example, host 102 and memory system 110 can send and receive data therebetween using predetermined protocols. Examples of communication standards, protocols, or interfaces supported by host 102 and memory system 110 for sending and receiving data include Universal Serial Bus (USB), Multimedia Card (MMC), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), High-Speed ​​Peripheral Component Interconnect (PCIe or PCI-e), Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), Mobile Industry Processor Interface (MIPI), etc. According to embodiments, host interface 132 is a layer for exchanging data with host 102 and is implemented or driven by firmware called the Host Interface Layer (HIL).

[0077] Integrated Drive Electronics (IDE) or Advanced Technology Accessory (ATA) can be used as one of the interfaces for sending and receiving data, and, for example, a cable including 40 wires connected in parallel can be used to support data transmission and reception between host 102 and memory system 110. When multiple memory systems 110 are connected to a single host 102, the multiple memory systems 110 can be classified as master and slave by using the DIP switches or positions to which the multiple memory systems 110 are connected. The memory system 110 set as master can be used as the master memory device. IDE (ATA) can include, for example, Fast-ATA, ATAPI, or Enhanced IDE (EIDE).

[0078] The Serial Advanced Technology Attachment (SATA) interface is a serial data communication interface compatible with various ATA standards for parallel data communication interfaces used by Integrated Drive Electronics (IDE) devices. The 40 pins of the IDE interface can be reduced to 6 pins in the SATA interface. For example, the 40 parallel signals of IDE can be converted into 6 serial signals in the SATA interface. The SATA interface is widely used in host 102 for data transmission and reception due to its faster data transmission and reception rates and lower resource consumption. The SATA interface can connect up to 30 external devices to a single transceiver included in host 102. Furthermore, the SATA interface supports hot-plugging, which allows external devices to be attached to or detached from host 102 even while data communication between host 102 and another device is in progress. Therefore, even when host 102 is powered on, memory system 110 can function as an attachment or port, similar to devices supported by Universal Serial Bus (USB). For example, in a host 102 with an eSATA port, the storage system 110 can be freely attached to or detached from the host 102 like an external hard drive.

[0079] The Small Computer System Interface (SCSI) is a serial data communication interface used to connect a computer or server to other peripheral devices. Compared to other interfaces such as IDE and SATA, SCSI offers high transfer speeds. In SCSI, the host 102 and at least one peripheral device (e.g., memory system 110) are connected in series, but data transmission and reception between the host 102 and each peripheral device can be performed through parallel data communication. In SCSI, devices such as memory system 110 can be easily connected to or disconnected from the host 102. SCSI can support connections of up to 15 other devices to a single transceiver included in the host 102.

[0080] Serial Attached SCSI (SAS) can be understood as a serial data communication version of SCSI. In SAS, the host 102 and multiple peripheral devices are connected in series, and data transmission and reception between the host 102 and each peripheral device can be performed according to a serial data communication scheme. SAS supports the connection between the host 102 and peripheral devices through serial cables instead of parallel cables, making it easier to manage equipment using SAS and enhancing operational reliability and communication performance. SAS can support connections from up to eight external devices to a single transceiver included in the host 102.

[0081] High-speed non-volatile memory (NVMe) is an interface based at least on High-Speed ​​Peripheral Component Interconnect (PCIe), which is designed to increase the performance and design flexibility of hosts 102, servers, computing devices, etc., equipped with a non-volatile memory system 110. PCIe can use slots or specific cables to connect computing devices (e.g., host 102) and peripheral devices (e.g., memory system 110). For example, PCIe can use multiple pins (e.g., 18 pins, 32 pins, 49 pins, or 82 pins) and at least one line (e.g., x1, x4, x8, or x16) to achieve high-speed data communication of hundreds of MB / s (e.g., 250 MB / s, 500 MB / s, 984.6250 MB / s, or 1969 MB / s). Depending on the implementation, PCIe schemes can achieve bandwidths from tens to hundreds of gigabits per second. NVMe can support operating speeds of non-volatile memory systems 110 (such as SSDs) that are faster than hard drives.

[0082] According to one implementation, host 102 and memory system 110 can be connected via Universal Serial Bus (USB). Universal Serial Bus (USB) is a scalable, hot-pluggable, plug-and-play serial interface that provides a cost-effective standard connection between host 102 and peripheral devices such as keyboards, mice, joysticks, printers, scanners, storage devices, modems, cameras, etc. Multiple peripheral devices, such as memory system 110, can be connected to a single transceiver included in host 102.

[0083] Reference Figure 2 Error correction circuit 138 can correct erroneous bits in data read from memory device 150 and may include an error correction code (ECC) encoder and an ECC decoder. The ECC encoder performs error correction encoding on data to be programmed into memory device 150 to generate encoded data with parity bits added, and stores the encoded data in memory device 150. When controller 130 reads data stored in memory device 150, ECC decoder can detect and correct erroneous bits contained in the data read from memory device 150. For example, after performing error correction decoding on data read from memory device 150, error correction circuit 138 determines whether error correction decoding was successful and outputs an indication signal (e.g., a correction success signal or a correction failure signal) based on the result of error correction decoding. Error correction circuit 138 may use parity bits already generated during the ECC encoding process for data stored in memory device 150 to correct erroneous bits in the read data. When the number of erroneous bits is greater than or equal to the number of correctable erroneous bits, error correction circuit 138 may instead output a correction failure signal indicating that error correction failed, instead of correcting the erroneous bits.

[0084] According to embodiments, the error correction circuit 138 can perform error correction operations based on coding modulation such as low-density parity-check (LDPC) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, turbo codes, Reed-Solomon (RS) codes, convolutional codes, recursive systematic codes (RSC), trellis-coded modulation (TCM), block-coded modulation (BCM), etc. The error correction circuit 138 may include all circuits, modules, systems, and / or devices for performing error correction operations based on at least one of the aforementioned codes. Figure 2 The error correction circuit 138 shown may include Figure 2 At least some of the components included in the controller 130 shown.

[0085] For example, the ECC decoder can perform hard-decision decoding or soft-decision decoding on data sent from memory device 150. Hard-decision decoding can be understood as one of two broadly categorized methods for error correction. Hard-decision decoding may include the operation of correcting erroneous bits by reading digital data "0" or "1" from non-volatile memory cells in memory device 150. Because hard-decision decoding deals with binary logic signals, the circuit / algorithm design or configuration can be simpler and the processing speed can be faster compared to soft-decision decoding.

[0086] Soft-decision decoding can quantize the threshold voltage in a non-volatile memory cell in memory device 150 using two or more quantized values ​​(e.g., multi-bit data, approximations, analog values, etc.) to correct erroneous bits based on the two or more quantized values. Controller 130 can receive two or more letters or quantized values ​​from multiple non-volatile memory cells in memory device 150 and then perform decoding based on information generated by characterizing the quantized values ​​as a combination of information such as conditional probability or likelihood.

[0087] According to the implementation, the ECC decoder can use Low-Density Parity-Generator Matrix (LDPC-GM) codes, which are designed for soft-decision decoding. The LDPC code uses an algorithm that reads the value of data in the memory device 150 as several bits based on reliability, rather than simply 1 or 0 data as in hard-decision decoding, and iteratively repeats this through message exchange to improve the reliability of the value. These values ​​are then ultimately determined as 1 or 0 data. For example, the decoding algorithm using LDPC codes can be understood as probabilistic decoding. In hard-decision decoding, the value output from the non-volatile memory cell is decoded as 0 or 1. Compared to hard-decision decoding, soft-decision decoding can determine the value stored in the non-volatile memory cell based on random information. Regarding bit flips (which can be considered errors that can occur in the memory device 150), soft-decision decoding can provide improved probabilities for correcting errors and recovering data, as well as providing the reliability and stability of the corrected data. The LDPC-GM code can have a scheme where internal LDGM codes can be cascaded with high-speed LDPC codes.

[0088] According to the implementation, the ECC decoder can use, for example, low-density parity-check convolutional codes (LDPC-CC) for soft-decision decoding. LDPC-CC can have a scheme using linear-time coding and pipelined decoding based on variable block length and shift registers.

[0089] According to the implementation, the ECC decoder can use, for example, a log-likelihood ratio Turbo code (LLR-TC) for soft-decision decoding. The log-likelihood ratio (LLR) can be calculated as a non-linear function of the distance between the sampled value and the ideal value. Alternatively, the Turbo code (TC) can include simple two-dimensional or three-dimensional codes (e.g., Hamming codes), and the decoding is repeated in both the row and column directions to improve the reliability of the values.

[0090] The power management unit (PMU) 140 can control the power supplied to the controller 130. The PMU 140 can monitor the power supplied to the memory system 110 (e.g., the voltage supplied to the controller 130) and supply power to the components included in the controller 130. The PMU 140 can not only detect power on or off, but also generate a trigger signal to enable the memory system 110 to perform an emergency backup of its current state when the power supply to the memory system 110 is unstable. According to embodiments, the PMU 140 may include means or components capable of accumulating power that can be used in emergency situations.

[0091] The memory interface 142 can be used as an interface for processing commands and data transferred between the controller 130 and the memory device 150, so as to allow the controller 130 to control the memory device 150 in response to commands or requests input from the host 102. If the memory device 150 is flash memory, the memory interface 142 can generate control signals for the memory device 150 and can process data input to or output from the memory device 150 under the control of the processor 134.

[0092] For example, when the memory device 150 includes NAND flash memory, the memory interface 142 includes a NAND flash memory controller (NFC). The memory interface 142 can provide an interface for handling commands and data between the controller 130 and the memory device 150. According to an embodiment, the memory interface 142 can be implemented or driven by firmware called a flash interface layer (FIL) for exchanging data with the memory device 150.

[0093] According to the implementation, the memory interface 142 may support an Open NAND Flash Interface (ONFi), a toggle mode, etc., for data input / output with the memory device 150. For example, ONFi may use a data path (e.g., channel, path, etc.) that includes at least one signal line capable of bidirectional transmission and reception in units of 8 bits or 16 bits of data. Data communication between the controller 130 and the memory device 150 may be implemented through at least one interface relating to Asynchronous Single Data Rate (SDR), Synchronous Double Data Rate (DDR), Switched Double Data Rate (DDR), etc.

[0094] Memory 144 can be used as working memory for memory system 110 or controller 130, while also temporarily storing transaction data for operations performed in memory system 110 and controller 130. For example, memory 144 can temporarily store read data output from memory device 150 in response to a read request from host 102 before outputting read data to host 102. Additionally, controller 130 can temporarily store write data input from host 102 in memory 144 before programming write data into memory device 150. When controller 130 controls operations such as data read operations, data write or programming operations, and data erase operations of memory device 150, data transferred between controller 130 and memory device 150 of memory system 110 can be temporarily stored in memory 144.

[0095] In addition to reading or writing data, memory 144 may store information (e.g., mapped data, read requests, programming requests, etc.) used for inputting or outputting data between host 102 and memory device 150. Depending on the implementation, memory 144 may include one or more of a command queue, programming memory, data memory, write buffer / cache, read buffer / cache, data buffer / cache, mapping buffer / cache, etc. Controller 130 may allocate some storage space in memory 144 for components established to perform data input / output operations. For example, a write buffer established in memory 144 may be used to temporarily store target data undergoing programming operations.

[0096] In implementations, memory 144 can be implemented using volatile memory. For example, memory 144 can be implemented using static random access memory (SRAM), dynamic random access memory (DRAM), or both. Although Figure 2 An example of a memory 144 located within the controller 130 is illustrated, but the implementation is not limited thereto. The memory 144 may be located inside or outside the controller 130. For example, the memory 144 may be embodied by an external volatile memory having a memory interface for transferring data and / or signals between the memory 144 and the controller 130.

[0097] Processor 134 can control the overall operation of memory system 110. For example, processor 134 can control programming or reading operations of memory device 150 in response to write or read requests from host 102. According to embodiments, processor 134 can execute firmware to control programming or reading operations in memory system 110. In this document, firmware may be referred to as flash translation layer (FTL). According to embodiments, processor 134 can be implemented using a microprocessor, central processing unit (CPU), etc.

[0098] According to an implementation, the memory system 110 can be implemented using at least one multi-core processor. A multi-core processor is a circuit or chip in which two or more cores, considered to be distinct processing regions, are integrated. For example, when multiple cores in a multi-core processor independently drive or execute multiple flash translation layers (FTLs), the data input / output speed (or performance) of the memory system 110 can be improved. According to an implementation, data input / output (I / O) operations in the memory system 110 can be performed independently by different cores in the multi-core processor.

[0099] The processor 134 in the controller 130 can perform operations corresponding to requests or commands input from the host 102. Furthermore, the memory system 110 can perform operations independently of commands or requests input from the host 102. In one case, operations performed by the controller 130 in response to requests or commands input from the host 102 can be considered foreground operations, while operations performed by the controller 130 independently of requests or commands input from the host 102 can be considered background operations. The controller 130 can perform foreground or background operations for reading, writing, or erasing data in the memory device 150. Additionally, parameter setting operations corresponding to setting parameter commands or setting feature commands sent as setting commands from the host 102 can be considered foreground operations. As an example of a background operation that can be performed without commands sent from the host 102, the controller 130 can perform garbage collection (GC), wear leveling (WL), bad block management for identifying and handling bad blocks, etc.

[0100] According to the implementation, substantially similar operations can be performed as both foreground and background operations. For example, garbage collection can be considered a foreground operation when the memory system 110 performs garbage collection (e.g., manual GC) in response to a request or command input from the host 102. Garbage collection can be considered a background operation when the memory system 110 performs garbage collection (e.g., automatic GC) independently of the host 102.

[0101] When the memory device 150 includes multiple dies (or multiple chips) and each die includes multiple non-volatile memory cells, the controller 130 can perform parallel processing of multiple requests or commands input from the host 102 to improve the performance of the memory system 110. For example, the sent requests or commands can be divided into multiple groups including at least some of the multiple planes, multiple dies, or multiple chips included in the memory device 150, and the multiple groups of requests or commands can be processed individually or in parallel in each plane, each die, or each chip.

[0102] The memory interface 142 in controller 130 can be connected to multiple dies or chips in memory device 150 via at least one channel and at least one path. When controller 130 distributes and stores data in multiple dies via each channel or path in response to a request or command associated with multiple pages including non-volatile memory cells, multiple operations corresponding to the request or command can be executed simultaneously or in parallel in multiple dies or planes. This processing method or scheme can be considered an interleaving method. Because the data input / output speed of memory system 110 is increased by operating in an interleaving method, the data I / O performance of memory system 110 can be improved.

[0103] By way of example, and not limitation, controller 130 can identify the state of multiple channels (or pathways) associated with multiple dies included in memory device 150. Controller 130 can determine the state of each channel or pathway as one of busy, ready, active, idle, normal, and abnormal states. The determination by the controller of which channel or pathway to deliver instructions (and / or data) can be associated with a physical block address. Controller 130 can reference descriptors delivered from memory device 150. A descriptor can include a block or page containing parameters describing certain things about memory device 150. Descriptors can have a predetermined format or structure. For example, descriptors can include device descriptors, configuration descriptors, cell descriptors, etc. Controller 130 can refer to or use descriptors to determine which channel or pathway to use to exchange instructions or data.

[0104] Reference Figure 2 The memory device 150 in the memory system 110 may include a plurality of memory blocks 152, 154, and 156. Each of the plurality of memory blocks 152, 154, and 156 includes a plurality of non-volatile memory cells. According to an embodiment, memory blocks 152, 154, and 156 may be a group of non-volatile memory cells that are erased together. Memory blocks 152, 154, and 156 may include a plurality of pages, which are a group of non-volatile memory cells that are read or programmed together.

[0105] In one embodiment, each memory block 152, 154, or 156 may have a highly integrated three-dimensional stacked structure. Furthermore, the memory device 150 may include multiple dies, each die including multiple planes, and each plane including multiple memory blocks 152, 154, 156. The configuration of the memory device 150 may be varied depending on the performance of the memory system 110.

[0106] Figure 2 An example of a memory device 150 is shown, comprising multiple memory blocks 152, 154, and 156. Depending on the number of bits that can be stored in a single memory cell, the multiple memory blocks 152, 154, and 156 can be any of a single-level cell (SLC) memory block, a multi-level cell (MLC) memory block, etc. An SLC memory block comprises multiple pages implemented by memory cells, each storing one bit of data. SLC memory blocks can have higher data I / O performance and greater endurance than MLC memory blocks. An MLC memory block comprises multiple pages implemented by memory cells, each storing multiple bits of data (e.g., two or more bits of data). Compared to SLC memory blocks, MLC memory blocks can have a larger storage capacity for the same space. From a storage capacity perspective, MLC memory blocks can be highly integrated.

[0107] In one embodiment, the memory device 150 may be implemented using MLC memory blocks such as two-level cell (DLC) memory blocks, three-level cell (TLC) memory blocks, four-level cell (QLC) memory blocks, and combinations thereof. A DLC memory block may include multiple pages implemented by memory cells capable of storing 2 bits of data per memory cell. A TLC memory block may include multiple pages implemented by memory cells capable of storing 3 bits of data per memory cell. A QLC memory block may include multiple pages implemented by memory cells capable of storing 4 bits of data per memory cell. In another embodiment, the memory device 150 may be implemented using blocks comprising multiple pages implemented by memory cells capable of storing five or more bits of data per memory cell.

[0108] According to one implementation, the controller 130 can use an MLC memory block included in the memory device 150 as an SLC memory block, which stores one bit of data in a memory cell. The data input / output speed of a Multilevel Cell (MLC) memory block can be slower than that of an SLC memory block. That is, when an MLC memory block is used as an SLC memory block, a margin for read or programmable operations can be reduced. For example, when an MLC memory block is used as an SLC memory block, the controller 130 can perform data input / output operations at a higher speed. Therefore, the controller 130 can use an MLC memory block as an SLC buffer to temporarily store data, because a buffer may require a high data input / output speed to improve the performance of the memory system 110.

[0109] Furthermore, according to an embodiment, the controller 130 can program data multiple times in the MLC without performing an erase operation on a specific MLC memory block included in the memory device 150. Typically, non-volatile memory cells do not support data overwriting. However, the controller 130 can utilize the characteristic of the MLC to store multiple bits of data to program one bit of data multiple times in the MLC. For an MLC overwrite operation, when programming one bit of data in the MLC, the controller 130 can store the number of programming operations as separate operation information. According to an embodiment, an operation to evenly level the threshold voltage of the MLC can be performed before another one bit of data is programmed into the same MLC where one bit of data has already been stored.

[0110] In one embodiment, the memory device 150 is implemented as a non-volatile memory such as flash memory (e.g., NAND flash memory, NOR flash memory, etc.). In another embodiment, the memory device 150 may be implemented by at least one of phase-change random access memory (PCRAM), ferroelectric random access memory (FRAM), spin-torque random access memory (STT-RAM), and spin-torque magnetic random access memory (STT-MRAM).

[0111] Figure 3 An example of Incremental Step Pulse Programming (ISPP) operation is shown.

[0112] Reference Figure 3 Data can be programmed into non-volatile memory cells in an erased state. When a programming pulse is supplied to the word line connected to the non-volatile memory cell, the threshold voltage distribution of the non-volatile memory cell shifts to the right (in the direction of increasing threshold voltage) from the erased state. If programming pulses are continuously supplied to the non-volatile memory cells, the threshold voltage distribution of the non-volatile memory cells can be continuously shifted to the right. Programming pulses can be supplied until most of the multiple non-volatile memory cells in the threshold voltage distribution have a threshold voltage higher than the target voltage VTARG.

[0113] More specifically, when the programming operation begins (operation 212), the memory device 150 may apply programming pulses to a plurality of non-volatile memory cells containing data to be programmed (operation 214). After applying the programming pulses, the memory device 150 may verify that most of the plurality of non-volatile memory cells have a voltage higher than the target voltage V. TARG Threshold voltage V TH (Operation 216). When the verification result FAIL (failure) determines that most of the multiple non-volatile memory cells do not have a voltage higher than the target voltage V. TARG Threshold voltage V TH At this time, memory device 150 applies another programming pulse to the corresponding non-volatile memory cell (operation 214). When it is determined, based on another verification result PASS, that most of the multiple non-volatile memory cells have a voltage higher than the target voltage V. TARG Threshold voltage V TH At this time, the memory device 150 can end the programming operation (operation 218).

[0114] To narrow the threshold voltage distribution of multiple non-volatile memory cells, it is advantageous to slightly shift the threshold voltage distribution of the multiple non-volatile memory cells to the right when a single programming pulse is applied, rather than shifting them significantly to the right. On the other hand, the number of programming pulses applied can be increased when the threshold voltage distribution of the multiple non-volatile memory cells is slightly shifted to the right. According to embodiments, this can be three times or more the number of bits of data that can be stored in the non-volatile memory cell. For example, when 2 bits of data can be stored in a non-volatile memory cell, the non-volatile memory cell can have four programming states corresponding to the 2 bits of data (e.g., "00", "01", "10", and "11"). To form a tighter threshold voltage distribution (i.e., a narrower distribution), the degree to which the threshold voltage distribution of the multiple non-volatile memory cells shifts to the right in response to a single programming pulse can be less than the difference between two adjacent programming states. For example, when two or more programming pulses are applied, it can be designed to shift according to the difference between two adjacent programming states. In this case, the number of programming pulses applied can be eight or more, which is four times the number of bits of extra data.

[0115] According to embodiments of this disclosure, the degree to which the threshold voltage distribution of multiple non-volatile memory cells shifts when a single programming pulse is applied can be understood as the target level. (Refer to...) Figure 6 The target level will be described in more detail.

[0116] Figure 4 A method for storing multiple bits of data in a non-volatile memory cell according to an embodiment of the present disclosure is illustrated. Figure 4 An example of a programming operation performed in a memory device 150 comprising non-volatile memory cells each capable of storing 3 bits of data is illustrated.

[0117] Data stored in non-volatile memory cells can be based on the threshold voltage V of the corresponding memory cell. TH The threshold voltage V of the memory cell is used to distinguish them. TH The threshold voltage V can vary depending on the number of electrons or charges injected into the floating gate of the corresponding memory cell. A single-level cell (SLC) can be divided into two ranges. TH It stores 1-bit data, either "0" or "1". On the other hand, the three-level cell (TLC) in the memory device 150 can have eight threshold voltage ranges.

[0118] Reference Figure 4To reduce the number of programming pulses applied during Incremental Step Pulse Programming (ISPP) operations, the application of programming pulses to the Level 3 Cell (TLC) in response to the data bits stored in the TLC can be controlled differently. The data stored in the TLC can be divided into LSB data, CSB data, and MSB data. When programming LSB data, the number of programming pulses applied can be minimized, while the number of programming pulses applied when programming CSB data can be greater than that applied when programming LSB data. When programming MSB data, the number of programming pulses applied can be maximized.

[0119] In a three-level cell (TLC) memory device, each physical page can be divided into three logical pages: the LSB page, the CSB page, and the MSB page. The programming pulse applied to each page can be different. That is, different positive threshold voltages (V) can be triggered during the programming of the LSB, CSB, and MSB data. TH The distribution shifts. For example, the threshold voltage V of multiple non-volatile memory cells. TH The maximum number of cells can be moved during LSB page programming, and the threshold voltage V of multiple non-volatile memory cells is [not specified]. TH Minimal movement is achieved during MSB page programming. According to the implementation, the shortest latency and lowest power consumption are achieved when the number of programming pulses applied during LSB page programming is minimized. Conversely, increasing the number of programming pulses applied during MSB page programming increases latency and power consumption.

[0120] Figure 5 The programming voltage application operation and verification operation of the ISPP operation according to an embodiment of the present disclosure are illustrated.

[0121] Reference Figure 5 After performing the programming voltage application operation Pgm during ISPP operation, the memory device 150 performs a verification operation Ver corresponding to the programming voltage application operation Pgm. Each programming voltage application operation Pgm can adjust the threshold voltage V of the non-volatile memory cell. TH Increase. For example, each programming voltage applied to operation Pgm will increase the threshold voltage V of the non-volatile memory cell. TH Increase the first potential difference ΔV. After performing the programming voltage application operation Pgm, the threshold voltage V of the non-volatile memory cell... TH It can be compared with the verification voltage during the verification operation. When the threshold voltage V of the non-volatile memory cell... THIf the voltage drops below the verification voltage, another programming voltage application operation Pgm can be performed to add more electrons to the floating gate of the non-volatile memory cell. Thereafter, a verification operation Ver is performed in response to the corresponding programming voltage application operation Pgm. Repeated programming voltage application operations Pgm can be performed until the threshold voltage V of the non-volatile memory cell is reached. TH To achieve the target voltage (e.g., the verification voltage).

[0122] According to the implementation method, the number of repetitions of the programming voltage application operation Pgm and the verification operation Ver can vary depending on standby time or delay time, power consumption, accuracy, etc. When the threshold voltage V of the non-volatile memory cell is finely increased through the programming voltage application operation Pgm... TH This increases the accuracy of the programming voltage application operation. However, because more programming voltage applications can be performed, the latency and power consumption can be longer and greater. On the other hand, when the threshold voltage V of the non-volatile memory cell... TH By significantly increasing the value of each programming voltage application operation Pgm, the power consumption and operation time of the programming voltage application operation Pgm can be reduced and shortened. The operation time Δt of the programming voltage application operation Pgm and the verification operation Ver can be determined based on the target of each programming voltage application operation Pgm (e.g., threshold voltage V). TH Changes (due to changes in the environment).

[0123] Reference Figure 4 and Figure 5 In a memory device comprising a three-level non-volatile memory cell (TLC), the programming voltage application operation Pgm and the verification operation Ver can be performed differently depending on the purpose and process of programming data in the least significant bit (LSB), center significant bit (CSB), and most significant bit (MSB) of the memory cell. Figure 4 As an example, a memory device including a three-level non-volatile memory cell (TLC) has been described, but the above programming operations can also be applied to memory devices including a four-level non-volatile memory cell (QLC) for storing 4 bits of data, or a non-volatile memory cell capable of storing 5 or more bits of data.

[0124] According to the implementation, for each programming cycle during ISPP operation, the voltage level of the programming pulse applied to the non-volatile memory cell in the programming voltage application operation Pgm can be gradually increased according to a preset voltage ΔV. However, the voltage level of the verification pulse applied to the non-volatile memory cell in the verification operation Ver corresponding to the programming voltage application operation Pgm can be substantially the same (i.e., unchanged). In the verification operation Ver for each programming cycle, substantially the same verification pulse is applied to the non-volatile memory cell, but the time Δt for applying the verification pulse can be changed. Furthermore, when the verification operation is performed by reflecting noise generated according to the operating characteristics of the memory device 150, the memory device 150 can change or adjust the voltage level of the verification pulse.

[0125] Figure 6 The target level corresponding to a plurality of programming pulses according to an embodiment of the present disclosure is illustrated. Figure 6 The programming state of a non-volatile memory cell storing 2 bits of data and the target level according to the programming pulse are shown.

[0126] Reference Figure 6 The non-volatile memory cell may have an erase state P0 and three programming states P1 to P3. For example, the memory device 150 may apply a second reference voltage REF2 to the non-volatile memory cell to distinguish the erase state P0 and the first programming state P1 from the second programming state P2 and the third programming state P3. In the memory device 150, the first reference voltage REF1 may be used to distinguish the erase state P0 from the first programming state P1. The memory device 150 may use a third reference voltage REF3 to distinguish the second programming state P2 and the third programming state P3 from each other. For example, the erase state P0 may be represented as 2 bits of data "11", the first programming state P1 may be represented as 2 bits of data "10", the second programming state P2 may be represented as 2 bits of data "00", and the third programming state P3 may be represented as 2 bits of data "01". According to the embodiment, the number of bits of data that can be stored in the non-volatile memory cell may be changed. In addition, the number of reference voltages (or reference voltage levels) used to distinguish multi-bit data can be changed.

[0127] Multiple programming pulses can be applied during the process of programming a non-volatile memory cell from an erase state P0 to one of a first programming state P1 to a third programming state P3. When a programming pulse is applied to a specific memory cell, the threshold voltage of the corresponding memory cell can be gradually increased. For example, to increase the threshold voltage of a specific non-volatile memory cell from a second programming state P2 to a third programming state P3, multiple programming pulses can be applied in stages. Figure 6In this process, by applying eight programming pulses or applying the programming pulses eight times, the threshold voltage distribution of a non-volatile memory cell can be gradually increased from the second programming state P2 to the third programming state P3. The greater the number of programming pulses applied to a specific memory cell to increase the preset voltage of the threshold voltage, the narrower the width of the threshold voltage distribution.

[0128] If the threshold voltage distribution of a non-volatile memory cell can be slightly shifted to the right by the applied programming pulse of the programming voltage application operation, a verification operation can be performed in response to the programming voltage application operation. For example, after applying the Nth programming pulse, the memory device 150 can perform a verification operation on the N target level corresponding to the Nth programming pulse. According to an embodiment, after applying the Nth programming pulse, verification operations are performed on multiple target levels (e.g., N target level, N-1 target level, N-2 target level) corresponding to the Nth programming pulse, the (N-1)th programming pulse, and the (N-2)th programming pulse, respectively. If verification operations are performed on several target levels after applying a single programming pulse, the memory device 150 can more accurately determine the threshold voltage distribution of multiple non-volatile memory cells. Based on the verification, the memory device 150 can narrow the width of the threshold voltage distribution corresponding to one of the first programming states P1 to the third programming states P3. Furthermore, the memory device 150 can more accurately determine the degree of wear or the result of the operation.

[0129] When multiple programming pulses are applied while data is being stored in multiple non-volatile memory cells included in memory group 330, reference Figure 1 The described control circuitry 180 may include information about the target level to be verified in response to each programming pulse. Additionally, based on the result of the verification operation performed in response to each programming pulse, the control circuitry 180 may include information about the level and duration of the next programming pulse applied to the plurality of non-volatile memory cells. According to an embodiment, such information may be stored in the form of a lookup table.

[0130] Figure 7 A first example of a method for operating a memory device according to an embodiment of the present disclosure is illustrated.

[0131] Reference Figure 7 The method 510 for operating a memory device may include applying programming pulses to a plurality of non-volatile memory cells (operation 512) and comparing the number of programming pulses applied (cycle count) with a maximum blind value (operation 514). See reference... Figure 3 As described, programming pulses can be applied several times to program data into multiple non-volatile memory cells.

[0132] In this document, a blind value can indicate at least one target level for which at least one programming pulse is applied without verification. The blind value can represent how many target levels the memory device 150 skips or omits verification. The memory device 150 may not perform verification with respect to the target level when the estimated target level is within a range of threshold voltage distributions of the non-volatile memory cells that will not result in errors when identifying data. For example, referring to… Figure 6 When the target level is above the median in the distribution of the third programming state P3, the memory device 150 may not need to perform a verification operation regarding the target level. The reference voltage used to identify the third programming state P3 may be the third reference voltage REF3. In the distribution of the third programming states P3, the target level above the median is higher than the third reference voltage REF3, that is, the target level is located to the right of the third reference voltage. This programming or erasing operation without verification may be called a blind method. According to an embodiment, if the maximum level that needs to be verified in response to programming pulses applied to multiple non-volatile memory cells is N target levels, then N+1 target levels may be blind values ​​(i.e., verification regarding N+1 target levels may not be performed).

[0133] By comparing the number of programming pulses applied (loop count) with the maximum blind value in operation 514, the memory device 150 can avoid performing the programming voltage application operation or the verification operation in an infinite loop of continuously increasing the target level of the verification operation. When the maximum target level in response to the programming pulse is reached ("No" in operation 514), the memory device may stop increasing the target level for the verification operation. On the other hand, when the maximum target level corresponding to the programming pulse is not reached ("Yes" in operation 514), the memory device 150 may increase the target level for the verification operation to the next level (operation 516).

[0134] When at least one target level is determined in the verification operation, the memory device 150 can perform verification operation 520 (e.g., applying a verification voltage to a programmed memory cell). According to embodiments, verification operation 520 can be performed in response to multiple target levels. A current sensing circuit (CSC) can generate a check signal CS indicating whether at least some of the multiple non-volatile memory cells have reached a target threshold voltage. According to verification operation 520, the current sensing circuit CSC can selectively generate the check signal (operation 528).

[0135] According to an implementation, verification operation 520 may include performing a verification operation corresponding to N target levels (operation 522), performing a verification operation corresponding to N-1 target levels (operation 524), and performing a verification operation corresponding to N-2 target levels (operation 526). Verification operation 520 can be performed to check the threshold voltage distribution of non-volatile memory cells based on various target levels, which can be preset according to the number of bits of data stored in the non-volatile memory cells, the shift range of the threshold voltage distribution in response to a single programming pulse, etc. When multiple target levels (such as those with reference) can be considered... Figure 6 When performing verification operation 520, the memory device can determine the next programming pulse to narrow the width of the threshold voltage distribution (the threshold voltage distribution corresponding to the first programming state P1 to the third programming state P3).

[0136] Figure 8 The variation of the threshold voltage distribution in a programming operation according to an embodiment of the present disclosure is illustrated.

[0137] exist Figure 8 This describes the verification operation performed after a programming pulse is applied to shift the threshold voltage distribution to the right. Multiple programming pulses can be applied to achieve the programming states PV1 and PV2 of the non-volatile memory cells.

[0138] exist Figure 8 In the diagram, the threshold voltage distribution before the application of the programming pulse can be indicated by dashed lines. When targeting an N-level ( Figure 8 When a programming pulse (represented as "DPGM N level") is applied to multiple non-volatile memory cells, the threshold voltage distribution of the multiple non-volatile memory cells can shift from a dashed line shape to a solid line shape. In this case, if a programming operation is performed on the multiple non-volatile memory cells to have a first programming value PV1, it can be understood that the multiple non-volatile memory cells are fully programmed based on the shifted threshold voltage distribution. In this case, the memory device 150 can execute the programming voltage application operation for the N target level (in the N+1 target level) in response to the programming voltage application operation for the N target level. Figure 8Pre-verification (exemplified as "pre-verification of N+1 level") is performed. In the pre-verification of the N+1 level, the memory device 150 can identify that at least one non-volatile memory cell has been programmed with an N+1 target level. In this case, in the verification operation performed after the next programming pulse is applied, a verification operation can be performed regarding the level starting from the N+1 target level. In the current programming cycle (i.e., the Nth programming cycle), the memory device 150 can determine whether the number of non-volatile memory cells with a threshold voltage exceeding the N+1 target level is greater than a threshold. In the next programming cycle (i.e., the (N+1)th programming cycle), verification can start from the N+1 target level. When the number of non-volatile memory cells in the current programming cycle is greater than the threshold, the memory device 150 can skip or omit the verification operations regarding the N target level and the N-1 target level in the next programming cycle.

[0139] The threshold voltage distribution of multiple non-volatile memory cells can be symmetrical about the median. Therefore, if at least one non-volatile memory cell is sensed in a verification operation with respect to a target level higher than the target level in the current programming cycle, the memory device 150 can estimate a coarse threshold voltage distribution even if verification with respect to a target level lower than the target level is omitted or skipped in the next programming cycle.

[0140] Figure 9A and Figure 9B An improved programming and verification operation according to an embodiment of the present disclosure is illustrated.

[0141] Specifically Figure 9A and Figure 9B A method for improving the programming operation speed of memory device 150 is illustrated. To narrow the threshold voltage distribution among multiple non-volatile memory cells, it is advantageous to reduce the incremental step size of Incremental Step Pulse Programming (ISPP). However, as the incremental step size of ISPP decreases, the performance of programming operations performed in memory device 150 may degrade.

[0142] Reference Figure 9ADuring ISPP, the memory device 150 can reduce the number of programming pulses applied to multiple non-volatile memory cells. In the (i-1)th programming cycle, multiple programming pulses may have already been applied to multiple non-volatile memory cells connected to the selected word line. Subsequently, when at least one non-volatile memory cell that meets a specific target level is detected by the verification process (1-bit pass) corresponding to the (i-1)th programming cycle, the memory device 150 can determine to apply at least one programming pulse to the non-volatile memory cell in the next i-th programming cycle, targeting only a target level higher than the specific target level. That is, the application of programming pulses corresponding to target levels lower than the specific target level detected in the non-volatile memory cell can be omitted or skipped. Through this process, the operation time and power consumed in ISPP can be reduced.

[0143] Reference Figure 9B The memory device 150 can reduce the time spent on verification operations corresponding to the programming voltage application operation. After applying multiple programming pulses to a non-volatile memory cell, at least one non-volatile memory cell can be detected by a verification operation (1 bit pass) with respect to the N target level. A verification operation with respect to the N+1 target level corresponding to the next programming voltage application operation can be performed first. Verification operations with respect to the N target level and target levels lower than the N target level can be omitted or skipped. In this way, the memory device 150 can reduce the time spent on verification operations performed after the programming voltage application operation.

[0144] Figure 10 A second example of a method for operating a memory device according to an embodiment of the present disclosure is illustrated.

[0145] Reference Figure 10 The method 530 for operating a memory device may include: applying programming pulses to a plurality of non-volatile memory cells (operation 532) and performing a verification operation regarding a target level higher than the target level corresponding to the programming pulse, to check whether the number of memory cells having a threshold voltage greater than or equal to the higher target level exceeds a preset threshold (operation 534). According to an embodiment, method 530 may be performed by the memory device 150 during a programming cycle.

[0146] When the memory device 150 determines, through a verification operation concerning a target level higher than the target level corresponding to the applied programming pulse, that the number of non-volatile memory cells is greater than or equal to a preset threshold ("Yes" in operation 534), the target level for the verification operation corresponding to the current programming pulse may be increased (operation 536). When, through a verification operation concerning a target level higher than the target level corresponding to the applied programming pulse, the number of non-volatile memory cells is less than the preset threshold ("No" in operation 534), the target level for the verification operation corresponding to the current programming pulse may not be increased.

[0147] The memory device 150 can perform a verification operation (operation 538) regarding a target level higher than the target level corresponding to the current programming pulse. The verification result can be used to determine how to perform the verification operation corresponding to the programming pulse applied in the next programming cycle.

[0148] According to one embodiment, the memory device 150 can adjust the verification operation (operation 540) with respect to a preset target level after the verification operation. For example, the verification operation (operation 540) for multiple target levels nPV, n-1PV, n-2PV in the current programming cycle can be adjusted or skipped based on the number of memory cells checked during the verification operation. According to one embodiment, the verification operation 540 can include multiple verification operations in response to multiple target levels. The current sensing circuit (CSC) can generate a check signal CS indicating whether at least some of the multiple non-volatile memory cells have a threshold voltage that reaches the target level. In response to the verification operation 540, the current sensing circuit CSC can selectively generate the check signal (operation 548).

[0149] According to the implementation, verification operation 540 may include performing a verification operation regarding a target level of N (operation 542), performing a verification operation regarding a target level of N-1 (operation 544), and performing a verification operation regarding a target level of N-2 (operation 546). Verification operation 540 can be performed for various target levels determined based on factors such as the number of bits of data stored in the non-volatile memory cell, the range of shift or movement of the threshold voltage distribution in response to a programming pulse, etc. When verification operations are performed for target levels of N and levels below target level N, a reference is achieved. Figure 6 When describing the threshold voltage distribution from the first programming state P1 to the third programming state P3, the memory device 150 can determine the next programming pulse to narrow the width of the threshold voltage distribution.

[0150] According to an embodiment, the memory device 150 can perform a verification operation regarding a target level higher than the target level corresponding to the applied programming pulse. For example, when the number of non-volatile memory cells is greater than or equal to a preset threshold in a verification operation regarding a target level higher than the target level corresponding to the applied programming pulse ("Yes" in operation 534), the verification operation for at least some lower target levels in verification operation 540 can be skipped or omitted. See also Figure 9B As described, when verification operations for at least some lower target levels are omitted or skipped, the resources spent on verification operations can be reduced.

[0151] Figure 11 Verification operations according to embodiments of this disclosure are illustrated. Specifically, Figure 11 This describes a verification operation performed after a programming pulse is applied to a non-volatile memory cell. The verification operation may include a verification operation regarding an N+1 target level, which is higher than the N target level corresponding to the programming pulse used to program the non-volatile memory cell to the N target level.

[0152] Reference Figure 11 The memory device 150 can apply a programming pulse to program a non-volatile memory cell to a target level PV. After applying the programming pulse, a verification operation can be performed for multiple target levels. The verification operation (verification) can include a first verification operation (PV+ verification) with respect to a target level PV+ that is higher than the target level PV corresponding to the programming pulse, and a second verification operation (PV verification) with respect to the target level PV.

[0153] According to the implementation, the method for performing a first verification operation (PV+ verification) with respect to a higher target level PV+ (e.g., the target level of the next programming pulse) can be divided into two different methods, where the higher target level PV+ is higher than the target level PV corresponding to the programming pulse. In the first method, the voltage level used for the second verification operation (PV verification) is also used for the first verification operation (PV+ verification), but the first verification time tEVAL1 of the first verification operation (PV+ verification) is longer than the second verification time tEVAL2 or the third verification time tEVAL3 used for the second verification operation (PV verification). Because the same voltage level can be applied to the selected word line in both the first verification operation (PV+ verification) and the second verification operation (PV verification), the precharge operation can be performed only once before the first verification operation (PV+ verification). That is, after performing a single precharge operation tPreC1, both the first verification operation PV+ verification and the second verification operation PV verification can be performed.

[0154] The second method may include applying a voltage higher than that applied to the first verification operation (PV+ verification) compared to the second verification operation (PV verification). Because different voltage levels are applied to the selected word line in the first verification operation (PV+ verification) and the second verification operation (PV verification), the first verification time tEVAL1 may not be longer than the second verification time tEVAL2 or the third verification time tEVAL3. However, because different voltage levels are applied to the selected word line, a separate precharge operation should be performed further. That is, the first precharge operation tPreC1 can be performed before the first verification operation (PV+ verification), and the second precharge operation tPreC2 can be performed before the second verification operation (PV verification).

[0155] By using the two methods described above after applying a programming pulse to a target level, verification operations corresponding to the corresponding programming pulse can be performed with respect to multiple target levels. Specifically, the multiple target levels may include a target level PV+ that is higher than the target level PV corresponding to the applied programming pulse (e.g., the target level corresponding to the next programming pulse).

[0156] Figure 12 An example is given of the improved performance obtained by a method for operating a memory device according to an embodiment of the present disclosure.

[0157] Reference Figure 12 This reduces the number of verification operations during programming, thus improving programming performance. Multiple programming pulses PV1 to PV7 are used for applying the programming voltage, and... Figure 12 The multiple verification levels 1 to 18 described in the verification operation can be quantified as examples for understanding embodiments of the present invention. Multiple programming pulses and multiple verification levels used within the memory device 150 can be changed or adjusted according to the operating characteristics of the memory group 330.

[0158] Referring to the case where the verification operation is performed unchanged during the programming operation performed by the memory device 150 ( Figure 12As shown in the table above, verification operations corresponding to each of the first programming pulses PV1 to the seventh programming pulse PV7 can be performed with respect to five different target levels. For example, after applying the first programming pulse PV1, verification operations can be performed with respect to the five target levels 5 to 1. During the verification operation corresponding to the first programming pulse PV1, the memory device 150 can determine that the number of memory cells having a threshold voltage corresponding to a higher target level is less than a preset threshold. Therefore, after applying the second programming pulse PV2, verification operations can be performed with respect to the five target levels 7 to 3. During the verification operation corresponding to the second programming pulse PV2, the memory device 150 can determine that the number of memory cells having a threshold voltage corresponding to a higher target level is less than a preset threshold. Then, after applying the third programming pulse PV3, verification operations can be performed for the five target levels 9 to 5. In this case, no verification is adjusted.

[0159] like Figure 12 As illustrated in the table below, in the memory device 150 according to an embodiment of the present disclosure, when a first programming pulse PV1 is applied, verification operations can be performed with respect to the next (or higher) target level 6 and five target levels 5 to 1. In the verification operation with respect to the next target level 6, at least one non-volatile memory cell can be detected, or the memory device 150 can determine that the number of memory cells having a threshold voltage corresponding to a higher target level is greater than or equal to a preset threshold. The memory device 150 can adjust the target level for the verification operation in the next programming cycle. Thereafter, after the second programming pulse PV2 is applied, verification operations can be performed only with respect to target levels equal to or greater than the target level 6 that satisfies the aforementioned preset condition. That is, verification operations are omitted or skipped with respect to target levels lower than target level 6 (e.g., levels 5 and 4). Therefore, for the second programming pulse PV2, verification operations with respect to three target levels 8 to 6 can be performed. Here, target level 8 can correspond to the third programming pulse PV3, and target levels 7 and 6 can correspond to the second programming pulse PV2. For the verification operation performed in response to the second programming pulse PV2 with respect to the three target levels 8 to 6, the memory device 150 may perform... Figure 11 The first verification operation (PV+ verification) and the second verification operation (PV verification) are described in the document. When at least one non-volatile memory cell or the number of memory cells having a threshold voltage corresponding to a higher target level is detected in the first verification operation (PV+ verification) corresponding to each programming pulse is greater than or equal to a preset threshold, verification can be performed only regarding... Figure 12The three target levels shown continuously execute the verification operation corresponding to each programming pulse. Compared to the case where verification operations are performed at a preset number of levels in response to each programming pulse (see the table above), the number of verification operations (see the table below) can be significantly reduced. This process improves the programming performance of the memory device 150.

[0160] As described above, the memory device according to the embodiments of the present disclosure can improve the data input / output speed.

[0161] Furthermore, according to embodiments of this disclosure, the security of data items stored in the memory device can be improved and the wear and tear on the memory device can be reduced.

[0162] While the teachings have been illustrated and described with reference to specific embodiments, it will be apparent to those skilled in the art, based on this disclosure, that various changes and modifications can be made without departing from the spirit and scope of the disclosure as defined in the appended claims. Furthermore, embodiments can be combined to form additional embodiments.

[0163] Cross-references to related applications

[0164] This patent application claims priority to Korean Patent Application No. 10-2021-0045258, filed on April 7, 2021, the entire disclosure of which is incorporated herein by reference.

Claims

1. A memory device comprising: A unit group, the unit group comprising multiple non-volatile memory units capable of storing data; as well as A control circuit executes multiple programming cycles for storing the data, each programming cycle including a programming voltage application operation for the multiple non-volatile memory cells and a verification operation corresponding to the programming voltage application operation. The control circuit, during the corresponding programming cycle, performs the verification operation for the target level N, the N-1 target level below the target level N, and the N+1 target level above the target level N in response to the application of the programming voltage for the target level N. Wherein, when the number of non-volatile memory cells having a threshold voltage exceeding the N+1 target level meets a preset standard, the control circuit skips the next verification operation for a target level lower than the N+1 target level in response to applying an operation for the next programming voltage for the N+1 target level.

2. The memory device according to claim 1, wherein, The number of target levels corresponding to the plurality of programming cycles is three times the number of bits of data to be stored in each of the plurality of nonvolatile memory cells.

3. The memory device according to claim 1, wherein, The control circuit performs the verification operation corresponding to the programming voltage application operation by applying a first voltage to the selected word line for a first verification operation for the N+1 target level and applying a second voltage lower than the first voltage to the selected word line for a second verification operation for the N-1 target level and the N target level.

4. The memory device according to claim 3, wherein, The control circuit precharges the bit lines connected to the plurality of non-volatile memory cells before the first verification operation and the second verification operation.

5. The memory device according to claim 1, in, The control circuit performs the verification operation corresponding to the programming voltage application operation by applying a first voltage to the selected word line for a first verification operation for the N+1 target level and a second verification operation for the N-1 target level or the N target level, and The control circuit performs the first verification operation for a longer period than the second verification operation.

6. The memory device according to claim 5, wherein, The control circuit precharges the bit lines connected to the plurality of non-volatile memory cells prior to the first verification operation.

7. The memory device according to claim 1, wherein, The control circuit changes or adjusts the preset standard based on the programming / erasing cycles of the plurality of non-volatile memory cells.

8. A memory system comprising: A controller that determines a location for storing programming data and transmits programming commands along with the programming data; as well as A memory device, connected to the controller via a data path, receives the programming commands and the programming data, and outputs a success or failure message regarding the programming operation performed on the programming data. The memory device includes: At least one storage block, the at least one storage block comprising a plurality of non-volatile memory cells capable of storing the programming data; and A control circuit executes multiple programming cycles for storing the programming data in at least a few non-volatile memory cells linked to a selected word line in the at least one memory block. Each programming cycle includes a programming voltage application operation and a verification operation corresponding to the programming voltage application operation. The control circuit, during the corresponding programming cycle, performs the verification operation for the target level N, the N-1 target level below the target level N, and the N+1 target level above the target level N in response to the application of the programming voltage for the target level N. Wherein, when the number of non-volatile memory cells having a threshold voltage exceeding the N+1 target level meets a preset standard, the control circuit skips the next verification operation for a target level lower than the N+1 target level in response to applying an operation for the next programming voltage for the N+1 target level.

9. The memory system according to claim 8, wherein, The memory device includes: A buffer, which temporarily stores the programming data to be stored in the location; and A voltage supply circuit, controlled by the control circuit, applies a first voltage to the selected word line and applies a second voltage with a different level from the first voltage to the unselected word line.

10. The memory system according to claim 8, wherein, The number of target levels corresponding to the plurality of programming cycles is three times the number of bits of the programming data to be stored in each of the plurality of nonvolatile memory cells.

11. The memory system according to claim 8, wherein, The control circuit performs the verification operation corresponding to the programming voltage application operation by applying a first voltage to the selected word line for a first verification operation for the N+1 target level and applying a second voltage lower than the first voltage to the selected word line for a second verification operation for the N-1 target level and the N target level.

12. The memory system according to claim 11, wherein, The control circuit precharges the bit lines connected to the at least some non-volatile memory cells before the first verification operation and the second verification operation.

13. The memory system according to claim 10, in, The control circuit performs the verification operation corresponding to the programming voltage application operation by applying a first voltage to the selected word line for a first verification operation for the N+1 target level and a second verification operation for the N-1 target level or the N target level. The control circuit performs the first verification operation for a longer period than the second verification operation.

14. The memory system according to claim 13, wherein, The control circuit precharges the bit lines connected to the at least some non-volatile memory cells prior to the first verification operation.

15. The memory system according to claim 8, wherein, The control circuit changes or adjusts the preset standard based on the programming / erasing cycles of the plurality of non-volatile memory cells.

16. A method for operating a memory device, the method comprising the steps of: Receive programming data, information about the location for storing the programming data, and programming commands; Select the word line corresponding to the information about the location; as well as Multiple programming cycles are executed to store the programming data in at least some non-volatile memory cells connected to the selected word line. Each programming cycle includes a programming voltage application operation and a verification operation corresponding to the programming voltage application operation. The steps of executing the plurality of programming loops include the following steps: during the respective programming loops, In response to the application of the programming voltage for the N target level, the verification operation is performed for the N target level, the N-1 target level below the N target level, and the N+1 target level above the N target level; Determine whether the number of non-volatile memory cells with a threshold voltage exceeding the N+1 target level meets a preset standard; and Based on the determined result, in response to the application of the next programming voltage for the N+1 target level, the next verification operation for the target level lower than the N+1 target level is skipped.

17. The method according to claim 16, wherein, The steps for performing the verification operation include the following: For the first verification operation targeting the N+1 target level, a first voltage is applied to the selected word line; and For the second verification operation targeting the N-1 target level and the N target level, a second voltage lower than the first voltage is applied to the selected word line.

18. The method according to claim 17, wherein, The steps for performing the verification operation also include the following steps: Prior to the first verification operation, the bit lines connected to the at least some non-volatile memory cells are pre-charged; and Prior to the second verification operation, the bit lines connected to the at least some of the non-volatile memory cells are pre-charged.

19. The method of claim 16, wherein, The steps for performing the verification operation include the following: For the first verification operation targeting the N+1 target level and the second verification operation targeting the N-1 target level or the N target level, a first voltage is applied to the selected word line, and The first verification operation takes longer than the second verification operation.

20. The method according to claim 19, wherein, The steps of performing the verification operation include the following steps: prior to the first verification operation, precharging the bit lines connected to the at least some non-volatile memory cells.

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