Mode control structure, test mode control method, and memory

Abstract

The present disclosure relates to the field of semiconductor circuit design, and particularly to a mode control structure, a test mode control method, and a memory, including: a configuration module, configured to receive a pre-control signal of the memory and a mode selection signal of a mode register, and if the pre-control signal is valid, generate an intermediate control signal based on the mode selection signal; a transmission module, generating a test reset signal based on the mode decoding signal and the intermediate control signal; a control unit, disposed in the transmission module, configured to receive a reset cancellation signal, and configured to remove the reset pulse included in the test reset signal based on the reset cancellation signal; a test signal generation module, configured to generate a test indication signal based on the test reset signal; when the 7th bit A is set to 0, the DFT reset signal generated inside the memory is eliminated, so that the test indication signal of the memory is prevented from being reset, and the memory can stably be in the test mode for testing.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor circuit design, and particularly to a mode control structure, a test mode control method, and a memory. Background Art

[0002] Dynamic Random Access Memory (DRAM) has a test mode, which is usually used by manufacturers for the production and detection of memories and is not open to users. Therefore, when configuring MRS0 on the system, the A7 bit is set to 0, so that the memory operates in the normal mode. Existing DRAM designs also clear the signals that enabled the test mode before to ensure that users do not enable the test mode, so as to prevent the memory from triggering unexpected effects.

[0003] However, during the CP test, BI test, and FT test of the memory, if there is a problem with the memory, it is difficult to locate the specific location of the error. If the test can be performed in the test mode during the memory test, it is convenient to locate the specific location of the problem.

[0004] For the current DRAM structure, during the configuration of the mode register, when the A7 bit is set to 0, a DFT (design for test) reset signal is generated inside the memory to reset the test indication signal of the memory. At this time, the memory cannot be stably in the test mode. Summary of the Invention

[0005] Embodiments of the present disclosure provide a mode control structure, a test mode control method, and a memory. When the A7 bit is set to 0, the DFT reset signal generated inside the memory is eliminated, so that the test indication signal of the memory is not reset, and the memory can be stably in the test mode for testing.

[0006] An embodiment of the present disclosure provides a mode control structure, including: a configuration module configured to receive a pre-control signal of a memory and a mode selection signal of a mode register, and the configuration module is configured to generate an intermediate control signal based on the mode selection signal if the pre-control signal is valid; a transmission module, one input terminal of which is connected to the output terminal of the configuration module, and the other input terminal is configured to receive a mode decoding signal, wherein the mode decoding signal includes a reset pulse generated by decoding a control command of the mode register, and the transmission module is configured to generate a test reset signal based on the mode decoding signal and the intermediate control signal; a control unit disposed in the transmission module and configured to receive a reset cancellation signal, and the control unit is configured to remove the reset pulse included in the test reset signal based on the reset cancellation signal; a test signal generation module connected to the output terminal of the transmission module and configured to generate a test indication signal based on the test reset signal, and the test indication signal is used to indicate whether the memory is in a test mode.

[0007] In the embodiment of the present disclosure, by setting the control unit, the control unit receives the reset cancellation signal and eliminates the influence of the reset pulse in the mode decoding signal on the generated test reset signal, so that the generated test reset signal no longer includes the reset pulse, thereby avoiding the test indication signal from being reset and enabling the memory to be stably tested in the test mode.

[0008] In addition, the configuration module includes: a first NAND gate, each input terminal of which is respectively configured to receive a sub-selection signal, and a plurality of sub-selection signals received by all input terminals of the first NAND gate constitute the mode selection signal; a first NOR gate, one input terminal of which is connected to the output terminal of the first NAND gate, the other input terminal is configured to receive the pre-control signal, and the output terminal is configured to output the intermediate control signal.

[0009] In addition, the transmission module includes: a second NAND gate, one input terminal of which is configured to receive the intermediate control signal, the other input terminal is configured to receive the mode decoding signal, and the output terminal is configured to output a first intermediate signal; a third NAND gate, one input terminal of which is configured to receive the first intermediate signal, the other input terminal is configured to receive the reset signal, and the output terminal is configured to output a second intermediate signal; a control OR gate, one input terminal of which is configured to receive the second intermediate signal, the other input terminal is configured to receive the test control signal, and the output terminal is configured to output the test reset signal.

[0010] In addition, the control unit is configured to receive the mode decoding signal, and the control unit is configured to remove the reset pulse included in the mode decoding signal based on the reset cancellation signal; the second NAND gate generates the first intermediate signal based on the adjusted mode decoding signal and the intermediate control signal.

[0011] In addition, the control unit is configured to receive a second intermediate signal, and based on a reset cancellation signal, remove a reset pulse included in the second intermediate signal; the control OR gate generates a test reset signal based on the adjusted second intermediate signal and a test control signal.

[0012] In addition, the control unit is configured to receive a test reset signal, and based on a reset cancellation signal, remove a reset pulse included in the test reset signal; the test signal generation module generates a test indication signal based on the adjusted test reset signal.

[0013] In addition, the control unit includes: a fourth NAND gate, one input terminal of which is configured to receive a reset cancellation signal, and the other input terminal is connected to the transmission module; a control inverter, the input terminal of which is connected to the output terminal of the fourth NAND gate, and the output terminal is connected to the transmission module.

[0014] In addition, the control unit is configured to receive a first intermediate signal, and based on a reset cancellation signal, remove a reset pulse included in the first intermediate signal; the third NAND gate generates a second intermediate signal based on the adjusted first intermediate signal and a reset signal.

[0015] In addition, the control unit includes: a second NOR gate, one input terminal of which is configured to receive a reset cancellation signal, and the other input terminal is configured to receive a first intermediate signal; a control inverter, the input terminal of which is connected to the output terminal of the second NOR gate, and the output terminal is connected to the output terminal of the third NAND gate.

[0016] In addition, the mode control structure further includes: a driving module configured to provide a reset cancellation signal according to a driving pulse.

[0017] In addition, the driving module includes: a first control NOR gate and a second control NOR gate, wherein one input terminal of the first control NOR gate is connected to the output terminal of the second control NOR gate, one input terminal of the second control NOR gate is connected to the output terminal of the first control NOR gate, the other input terminal of the first control NOR gate is configured to receive a driving pulse, and the output terminal is configured to output a reset cancellation signal, and the other input terminal of the second control NOR gate is configured to receive a switch signal for turning on the driving module.

[0018] In addition, the driving module includes: a first control NAND gate and a second control NAND gate, wherein one input terminal of the first control NAND gate is connected to the output terminal of the second control NAND gate, one input terminal of the second control NAND gate is connected to the output terminal of the first control NAND gate, the other input terminal of the first control NAND gate is configured to receive a switch signal for turning on the driving module, and the output terminal of the second control NAND gate is configured to output a reset cancellation signal.

[0019] In addition, the switching signal is provided based on the antifuse memory cell of the memory. When the antifuse memory cell is not blown, the provided switching signal is at a high level to turn on the driving module; when the antifuse memory cell is blown, the provided switching signal is at a low level to turn off the driving module, thereby prohibiting the provision of the reset cancellation signal and preventing the memory provided to the user from entering the test mode, which may affect the normal use of the user.

[0020] Another embodiment of the present disclosure further provides a memory, which uses the mode control structure provided in the above embodiment to control the working mode of the memory. When the A7 bit is set to 0, the DFT (design for test) reset signal generated inside the memory is eliminated, so that the test indication signal of the memory is not reset, and the memory can stably operate in the test mode for testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not limit the embodiments unless otherwise stated. The figures in the drawings do not constitute a proportional limitation; in order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required to be used in the embodiments. Obviously, the following described drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0022] Figure 1 is a schematic structural diagram of the mode control structure provided in an embodiment of the present disclosure;

[0023] Figures 2 to 5 is a schematic diagram of different specific structures of the mode control structure provided in an embodiment of the present disclosure;

[0024] Figure 6 is a timing diagram of each signal in the mode control structure provided in an embodiment of the present disclosure;

[0025] Figure 7 is a schematic structural diagram of a specific driving module provided in an embodiment of the present disclosure;

[0026] Figure 8 is a schematic structural diagram of another specific driving module provided in an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0027] As can be seen from the background art, for the current DRAM structure, during the process of configuring the mode register, when the A7 bit is set to 0, a DFT (design for test) reset signal will be generated inside the memory to reset the test indication signal of the memory. At this time, the memory cannot stably operate in the test mode.

[0028] An embodiment of the present disclosure provides a mode control structure. When the A7 bit is set to 0, the DFT reset signal generated inside the memory is eliminated, so that the test indication signal of the memory is prevented from being reset, and the memory can stably operate in the test mode for testing.

[0029] Those of ordinary skill in the art can understand that, in various embodiments of the present disclosure, many technical details are provided to help readers better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented. The following division of each embodiment is for convenience of description and should not constitute any limitation to the specific implementation manner of the present disclosure. Each embodiment can be combined with each other and cross-referenced on the premise of no contradiction.

[0030] Figure 1 It is a schematic structural diagram of the mode control structure provided in this embodiment. Figures 2 to 5 It is a schematic diagram of different specific structures of the mode control structure provided in this embodiment. Figure 6 It is a timing diagram of each signal in the mode control structure provided in this embodiment. Figure 7 It is a schematic structural diagram of a specific driving module provided in this embodiment. Figure 8 It is a schematic structural diagram of another specific driving module provided in this embodiment. The mode control structure provided in this embodiment will be described in detail below with reference to the accompanying drawings, as follows:

[0031] Refer to Figures 1 to 5 , the mode control structure includes:

[0032] A configuration module 101, configured to receive the pre-control signal PAMRT<7> and the mode control signal of the memory. The configuration module 101 is configured such that if the pre-control signal PAMRT<7> is valid, an intermediate control signal is generated based on the mode selection signal.

[0033] It should be noted that the pre-control signal PAMRT<7> is the A7 signal in the memory. In this embodiment, the validity of the pre-control signal PAMRT<7> means that the A7 signal is at a low level.

[0034] A transmission module 201, one input terminal is connected to the output terminal of the configuration module 101, and the other input terminal is used to receive the mode decoding signal MRSSET. The mode decoding signal MRSSET includes a reset pulse generated by decoding the control command of the mode register. The transmission module 201 is configured to generate a test reset signal TDFTRST based on the mode decoding signal MRSSET and the intermediate control signal.

[0035] It should be noted that for the pattern decoding signal MRSSET, the reset pulse generated by the control command of the included decoding mode register is the DFT (design for test) reset signal mentioned in the background art.

[0036] The control unit 301 is disposed in the transmission module 201 and is configured to receive a reset cancellation signal. The control unit 301 is configured to remove the reset pulse included in the test reset signal based on the reset cancellation signal.

[0037] The test signal generation module 401 is connected to the output end of the transmission module 201 and is configured to generate a test indication signal based on the test reset signal. The test indication signal is used to indicate whether the memory is in the test mode.

[0038] Specifically, when the test indication signal is at a high level, the memory is in the test mode; when the test indication signal is at a low level, the memory is in the normal mode.

[0039] In the embodiment of the present disclosure, by setting the control unit 301, the control unit 301 clears the influence of the reset pulse in the pattern decoding signal MRSSET on the generated test reset signal TDFTRST through the received reset cancellation signal, so that the generated test reset signal TDFTRST no longer includes the reset pulse, thereby avoiding the test indication signal from being reset and enabling the memory to be stably tested in the test mode.

[0040] Reference Figures 2 to 5 , in some embodiments, the configuration module 101 includes: a first NAND gate 110, each input terminal of which is respectively used to receive a sub-selection signal. Among them, a plurality of sub-selection signals received by all input terminals of the first NAND gate 110 constitute a pattern selection signal. A first NOR gate 120, one input terminal of which is connected to the output terminal of the first NAND gate 110, and the other input terminal is used to receive a pre-control signal PAMRT<7>, and the output terminal is used to output an intermediate control signal. Specifically, in this embodiment, the sub-selection signals are PBGMRB<0>, PBAMRB<0>, and PBAMRB<1>, that is, the BG0 signal, BA0 signal, and BA1 signal of the memory.

[0041] In some embodiments, the transmission module 201 includes: a second NAND gate 210, one input terminal for receiving an intermediate control signal, another input terminal for receiving a mode decoding signal MRSSET, and an output terminal for outputting a first intermediate signal MRSETB. A third NAND gate 220, one input terminal for receiving the first intermediate signal MRSETB, another input terminal for receiving a reset signal, and an output terminal for outputting a second intermediate signal PMRSTT. A control OR gate 230, one input terminal for receiving the second intermediate signal PMRSTT, another input terminal for receiving a test control signal TCLRT, and an output terminal for outputting a test reset signal TDFTRST.

[0042] Specifically, in this embodiment, the reset signal includes a first reset signal PRESET and a second reset signal TWRSTPB. For the values of the first reset signal PRESET and the second reset signal TWRSTPB, they are at a low level in other test modes and hinder the current test mode. Therefore, in this embodiment, the first reset signal PRESET and the second reset signal TWRSTPB are constantly at a high level. For the test control signal TCLRT, the test control signal TCLRT is used to invalidate the operation of the mode register. Therefore, in this embodiment, the test control signal TCLRT is constantly at a low level.

[0043] For the control unit 301, four setting methods of the control unit 301 are given in this embodiment, which are specifically as follows:

[0044] In some embodiments, referring to Figure 2 , the control unit 301 is configured to receive the mode decoding signal MRSSET, and the control unit 301 is configured to remove the reset pulse included in the mode decoding signal MRSSET based on a reset cancellation signal. The second NAND gate 210 generates a first intermediate signal based on the adjusted mode decoding signal MRSSET and the intermediate control signal.

[0045] In this example, the control unit 301 includes: a fourth NAND gate 310, one input terminal for receiving the reset cancellation signal, and another input terminal connected to an input terminal of the transmission module 201 for receiving the mode decoding signal MRSSET; a control inverter 320, an input terminal connected to the output terminal of the fourth NAND gate 310, and an output terminal connected to an input terminal of the second NAND gate 210 of the transmission module 201 for outputting the adjusted mode decoding signal MRSSET.

[0046] Referring to Figure 6, PBGMRB<0> = 1, PBAMRB<0> = 1, PBAMRB<1> = 1, that is, the mode selection input of the mode register is 111, the pre-control signal PAMRT<7> = 0, and the intermediate control signal generated according to the first NAND gate 110 and the first NOR gate 120 is high level; the mode decoding signal MRSSET before adjustment contains a reset pulse. At this time, the timing of the mode decoding signal MRSSET is 1°, correspondingly, the timing of the first intermediate signal MRSETB output by the second NAND gate 210 is 3°, correspondingly, the first reset signal PRESET and the second reset signal TWRSTPB are high level, correspondingly, the timing of the second intermediate signal MRSETB output by the third NAND gate 220 is 5°, correspondingly, the timing of the test reset signal TDFTRST output by the control NOR gate 230 is 7°, the test control signal TCLRT is constantly low level, and correspondingly, the timing of the test reset signal TDFTRST generated by the test signal generation module 401 is 9°.

[0047] The reset pulse signal is low level. The fourth NAND gate 310 and the control inverter 320 generate the adjusted mode decoding signal MRSSET based on the reset pulse signal and the mode decoding signal MRSSET before adjustment, and the timing is 2°. The reset pulse contained in the mode decoding signal MRSSET is removed. Correspondingly, the timing of the first intermediate signal MRSETB output by the second NAND gate 210 is 4°, correspondingly, the first reset signal PRESET and the second reset signal TWRSTPB are high level, correspondingly, the timing of the second intermediate signal MRSETB output by the third NAND gate 220 is 6°, correspondingly, the timing of the test reset signal TDFTRST output by the control NOR gate 230 is 8°, the test control signal TCLRT is constantly low level, and correspondingly, the timing of the test reset signal TDFTRST generated by the test signal generation module 401 is 10°, and the test indication signal remains high, avoiding the reset of the test indication signal, so that the memory can be stably in the test mode for testing.

[0048] In some embodiments, refer to Figure 3 , the control unit 301 is used to receive the second intermediate signal PMRSTT, and the control unit 301 is configured to remove the reset pulse contained in the second intermediate signal PMRSTT based on the reset cancellation signal, and the control NOR gate 230 generates the test reset signal TDFTRST based on the adjusted second intermediate signal PMRSTT and the test control signal TCLRT.

[0049] In this example, the control unit 301 includes: a fourth NAND gate 310, one input terminal for receiving a reset cancellation signal, and the other input terminal connected to the output terminal of the third NAND gate 220 of the transmission module 201 for receiving a second intermediate signal PMRSTT; a control inverter 320, the input terminal connected to the output terminal of the fourth NAND gate 310, and the output terminal connected to one input terminal of the control OR gate 230 of the transmission module 201 for outputting an adjusted second intermediate signal PMRSTT.

[0050] Reference Figure 6 , PBGMRB<0>=1, PBAMRB<0>=1, PBAMRB<1>=1, that is, the mode selection input of the mode register is 111, the pre-control signal PAMRT<7>=0, and the intermediate control signal generated by the first NAND gate 110 and the first NOR gate 120 is high level; the timing of the mode decoding signal MRSSET before adjustment is 1°, correspondingly, the timing of the first intermediate signal MRSETB output by the second NAND gate 210 is 3°, the reset pulse signal is low level, the first reset signal PRESET and the second reset signal TWRSTPB are high level, correspondingly, the timing of the adjusted second intermediate signal MRSETB generated by the fourth NAND gate 310 and the control inverter 320 based on the reset pulse signal and the second intermediate signal MRSETB before adjustment is 6°, removing the reset pulse included in the second intermediate signal MRSETB, correspondingly, the timing of the test reset signal TDFTRST output by the control NOR gate 230 is 8°, the test control signal TCLRT is constantly low level, correspondingly, the timing of the test reset signal TDFTRST generated by the test signal generation module 401 is 10°, and the test indication signal remains high, avoiding the reset of the test indication signal, so that the memory can be stably in the test mode for testing.

[0051] In some embodiments, reference Figure 4 , the control unit 301 is used to receive the test reset signal TDFTRST, and the control unit 301 is configured to remove the reset pulse included in the test reset signal TDFTRST based on the reset cancellation signal, and the test signal generation module 401 generates a test indication signal based on the adjusted test reset signal TDFTRST.

[0052] In this example, the control unit 301 includes: a fourth NAND gate 310, one input terminal for receiving a reset cancellation signal, and the other input terminal connected to the output terminal of the control OR gate 230 of the transmission module 201 for receiving the test reset signal TDFTRST; a control inverter 320, the input terminal connected to the output terminal of the fourth NAND gate 310, and the output terminal connected to the output terminal of the transmission module 201 for outputting an adjusted test reset signal TDFTRST.

[0053] ReferenceFigure 6 When PBGMRB<0> = 1, PBAMRB<0> = 1, and PBAMRB<1> = 1, that is, the mode selection input of the mode register is 111, and the pre-control signal PAMRT<7> = 0, the intermediate control signal generated by the first NAND gate 110 and the first NOR gate 120 is at a high level; the timing of the mode decoding signal MRSSET before adjustment is 1°, correspondingly, the timing of the first intermediate signal MRSETB output by the second NAND gate 210 is 3°, the first reset signal PRESET and the second reset signal TWRSTPB are at a high level, correspondingly, the timing of the second intermediate signal MRSETB output by the third NAND gate 220 is 5°, correspondingly, the timing of the test reset signal TDFTRST output by the control NOR gate 230 is 7°, the reset pulse signal is at a low level, the test control signal TCLRT is constantly at a low level, correspondingly, the fourth NAND gate 310 and the control inverter 320 generate the adjusted test reset signal TDFTRST based on the reset pulse signal and the test reset signal TDFTRST before adjustment, and the timing is 10°. The reset pulse included in the test reset signal TDFTRST is removed, and the test indication signal remains high, avoiding the reset of the test indication signal, so that the memory can be stably in the test mode for testing.

[0054] In some embodiments, refer to Figure 5 The control unit 301 is configured to receive the first intermediate signal MRSETB, and the control unit 301 is configured to remove the reset pulse included in the first intermediate signal MRSETB based on the reset cancellation signal, and the third NAND gate 220 generates the second intermediate signal PMRSTT based on the adjusted first intermediate signal MRSETB and the reset signal.

[0055] In this example, the control unit 301 includes: a second NOR gate 330, one input terminal is used to receive the reset cancellation signal, and the other input terminal is connected to the output terminal of the second NOR gate 210 of the transmission module 201 for receiving the first intermediate signal MRSETB; a control inverter 320, the input terminal is connected to the output terminal of the second NOR gate 330, and the output terminal is connected to the output terminal of the third NOR gate 220 of the transmission module 201 for outputting the adjusted first intermediate signal MRSETB.

[0056] In this example, PBGMRB<0> = 1, PBAMRB<0> = 1, PBAMRB<1> = 1, that is, the mode selection input of the mode register is 111, the pre-control signal PAMRT<7> = 0, and the intermediate control signal generated according to the first NAND gate 110 and the first NOR gate 120 is at a high level; the timing of the mode decoding signal MRSSET before adjustment is 1°, the reset pulse signal is at a high level, and correspondingly, the timing of the adjusted first intermediate signal MRSETB generated by the second NOR gate 330 and the control inverter 320 based on the reset pulse signal and the first intermediate signal MRSETB before adjustment is 4°, the first reset signal PRESET and the second reset signal TWRSTPB are at a high level, and correspondingly, the timing of the second intermediate signal MRSETB output by the third NAND gate 220 is 6°, and correspondingly, the timing of the test reset signal TDFTRST output by the control NOR gate 230 is 8°, the test control signal TCLRT is constantly at a low level, and correspondingly, the timing of the test reset signal TDFTRST generated by the test signal generation module 401 is 10°, and the test indication signal remains at a high level, avoiding the reset of the test indication signal, so that the memory can be stably in the test mode for testing.

[0057] Reference Figure 7 and Figure 8 , in some embodiments, the mode control structure further includes: a driving module 501 for providing a reset cancellation signal according to a driving pulse.

[0058] In one example, reference Figure 7 , the driving module 501 includes: a first control NOR gate 510 and a second control NOR gate 520, wherein one input terminal of the first control NOR gate 510 is connected to the output terminal of the second control NOR gate 520, one input terminal of the second control NOR gate 520 is connected to the output terminal of the first control NOR gate 510, the other input terminal of the first control NOR gate 510 is used for receiving the driving pulse, and the output terminal is used for outputting the reset cancellation signal, and the other input terminal of the second control NOR gate 520 is used for receiving a switch signal, and the switch signal is used to turn on the driving module 501.

[0059] Specifically, the driving module 501 is an RS flip-flop composed of NOR gates. At this time, the RS flip-flop is triggered based on a high level, and at this time, the clear input terminal is used for receiving the driving pulse, and the set input terminal is used for receiving the switch signal input based on an inverter. When the switch signal is at a high level, the driving module 501 is started. At this time, when there is a high-level pulse in the driving pulse, a low-level reset cancellation signal is generated, thus avoiding the reset of the test indication signal, so that the memory can be stably in the test mode for testing; when the switch signal is at a low level, the generated reset cancellation signal is at a high level and cannot be used for the reset of the test indication signal, that is, the driving module 501 is turned off.

[0060] In one example, referring to Figure 8 , the driving module 501 includes: a first control NAND gate 530 and a second control NAND gate 540. One input terminal of the first control NAND gate 530 is connected to the output terminal of the second control NAND gate 540, and one input terminal of the second control NAND gate 540 is connected to the output terminal of the first control NAND gate 530. Another input terminal of the first control NAND gate 530 is used to receive a switch signal, and the switch signal is used to turn on the driving module 501. Another input terminal of the second control NAND gate 540 is used to receive a driving pulse, and the output terminal is used to output a reset cancellation signal.

[0061] Specifically, the driving module 501 is an RS flip-flop composed of NAND gates. At this time, the RS flip-flop is triggered based on a low level. At this time, the reset input terminal is used to receive the driving pulse output based on an inverter, and the set input terminal is used to receive the switch signal. When the switch signal is at a high level, the driving module 501 is started. At this time, when there is a high-level pulse in the driving pulse, a low-level reset cancellation signal is generated, thereby avoiding the reset of the test indication signal, so that the memory can be stably tested in the test mode; when the switch signal is at a low level, the generated reset cancellation signal is at a high level and cannot be used for the reset of the test indication signal, that is, the driving module 501 is turned off.

[0062] In some embodiments, the switch signal is provided based on the anti-fuse memory cell of the memory, that is, when the anti-fuse memory cell is not blown, the provided switch signal is at a high level to turn on the driving module 501; when the anti-fuse memory cell is blown, the provided switch signal is at a low level to turn off the driving module 501, thereby prohibiting the provision of the reset cancellation signal and avoiding the memory provided to the user from entering the test mode, which affects the normal use of the user.

[0063] In the embodiment of the present disclosure, by setting the control unit 301, the control unit 301 clears the influence of the reset pulse in the mode decoding signal MRSSET on the generated test reset signal TDFTRST through the received reset cancellation signal, so that the generated test reset signal TDFTRST no longer contains the reset pulse, thereby avoiding the reset of the test indication signal, so that the memory can be stably tested in the test mode.

[0064] Each unit involved in this embodiment is a logic unit. In practical applications, a logic unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. In addition, in order to highlight the innovative part of the present disclosure, units not closely related to solving the technical problems proposed by the present disclosure are not introduced in this embodiment, but this does not mean that there are no other units in this embodiment.

[0065] It should be noted that the features disclosed in the mode control structure provided in the above embodiments can be arbitrarily combined without conflict to obtain new embodiments of the mode control structure.

[0066] Another embodiment of the present disclosure provides a memory, which uses the mode control structure provided in the above embodiment to control the working mode of the memory. When the A7 bit is set to 0, the DFT reset signal generated inside the memory is eliminated, so that the test indication signal of the memory is avoided from being reset, and the memory can be stably in the test mode for testing.

[0067] Specifically, the memory can be a storage unit or device based on semiconductor devices or components. For example, the memory device can be a volatile memory, such as a dynamic random access memory DRAM, a synchronous dynamic random access memory SDRAM, a double data rate synchronous dynamic random access memory DDR SDRAM, a low power double data rate synchronous dynamic random access memory LPDDR SDRAM, a graphics double data rate synchronous dynamic random access memory GDDR SDRAM, a double data rate type double synchronous dynamic random access memory DDR2 SDRAM, a double data rate type triple synchronous dynamic random access memory DDR3 SDRAM, a double data rate fourth generation synchronous dynamic random access memory DDR4 SDRAM, a thyristor random access memory TRAM, etc.; or it can be a non-volatile memory, such as a phase change random access memory PRAM, a magnetic random access memory MRAM, a resistive random access memory RRAM, etc.

[0068] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present disclosure, and in practical applications, various changes can be made in form and details without departing from the spirit and scope of the present disclosure.

Claims

1. A mode control structure, characterized in that, Comprising: A configuration module, configured to receive a pre-control signal of a memory and a mode selection signal of a mode register. The configuration module is configured to generate an intermediate control signal based on the mode selection signal if the pre-control signal is valid; A transmission module, one input terminal connected to the output terminal of the configuration module, and the other input terminal for receiving a mode decoding signal. The mode decoding signal includes a reset pulse generated by decoding a control command of the mode register. The transmission module is configured to generate a test reset signal based on the mode decoding signal and the intermediate control signal; A control unit, disposed in the transmission module, for receiving a reset cancellation signal. The control unit is configured to remove the reset pulse included in the test reset signal based on the reset cancellation signal; A test signal generation module, connected to the output terminal of the transmission module, and configured to generate a test indication signal based on the test reset signal. The test indication signal is used to indicate whether the memory is in a test mode.

2. The pattern control structure according to claim 1, wherein The configuration module includes: A first NAND gate, each input terminal respectively for receiving a sub-selection signal. A plurality of the sub-selection signals received by all input terminals of the first NAND gate constitute the mode selection signal; A first NOR gate, one input terminal connected to the output terminal of the first NAND gate, the other input terminal for receiving the pre-control signal, and the output terminal for outputting the intermediate control signal.

3. The pattern control structure according to claim 1, characterized in that, The transmission module includes: A second NAND gate, one input terminal for receiving the intermediate control signal, the other input terminal for receiving the mode decoding signal, and the output terminal for outputting a first intermediate signal; A third NAND gate, one input terminal for receiving the first intermediate signal, the other input terminal for receiving a reset signal, and the output terminal for outputting a second intermediate signal; A control OR gate, one input terminal for receiving the second intermediate signal, the other input terminal for receiving a test control signal, and the output terminal for outputting the test reset signal.

4. The pattern control structure according to claim 3, wherein, Comprising: The control unit is configured to receive the mode decoding signal, and the control unit is configured to remove the reset pulse included in the mode decoding signal based on the reset cancellation signal; The second NAND gate generates the first intermediate signal based on the adjusted mode decoding signal and the intermediate control signal.

5. The pattern control structure according to claim 3, wherein Comprising: The control unit is configured to receive the second intermediate signal, and the control unit is configured to remove the reset pulse included in the second intermediate signal based on the reset cancellation signal; The control OR gate generates the test reset signal based on the adjusted second intermediate signal and the test control signal.

6. The pattern control structure according to claim 3, characterized in that Comprising: The control unit is configured to receive the test reset signal, and the control unit is configured to remove the reset pulse included in the test reset signal based on the reset cancellation signal; The test signal generation module generates the test indication signal based on the adjusted test reset signal.

7. The pattern control structure according to any one of claims 4 to 6, characterized in that, The control unit includes: A fourth NAND gate, one input terminal for receiving the reset cancellation signal, and the other input terminal connected to the transmission module; The control inverter has its input terminal connected to the output terminal of the fourth NAND gate and its output terminal connected to the transmission module.

8. The pattern control structure according to claim 3, characterized in that, It includes: The control unit is configured to receive the first intermediate signal and is configured to remove the reset pulse included in the first intermediate signal based on the reset cancellation signal. The third NAND gate generates the second intermediate signal based on the adjusted first intermediate signal and the reset signal.

9. The pattern control structure according to claim 8, characterized in that, The control unit includes: A second NOR gate, one input terminal for receiving the reset cancellation signal and the other input terminal for receiving the first intermediate signal. The control inverter has its input terminal connected to the output terminal of the second NOR gate and its output terminal connected to the output terminal of the third NAND gate.

10. The pattern control structure according to claim 1, wherein, It further includes: A driving module for providing the reset cancellation signal according to a driving pulse.

11. The pattern control structure according to claim 10, characterized in that, The driving module includes: a first control NOR gate and a second control NOR gate. Among them, one input terminal of the first control NOR gate is connected to the output terminal of the second control NOR gate, one input terminal of the second control NOR gate is connected to the output terminal of the first control NOR gate, the other input terminal of the first control NOR gate is for receiving the driving pulse, and the output terminal is for outputting the reset cancellation signal. The other input terminal of the second control NOR gate is for receiving a switch signal, and the switch signal is used to turn on the driving module.

12. The pattern control structure according to claim 10, wherein The driving module includes: a first control NAND gate and a second control NAND gate. Among them, one input terminal of the first control NAND gate is connected to the output terminal of the second control NAND gate, one input terminal of the second control NAND gate is connected to the output terminal of the first control NAND gate, the other input terminal of the first control NAND gate is for receiving the switch signal, and the switch signal is used to turn on the driving module. The other input terminal of the second control NAND gate is for receiving the driving pulse, and the output terminal is for outputting the reset cancellation signal.

13. The pattern control structure according to claim 11 or 12, characterized in that, The switch signal is provided based on the anti-fuse memory cell of the memory.

14. A memory, characterized in that, The working mode of the memory is controlled by using the mode control structure according to any one of claims 1 to 13.

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