Plasma generation apparatus, semiconductor process apparatus, and wafer processing method

Abstract

The application discloses a kind of plasma generation device, semiconductor process equipment and wafer processing method, it is related to the field of semiconductors.A kind of plasma generation device includes: first electrode, second electrode and additional electrode;First electrode, second electrode and additional electrode are all arranged in process chamber, first electrode and second electrode are mutually spaced, additional electrode is arranged in first electrode, and mutually insulated between the two, additional electrode is used to be connected with first radio frequency power supply, second electrode is used to be connected with second radio frequency power supply and third radio frequency power supply respectively, and second electrode is used to carry wafer.A kind of semiconductor process equipment includes the above-mentioned plasma generation device.A kind of wafer processing method is applied to the above-mentioned semiconductor process equipment.The application can solve the problem that obvious inclination is caused to etching topography due to the deformation of plasma sheath.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and specifically relates to a plasma generation device, semiconductor process equipment and wafer processing method. Background Art

[0002] With the rapid development of the integrated circuit manufacturing industry, etching technology has also greatly advanced. Capacitively coupled plasma (CCP) equipment is one of the most widely used plasma generation devices. A CCP device consists of a vacuum chamber and two planar electrodes connected to an RF power supply. The two planar electrodes form a parallel plate capacitor. RF input power is capacitively coupled to the plasma through a matching network. CCPs are primarily used in reactive plasma etching processes.

[0003] Generally speaking, a photoresist material forms a characteristic pattern on the surface of the wafer to be etched. The characteristic pattern is then etched into the wafer by exposing the wafer to the corresponding etching gas, thereby forming a corresponding etched morphology on the wafer surface. During the etching process, ions are accelerated in the plasma sheath and bombard the wafer surface. Therefore, the shape of the sheath formed by the plasma has a significant impact on the etched morphology. However, when the plasma is unevenly distributed in some areas due to drastic changes in the electric field or due to reasons such as the etching gas flow field, the shape of the plasma sheath will also be deformed, resulting in a significant tilt of the etched morphology on the wafer surface, thereby affecting the wafer yield, as shown in Figure 1. Summary of the Invention

[0004] The purpose of the embodiments of the present application is to provide a plasma generating device, semiconductor process equipment and wafer processing method, which can solve the problem of obvious tilt of the etching morphology due to deformation of the sheath layer.

[0005] In order to solve the above technical problems, this application is implemented as follows:

[0006] An embodiment of the present application provides a plasma generating device, which is applied to a process chamber of a semiconductor process equipment. The plasma generating device includes: a first electrode, a second electrode, and an additional electrode;

[0007] The first electrode, the second electrode and the additional electrode are all arranged in the process chamber, the first electrode and the second electrode are spaced apart from each other, the additional electrode is arranged on the first electrode, and the two are insulated from each other, the additional electrode is used to connect to the first RF power supply, the second electrode is used to connect to the second RF power supply and the third RF power supply respectively, and the second electrode is used to support the wafer.

[0008] The embodiment of the present application further provides a semiconductor process equipment, comprising: a process chamber, a carrier base, a gas supply system, and the above-mentioned plasma generating device;

[0009] The supporting base is the second electrode, and the supporting base is arranged in the process chamber and connected to the second radio frequency power supply and the third radio frequency power supply respectively;

[0010] The gas outlet end of the gas supply system is communicated with the process chamber.

[0011] The present application also provides a wafer processing method, which is applied to the above-mentioned semiconductor process equipment, and the method includes:

[0012] Determining the position and size of the additional electrode and the power value of the first radio frequency power supply according to the etching morphology of the etched wafer;

[0013] Placing the wafer to be etched on the surface of the supporting base;

[0014] The additional electrode is loaded with a first radio frequency power, and the second electrode is loaded with a second radio frequency power and a third radio frequency power respectively, so as to perform an etching process.

[0015] In the embodiment of the present application, by setting up an additional electrode, it can cooperate with the first electrode and the second electrode to change the shape of the plasma distributed in the relative area of ​​the additional electrode, thereby correcting the shape of the plasma sheath on the wafer surface in the corresponding area, and then improving the etching morphology so that the etching morphology is no longer tilted. Therefore, the etching accuracy can be improved and the wafer yield can be guaranteed. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Schematic diagram of the tilt of the wafer surface etching morphology caused by changes in the plasma sheath during wafer etching using a capacitively coupled plasma device in the related art;

[0017] Figure 2 A schematic diagram of a plasma generating device and other structures disclosed in an embodiment of the present application;

[0018] Figure 3 A schematic diagram of a plasma generating device disclosed in an embodiment of the present application;

[0019] Figure 4 This is a schematic diagram of the principle of forming a DC bias when radio frequency power is applied to the additional electrode of the plasma generating device disclosed in an embodiment of the present application;

[0020] Figure 5 This is a schematic diagram of the plasma generating device disclosed in an embodiment of the present application when the additional electrode is loaded with a radio frequency power of 0 W;

[0021] Figure 6This is a schematic diagram of the plasma generation device disclosed in an embodiment of the present application when the additional electrode is loaded with a radio frequency power of P1W, where P1>0;

[0022] Figure 7 This is a schematic diagram of the plasma generation device disclosed in an embodiment of the present application when the additional electrode is loaded with a radio frequency power of P2W, where P2>P1.

[0023] Description of reference numerals:

[0024] 100- plasma generating device;

[0025] 110 - first electrode; 111 - electrode body; 112 - metal substrate; 120 - second electrode; 130 - additional electrode; 131 - dielectric ring; 132 - metal layer; 140 - filter; 150 - matching device;

[0026] 210 - first RF power supply; 220 - second RF power supply; 230 - third RF power supply;

[0027] 300-process chamber;

[0028] 400-Bearing base. DETAILED DESCRIPTION

[0029] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0030] The terms "first," "second," and the like in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of this application can be implemented in an order other than that illustrated or described herein, and that the objects distinguished by "first," "second," and the like are generally of the same type, and do not limit the number of objects; for example, the first object can be one or more. In addition, the term "and / or" in the specification and claims refers to at least one of the connected objects, and the character " / " generally indicates that the objects connected are in an "or" relationship.

[0031] The embodiments of the present application are described in detail below through specific embodiments and their application scenarios in conjunction with the accompanying drawings.

[0032] refer to Figures 2 to 7The present invention discloses a plasma generating apparatus 100 for use in a process chamber 300 of semiconductor processing equipment. Optionally, the plasma generating apparatus 100 may be a capacitively coupled plasma apparatus, and in particular, a reactive ion etching apparatus. Of course, the plasma generating apparatus 100 in the present invention may also be of other types, which are not specifically limited herein.

[0033] The disclosed plasma generating device 100 includes a first electrode 110, a second electrode 120, and an additional electrode 130. The first electrode 110, the second electrode 120, and the additional electrode 130 can all be disposed within a process chamber 300, with the first electrode 110 and the second electrode 120 spaced apart from each other. The second electrode 120 is used to support a wafer.

[0034] In actual applications, the second electrode 120 can be connected to a second RF power source 220 and a third RF power source 230, respectively. The second RF power source 220 can be a high-frequency power source, such as for ignition, and the third RF power source 230 can be a low-frequency power source, such as for bias. In this way, the second RF power source 220 can apply high-frequency power to the second electrode 120 to achieve ignition, and the third RF power source 230 can apply low-frequency power to the second electrode 120 to achieve bias, thereby meeting process requirements.

[0035] The first electrode 110 and the second electrode 120 are spaced apart from each other so that the first electrode 110 and the second electrode 120 can form a flat plate capacitor. At this time, the RF power is coupled to the plasma through the matching network in a capacitive coupling manner, so that the surface of the wafer supported on the second electrode 120 is etched by the plasma.

[0036] During the etching process, ions are accelerated in the plasma sheath between the first electrode 110 and the second electrode 120, bombarding the wafer surface to achieve etching. However, due to the local plasma being disturbed by factors such as drastic changes in the electric field or the etching gas flow field, the plasma distribution becomes uneven, which causes the plasma sheath to deform, causing the plasma motion direction to change, and further causing the etching morphology to become significantly tilted. Ultimately, the etched wafer surface quality is relatively poor, affecting the wafer etching accuracy.

[0037] To address the aforementioned issues, the plasma generation device in the embodiment of the present application is equipped with an additional electrode 130. This additional electrode 130 is disposed on the first electrode 110 and is insulated from the first electrode 110. In practical applications, the additional electrode 130 can be connected to the first RF power source 210 so that the first RF power source 210 can apply a corresponding amount of RF power to the additional electrode 130. Therefore, the additional electrode 130, loaded with RF power, can influence the distribution of the plasma to a certain extent, thereby improving the shape of the plasma sheath and thereby enhancing the etch morphology of the wafer surface.

[0038] The specific principles are:

[0039] Plasma is produced by the ionization of gas. During this ionization process, positive ions and electrons form pairs, resulting in a roughly equal number of positive ions and electrons in the plasma. Therefore, the plasma can be considered electrically neutral overall. However, at the interface between plasma and solids such as metals and dielectrics, electrons have a much lower mass than positive ions and are therefore more rapidly thermally mobile, leading to the accumulation of negative charges on the vessel walls. To shield the electric field created by these negative charges, a positive space charge layer, known as the plasma sheath, is formed within a certain thickness. Ions are accelerated within this plasma sheath, bombarding the wafer and etching the wafer surface.

[0040] Under normal circumstances, the plasma sheath is parallel to the wafer surface. After being accelerated in the plasma sheath, ions etch a topography perpendicular to the wafer surface. However, in some abnormal situations, such as those affected by factors such as the electric field and the etching gas flow field, the plasma density distribution becomes uneven due to uneven electric field distribution or distorted etching gas flow field, causing the plasma sheath to deform and no longer be parallel to the wafer surface. As a result, the ions are no longer incident perpendicularly on the wafer surface, ultimately causing the etched topography to tilt.

[0041] like Figure 3 and Figure 4 As shown, by adding an additional electrode 130 and applying an appropriate amount of RF power to the additional electrode 130 through the first RF power supply 210, electrons and ions are attracted to the additional electrode 130 respectively within one RF cycle. However, the mass of electrons is much lower than the mass of ions. Therefore, within one cycle, the number of electrons reaching the additional electrode 130 will be much greater than the number of ions, and the additional electrode 130 will become a negative potential. The number of electrons attracted will decrease in the next RF cycle until the amount of electrons and ions reaching the electrode remains the same within one RF cycle. At this time, the difference between the potential of the additional electrode 130 and the zero potential is the negative DC bias, that is, Figure 4 V in DC .

[0042] A negative DC bias is generated at the position corresponding to the additional electrode 130. In order to shield the electric field generated by the negative DC bias, the positive space charge needs to form a thicker plasma sheath than the original one, which changes the shape of the plasma distributed at the position corresponding to the additional electrode 130. The shape of the plasma sheath on the wafer surface at the corresponding position is corrected to improve the etching morphology. The greater the RF power loaded on the additional electrode 130, the greater the negative DC bias generated, and the more obvious the impact on the plasma at the corresponding position, such as Figures 5 to 7 As shown, Figure 5 The RF power loaded in is 0W. Figure 6 The RF power loaded in is P1W, Figure 7 The RF power loaded is P2W, and P2>P1 is greater than 0. Therefore, it is necessary to load an appropriate amount of RF power to the additional electrode 130 to improve the shape of the plasma sheath, so that the ions accelerated by the plasma sheath are vertically injected into the wafer surface, thereby improving the etching morphology of the wafer surface.

[0043] In the embodiment of the present application, by providing an additional electrode 130, it can cooperate with the first electrode 110 and the second electrode 120 to change the shape of the plasma distributed in the area opposite to the additional electrode 130, thereby correcting the shape of the plasma sheath on the wafer surface in the corresponding area, thereby improving the etching morphology and making the etching morphology no longer tilted. Therefore, it is possible to improve the etching accuracy and ensure the wafer yield. It should be noted here that the magnitude of the RF power applied to the additional electrode 130 can be adjusted according to the etching morphology of the surface of the previous wafer (i.e., the etched wafer) so that the RF power applied to the additional electrode 130 is appropriate, thereby making it possible to prevent the surface of the currently etched wafer from having abnormal etching morphology, thereby ensuring the etching accuracy of the currently etched wafer and even the subsequently etched wafers.

[0044] In some embodiments, the additional electrode 130 is movably disposed on the first electrode 110, so that the additional electrode 130 cooperates with the first electrode 110 and the second electrode 120 to change the distribution of the plasma. It should be noted that the position of the additional electrode 130 can be adjusted based on the location of the tilt of the etched topography on the surface of the etched wafer.

[0045] In addition, the additional electrode 130 is connected to the first RF power supply 210 so that RF power is applied to the additional electrode 130 through the first RF power supply 210. Moreover, the magnitude of the RF power applied to the additional electrode 130 can be controlled to adjust the distribution of the plasma sheath on the wafer surface under the additional electrode 130, thereby improving the problem of tilted etching morphology at any part of the wafer.

[0046] In some embodiments, the additional electrode 130 may include a dielectric ring 131 and a metal layer 132, wherein the dielectric ring 131 is movably disposed on the first electrode 110, and the metal layer 132 is disposed within the dielectric ring 131 and connected to the first RF power source 210. Thus, the dielectric ring 131 and the metal layer 132 within it may together constitute the additional electrode 130. The metal layer 132 may be connected to the first RF power source 210 so that the first RF power source 210 can load RF power to the metal layer 132, and the metal layer 132 loaded with RF power may influence the distribution of the plasma sheath. Of course, the additional electrode 130 may also employ other structures or types, which are not specifically limited in this embodiment of the present application.

[0047] Furthermore, the dielectric ring 131 may be an insulating dielectric ring, with the metal layer 132 disposed within the insulating dielectric ring. Thus, the insulating dielectric ring isolates the metal layer 132 from the first electrode 110 to achieve insulation and prevent electrical contact. Alternatively, the insulating dielectric ring may include a quartz ring or a ceramic ring. Of course, the dielectric ring 131 may also be made of other insulating materials. The present embodiment does not specifically limit the material of the dielectric ring 131.

[0048] To accommodate the shape of the dielectric ring 131, in some embodiments, the metal layer 132 may be an annular metal layer, coaxially disposed with the dielectric ring 131. Based on this, the position of the metal layer 132 on the first electrode 110 can be determined by setting the position of the dielectric ring 131 on the first electrode 110. This facilitates adjustment of the position of the metal layer 132, achieving greater positional accuracy between the metal layer 132 of the additional electrode 130 and the location of the inclined etched topography on the wafer surface. Therefore, the position of the entire additional electrode 130 can be adjusted by adjusting the position of the dielectric ring 131 on the first electrode 110, further precisely positioning the additional electrode 130 and the inclined etched topography on the wafer surface, thereby improving the etched topography on the wafer surface.

[0049] In some embodiments, the first electrode 110 may include an electrode body 111 and a metal substrate 112, wherein the metal substrate 112 is fixed to the top of the process chamber 300, the electrode body 111 is fixed to the metal substrate 112, and the additional electrode 130 is disposed on a side of the electrode body 111 facing away from the second electrode 120. In this manner, the additional electrode 130 is fixedly mounted while being close to the first electrode 110 and spaced apart from the second electrode 120. Thus, the additional electrode 130 can influence the distribution of plasma between the first electrode 110 and the second electrode 120.

[0050] Furthermore, the metal substrate 112 may be provided with a location for mounting the additional electrode 130, thereby providing space for mounting the additional electrode 130. Alternatively, a groove may be provided on the surface of the metal substrate 112 that contacts the electrode body 111, with the additional electrode 130 embedded in the groove. The additional electrode 130 is in contact with the surface of the electrode body 111 that faces the metal substrate 112. In this manner, the additional electrode 130 is enclosed between the metal substrate 112 and the electrode body 111, thereby enabling mounting of the additional electrode 130.

[0051] In some embodiments, the plasma generating apparatus 100 may further include a filter 140 connected between the additional electrode 130 and the first RF power source 210. Thus, when RF power is applied to the additional electrode 130 via the first RF power source 210 (or a DC power source, etc.), the filter 140 can filter out interference from the RF power applied to the additional electrode 130 by the RF power applied to the second electrode 120, thereby ensuring normal application of RF power to the additional electrode 130.

[0052] In other embodiments, the plasma generating apparatus 100 may further include a matching box 150 connected between the filter 140 and the first RF power source 210, thereby reducing reflected RF power. Furthermore, the second RF power source 220 and the third RF power source 230, which supply RF power to the second electrode 120, may also be connected to a matching box 150 between themselves and the second electrode 120, thereby reducing reflected RF power.

[0053] In an embodiment of the present application, the position of the additional electrode 130 is used to be set corresponding to the area on the wafer surface where abnormal etching morphology occurs. In this way, the additional electrode 130 can affect the plasma distribution in the corresponding area, thereby improving the distribution of plasma in the area, thereby adjusting the plasma sheath distribution in the area on the wafer surface where abnormal etching morphology occurs corresponding to the additional electrode 130, which is beneficial to improving the etching morphology of the area.

[0054] To comprehensively improve areas with abnormal etch morphology, in some embodiments, the projected area of ​​the additional electrode 130 within a first plane is larger than the projected area of ​​the wafer surface area with abnormal etch morphology within the first plane, where the first plane is parallel to the wafer surface. This allows the additional electrode 130 to fully cover areas of the wafer surface where abnormal etch morphology may occur, ensuring that areas with abnormal etch morphology are fully affected by the additional electrode 130. Consequently, the entire wafer surface is free of tilted etch morphology, ensuring wafer etching accuracy.

[0055] Considering that the additional electrode 130 primarily comprises a dielectric ring 131 and an annular metal layer 132, forming a ring-shaped structure, the additional electrode 130 can be configured to have a radial width greater than the width of the wafer surface region exhibiting the abnormal etch morphology in order to comprehensively improve the region exhibiting the abnormal etch morphology. This also allows for comprehensive coverage of the region exhibiting the abnormal etch morphology, thereby preventing tilted etch morphology across the entire wafer surface and ensuring wafer etching accuracy.

[0056] It should be noted that the overall size of the additional electrode 130 and its radial width can be adaptively adjusted according to the position, shape, size, etc. of the deformation of the plasma sheath to achieve an improvement effect.

[0057] Based on the above-mentioned plasma generation device 100, the embodiment of the present application further discloses a semiconductor process equipment, which may include a process chamber 300, a supporting base 400, a gas supply system (not shown in the figure), and the above-mentioned plasma generation device 100. The supporting base 400 may serve as the second electrode 120, is disposed in the process chamber 300, and is connected to the second RF power supply 220 and the third RF power supply 230, respectively. The supporting base 400 may not only support the wafer, but also form a parallel capacitor with the first electrode 110 to form an electric field in the process chamber 300 when powered on. Optionally, the supporting base 400 may be an electrostatic chuck, which can firmly adhere the wafer to its surface to prevent the wafer from moving arbitrarily during the etching process and affecting the etching accuracy.

[0058] Since the etching gas needs to be ionized to form plasma during the etching process, in the embodiment of the present application, the gas outlet end of the gas supply system is connected to the process chamber 300, and the etching gas is introduced into the process chamber 300 through the gas supply system so that the etching gas is ionized in the process chamber 300 to generate plasma, thereby achieving etching of the wafer surface.

[0059] It should be noted here that the specific principles and processes of the etching process of wafers using semiconductor process equipment, as well as the specific structure of the semiconductor process equipment can all be referred to relevant technologies and will not be repeated here.

[0060] The present application also discloses a wafer processing method, which is applied to the above-mentioned semiconductor process equipment. The disclosed wafer processing method includes:

[0061] The position and size of the additional electrode 130 and the power value loaded by the first RF power supply 210 are determined according to the etching morphology of the etched wafer.

[0062] Place the wafer to be etched on the surface of the supporting base 400;

[0063] Introducing etching gas into the process chamber 300;

[0064] The additional electrode 130 is loaded with a first radio frequency power, and the second electrode 120 is loaded with a second radio frequency power and a third radio frequency power, respectively, to perform an etching process.

[0065] Optionally, the first radio frequency power loaded by the additional electrode 130 is less than 10 MHz, and the smaller the frequency, the greater the V dc In addition, the second RF power loaded on the second electrode 120 may be a high frequency power, and the third RF power loaded on the second electrode 120 may be a low frequency power to meet process requirements.

[0066] Through the above-mentioned processing method, the plasma sheath can be made parallel to the wafer surface, and by controlling the magnitude of the RF power loaded on the additional electrode 130, the distribution of the plasma sheath on the wafer surface under the additional electrode 130 can be adjusted, thereby improving the problem of tilted etching morphology that occurs in the corresponding wafer portion under the additional electrode 130, so as to form a complete etching morphology on the wafer surface and ensure the etching accuracy of the wafer.

[0067] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

Claims

1. A plasma generating device (100), applied to a process chamber (300) of a semiconductor process equipment, characterized in that: The plasma generating device (100) comprises: a first electrode (110), a second electrode (120) and an additional electrode (130); The first electrode (110), the second electrode (120) and the additional electrode (130) are all arranged in the process chamber (300), the first electrode (110) and the second electrode (120) are arranged at intervals from each other, so that the first electrode (110) and the second electrode (120) form a flat plate capacitor, the additional electrode (130) is arranged on the first electrode (110), and the two are insulated from each other, the additional electrode (130) is used to be connected to the first radio frequency power supply (210), the second electrode (120) is used to be connected to the second radio frequency power supply (220) and the third radio frequency power supply (230), respectively, and the second electrode (120) is used to carry a wafer.

2. The plasma generating device (100) according to claim 1, characterized in that The additional electrode (130) includes a dielectric ring (131) and a metal layer (132); The dielectric ring (131) is movably arranged on the first electrode (110), and the metal layer (132) is arranged inside the dielectric ring (131) and connected to the first radio frequency power source (210).

3. The plasma generating device (100) according to claim 2, characterized in that The dielectric ring (131) is an insulating dielectric ring, and the insulating dielectric ring includes a quartz ring or a ceramic ring.

4. The plasma generating device (100) according to claim 2, characterized in that The metal layer (132) is an annular metal layer, and the annular metal layer and the dielectric ring (131) are coaxially arranged.

5. The plasma generating device (100) according to claim 1, characterized in that The first electrode (110) comprises an electrode body (111) and a metal substrate (112); The metal substrate (112) is fixed to the top of the process chamber (300), and the electrode body (111) is fixed to the metal substrate (112); The additional electrode (130) is arranged on a side of the electrode body (111) facing away from the second electrode (120).

6. The plasma generating device (100) according to claim 5, characterized in that A surface of the metal substrate (112) in contact with the electrode body (111) is provided with a groove, the additional electrode (130) is arranged in the groove, and the additional electrode (130) is in contact with the surface of the electrode body (111) facing the metal substrate (112).

7. The plasma generating device (100) according to claim 1, 5 or 6, characterized in that: The first electrode (110) is grounded, or the first electrode (110) is connected to the process chamber (300) via an insulating isolation ring.

8. The plasma generating device (100) according to any one of claims 2 to 5, characterized in that The position of the additional electrode (130) is used to be set corresponding to an area on the surface of the wafer where an abnormal etching morphology occurs; And / or, the projected area of ​​the additional electrode (130) in the first plane is larger than the projected area of ​​the region where the etching morphology abnormality occurs on the surface of the wafer in the first plane, wherein the first plane is parallel to the surface of the wafer; And / or, the width of the additional electrode (130) in its own radial direction is greater than the width of the region on the surface of the wafer where the etching morphology abnormality occurs.

9. A semiconductor process equipment, characterized in that: include: A process chamber (300), a supporting base (400), a gas supply system, and a plasma generating device (100) according to any one of claims 1 to 8; The supporting base (400) is the second electrode (120), and the supporting base (400) is arranged in the process chamber (300) and is connected to the second radio frequency power supply (220) and the third radio frequency power supply (230), respectively; The gas outlet end of the gas supply system is in communication with the process chamber (300).

10. A wafer processing method, applied to the semiconductor process equipment according to claim 9, characterized in that: The method comprises: Determining the position and size of the additional electrode (130) and the power value loaded by the first radio frequency power supply (210) according to the etching morphology of the etched wafer; The wafer to be etched is placed on the surface of the supporting base (400); the first radio frequency power is loaded on the additional electrode (130), and the second radio frequency power and the third radio frequency power are loaded on the second electrode (120) respectively, to perform an etching process.

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