Display panel and display device

Abstract

The application provides a display panel and a display device; the display panel avoids parasitic capacitance between a stage transmission signal line and metal tracks above the first semiconductor layer of a gate drive unit by arranging the stage transmission signal line between the first semiconductor layer and a substrate, so that the stage transmission signal line can be arranged in overlap with at least part of the gate drive unit in a non-display area, thus the display panel does not need to additionally arrange a corresponding wiring area for the stage transmission signal line, and the space of the frame occupied by the stage transmission signal line is reduced, and the frame of the display panel is shortened.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] In order to realize narrow frame, the existing display device will adopt a gate drive circuit to control a pixel drive circuit. In the gate drive circuit, in order to realize the transmission of signals, a stage transmission signal line is used to connect different stages of gate drive units, so that the signals can be transmitted. However, since the stage transmission signal line overlaps with other metals, the parasitic capacitance is large, so that the stage transmission signal line cannot be arranged in the area corresponding to the gate drive unit, and a separate area needs to be arranged for the stage transmission signal line, resulting in a large frame of the display panel.

[0003] Therefore, the existing display device has the technical problem of a large frame caused by the need to arrange a separate area for the stage transmission signal line. SUMMARY

[0004] Embodiments of the present application provide a display panel and a display device to alleviate the technical problem of a large frame caused by the need to arrange a separate area for the stage transmission signal line in the existing display device.

[0005] Embodiments of the present application provide a display panel, which comprises a display area and a non-display area arranged on at least one side of the display area; the display panel further comprises:

[0006] a substrate;

[0007] a drive circuit layer arranged on one side of the substrate, the drive circuit layer comprising a plurality of gate drive units arranged in the non-display area, and a stage transmission signal line connecting different stages of the gate drive units;

[0008] The drive circuit layer comprises a first semiconductor layer arranged on one side of the substrate, the first semiconductor layer comprising a plurality of first semiconductors arranged in the non-display area, and the gate drive unit comprising the first semiconductor.

[0009] The stage transmission signal line is arranged between the first semiconductor layer and the substrate, and overlaps at least part of the gate drive unit in the non-display area.

[0010] In some embodiments, the drive circuit layer further comprises a first metal layer arranged on the side of the first semiconductor layer away from the substrate, the first metal layer comprising a gate electrode arranged in the non-display area, and the gate drive unit comprising the gate electrode.

[0011] The stage transmission signal line overlaps at least part of the gate electrode in the non-display area.

[0012] In some embodiments, the driving circuit layer further comprises: a second metal layer disposed on a side of the first metal layer away from the substrate, the second metal layer comprising metal traces disposed in the non-display region, and the gate driving unit comprises the metal traces.

[0013] The stage transmission signal line is disposed in the non-display region and overlaps at least partially with the metal traces.

[0014] In some embodiments, the driving circuit layer further comprises: a source-drain layer disposed on a side of the second metal layer away from the first metal layer, and the gate driving unit comprises a transistor, the transistor comprising a first electrode and a second electrode disposed in the source-drain layer, and the first electrode is connected to the stage transmission signal line through a first via.

[0015] In some embodiments, the first electrode is connected to the first semiconductor through a second via, and a width of the first via is greater than a width of the second via.

[0016] In some embodiments, the driving circuit layer further comprises: a source-drain layer disposed on a side of the second metal layer away from the first metal layer, and the gate driving unit comprises a transistor, the transistor comprising a first electrode and a second electrode disposed in the source-drain layer, and the display panel further comprises a connecting metal, the first electrode is connected to the stage transmission signal line through the connecting metal, and the connecting metal is connected to the stage transmission signal line through a via.

[0017] In some embodiments, the display panel further comprises a light emitting layer disposed on a side of the driving circuit layer away from the substrate, the light emitting layer comprising: a pixel light emitting unit disposed in the display region,

[0018] The driving circuit layer further comprises a pixel driving unit disposed in the display region and driving the pixel light emitting unit, and a light shielding layer disposed between the pixel driving unit and the substrate,

[0019] The light shielding layer comprises: a light shielding portion disposed in the display region and overlapping with the pixel driving unit, and the stage transmission signal line disposed in the non-display region.

[0020] In some embodiments, the first semiconductor layer further comprises a plurality of second semiconductors disposed in the display region, and the pixel driving unit comprises the second semiconductors.

[0021] The first semiconductor comprises a first channel region, and the stage transmission signal line is not disposed overlapping with the first channel region.

[0022] The second semiconductor comprises a second channel region, and the light shielding portion is disposed overlapping with the second channel region.

[0023] In some embodiments, the driving circuit layer further comprises: a second semiconductor layer disposed on a side of the first semiconductor layer away from the substrate,

[0024] The second semiconductor layer comprises a plurality of third semiconductors disposed in the display area, the pixel driving unit further comprises the third semiconductors, and the third semiconductors comprise a metal oxide material;

[0025] The light shielding part is disposed without overlapping the third semiconductors.

[0026] In some embodiments, the pixel driving unit comprises:

[0027] A first initialization transistor connected to a first initialization signal line, a gate of the first initialization transistor connected to a first scan signal line of a first gate driving unit, and the first initialization transistor used for inputting a first initialization signal to a first node under control of a first scan signal;

[0028] A switch transistor used for inputting a data signal to a second node under control of a second scan signal;

[0029] A driving transistor used for driving the pixel light emitting unit to emit light under control of potentials of the first node and the second node;

[0030] A compensation transistor connected to the driving transistor through the first node and a third node, a gate of the compensation transistor connected to a second scan signal line of a second gate driving unit, and the compensation transistor used for compensating a threshold voltage of the driving transistor under control of a third scan signal;

[0031] The gate driving unit comprises: the first gate driving unit and the second gate driving unit of different stages, one end of a stage transmission signal line connected to the first gate driving unit, and the other end of the stage transmission signal line connected to the second gate driving unit along the gate driving circuit area.

[0032] In some embodiments, the gate driving unit further comprises a third gate driving unit, the gate driving circuit area comprises a first wiring area and a second wiring area, the first gate driving unit and the second gate driving unit are disposed in the first wiring area, the third gate driving unit is disposed in the second wiring area, and at least part of the stage transmission signal line is disposed in the second wiring area.

[0033] In some embodiments, the first gate driving unit is connected to the stage transmission signal line through a via at a junction of the first wiring area and the second wiring area, and the second gate driving unit is connected to the stage transmission signal line through a via at the junction of the first wiring area and the second wiring area.

[0034] In some embodiments, the display panel further comprises a connection trace area arranged between the gate drive circuit area and the display area, the second trace area is arranged between the first trace area and the connection trace area, and the stage transmission signal line extends from the second trace area to the connection trace area.

[0035] Meanwhile, the application provides a display device, which comprises the display panel and the driving chip as described in any of the above embodiments.

[0036] Beneficial effects: the application provides a display panel and a display device; the display panel comprises a display area and a non-display area arranged on at least one side of the display area, and the display panel comprises a substrate and a driving circuit layer, the driving circuit layer is arranged on one side of the substrate, the driving circuit layer comprises a plurality of gate drive units arranged in the non-display area and a stage transmission signal line connecting the gate drive units of different stages, wherein the driving circuit layer comprises a first semiconductor layer arranged on one side of the substrate, the first semiconductor layer comprises a plurality of first semiconductors arranged in the non-display area, the gate drive unit comprises the first semiconductor, the stage transmission signal line is arranged between the first semiconductor layer and the substrate, and at least partially overlaps the gate drive unit in the non-display area. By arranging the stage transmission signal line between the first semiconductor layer and the substrate, the application avoids the parasitic capacitance between the stage transmission signal line and the metal trace above the first semiconductor layer of the gate drive unit, so that the stage transmission signal line can be arranged to overlap at least part of the gate drive unit in the non-display area, which can avoid the need to additionally arrange a corresponding wiring area for the stage transmission signal line, thereby reducing the space of the frame occupied by the stage transmission signal line and shortening the frame of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0037] The technical solutions and other beneficial effects of the application will be apparent from the following detailed description of the specific embodiments of the application, combined with the accompanying drawings.

[0038] Figure 1 The first schematic diagram of the display panel provided by the embodiments of the application.

[0039] Figure 2 The circuit diagram of the display panel provided by the embodiments of the application.

[0040] Figure 3 The perspective view of the display panel provided by the embodiments of the application.

[0041] Figure 4 The comparison diagram of the current display device and the arrangement area of each component of the display panel of the application. DETAILED DESCRIPTION

[0042] With reference to the drawings and embodiments of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person skilled in the art without creative work fall within the scope of protection of the present application.

[0043] Embodiments of the present application aim at the technical problem that setting light units on a gate drive circuit causes a low yield of a display device in the prior display device, and provide a display panel and a display device to alleviate the above technical problem.

[0044] As shown in Figures 1 to 3 Embodiments of the present application provide a display panel, which comprises a display area 181 and a non-display area 182 arranged at least one side of the display area 181; the display panel 1 further comprises:

[0045] a substrate 11;

[0046] a drive circuit layer arranged at one side of the substrate 11, the drive circuit layer comprising a plurality of gate drive units 22 of different levels (a gate drive unit of one level is shown in FIG. 2) arranged in the non-display area 182 and a level transmission signal line 122 connecting the gate drive units 22 of different levels; Figure 3

[0047] wherein the drive circuit layer comprises a first semiconductor layer 141 arranged at one side of the substrate 11, the first semiconductor layer 141 comprising a plurality of first semiconductors 141a arranged in the non-display area, and the gate drive units 22 comprising the first semiconductors 141a;

[0048] the level transmission signal line 122 is arranged between the first semiconductor layer 141 and the substrate 11, and is arranged to overlap at least part of the gate drive units 22 in the non-display area 182.

[0049] Embodiments of the present application provide a display panel, which arranges the level transmission signal line between the first semiconductor layer and the substrate, avoids parasitic capacitance between the level transmission signal line and the metal wiring above the first semiconductor layer of the gate drive unit, and enables the level transmission signal line to be arranged to overlap at least part of the gate drive units in the non-display area, so that a corresponding wiring area does not need to be additionally arranged for the level transmission signal line, thereby reducing the space of the frame occupied by the level transmission signal line and shortening the frame of the display panel.

[0050] It should be noted that, Figure 1 is a cross-sectional view of the display panel, therefore, Figure 1 ​The image does not show all the components of a single sub-pixel; only some transistors, traces, and capacitors are shown. Therefore, it can be understood that... Figure 1 The pixel driving unit in the image includes not only two transistors, but also other components; similarly, Figure 1 The gate driving unit shown includes not only a single transistor but also other components. Specifically, the pixel driving unit includes components that can be... Figure 2 The circuit diagram shows several components.

[0051] It should be noted that while LED is used to indicate the pixel light-emitting unit, this application does not limit the pixel light-emitting unit to a light-emitting diode; the pixel light-emitting unit can be an organic light-emitting diode.

[0052] Specifically, such as Figure 1 As shown, the first semiconductor layer 141 further includes a second semiconductor, which is disposed in the pixel driving unit 21. Figure 1 Not indicated in the text.

[0053] In one embodiment, such as Figure 1 As shown, the driving circuit layer further includes: a first metal layer 143 disposed on the side of the first semiconductor layer 141 away from the substrate 11, the first metal layer 143 including a gate 143a disposed in the non-display area 182, and the gate driving unit 22 including the gate 143a.

[0054] The cascade signal lines are arranged to overlap with at least a portion of the gate in the non-display area. By making the cascade signal lines overlap with at least a portion of the gate in the non-display area, the cascade signal lines can reuse the area where the gate is located in the non-display area, thereby avoiding the need to set up additional wiring areas for the cascade signal lines, and thus shortening the corresponding bezel area to achieve a narrower bezel. At the same time, the spacing between the cascade signal lines and the gate is large, and the thickness of the insulating layer between the cascade signal lines and the gate is large, avoiding the formation of parasitic capacitance between the cascade signal lines and the gate.

[0055] In one embodiment, such as Figure 1 As shown, the driving circuit layer further includes: a second metal layer 145 disposed on the side of the first metal layer 143 away from the substrate 11, the second metal layer 145 including a metal trace 145a disposed in the non-display area 182, and the gate driving unit 22 including the metal trace 145a.

[0056] The stage transmission signal line 122 is arranged to overlap at least part of the metal trace 145a in the non-display area 182. Specifically, the metal trace 145a can include a first plate of a capacitor in the gate drive unit and a trace in the same layer as the first plate, and the first metal layer 143 is provided with a second plate of the capacitor at a position corresponding to the first plate, and the first plate and the second plate constitute the capacitor in the gate drive unit.

[0057] In the embodiment, by arranging the stage transmission signal line to overlap at least part of the metal trace in the non-display area, the stage transmission signal line can reuse the area where the metal trace is located in the non-display area, thereby avoiding the need to additionally provide a wiring area for the stage transmission signal line, and thereby shortening the corresponding frame area to achieve a narrower frame. At the same time, the stage transmission signal line and the metal trace have a large spacing, and the thickness of the insulating layer between the stage transmission signal line and the metal trace is large, thereby avoiding the formation of a parasitic capacitor between the stage transmission signal line and the metal trace.

[0058] In one embodiment, as shown in Figure 1 The driving circuit layer further includes a source-drain layer 151 arranged on a side of the second metal layer 145 away from the first metal layer 143, and the gate drive unit 22 includes a transistor including a first electrode 151a and a second electrode 151b arranged on the source-drain layer 151, and the first electrode 151a is connected to the stage transmission signal line 122 through a first via. By connecting the stage transmission signal line to the first electrode of the transistor, the signal of the stage transmission signal line can be transmitted, and the stage transmission signal line only occupies the space of the width of the via in the connection trace area, while the stage transmission signal line can be arranged in the gate drive circuit area, thereby reducing the space occupied by the stage transmission signal line and reducing the frame of the display panel.

[0059] In one embodiment, the first electrode is a source electrode, and the second electrode is a drain electrode; or the first electrode is a drain electrode, and the second electrode is a source electrode.

[0060] In one embodiment, as shown in Figure 1 The first electrode 151a is connected to the first semiconductor 141a through a second via, and the width of the first via is greater than the width of the second via. By making the width of the first via greater than the width of the second via, when the first electrode is connected to the stage transmission signal line through the first via, the larger aperture of the first via avoids the breakage of part of the first electrode in the first via, which can cause display defects.

[0061] Specifically, the light shielding layer is arranged under the first semiconductor layer, so that the depth of the first via hole is greater than the depth of the second via hole, and thus the aperture of the first via hole is greater than the aperture of the second via hole when the first electrode is connected to the stage transmission signal line through the via hole, so as to avoid the first electrode from being broken when passing through the first via hole and causing poor signal transmission.

[0062] In an embodiment, the display panel further comprises a buffer layer 13, a first insulating layer 142, a second insulating layer 144, a third insulating layer 146, a fourth insulating layer 148, a fifth insulating layer 150, and a third metal layer 149, the buffer layer 13 is arranged between the light shielding layer 12 and the first semiconductor layer 141, the first insulating layer 142 is arranged between the first semiconductor layer 141 and the first metal layer 143, the second insulating layer 144 is arranged between the first metal layer 143 and the second metal layer 145, the third insulating layer 146 is arranged between the second metal layer 145 and the second semiconductor layer 147, the fourth insulating layer 148 is arranged between the second semiconductor layer 147 and the third metal layer 149, and the fifth insulating layer 150 is arranged between the third metal layer 149 and the source-drain electrode layer 151.

[0063] The first via hole comprises a portion located in the buffer layer, a portion located in the first insulating layer, a portion located in the second insulating layer, a portion located in the third insulating layer, a portion located in the fourth insulating layer, and a portion located in the fifth insulating layer, and the portions of the first via hole located in the buffer layer, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer are partially overlapped on the substrate.

[0064] In an embodiment, the driving circuit layer further comprises a source-drain electrode layer arranged on a side of the second metal layer away from the first metal layer, the gate driving unit comprises a transistor, the transistor comprises a first electrode and a second electrode arranged on the source-drain electrode layer, the display panel is formed with a connecting metal, the first electrode is connected to the stage transmission signal line through the connecting metal, and the connecting metal is connected to the stage transmission signal line through a via hole. By arranging the connecting metal in the via hole and connecting the connecting metal to the stage transmission signal line through the via hole, the first electrode can be connected to the stage transmission signal line through the connecting metal, so as to avoid the first electrode from being broken in the via hole and improve the connection effect of the first electrode and the connecting metal.

[0065] It should be noted that the above embodiments respectively describe the setting region of the stage transmission signal line and the connection mode of the stage transmission signal line in detail, but the setting region of the stage transmission signal line and the connection mode of the stage transmission signal line can be combined to achieve better technical effects. For example, the first gate drive unit is connected to the stage transmission signal line through the via at the junction of the first wire region and the second wire region, the second gate drive unit is connected to the stage transmission signal line through the via at the junction of the first wire region and the second wire region, the stage transmission signal line is arranged on the light shielding layer, and the output end of the gate drive unit is connected to the stage transmission signal line through the via, so that the stage transmission signal line is arranged on the light shielding layer, the thickness of the display panel is avoided to be increased, the stage transmission signal line is connected to the first gate drive unit and the second gate drive unit through the via at the junction of the first wire region and the second wire region, the frame of the display panel is avoided to be occupied, so that the frame of the display panel is reduced and the thickness of the display panel is not increased. Therefore, the setting region of other stage transmission signal lines and the connection mode of the stage transmission signal lines can also be combined to achieve better effects, which will not be described here.

[0066] In an embodiment, as shown in Figure 1 The display panel further includes a light emitting layer arranged on a side of the driving circuit layer away from the substrate, and the light emitting layer includes: a pixel light emitting unit arranged in the display area,

[0067] The driving circuit layer further includes a pixel drive unit arranged in the display area and driving the pixel light emitting unit, and a light shielding layer 12 arranged between the pixel drive unit and the substrate.

[0068] The light shielding layer 12 includes: a light shielding part 121 arranged in the display area and overlapping with the pixel drive unit, and a stage transmission signal line 122 arranged in the non-display area.

[0069] By placing the stage transmission signal line in the light-shielding layer 12, the stage transmission signal line 122 and the light-shielding part 121 of the display area can be fabricated together using the same process. This reuses the fabrication process of the light-shielding part 121, reducing the fabrication difficulty of the stage transmission signal line 122, saving process steps, and reducing manufacturing costs. Simultaneously, the stage transmission signal line can extend to the gate driving circuit area. The stage transmission signal line only occupies the space of the via connection portion, while the extended portion of the stage transmission signal line can be placed in the gate driving circuit area, reducing the space occupied by the stage transmission signal line. Furthermore, due to the large thickness of the insulating layer between the light-shielding layer and the first and second metal layers, the parasitic capacitance between the light-shielding layer and the first and second metal layers is small or even non-existent, avoiding an increase in the parasitic capacitance of the display panel. Since the display panel has a light-shielding layer, there is no need to add a metal film layer, reducing the thickness of the display panel. Compared to using other film layers to form the stage transmission signal line, this reduces the thickness of the display panel and the parasitic capacitance.

[0070] In one embodiment, the first semiconductor layer further includes a plurality of second semiconductors disposed in the display area, and the pixel driving unit includes the second semiconductors;

[0071] The first semiconductor includes a first channel region, and the transmission signal line is not overlapped with the first channel region;

[0072] The second semiconductor includes a second channel region, and the light-shielding portion overlaps with the second channel region.

[0073] In this embodiment, the light-shielding portion 121 overlaps with the second channel region of the second semiconductor, which can shield the adverse effects of the charge below the second channel region on it, enhancing the working performance of the corresponding transistor in the pixel driving unit. Simultaneously, the transmission signal line 122 does not overlap with the first channel region of the first semiconductor, preventing the transmission signal line from adversely affecting the transistor in the gate driving unit and hindering its normal operation. In practical applications, the light-shielding portion 121 can be grounded or connected to a constant potential to shield the charge, while the transmission signal line 122 conducts changing potentials, generating an electric field that can adversely affect the transistor; therefore, it needs to be positioned away from the first channel region of the first semiconductor.

[0074] In one embodiment, such as Figure 1 As shown, the driving circuit layer further includes a second semiconductor layer 147 disposed on the side of the first semiconductor layer 141 away from the substrate.

[0075] The second semiconductor layer 147 includes a plurality of third semiconductors disposed in the display area, the pixel driving unit further includes the third semiconductors, and the third semiconductors include a metal oxide material (for example, IGZO, which stands for "indium gallium zinc oxide", or the like);

[0076] The light shielding portion is disposed not to overlap the third semiconductors.

[0077] In the present embodiment, the gate driving unit can be prepared by using transistors of different material types, for example Figure 2 T1, T2, T5, T6, and T7 in FIG. 1, which can be prepared by using low-temperature polysilicon for their semiconductors, and T3 and T4, which can be prepared by using metal oxide for their semiconductors. As shown in FIG. 2, Figure 1 The semiconductor layers of the low-temperature polysilicon transistor and the metal oxide transistor are generally not disposed in the same layer, i.e., the first semiconductor layer and the second semiconductor layer are stacked, and the light shielding portion is mainly provided for the low-temperature polysilicon transistor, for example, T1, while the metal oxide transistor can be provided in a double-gate structure (for example, 145 and 149 in FIG. 1), and does not need to be additionally shielded by the light shielding portion. Figure 1

[0078] In an embodiment, the display panel further includes a stage transfer metal layer disposed on a side of the light shielding layer away from the first semiconductor layer, and the stage transfer metal layer includes a stage transfer signal line. By disposing the stage transfer metal layer on the side of the light shielding layer away from the first semiconductor layer, the stage transfer metal layer forms a stage transfer signal layer, so that the stage transfer signal line is disposed in the gate driving circuit area, and the frame of the display panel is reduced.

[0079] In an embodiment, as shown in FIG. 3, Figure 1 Figure 2 The pixel driving unit 21 includes:

[0080] A first initialization transistor T4 connected to a first initialization signal line VI-G, a gate of the first initialization transistor T4 being connected to a first scan signal line N Scan(n-5) of the first gate driving unit, and the first initialization transistor T4 being configured to input a first initialization signal to a first node under control of a first scan signal;

[0081] A switch transistor T2 configured to input a data signal to a second node under control of a second scan signal;

[0082] A driving transistor T1 configured to drive the pixel light emitting unit LED to emit light under control of potentials of the first node and the second node;

[0083] ​​A compensation transistor T3 is connected with the driving transistor T1 through the first node and the third node, a gate of the compensation transistor T3 is connected to a second scan signal line N Scan(n) of the second gate drive unit, and the compensation transistor T3 is used for compensating a threshold voltage of the driving transistor T1 under control of a third scan signal.

[0084] The gate drive unit 22 includes the first gate drive unit and the second gate drive unit of different stages, one end of the stage transmission signal line 122 is connected to the first gate drive unit, and the other end of the stage transmission signal line 122 is connected to the second gate drive unit along the gate drive circuit area 183.

[0085] By connecting the first initialization transistor and the compensation transistor to the first scan signal line and the second scan signal line of the first gate drive unit and the second gate drive unit respectively, the first initialization transistor and the compensation transistor can be turned on at different stages, so as to reset and compensate the threshold voltage of the driving transistor respectively, and signal crosstalk caused by turning on the first initialization transistor and the compensation transistor at the same time is avoided. By increasing the 5-stage gate drive unit, the driving time of the first initialization transistor and the compensation transistor is separated, so that the increased 5-stage gate drive unit can turn on the first initialization transistor in the first 10 rows of pixel drive units, for example, the 6th-stage gate drive unit drives the compensation transistor in the first and second rows of pixel drive units, and simultaneously drives the first initialization transistor in the 11th and 12th rows of pixel drive units, so that the first initialization transistor and the compensation transistor can be driven separately.

[0086] Therefore, the first gate drive unit and the second gate drive unit need to use the stage transmission signal line for stage transmission of signals. Compared with the current stage transmission signal line formed by the third metal layer, the third metal layer cannot overlap the first metal layer and the second metal layer, and therefore, the stage transmission signal line occupies a large space and increases the frame. In the present application, the stage transmission signal line is connected to the first gate drive unit and the second gate drive unit from the gate drive circuit area, so as to avoid occupation of space by the stage transmission signal line and reduce the frame of the display panel.

[0087] In an embodiment, the first initialization transistor and the compensation transistor are oxide semiconductor transistors.

[0088] In an embodiment, as Figure 2 , Figure 3As shown, the gate driving unit further includes a third gate driving unit. The gate driving circuit area includes a first routing area 183a and a second routing area 183b. The first gate driving unit and the second gate driving unit are disposed in the first routing area 183a, the third gate driving unit is disposed in the second routing area, and at least a portion of the stage transmission signal lines are disposed in the second routing area 183b. By disposing of at least a portion of the stage transmission signal lines in the second routing area, this application avoids signal crosstalk when the stage transmission signal lines connect the first gate driving unit and the second gate driving unit. Simultaneously, disposing of the stage transmission signal lines in the second routing area avoids the stage transmission signal lines occupying space, reducing the width of the display panel bezel.

[0089] Specifically, such as Figure 2 As shown, the gate driving unit uses the scan signal line P Scan(n) controlling the P-type transistor and the scan signal line N Scan(n) controlling the N-type transistor to control the transistors respectively. Therefore, it is necessary to set up the first and second routing areas to set up the gate driving units corresponding to the scan signal line N Scan(n) and the gate driving units corresponding to the scan signal line P Scan(n) respectively. Figure 3 As shown, Figure 3 The diagram illustrates the gate driving unit corresponding to NScan(n) and the gate driving unit corresponding to the scan signal line PScan(n) in a certain stage gate driving unit, as well as the wiring arrangement connected to the display area. In this embodiment, the stage transmission signal line is located in the second wiring area 183b, i.e. Figure 3 The stage transmission signal line setting area 185 is located in the second wiring area 183b, which reduces the border occupied by the stage transmission signal lines and reduces the border of the display panel.

[0090] In one embodiment, the first gate driving unit is connected to the cascade signal line through a via at the junction of the first and second trace areas, and the second gate driving unit is connected to the cascade signal line through a via at the junction of the first and second trace areas. By connecting the first and second gate driving units to the cascade signal line through vias at the junction of the first and second trace areas, signal transmission can be performed through the cascade signal line. Furthermore, the connection point between the cascade signal line and the gate driving unit is located in the gate driving circuit area, avoiding the cascade signal line from occupying space. Additionally, the gate driving unit does not need to extend, preventing metal overlap or short circuits in the gate driving unit that could cause crosstalk.

[0091] from Figure 3It can be seen that the gate drive unit corresponding to N Scan(n) is connected to the stage transmission signal line at the first connection 311, so that the upper stage gate drive unit can transmit signals to the lower stage gate drive unit through the stage transmission signal line, and the gate drive unit corresponding to N Scan(n) is connected to the transistor in the pixel drive unit in the display area through the second connection 312, so as to drive the transistor. Since the gate drive unit and the stage transmission signal line are connected at the junction of the first wiring area and the second wiring area, the signal interference between the gate drive unit corresponding to N Scan(n) and the gate drive unit corresponding to P Scan(n) is avoided, or the metal overlap and short circuit are avoided.

[0092] In an embodiment, as shown in Figure 1 、 Figure 3 The display panel 1 further includes a connection wiring area 184 arranged between the gate drive circuit area 183 and the display area 181. The second wiring area 183b is arranged between the first wiring area 183a and the connection wiring area 184. The stage transmission signal line 122 extends from the second wiring area 183b to the connection wiring area 184. In the present application, the stage transmission signal line extends from the second wiring area to the connection wiring area, so that the stage transmission signal line can be connected with the signal line to realize signal transmission. The stage transmission signal line only needs to occupy part of the connection wiring area at the connection, thereby reducing the occupied space of the stage transmission signal line and reducing the frame of the display panel.

[0093] In an embodiment, as shown in Figure 2 The pixel drive unit further includes a second initialization transistor T7 connected with a second initialization signal line VI-ANO, for inputting a second initialization signal to the anode of the light emitting device LED under the control of a fourth scan signal.

[0094] A first light emitting control transistor T5 is connected with the drive transistor T1 through a second node, for conducting the current of the power supply high potential signal line ELVDD to the drive transistor T1 under the control of a light emitting control signal.

[0095] A second light emitting control transistor T6 is connected with the drive transistor T1 through a third node, for conducting the current of the drive transistor T1 to the anode of the light emitting device LED under the control of a light emitting control signal.

[0096] In an embodiment, as shown in Figure 2As shown, the pixel driving unit further comprises a storage capacitor Cst and a boost capacitor Cboost, one end of the storage capacitor Cst is connected with the power high potential signal line VDD, the other end of the storage capacitor Cst is connected with the first node, one end of the boost capacitor is connected with the first initialization transistor T4, and the other end of the boost capacitor is connected with the gate of the switch transistor T2.

[0097] It can be understood that, in the embodiment of the present application, as Figure 2 shown, the data line Data transmits a data signal, the first initialization signal line VI-G transmits a first initialization signal, the second initialization signal line VI-ANO transmits a second initialization signal, the first scan signal line N Scan(n-5) transmits a first scan signal, the second scan signal line N Scan(n) transmits a second scan signal, the third scan signal line P Scan(n) transmits a third scan signal, the fourth scan signal line P Scan(n-1) transmits a fourth scan signal, the light-emitting control signal line EM transmits a light-emitting control signal, and the power low potential signal line ELVSS transmits a low potential.

[0098] Wherein, P Scan(n) represents a current scan line, P Scan(n-1) represents a previous scan line, and the above-mentioned scan lines are used for controlling P-type transistors.

[0099] The working principle of the circuit is as follows: in the first stage, the first initialization transistor T4 and the second initialization transistor T7 are turned on, the initialization signal output by the first initialization signal line VI-G resets the gate of the driving transistor T1, and the initialization signal output by the second initialization signal line VI-ANO resets the pixel light-emitting unit LED; in the second stage, the switch transistor T2 and the compensation transistor T3 are turned on, and the data signal input by the data line Data is written into the gate of the driving transistor T1; in the third stage, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on, and the pixel light-emitting unit LED is driven to emit light.

[0100] As Figure 4 shown, Figure 4 (a) in FIG. 1 is a schematic diagram of the setting area of each component of the current display device, Figure 4 (b) in FIG. 1 is a schematic diagram of the setting area of each part of the display panel of the present application. From Figure 4 (a) in FIG. 1, it can be seen that outside the display area 211, the gate drive circuit setting area 212 and the stage transmission signal line setting area 213 need to be set respectively, resulting in a large frame of the display device. And the stage transmission signal line is set in the gate drive circuit area in the present application, as Figure 4As shown in (b), it can be seen that the stage transmission signal line setting area 185 and the gate drive circuit area 183 overlap. The stage transmission signal line setting area 185 is located within the gate drive circuit area 183, which reduces the bezel of the display panel.

[0101] The embodiments of this application are as follows: Figure 2 The circuit diagram in the example is described in detail, but the embodiments of this application are not limited to this. For example, a display panel using a 7T1C (7 transistors and one capacitor) circuit can also adopt the design of this application.

[0102] In one embodiment, to improve the flexibility and water and oxygen barrier capabilities of the display panel, such as Figure 1 As shown, the substrate 11 includes a first flexible layer 111, a barrier layer 112, and a second flexible layer 113.

[0103] In one embodiment, such as Figure 1 As shown, the display panel also includes a planarization layer 152.

[0104] In one embodiment, the material of the first semiconductor layer is low-temperature polycrystalline silicon, and the material of the active layer is an oxide, specifically indium gallium zinc oxide.

[0105] like Figure 1 As shown in the figure, the structure of the display panel is illustrated using LTPO technology as an example. However, the embodiments of this application are not limited to this. For example, the display panel may use LTPS (Low Temperature Poly-silicon) technology.

[0106] Meanwhile, this application provides a display device, which includes the display panel and driver chip described in any of the above embodiments.

[0107] As can be seen from the above embodiments:

[0108] The embodiment of the present application provides a display panel and a display device; the display panel comprises a display area and a non-display area arranged on at least one side of the display area, and the display panel comprises a substrate and a drive circuit layer, the drive circuit layer is arranged on one side of the substrate, the drive circuit layer comprises a plurality of gate drive units arranged in the non-display area and a stage transmission signal line connected with the gate drive units of different stages, wherein the drive circuit layer comprises: a first semiconductor layer arranged on one side of the substrate, the first semiconductor layer comprises a plurality of first semiconductors arranged in the non-display area, the gate drive unit comprises the first semiconductor, the stage transmission signal line is arranged between the first semiconductor layer and the substrate, and at least partially overlaps with the gate drive unit in the non-display area. The stage transmission signal line is arranged between the first semiconductor layer and the substrate, so that the parasitic capacitance between the stage transmission signal line and the metal wire on the first semiconductor layer is avoided, the stage transmission signal line can be arranged to overlap at least part of the gate drive unit in the non-display area, so that the corresponding wiring area of the stage transmission signal line does not need to be additionally arranged, and the space of the frame occupied by the stage transmission signal line is reduced, and the frame of the display panel is shortened.

[0109] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0110] The display panel and the display device provided by the embodiment of the present application are described in detail above, and the principle and implementation mode of the present application are described by applying specific examples in this paper, and the above embodiment is only used to help understand the technical solution and the core idea of the present application; the ordinary skilled in the art should understand that the technical solution recorded in the above embodiments can be modified, or some technical features can be replaced; and these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the present application.

Claims

1. A display panel, characterized in that, include: A display area and a non-display area disposed on at least one side of the display area; The display panel also includes: Substrate; A driving circuit layer is disposed on one side of the substrate. The driving circuit layer includes: a multi-stage gate driving unit disposed in the non-display area, and a stage transmission signal line connecting the gate driving units of different stages. The driving circuit layer includes: a first semiconductor layer disposed on one side of the substrate, the first semiconductor layer including a plurality of first semiconductors disposed in the non-display area, and the gate driving unit including the first semiconductors; The transmission signal line is disposed between the first semiconductor layer and the substrate, and overlaps with at least a portion of the gate driving unit in the non-display area; The display panel further includes a light-emitting layer disposed on the side of the driving circuit layer away from the substrate. The light-emitting layer includes: pixel light-emitting units disposed in the display area. The driving circuit layer further includes a pixel driving unit disposed in the display area and driving the pixel light-emitting units. The pixel driving unit includes: a first initialization transistor connected to a first initialization signal line, the gate of the first initialization transistor being connected to a first scan signal line of a first gate driving unit, the first initialization transistor being used to input a first initialization signal to a first node under the control of a first scan signal; a switching transistor being used to input a data signal to a second node under the control of a second scan signal; a driving transistor being used to drive the pixel light-emitting units to emit light under the control of the potentials of the first node and the second node; and a compensation transistor connected to the driving transistor through the first node and a third node, the gate of the compensation transistor being connected to a second scan signal line of a second gate driving unit, the compensation transistor being used to compensate the threshold voltage of the driving transistor under the control of a third scan signal. The gate driving unit includes first gate driving units and second gate driving units of different levels, one end of the level transmission signal line being connected to the first gate driving unit, and the other end of the level transmission signal line being connected to the second gate driving unit along the gate driving circuit area. The driving circuit layer further includes: a first metal layer disposed on the side of the first semiconductor layer away from the substrate, a second metal layer disposed on the side of the first metal layer away from the substrate, and a source-drain layer disposed on the side of the second metal layer away from the first metal layer. The first metal layer includes a gate disposed in the non-display area, and the gate driving unit includes the gate. The transmission signal line overlaps with at least a portion of the gate in the non-display area. The second metal layer includes a metal trace disposed in the non-display area, and the gate driving unit includes the metal trace. The transmission signal line overlaps with at least a portion of the metal trace in the non-display area. The gate driving unit includes a transistor, and the transistor includes a first electrode and a second electrode disposed in the source-drain layer. The first electrode is connected to the transmission signal line through a first via.

2. The display panel as described in claim 1, characterized in that, The first electrode is connected to the first semiconductor through a second via, and the width of the first via is greater than the width of the second via.

3. The display panel as described in claim 1, characterized in that, The display panel further includes a light-shielding layer disposed between the pixel driving unit and the substrate. The light-shielding layer includes: a light-shielding part disposed in the display area and overlapping with the pixel driving unit, and the transmission signal line disposed in the non-display area.

4. The display panel as described in claim 3, characterized in that, The first semiconductor layer further includes a plurality of second semiconductors disposed in the display area, and the pixel driving unit includes the second semiconductors; The first semiconductor includes a first channel region, and the transmission signal line is not overlapped with the first channel region; The second semiconductor includes a second channel region, and the light-shielding portion overlaps with the second channel region.

5. The display panel as described in claim 4, characterized in that, The driving circuit layer further includes a second semiconductor layer disposed on the side of the first semiconductor layer away from the substrate. The second semiconductor layer includes a plurality of third semiconductors disposed in the display area, and the pixel driving unit further includes the third semiconductors, the third semiconductors comprising a metal oxide material; The light-shielding part is disposed without overlapping with the third semiconductor.

6. The display panel as described in claim 1, characterized in that, The gate driving unit further includes a third gate driving unit. The gate driving circuit region includes a first routing region and a second routing region. The first gate driving unit and the second gate driving unit are disposed in the first routing region, and the third gate driving unit is disposed in the second routing region. At least a portion of the transmission signal lines are disposed in the second routing region.

7. The display panel as described in claim 6, characterized in that, The first gate driving unit is connected to the stage transmission signal line through a via at the junction of the first trace area and the second trace area, and the second gate driving unit is connected to the stage transmission signal line through a via at the junction of the first trace area and the second trace area.

8. The display panel as described in claim 6, characterized in that, The display panel further includes a connection trace area disposed between the gate driving circuit area and the display area, the second trace area being disposed between the first trace area and the connection trace area, and the transmission signal line extending from the second trace area to the connection trace area.

9. A display device, characterized in that, Includes the display panel and driver chip as described in any one of claims 1 to 8.

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